1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 19 struct mpi3mr_drv_cmd *drv_cmd); 20 21 static int poll_queues; 22 module_param(poll_queues, int, 0444); 23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 24 25 #if defined(writeq) && defined(CONFIG_64BIT) 26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 27 { 28 writeq(b, addr); 29 } 30 #else 31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 32 { 33 __u64 data_out = b; 34 35 writel((u32)(data_out), addr); 36 writel((u32)(data_out >> 32), (addr + 4)); 37 } 38 #endif 39 40 static inline bool 41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 42 { 43 u16 pi, ci, max_entries; 44 bool is_qfull = false; 45 46 pi = op_req_q->pi; 47 ci = READ_ONCE(op_req_q->ci); 48 max_entries = op_req_q->num_requests; 49 50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 51 is_qfull = true; 52 53 return is_qfull; 54 } 55 56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 57 { 58 u16 i, max_vectors; 59 60 max_vectors = mrioc->intr_info_count; 61 62 for (i = 0; i < max_vectors; i++) 63 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 64 } 65 66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 67 { 68 mrioc->intr_enabled = 0; 69 mpi3mr_sync_irqs(mrioc); 70 } 71 72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 73 { 74 mrioc->intr_enabled = 1; 75 } 76 77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 78 { 79 u16 i; 80 81 mpi3mr_ioc_disable_intr(mrioc); 82 83 if (!mrioc->intr_info) 84 return; 85 86 for (i = 0; i < mrioc->intr_info_count; i++) 87 free_irq(pci_irq_vector(mrioc->pdev, i), 88 (mrioc->intr_info + i)); 89 90 kfree(mrioc->intr_info); 91 mrioc->intr_info = NULL; 92 mrioc->intr_info_count = 0; 93 mrioc->is_intr_info_set = false; 94 pci_free_irq_vectors(mrioc->pdev); 95 } 96 97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 98 dma_addr_t dma_addr) 99 { 100 struct mpi3_sge_common *sgel = paddr; 101 102 sgel->flags = flags; 103 sgel->length = cpu_to_le32(length); 104 sgel->address = cpu_to_le64(dma_addr); 105 } 106 107 void mpi3mr_build_zero_len_sge(void *paddr) 108 { 109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 110 111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 112 } 113 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 115 dma_addr_t phys_addr) 116 { 117 if (!phys_addr) 118 return NULL; 119 120 if ((phys_addr < mrioc->reply_buf_dma) || 121 (phys_addr > mrioc->reply_buf_dma_max_address)) 122 return NULL; 123 124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 125 } 126 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 128 dma_addr_t phys_addr) 129 { 130 if (!phys_addr) 131 return NULL; 132 133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 134 } 135 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 137 u64 reply_dma) 138 { 139 u32 old_idx = 0; 140 unsigned long flags; 141 142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 143 old_idx = mrioc->reply_free_queue_host_index; 144 mrioc->reply_free_queue_host_index = ( 145 (mrioc->reply_free_queue_host_index == 146 (mrioc->reply_free_qsz - 1)) ? 0 : 147 (mrioc->reply_free_queue_host_index + 1)); 148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 149 writel(mrioc->reply_free_queue_host_index, 150 &mrioc->sysif_regs->reply_free_host_index); 151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 152 } 153 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 155 u64 sense_buf_dma) 156 { 157 u32 old_idx = 0; 158 unsigned long flags; 159 160 spin_lock_irqsave(&mrioc->sbq_lock, flags); 161 old_idx = mrioc->sbq_host_index; 162 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 163 (mrioc->sense_buf_q_sz - 1)) ? 0 : 164 (mrioc->sbq_host_index + 1)); 165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 166 writel(mrioc->sbq_host_index, 167 &mrioc->sysif_regs->sense_buffer_free_host_index); 168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 169 } 170 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 172 struct mpi3_event_notification_reply *event_reply) 173 { 174 char *desc = NULL; 175 u16 event; 176 177 event = event_reply->event; 178 179 switch (event) { 180 case MPI3_EVENT_LOG_DATA: 181 desc = "Log Data"; 182 break; 183 case MPI3_EVENT_CHANGE: 184 desc = "Event Change"; 185 break; 186 case MPI3_EVENT_GPIO_INTERRUPT: 187 desc = "GPIO Interrupt"; 188 break; 189 case MPI3_EVENT_CABLE_MGMT: 190 desc = "Cable Management"; 191 break; 192 case MPI3_EVENT_ENERGY_PACK_CHANGE: 193 desc = "Energy Pack Change"; 194 break; 195 case MPI3_EVENT_DEVICE_ADDED: 196 { 197 struct mpi3_device_page0 *event_data = 198 (struct mpi3_device_page0 *)event_reply->event_data; 199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 200 event_data->dev_handle, event_data->device_form); 201 return; 202 } 203 case MPI3_EVENT_DEVICE_INFO_CHANGED: 204 { 205 struct mpi3_device_page0 *event_data = 206 (struct mpi3_device_page0 *)event_reply->event_data; 207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 208 event_data->dev_handle, event_data->device_form); 209 return; 210 } 211 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 212 { 213 struct mpi3_event_data_device_status_change *event_data = 214 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 216 event_data->dev_handle, event_data->reason_code); 217 return; 218 } 219 case MPI3_EVENT_SAS_DISCOVERY: 220 { 221 struct mpi3_event_data_sas_discovery *event_data = 222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 225 "start" : "stop", 226 le32_to_cpu(event_data->discovery_status)); 227 return; 228 } 229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 230 desc = "SAS Broadcast Primitive"; 231 break; 232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 233 desc = "SAS Notify Primitive"; 234 break; 235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 236 desc = "SAS Init Device Status Change"; 237 break; 238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 239 desc = "SAS Init Table Overflow"; 240 break; 241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 242 desc = "SAS Topology Change List"; 243 break; 244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 245 desc = "Enclosure Device Status Change"; 246 break; 247 case MPI3_EVENT_ENCL_DEVICE_ADDED: 248 desc = "Enclosure Added"; 249 break; 250 case MPI3_EVENT_HARD_RESET_RECEIVED: 251 desc = "Hard Reset Received"; 252 break; 253 case MPI3_EVENT_SAS_PHY_COUNTER: 254 desc = "SAS PHY Counter"; 255 break; 256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 257 desc = "SAS Device Discovery Error"; 258 break; 259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 260 desc = "PCIE Topology Change List"; 261 break; 262 case MPI3_EVENT_PCIE_ENUMERATION: 263 { 264 struct mpi3_event_data_pcie_enumeration *event_data = 265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 266 ioc_info(mrioc, "PCIE Enumeration: (%s)", 267 (event_data->reason_code == 268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 269 if (event_data->enumeration_status) 270 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 271 le32_to_cpu(event_data->enumeration_status)); 272 return; 273 } 274 case MPI3_EVENT_PREPARE_FOR_RESET: 275 desc = "Prepare For Reset"; 276 break; 277 } 278 279 if (!desc) 280 return; 281 282 ioc_info(mrioc, "%s\n", desc); 283 } 284 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 286 struct mpi3_default_reply *def_reply) 287 { 288 struct mpi3_event_notification_reply *event_reply = 289 (struct mpi3_event_notification_reply *)def_reply; 290 291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 292 mpi3mr_print_event_data(mrioc, event_reply); 293 mpi3mr_os_handle_events(mrioc, event_reply); 294 } 295 296 static struct mpi3mr_drv_cmd * 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 298 struct mpi3_default_reply *def_reply) 299 { 300 u16 idx; 301 302 switch (host_tag) { 303 case MPI3MR_HOSTTAG_INITCMDS: 304 return &mrioc->init_cmds; 305 case MPI3MR_HOSTTAG_CFG_CMDS: 306 return &mrioc->cfg_cmds; 307 case MPI3MR_HOSTTAG_BSG_CMDS: 308 return &mrioc->bsg_cmds; 309 case MPI3MR_HOSTTAG_BLK_TMS: 310 return &mrioc->host_tm_cmds; 311 case MPI3MR_HOSTTAG_PEL_ABORT: 312 return &mrioc->pel_abort_cmd; 313 case MPI3MR_HOSTTAG_PEL_WAIT: 314 return &mrioc->pel_cmds; 315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS: 316 return &mrioc->transport_cmds; 317 case MPI3MR_HOSTTAG_INVALID: 318 if (def_reply && def_reply->function == 319 MPI3_FUNCTION_EVENT_NOTIFICATION) 320 mpi3mr_handle_events(mrioc, def_reply); 321 return NULL; 322 default: 323 break; 324 } 325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 328 return &mrioc->dev_rmhs_cmds[idx]; 329 } 330 331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 334 return &mrioc->evtack_cmds[idx]; 335 } 336 337 return NULL; 338 } 339 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 342 { 343 u16 reply_desc_type, host_tag = 0; 344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 345 u32 ioc_loginfo = 0; 346 struct mpi3_status_reply_descriptor *status_desc; 347 struct mpi3_address_reply_descriptor *addr_desc; 348 struct mpi3_success_reply_descriptor *success_desc; 349 struct mpi3_default_reply *def_reply = NULL; 350 struct mpi3mr_drv_cmd *cmdptr = NULL; 351 struct mpi3_scsi_io_reply *scsi_reply; 352 u8 *sense_buf = NULL; 353 354 *reply_dma = 0; 355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 357 switch (reply_desc_type) { 358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 360 host_tag = le16_to_cpu(status_desc->host_tag); 361 ioc_status = le16_to_cpu(status_desc->ioc_status); 362 if (ioc_status & 363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 366 break; 367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 371 if (!def_reply) 372 goto out; 373 host_tag = le16_to_cpu(def_reply->host_tag); 374 ioc_status = le16_to_cpu(def_reply->ioc_status); 375 if (ioc_status & 376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 382 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 383 } 384 break; 385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 387 host_tag = le16_to_cpu(success_desc->host_tag); 388 break; 389 default: 390 break; 391 } 392 393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 394 if (cmdptr) { 395 if (cmdptr->state & MPI3MR_CMD_PENDING) { 396 cmdptr->state |= MPI3MR_CMD_COMPLETE; 397 cmdptr->ioc_loginfo = ioc_loginfo; 398 cmdptr->ioc_status = ioc_status; 399 cmdptr->state &= ~MPI3MR_CMD_PENDING; 400 if (def_reply) { 401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 403 mrioc->reply_sz); 404 } 405 if (cmdptr->is_waiting) { 406 complete(&cmdptr->done); 407 cmdptr->is_waiting = 0; 408 } else if (cmdptr->callback) 409 cmdptr->callback(mrioc, cmdptr); 410 } 411 } 412 out: 413 if (sense_buf) 414 mpi3mr_repost_sense_buf(mrioc, 415 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 416 } 417 418 static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 419 { 420 u32 exp_phase = mrioc->admin_reply_ephase; 421 u32 admin_reply_ci = mrioc->admin_reply_ci; 422 u32 num_admin_replies = 0; 423 u64 reply_dma = 0; 424 struct mpi3_default_reply_descriptor *reply_desc; 425 426 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 427 admin_reply_ci; 428 429 if ((le16_to_cpu(reply_desc->reply_flags) & 430 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 431 return 0; 432 433 do { 434 if (mrioc->unrecoverable) 435 break; 436 437 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 438 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 439 if (reply_dma) 440 mpi3mr_repost_reply_buf(mrioc, reply_dma); 441 num_admin_replies++; 442 if (++admin_reply_ci == mrioc->num_admin_replies) { 443 admin_reply_ci = 0; 444 exp_phase ^= 1; 445 } 446 reply_desc = 447 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 448 admin_reply_ci; 449 if ((le16_to_cpu(reply_desc->reply_flags) & 450 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 451 break; 452 } while (1); 453 454 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 455 mrioc->admin_reply_ci = admin_reply_ci; 456 mrioc->admin_reply_ephase = exp_phase; 457 458 return num_admin_replies; 459 } 460 461 /** 462 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 463 * queue's consumer index from operational reply descriptor queue. 464 * @op_reply_q: op_reply_qinfo object 465 * @reply_ci: operational reply descriptor's queue consumer index 466 * 467 * Returns reply descriptor frame address 468 */ 469 static inline struct mpi3_default_reply_descriptor * 470 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 471 { 472 void *segment_base_addr; 473 struct segments *segments = op_reply_q->q_segments; 474 struct mpi3_default_reply_descriptor *reply_desc = NULL; 475 476 segment_base_addr = 477 segments[reply_ci / op_reply_q->segment_qd].segment; 478 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 479 (reply_ci % op_reply_q->segment_qd); 480 return reply_desc; 481 } 482 483 /** 484 * mpi3mr_process_op_reply_q - Operational reply queue handler 485 * @mrioc: Adapter instance reference 486 * @op_reply_q: Operational reply queue info 487 * 488 * Checks the specific operational reply queue and drains the 489 * reply queue entries until the queue is empty and process the 490 * individual reply descriptors. 491 * 492 * Return: 0 if queue is already processed,or number of reply 493 * descriptors processed. 494 */ 495 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 496 struct op_reply_qinfo *op_reply_q) 497 { 498 struct op_req_qinfo *op_req_q; 499 u32 exp_phase; 500 u32 reply_ci; 501 u32 num_op_reply = 0; 502 u64 reply_dma = 0; 503 struct mpi3_default_reply_descriptor *reply_desc; 504 u16 req_q_idx = 0, reply_qidx; 505 506 reply_qidx = op_reply_q->qid - 1; 507 508 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 509 return 0; 510 511 exp_phase = op_reply_q->ephase; 512 reply_ci = op_reply_q->ci; 513 514 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 515 if ((le16_to_cpu(reply_desc->reply_flags) & 516 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 517 atomic_dec(&op_reply_q->in_use); 518 return 0; 519 } 520 521 do { 522 if (mrioc->unrecoverable) 523 break; 524 525 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 526 op_req_q = &mrioc->req_qinfo[req_q_idx]; 527 528 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 529 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 530 reply_qidx); 531 atomic_dec(&op_reply_q->pend_ios); 532 if (reply_dma) 533 mpi3mr_repost_reply_buf(mrioc, reply_dma); 534 num_op_reply++; 535 536 if (++reply_ci == op_reply_q->num_replies) { 537 reply_ci = 0; 538 exp_phase ^= 1; 539 } 540 541 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 542 543 if ((le16_to_cpu(reply_desc->reply_flags) & 544 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 545 break; 546 #ifndef CONFIG_PREEMPT_RT 547 /* 548 * Exit completion loop to avoid CPU lockup 549 * Ensure remaining completion happens from threaded ISR. 550 */ 551 if (num_op_reply > mrioc->max_host_ios) { 552 op_reply_q->enable_irq_poll = true; 553 break; 554 } 555 #endif 556 } while (1); 557 558 writel(reply_ci, 559 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 560 op_reply_q->ci = reply_ci; 561 op_reply_q->ephase = exp_phase; 562 563 atomic_dec(&op_reply_q->in_use); 564 return num_op_reply; 565 } 566 567 /** 568 * mpi3mr_blk_mq_poll - Operational reply queue handler 569 * @shost: SCSI Host reference 570 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 571 * 572 * Checks the specific operational reply queue and drains the 573 * reply queue entries until the queue is empty and process the 574 * individual reply descriptors. 575 * 576 * Return: 0 if queue is already processed,or number of reply 577 * descriptors processed. 578 */ 579 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 580 { 581 int num_entries = 0; 582 struct mpi3mr_ioc *mrioc; 583 584 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 585 586 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset || 587 mrioc->unrecoverable)) 588 return 0; 589 590 num_entries = mpi3mr_process_op_reply_q(mrioc, 591 &mrioc->op_reply_qinfo[queue_num]); 592 593 return num_entries; 594 } 595 596 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 597 { 598 struct mpi3mr_intr_info *intr_info = privdata; 599 struct mpi3mr_ioc *mrioc; 600 u16 midx; 601 u32 num_admin_replies = 0, num_op_reply = 0; 602 603 if (!intr_info) 604 return IRQ_NONE; 605 606 mrioc = intr_info->mrioc; 607 608 if (!mrioc->intr_enabled) 609 return IRQ_NONE; 610 611 midx = intr_info->msix_index; 612 613 if (!midx) 614 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 615 if (intr_info->op_reply_q) 616 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 617 intr_info->op_reply_q); 618 619 if (num_admin_replies || num_op_reply) 620 return IRQ_HANDLED; 621 else 622 return IRQ_NONE; 623 } 624 625 #ifndef CONFIG_PREEMPT_RT 626 627 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 628 { 629 struct mpi3mr_intr_info *intr_info = privdata; 630 int ret; 631 632 if (!intr_info) 633 return IRQ_NONE; 634 635 /* Call primary ISR routine */ 636 ret = mpi3mr_isr_primary(irq, privdata); 637 638 /* 639 * If more IOs are expected, schedule IRQ polling thread. 640 * Otherwise exit from ISR. 641 */ 642 if (!intr_info->op_reply_q) 643 return ret; 644 645 if (!intr_info->op_reply_q->enable_irq_poll || 646 !atomic_read(&intr_info->op_reply_q->pend_ios)) 647 return ret; 648 649 disable_irq_nosync(intr_info->os_irq); 650 651 return IRQ_WAKE_THREAD; 652 } 653 654 /** 655 * mpi3mr_isr_poll - Reply queue polling routine 656 * @irq: IRQ 657 * @privdata: Interrupt info 658 * 659 * poll for pending I/O completions in a loop until pending I/Os 660 * present or controller queue depth I/Os are processed. 661 * 662 * Return: IRQ_NONE or IRQ_HANDLED 663 */ 664 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 665 { 666 struct mpi3mr_intr_info *intr_info = privdata; 667 struct mpi3mr_ioc *mrioc; 668 u16 midx; 669 u32 num_op_reply = 0; 670 671 if (!intr_info || !intr_info->op_reply_q) 672 return IRQ_NONE; 673 674 mrioc = intr_info->mrioc; 675 midx = intr_info->msix_index; 676 677 /* Poll for pending IOs completions */ 678 do { 679 if (!mrioc->intr_enabled || mrioc->unrecoverable) 680 break; 681 682 if (!midx) 683 mpi3mr_process_admin_reply_q(mrioc); 684 if (intr_info->op_reply_q) 685 num_op_reply += 686 mpi3mr_process_op_reply_q(mrioc, 687 intr_info->op_reply_q); 688 689 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP); 690 691 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 692 (num_op_reply < mrioc->max_host_ios)); 693 694 intr_info->op_reply_q->enable_irq_poll = false; 695 enable_irq(intr_info->os_irq); 696 697 return IRQ_HANDLED; 698 } 699 700 #endif 701 702 /** 703 * mpi3mr_request_irq - Request IRQ and register ISR 704 * @mrioc: Adapter instance reference 705 * @index: IRQ vector index 706 * 707 * Request threaded ISR with primary ISR and secondary 708 * 709 * Return: 0 on success and non zero on failures. 710 */ 711 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 712 { 713 struct pci_dev *pdev = mrioc->pdev; 714 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 715 int retval = 0; 716 717 intr_info->mrioc = mrioc; 718 intr_info->msix_index = index; 719 intr_info->op_reply_q = NULL; 720 721 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 722 mrioc->driver_name, mrioc->id, index); 723 724 #ifndef CONFIG_PREEMPT_RT 725 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 726 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 727 #else 728 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary, 729 NULL, IRQF_SHARED, intr_info->name, intr_info); 730 #endif 731 if (retval) { 732 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 733 intr_info->name, pci_irq_vector(pdev, index)); 734 return retval; 735 } 736 737 intr_info->os_irq = pci_irq_vector(pdev, index); 738 return retval; 739 } 740 741 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 742 { 743 if (!mrioc->requested_poll_qcount) 744 return; 745 746 /* Reserved for Admin and Default Queue */ 747 if (max_vectors > 2 && 748 (mrioc->requested_poll_qcount < max_vectors - 2)) { 749 ioc_info(mrioc, 750 "enabled polled queues (%d) msix (%d)\n", 751 mrioc->requested_poll_qcount, max_vectors); 752 } else { 753 ioc_info(mrioc, 754 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 755 mrioc->requested_poll_qcount, max_vectors); 756 mrioc->requested_poll_qcount = 0; 757 } 758 } 759 760 /** 761 * mpi3mr_setup_isr - Setup ISR for the controller 762 * @mrioc: Adapter instance reference 763 * @setup_one: Request one IRQ or more 764 * 765 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 766 * 767 * Return: 0 on success and non zero on failures. 768 */ 769 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 770 { 771 unsigned int irq_flags = PCI_IRQ_MSIX; 772 int max_vectors, min_vec; 773 int retval; 774 int i; 775 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 776 777 if (mrioc->is_intr_info_set) 778 return 0; 779 780 mpi3mr_cleanup_isr(mrioc); 781 782 if (setup_one || reset_devices) { 783 max_vectors = 1; 784 retval = pci_alloc_irq_vectors(mrioc->pdev, 785 1, max_vectors, irq_flags); 786 if (retval < 0) { 787 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 788 retval); 789 goto out_failed; 790 } 791 } else { 792 max_vectors = 793 min_t(int, mrioc->cpu_count + 1 + 794 mrioc->requested_poll_qcount, mrioc->msix_count); 795 796 mpi3mr_calc_poll_queues(mrioc, max_vectors); 797 798 ioc_info(mrioc, 799 "MSI-X vectors supported: %d, no of cores: %d,", 800 mrioc->msix_count, mrioc->cpu_count); 801 ioc_info(mrioc, 802 "MSI-x vectors requested: %d poll_queues %d\n", 803 max_vectors, mrioc->requested_poll_qcount); 804 805 desc.post_vectors = mrioc->requested_poll_qcount; 806 min_vec = desc.pre_vectors + desc.post_vectors; 807 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 808 809 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 810 min_vec, max_vectors, irq_flags, &desc); 811 812 if (retval < 0) { 813 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 814 retval); 815 goto out_failed; 816 } 817 818 819 /* 820 * If only one MSI-x is allocated, then MSI-x 0 will be shared 821 * between Admin queue and operational queue 822 */ 823 if (retval == min_vec) 824 mrioc->op_reply_q_offset = 0; 825 else if (retval != (max_vectors)) { 826 ioc_info(mrioc, 827 "allocated vectors (%d) are less than configured (%d)\n", 828 retval, max_vectors); 829 } 830 831 max_vectors = retval; 832 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 833 834 mpi3mr_calc_poll_queues(mrioc, max_vectors); 835 836 } 837 838 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 839 GFP_KERNEL); 840 if (!mrioc->intr_info) { 841 retval = -ENOMEM; 842 pci_free_irq_vectors(mrioc->pdev); 843 goto out_failed; 844 } 845 for (i = 0; i < max_vectors; i++) { 846 retval = mpi3mr_request_irq(mrioc, i); 847 if (retval) { 848 mrioc->intr_info_count = i; 849 goto out_failed; 850 } 851 } 852 if (reset_devices || !setup_one) 853 mrioc->is_intr_info_set = true; 854 mrioc->intr_info_count = max_vectors; 855 mpi3mr_ioc_enable_intr(mrioc); 856 return 0; 857 858 out_failed: 859 mpi3mr_cleanup_isr(mrioc); 860 861 return retval; 862 } 863 864 static const struct { 865 enum mpi3mr_iocstate value; 866 char *name; 867 } mrioc_states[] = { 868 { MRIOC_STATE_READY, "ready" }, 869 { MRIOC_STATE_FAULT, "fault" }, 870 { MRIOC_STATE_RESET, "reset" }, 871 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 872 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 873 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 874 }; 875 876 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 877 { 878 int i; 879 char *name = NULL; 880 881 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 882 if (mrioc_states[i].value == mrioc_state) { 883 name = mrioc_states[i].name; 884 break; 885 } 886 } 887 return name; 888 } 889 890 /* Reset reason to name mapper structure*/ 891 static const struct { 892 enum mpi3mr_reset_reason value; 893 char *name; 894 } mpi3mr_reset_reason_codes[] = { 895 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 896 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 897 { MPI3MR_RESET_FROM_APP, "application invocation" }, 898 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 899 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 900 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" }, 901 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 902 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 903 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 904 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 905 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 906 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 907 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 908 { 909 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 910 "create request queue timeout" 911 }, 912 { 913 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 914 "create reply queue timeout" 915 }, 916 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 917 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 918 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 919 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 920 { 921 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 922 "component image activation timeout" 923 }, 924 { 925 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 926 "get package version timeout" 927 }, 928 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 929 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 930 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 931 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"}, 932 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" }, 933 }; 934 935 /** 936 * mpi3mr_reset_rc_name - get reset reason code name 937 * @reason_code: reset reason code value 938 * 939 * Map reset reason to an NULL terminated ASCII string 940 * 941 * Return: name corresponding to reset reason value or NULL. 942 */ 943 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 944 { 945 int i; 946 char *name = NULL; 947 948 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 949 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 950 name = mpi3mr_reset_reason_codes[i].name; 951 break; 952 } 953 } 954 return name; 955 } 956 957 /* Reset type to name mapper structure*/ 958 static const struct { 959 u16 reset_type; 960 char *name; 961 } mpi3mr_reset_types[] = { 962 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 963 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 964 }; 965 966 /** 967 * mpi3mr_reset_type_name - get reset type name 968 * @reset_type: reset type value 969 * 970 * Map reset type to an NULL terminated ASCII string 971 * 972 * Return: name corresponding to reset type value or NULL. 973 */ 974 static const char *mpi3mr_reset_type_name(u16 reset_type) 975 { 976 int i; 977 char *name = NULL; 978 979 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 980 if (mpi3mr_reset_types[i].reset_type == reset_type) { 981 name = mpi3mr_reset_types[i].name; 982 break; 983 } 984 } 985 return name; 986 } 987 988 /** 989 * mpi3mr_print_fault_info - Display fault information 990 * @mrioc: Adapter instance reference 991 * 992 * Display the controller fault information if there is a 993 * controller fault. 994 * 995 * Return: Nothing. 996 */ 997 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 998 { 999 u32 ioc_status, code, code1, code2, code3; 1000 1001 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1002 1003 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1004 code = readl(&mrioc->sysif_regs->fault); 1005 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 1006 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 1007 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 1008 1009 ioc_info(mrioc, 1010 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 1011 code, code1, code2, code3); 1012 } 1013 } 1014 1015 /** 1016 * mpi3mr_get_iocstate - Get IOC State 1017 * @mrioc: Adapter instance reference 1018 * 1019 * Return a proper IOC state enum based on the IOC status and 1020 * IOC configuration and unrcoverable state of the controller. 1021 * 1022 * Return: Current IOC state. 1023 */ 1024 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 1025 { 1026 u32 ioc_status, ioc_config; 1027 u8 ready, enabled; 1028 1029 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1030 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1031 1032 if (mrioc->unrecoverable) 1033 return MRIOC_STATE_UNRECOVERABLE; 1034 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1035 return MRIOC_STATE_FAULT; 1036 1037 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1038 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1039 1040 if (ready && enabled) 1041 return MRIOC_STATE_READY; 1042 if ((!ready) && (!enabled)) 1043 return MRIOC_STATE_RESET; 1044 if ((!ready) && (enabled)) 1045 return MRIOC_STATE_BECOMING_READY; 1046 1047 return MRIOC_STATE_RESET_REQUESTED; 1048 } 1049 1050 /** 1051 * mpi3mr_clear_reset_history - clear reset history 1052 * @mrioc: Adapter instance reference 1053 * 1054 * Write the reset history bit in IOC status to clear the bit, 1055 * if it is already set. 1056 * 1057 * Return: Nothing. 1058 */ 1059 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1060 { 1061 u32 ioc_status; 1062 1063 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1064 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1065 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1066 } 1067 1068 /** 1069 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1070 * @mrioc: Adapter instance reference 1071 * @reset_reason: Reset reason code 1072 * 1073 * Issue Message unit Reset to the controller and wait for it to 1074 * be complete. 1075 * 1076 * Return: 0 on success, -1 on failure. 1077 */ 1078 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1079 u32 reset_reason) 1080 { 1081 u32 ioc_config, timeout, ioc_status; 1082 int retval = -1; 1083 1084 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1085 if (mrioc->unrecoverable) { 1086 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1087 return retval; 1088 } 1089 mpi3mr_clear_reset_history(mrioc); 1090 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1091 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1092 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1093 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1094 1095 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1096 do { 1097 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1098 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1099 mpi3mr_clear_reset_history(mrioc); 1100 break; 1101 } 1102 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1103 mpi3mr_print_fault_info(mrioc); 1104 break; 1105 } 1106 msleep(100); 1107 } while (--timeout); 1108 1109 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1110 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1111 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1112 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1113 retval = 0; 1114 1115 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 1116 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1117 return retval; 1118 } 1119 1120 /** 1121 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1122 * during reset/resume 1123 * @mrioc: Adapter instance reference 1124 * 1125 * Return zero if the new IOCFacts parameters value is compatible with 1126 * older values else return -EPERM 1127 */ 1128 static int 1129 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1130 { 1131 u16 dev_handle_bitmap_sz; 1132 void *removepend_bitmap; 1133 1134 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1135 ioc_err(mrioc, 1136 "cannot increase reply size from %d to %d\n", 1137 mrioc->reply_sz, mrioc->facts.reply_sz); 1138 return -EPERM; 1139 } 1140 1141 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1142 ioc_err(mrioc, 1143 "cannot reduce number of operational reply queues from %d to %d\n", 1144 mrioc->num_op_reply_q, 1145 mrioc->facts.max_op_reply_q); 1146 return -EPERM; 1147 } 1148 1149 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1150 ioc_err(mrioc, 1151 "cannot reduce number of operational request queues from %d to %d\n", 1152 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1153 return -EPERM; 1154 } 1155 1156 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & 1157 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) 1158 ioc_err(mrioc, 1159 "critical error: multipath capability is enabled at the\n" 1160 "\tcontroller while sas transport support is enabled at the\n" 1161 "\tdriver, please reboot the system or reload the driver\n"); 1162 1163 dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8; 1164 if (mrioc->facts.max_devhandle % 8) 1165 dev_handle_bitmap_sz++; 1166 if (dev_handle_bitmap_sz > mrioc->dev_handle_bitmap_sz) { 1167 removepend_bitmap = krealloc(mrioc->removepend_bitmap, 1168 dev_handle_bitmap_sz, GFP_KERNEL); 1169 if (!removepend_bitmap) { 1170 ioc_err(mrioc, 1171 "failed to increase removepend_bitmap sz from: %d to %d\n", 1172 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 1173 return -EPERM; 1174 } 1175 memset(removepend_bitmap + mrioc->dev_handle_bitmap_sz, 0, 1176 dev_handle_bitmap_sz - mrioc->dev_handle_bitmap_sz); 1177 mrioc->removepend_bitmap = removepend_bitmap; 1178 ioc_info(mrioc, 1179 "increased dev_handle_bitmap_sz from %d to %d\n", 1180 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 1181 mrioc->dev_handle_bitmap_sz = dev_handle_bitmap_sz; 1182 } 1183 1184 return 0; 1185 } 1186 1187 /** 1188 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1189 * @mrioc: Adapter instance reference 1190 * 1191 * Set Enable IOC bit in IOC configuration register and wait for 1192 * the controller to become ready. 1193 * 1194 * Return: 0 on success, appropriate error on failure. 1195 */ 1196 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1197 { 1198 u32 ioc_config, ioc_status, timeout; 1199 int retval = 0; 1200 enum mpi3mr_iocstate ioc_state; 1201 u64 base_info; 1202 1203 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1204 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1205 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1206 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1207 ioc_status, ioc_config, base_info); 1208 1209 /*The timeout value is in 2sec unit, changing it to seconds*/ 1210 mrioc->ready_timeout = 1211 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1212 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1213 1214 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1215 1216 ioc_state = mpi3mr_get_iocstate(mrioc); 1217 ioc_info(mrioc, "controller is in %s state during detection\n", 1218 mpi3mr_iocstate_name(ioc_state)); 1219 1220 if (ioc_state == MRIOC_STATE_BECOMING_READY || 1221 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 1222 timeout = mrioc->ready_timeout * 10; 1223 do { 1224 msleep(100); 1225 } while (--timeout); 1226 1227 if (!pci_device_is_present(mrioc->pdev)) { 1228 mrioc->unrecoverable = 1; 1229 ioc_err(mrioc, 1230 "controller is not present while waiting to reset\n"); 1231 retval = -1; 1232 goto out_device_not_present; 1233 } 1234 1235 ioc_state = mpi3mr_get_iocstate(mrioc); 1236 ioc_info(mrioc, 1237 "controller is in %s state after waiting to reset\n", 1238 mpi3mr_iocstate_name(ioc_state)); 1239 } 1240 1241 if (ioc_state == MRIOC_STATE_READY) { 1242 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1243 retval = mpi3mr_issue_and_process_mur(mrioc, 1244 MPI3MR_RESET_FROM_BRINGUP); 1245 ioc_state = mpi3mr_get_iocstate(mrioc); 1246 if (retval) 1247 ioc_err(mrioc, 1248 "message unit reset failed with error %d current state %s\n", 1249 retval, mpi3mr_iocstate_name(ioc_state)); 1250 } 1251 if (ioc_state != MRIOC_STATE_RESET) { 1252 mpi3mr_print_fault_info(mrioc); 1253 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1254 retval = mpi3mr_issue_reset(mrioc, 1255 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1256 MPI3MR_RESET_FROM_BRINGUP); 1257 if (retval) { 1258 ioc_err(mrioc, 1259 "soft reset failed with error %d\n", retval); 1260 goto out_failed; 1261 } 1262 } 1263 ioc_state = mpi3mr_get_iocstate(mrioc); 1264 if (ioc_state != MRIOC_STATE_RESET) { 1265 ioc_err(mrioc, 1266 "cannot bring controller to reset state, current state: %s\n", 1267 mpi3mr_iocstate_name(ioc_state)); 1268 goto out_failed; 1269 } 1270 mpi3mr_clear_reset_history(mrioc); 1271 retval = mpi3mr_setup_admin_qpair(mrioc); 1272 if (retval) { 1273 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1274 retval); 1275 goto out_failed; 1276 } 1277 1278 ioc_info(mrioc, "bringing controller to ready state\n"); 1279 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1280 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1281 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1282 1283 timeout = mrioc->ready_timeout * 10; 1284 do { 1285 ioc_state = mpi3mr_get_iocstate(mrioc); 1286 if (ioc_state == MRIOC_STATE_READY) { 1287 ioc_info(mrioc, 1288 "successfully transitioned to %s state\n", 1289 mpi3mr_iocstate_name(ioc_state)); 1290 return 0; 1291 } 1292 if (!pci_device_is_present(mrioc->pdev)) { 1293 mrioc->unrecoverable = 1; 1294 ioc_err(mrioc, 1295 "controller is not present at the bringup\n"); 1296 retval = -1; 1297 goto out_device_not_present; 1298 } 1299 msleep(100); 1300 } while (--timeout); 1301 1302 out_failed: 1303 ioc_state = mpi3mr_get_iocstate(mrioc); 1304 ioc_err(mrioc, 1305 "failed to bring to ready state, current state: %s\n", 1306 mpi3mr_iocstate_name(ioc_state)); 1307 out_device_not_present: 1308 return retval; 1309 } 1310 1311 /** 1312 * mpi3mr_soft_reset_success - Check softreset is success or not 1313 * @ioc_status: IOC status register value 1314 * @ioc_config: IOC config register value 1315 * 1316 * Check whether the soft reset is successful or not based on 1317 * IOC status and IOC config register values. 1318 * 1319 * Return: True when the soft reset is success, false otherwise. 1320 */ 1321 static inline bool 1322 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1323 { 1324 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1325 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1326 return true; 1327 return false; 1328 } 1329 1330 /** 1331 * mpi3mr_diagfault_success - Check diag fault is success or not 1332 * @mrioc: Adapter reference 1333 * @ioc_status: IOC status register value 1334 * 1335 * Check whether the controller hit diag reset fault code. 1336 * 1337 * Return: True when there is diag fault, false otherwise. 1338 */ 1339 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1340 u32 ioc_status) 1341 { 1342 u32 fault; 1343 1344 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1345 return false; 1346 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1347 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1348 mpi3mr_print_fault_info(mrioc); 1349 return true; 1350 } 1351 return false; 1352 } 1353 1354 /** 1355 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1356 * @mrioc: Adapter reference 1357 * 1358 * Set diag save bit in IOC configuration register to enable 1359 * snapdump. 1360 * 1361 * Return: Nothing. 1362 */ 1363 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1364 { 1365 u32 ioc_config; 1366 1367 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1368 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1369 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1370 } 1371 1372 /** 1373 * mpi3mr_issue_reset - Issue reset to the controller 1374 * @mrioc: Adapter reference 1375 * @reset_type: Reset type 1376 * @reset_reason: Reset reason code 1377 * 1378 * Unlock the host diagnostic registers and write the specific 1379 * reset type to that, wait for reset acknowledgment from the 1380 * controller, if the reset is not successful retry for the 1381 * predefined number of times. 1382 * 1383 * Return: 0 on success, non-zero on failure. 1384 */ 1385 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1386 u32 reset_reason) 1387 { 1388 int retval = -1; 1389 u8 unlock_retry_count = 0; 1390 u32 host_diagnostic, ioc_status, ioc_config; 1391 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1392 1393 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1394 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1395 return retval; 1396 if (mrioc->unrecoverable) 1397 return retval; 1398 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1399 retval = 0; 1400 return retval; 1401 } 1402 1403 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1404 mpi3mr_reset_type_name(reset_type), 1405 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1406 1407 mpi3mr_clear_reset_history(mrioc); 1408 do { 1409 ioc_info(mrioc, 1410 "Write magic sequence to unlock host diag register (retry=%d)\n", 1411 ++unlock_retry_count); 1412 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1413 ioc_err(mrioc, 1414 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1415 mpi3mr_reset_type_name(reset_type), 1416 host_diagnostic); 1417 mrioc->unrecoverable = 1; 1418 return retval; 1419 } 1420 1421 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1422 &mrioc->sysif_regs->write_sequence); 1423 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1424 &mrioc->sysif_regs->write_sequence); 1425 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1426 &mrioc->sysif_regs->write_sequence); 1427 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1428 &mrioc->sysif_regs->write_sequence); 1429 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1430 &mrioc->sysif_regs->write_sequence); 1431 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1432 &mrioc->sysif_regs->write_sequence); 1433 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1434 &mrioc->sysif_regs->write_sequence); 1435 usleep_range(1000, 1100); 1436 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1437 ioc_info(mrioc, 1438 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1439 unlock_retry_count, host_diagnostic); 1440 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1441 1442 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1443 writel(host_diagnostic | reset_type, 1444 &mrioc->sysif_regs->host_diagnostic); 1445 switch (reset_type) { 1446 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1447 do { 1448 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1449 ioc_config = 1450 readl(&mrioc->sysif_regs->ioc_configuration); 1451 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1452 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1453 ) { 1454 mpi3mr_clear_reset_history(mrioc); 1455 retval = 0; 1456 break; 1457 } 1458 msleep(100); 1459 } while (--timeout); 1460 mpi3mr_print_fault_info(mrioc); 1461 break; 1462 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1463 do { 1464 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1465 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1466 retval = 0; 1467 break; 1468 } 1469 msleep(100); 1470 } while (--timeout); 1471 break; 1472 default: 1473 break; 1474 } 1475 1476 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1477 &mrioc->sysif_regs->write_sequence); 1478 1479 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1480 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1481 ioc_info(mrioc, 1482 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n", 1483 (!retval)?"successful":"failed", ioc_status, 1484 ioc_config); 1485 if (retval) 1486 mrioc->unrecoverable = 1; 1487 return retval; 1488 } 1489 1490 /** 1491 * mpi3mr_admin_request_post - Post request to admin queue 1492 * @mrioc: Adapter reference 1493 * @admin_req: MPI3 request 1494 * @admin_req_sz: Request size 1495 * @ignore_reset: Ignore reset in process 1496 * 1497 * Post the MPI3 request into admin request queue and 1498 * inform the controller, if the queue is full return 1499 * appropriate error. 1500 * 1501 * Return: 0 on success, non-zero on failure. 1502 */ 1503 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1504 u16 admin_req_sz, u8 ignore_reset) 1505 { 1506 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1507 int retval = 0; 1508 unsigned long flags; 1509 u8 *areq_entry; 1510 1511 if (mrioc->unrecoverable) { 1512 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1513 return -EFAULT; 1514 } 1515 1516 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1517 areq_pi = mrioc->admin_req_pi; 1518 areq_ci = mrioc->admin_req_ci; 1519 max_entries = mrioc->num_admin_req; 1520 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1521 (areq_pi == (max_entries - 1)))) { 1522 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1523 retval = -EAGAIN; 1524 goto out; 1525 } 1526 if (!ignore_reset && mrioc->reset_in_progress) { 1527 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1528 retval = -EAGAIN; 1529 goto out; 1530 } 1531 areq_entry = (u8 *)mrioc->admin_req_base + 1532 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1533 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1534 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1535 1536 if (++areq_pi == max_entries) 1537 areq_pi = 0; 1538 mrioc->admin_req_pi = areq_pi; 1539 1540 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1541 1542 out: 1543 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1544 1545 return retval; 1546 } 1547 1548 /** 1549 * mpi3mr_free_op_req_q_segments - free request memory segments 1550 * @mrioc: Adapter instance reference 1551 * @q_idx: operational request queue index 1552 * 1553 * Free memory segments allocated for operational request queue 1554 * 1555 * Return: Nothing. 1556 */ 1557 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1558 { 1559 u16 j; 1560 int size; 1561 struct segments *segments; 1562 1563 segments = mrioc->req_qinfo[q_idx].q_segments; 1564 if (!segments) 1565 return; 1566 1567 if (mrioc->enable_segqueue) { 1568 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1569 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1570 dma_free_coherent(&mrioc->pdev->dev, 1571 MPI3MR_MAX_SEG_LIST_SIZE, 1572 mrioc->req_qinfo[q_idx].q_segment_list, 1573 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1574 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1575 } 1576 } else 1577 size = mrioc->req_qinfo[q_idx].segment_qd * 1578 mrioc->facts.op_req_sz; 1579 1580 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1581 if (!segments[j].segment) 1582 continue; 1583 dma_free_coherent(&mrioc->pdev->dev, 1584 size, segments[j].segment, segments[j].segment_dma); 1585 segments[j].segment = NULL; 1586 } 1587 kfree(mrioc->req_qinfo[q_idx].q_segments); 1588 mrioc->req_qinfo[q_idx].q_segments = NULL; 1589 mrioc->req_qinfo[q_idx].qid = 0; 1590 } 1591 1592 /** 1593 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1594 * @mrioc: Adapter instance reference 1595 * @q_idx: operational reply queue index 1596 * 1597 * Free memory segments allocated for operational reply queue 1598 * 1599 * Return: Nothing. 1600 */ 1601 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1602 { 1603 u16 j; 1604 int size; 1605 struct segments *segments; 1606 1607 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1608 if (!segments) 1609 return; 1610 1611 if (mrioc->enable_segqueue) { 1612 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1613 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1614 dma_free_coherent(&mrioc->pdev->dev, 1615 MPI3MR_MAX_SEG_LIST_SIZE, 1616 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1617 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1618 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1619 } 1620 } else 1621 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1622 mrioc->op_reply_desc_sz; 1623 1624 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1625 if (!segments[j].segment) 1626 continue; 1627 dma_free_coherent(&mrioc->pdev->dev, 1628 size, segments[j].segment, segments[j].segment_dma); 1629 segments[j].segment = NULL; 1630 } 1631 1632 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1633 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1634 mrioc->op_reply_qinfo[q_idx].qid = 0; 1635 } 1636 1637 /** 1638 * mpi3mr_delete_op_reply_q - delete operational reply queue 1639 * @mrioc: Adapter instance reference 1640 * @qidx: operational reply queue index 1641 * 1642 * Delete operatinal reply queue by issuing MPI request 1643 * through admin queue. 1644 * 1645 * Return: 0 on success, non-zero on failure. 1646 */ 1647 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1648 { 1649 struct mpi3_delete_reply_queue_request delq_req; 1650 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1651 int retval = 0; 1652 u16 reply_qid = 0, midx; 1653 1654 reply_qid = op_reply_q->qid; 1655 1656 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1657 1658 if (!reply_qid) { 1659 retval = -1; 1660 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1661 goto out; 1662 } 1663 1664 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1665 mrioc->active_poll_qcount--; 1666 1667 memset(&delq_req, 0, sizeof(delq_req)); 1668 mutex_lock(&mrioc->init_cmds.mutex); 1669 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1670 retval = -1; 1671 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1672 mutex_unlock(&mrioc->init_cmds.mutex); 1673 goto out; 1674 } 1675 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1676 mrioc->init_cmds.is_waiting = 1; 1677 mrioc->init_cmds.callback = NULL; 1678 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1679 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1680 delq_req.queue_id = cpu_to_le16(reply_qid); 1681 1682 init_completion(&mrioc->init_cmds.done); 1683 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1684 1); 1685 if (retval) { 1686 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1687 goto out_unlock; 1688 } 1689 wait_for_completion_timeout(&mrioc->init_cmds.done, 1690 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1691 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1692 ioc_err(mrioc, "delete reply queue timed out\n"); 1693 mpi3mr_check_rh_fault_ioc(mrioc, 1694 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1695 retval = -1; 1696 goto out_unlock; 1697 } 1698 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1699 != MPI3_IOCSTATUS_SUCCESS) { 1700 ioc_err(mrioc, 1701 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1702 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1703 mrioc->init_cmds.ioc_loginfo); 1704 retval = -1; 1705 goto out_unlock; 1706 } 1707 mrioc->intr_info[midx].op_reply_q = NULL; 1708 1709 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1710 out_unlock: 1711 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1712 mutex_unlock(&mrioc->init_cmds.mutex); 1713 out: 1714 1715 return retval; 1716 } 1717 1718 /** 1719 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1720 * @mrioc: Adapter instance reference 1721 * @qidx: request queue index 1722 * 1723 * Allocate segmented memory pools for operational reply 1724 * queue. 1725 * 1726 * Return: 0 on success, non-zero on failure. 1727 */ 1728 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1729 { 1730 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1731 int i, size; 1732 u64 *q_segment_list_entry = NULL; 1733 struct segments *segments; 1734 1735 if (mrioc->enable_segqueue) { 1736 op_reply_q->segment_qd = 1737 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1738 1739 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1740 1741 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1742 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1743 GFP_KERNEL); 1744 if (!op_reply_q->q_segment_list) 1745 return -ENOMEM; 1746 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1747 } else { 1748 op_reply_q->segment_qd = op_reply_q->num_replies; 1749 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1750 } 1751 1752 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1753 op_reply_q->segment_qd); 1754 1755 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1756 sizeof(struct segments), GFP_KERNEL); 1757 if (!op_reply_q->q_segments) 1758 return -ENOMEM; 1759 1760 segments = op_reply_q->q_segments; 1761 for (i = 0; i < op_reply_q->num_segments; i++) { 1762 segments[i].segment = 1763 dma_alloc_coherent(&mrioc->pdev->dev, 1764 size, &segments[i].segment_dma, GFP_KERNEL); 1765 if (!segments[i].segment) 1766 return -ENOMEM; 1767 if (mrioc->enable_segqueue) 1768 q_segment_list_entry[i] = 1769 (unsigned long)segments[i].segment_dma; 1770 } 1771 1772 return 0; 1773 } 1774 1775 /** 1776 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1777 * @mrioc: Adapter instance reference 1778 * @qidx: request queue index 1779 * 1780 * Allocate segmented memory pools for operational request 1781 * queue. 1782 * 1783 * Return: 0 on success, non-zero on failure. 1784 */ 1785 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1786 { 1787 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1788 int i, size; 1789 u64 *q_segment_list_entry = NULL; 1790 struct segments *segments; 1791 1792 if (mrioc->enable_segqueue) { 1793 op_req_q->segment_qd = 1794 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1795 1796 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1797 1798 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1799 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1800 GFP_KERNEL); 1801 if (!op_req_q->q_segment_list) 1802 return -ENOMEM; 1803 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1804 1805 } else { 1806 op_req_q->segment_qd = op_req_q->num_requests; 1807 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1808 } 1809 1810 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 1811 op_req_q->segment_qd); 1812 1813 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 1814 sizeof(struct segments), GFP_KERNEL); 1815 if (!op_req_q->q_segments) 1816 return -ENOMEM; 1817 1818 segments = op_req_q->q_segments; 1819 for (i = 0; i < op_req_q->num_segments; i++) { 1820 segments[i].segment = 1821 dma_alloc_coherent(&mrioc->pdev->dev, 1822 size, &segments[i].segment_dma, GFP_KERNEL); 1823 if (!segments[i].segment) 1824 return -ENOMEM; 1825 if (mrioc->enable_segqueue) 1826 q_segment_list_entry[i] = 1827 (unsigned long)segments[i].segment_dma; 1828 } 1829 1830 return 0; 1831 } 1832 1833 /** 1834 * mpi3mr_create_op_reply_q - create operational reply queue 1835 * @mrioc: Adapter instance reference 1836 * @qidx: operational reply queue index 1837 * 1838 * Create operatinal reply queue by issuing MPI request 1839 * through admin queue. 1840 * 1841 * Return: 0 on success, non-zero on failure. 1842 */ 1843 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1844 { 1845 struct mpi3_create_reply_queue_request create_req; 1846 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1847 int retval = 0; 1848 u16 reply_qid = 0, midx; 1849 1850 reply_qid = op_reply_q->qid; 1851 1852 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1853 1854 if (reply_qid) { 1855 retval = -1; 1856 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 1857 reply_qid); 1858 1859 return retval; 1860 } 1861 1862 reply_qid = qidx + 1; 1863 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 1864 if (!mrioc->pdev->revision) 1865 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 1866 op_reply_q->ci = 0; 1867 op_reply_q->ephase = 1; 1868 atomic_set(&op_reply_q->pend_ios, 0); 1869 atomic_set(&op_reply_q->in_use, 0); 1870 op_reply_q->enable_irq_poll = false; 1871 1872 if (!op_reply_q->q_segments) { 1873 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 1874 if (retval) { 1875 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1876 goto out; 1877 } 1878 } 1879 1880 memset(&create_req, 0, sizeof(create_req)); 1881 mutex_lock(&mrioc->init_cmds.mutex); 1882 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1883 retval = -1; 1884 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 1885 goto out_unlock; 1886 } 1887 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1888 mrioc->init_cmds.is_waiting = 1; 1889 mrioc->init_cmds.callback = NULL; 1890 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1891 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 1892 create_req.queue_id = cpu_to_le16(reply_qid); 1893 1894 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 1895 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 1896 else 1897 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 1898 1899 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 1900 create_req.flags = 1901 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 1902 create_req.msix_index = 1903 cpu_to_le16(mrioc->intr_info[midx].msix_index); 1904 } else { 1905 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 1906 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 1907 reply_qid, midx); 1908 if (!mrioc->active_poll_qcount) 1909 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 1910 mrioc->intr_info_count - 1)); 1911 } 1912 1913 if (mrioc->enable_segqueue) { 1914 create_req.flags |= 1915 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1916 create_req.base_address = cpu_to_le64( 1917 op_reply_q->q_segment_list_dma); 1918 } else 1919 create_req.base_address = cpu_to_le64( 1920 op_reply_q->q_segments[0].segment_dma); 1921 1922 create_req.size = cpu_to_le16(op_reply_q->num_replies); 1923 1924 init_completion(&mrioc->init_cmds.done); 1925 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1926 sizeof(create_req), 1); 1927 if (retval) { 1928 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 1929 goto out_unlock; 1930 } 1931 wait_for_completion_timeout(&mrioc->init_cmds.done, 1932 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1933 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1934 ioc_err(mrioc, "create reply queue timed out\n"); 1935 mpi3mr_check_rh_fault_ioc(mrioc, 1936 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 1937 retval = -1; 1938 goto out_unlock; 1939 } 1940 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1941 != MPI3_IOCSTATUS_SUCCESS) { 1942 ioc_err(mrioc, 1943 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1944 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1945 mrioc->init_cmds.ioc_loginfo); 1946 retval = -1; 1947 goto out_unlock; 1948 } 1949 op_reply_q->qid = reply_qid; 1950 if (midx < mrioc->intr_info_count) 1951 mrioc->intr_info[midx].op_reply_q = op_reply_q; 1952 1953 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 1954 mrioc->active_poll_qcount++; 1955 1956 out_unlock: 1957 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1958 mutex_unlock(&mrioc->init_cmds.mutex); 1959 out: 1960 1961 return retval; 1962 } 1963 1964 /** 1965 * mpi3mr_create_op_req_q - create operational request queue 1966 * @mrioc: Adapter instance reference 1967 * @idx: operational request queue index 1968 * @reply_qid: Reply queue ID 1969 * 1970 * Create operatinal request queue by issuing MPI request 1971 * through admin queue. 1972 * 1973 * Return: 0 on success, non-zero on failure. 1974 */ 1975 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 1976 u16 reply_qid) 1977 { 1978 struct mpi3_create_request_queue_request create_req; 1979 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 1980 int retval = 0; 1981 u16 req_qid = 0; 1982 1983 req_qid = op_req_q->qid; 1984 1985 if (req_qid) { 1986 retval = -1; 1987 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 1988 req_qid); 1989 1990 return retval; 1991 } 1992 req_qid = idx + 1; 1993 1994 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 1995 op_req_q->ci = 0; 1996 op_req_q->pi = 0; 1997 op_req_q->reply_qid = reply_qid; 1998 spin_lock_init(&op_req_q->q_lock); 1999 2000 if (!op_req_q->q_segments) { 2001 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 2002 if (retval) { 2003 mpi3mr_free_op_req_q_segments(mrioc, idx); 2004 goto out; 2005 } 2006 } 2007 2008 memset(&create_req, 0, sizeof(create_req)); 2009 mutex_lock(&mrioc->init_cmds.mutex); 2010 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2011 retval = -1; 2012 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 2013 goto out_unlock; 2014 } 2015 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2016 mrioc->init_cmds.is_waiting = 1; 2017 mrioc->init_cmds.callback = NULL; 2018 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2019 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 2020 create_req.queue_id = cpu_to_le16(req_qid); 2021 if (mrioc->enable_segqueue) { 2022 create_req.flags = 2023 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 2024 create_req.base_address = cpu_to_le64( 2025 op_req_q->q_segment_list_dma); 2026 } else 2027 create_req.base_address = cpu_to_le64( 2028 op_req_q->q_segments[0].segment_dma); 2029 create_req.reply_queue_id = cpu_to_le16(reply_qid); 2030 create_req.size = cpu_to_le16(op_req_q->num_requests); 2031 2032 init_completion(&mrioc->init_cmds.done); 2033 retval = mpi3mr_admin_request_post(mrioc, &create_req, 2034 sizeof(create_req), 1); 2035 if (retval) { 2036 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 2037 goto out_unlock; 2038 } 2039 wait_for_completion_timeout(&mrioc->init_cmds.done, 2040 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2041 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2042 ioc_err(mrioc, "create request queue timed out\n"); 2043 mpi3mr_check_rh_fault_ioc(mrioc, 2044 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 2045 retval = -1; 2046 goto out_unlock; 2047 } 2048 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2049 != MPI3_IOCSTATUS_SUCCESS) { 2050 ioc_err(mrioc, 2051 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2052 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2053 mrioc->init_cmds.ioc_loginfo); 2054 retval = -1; 2055 goto out_unlock; 2056 } 2057 op_req_q->qid = req_qid; 2058 2059 out_unlock: 2060 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2061 mutex_unlock(&mrioc->init_cmds.mutex); 2062 out: 2063 2064 return retval; 2065 } 2066 2067 /** 2068 * mpi3mr_create_op_queues - create operational queue pairs 2069 * @mrioc: Adapter instance reference 2070 * 2071 * Allocate memory for operational queue meta data and call 2072 * create request and reply queue functions. 2073 * 2074 * Return: 0 on success, non-zero on failures. 2075 */ 2076 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2077 { 2078 int retval = 0; 2079 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2080 2081 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2082 mrioc->facts.max_op_req_q); 2083 2084 msix_count_op_q = 2085 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2086 if (!mrioc->num_queues) 2087 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2088 /* 2089 * During reset set the num_queues to the number of queues 2090 * that was set before the reset. 2091 */ 2092 num_queues = mrioc->num_op_reply_q ? 2093 mrioc->num_op_reply_q : mrioc->num_queues; 2094 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2095 num_queues); 2096 2097 if (!mrioc->req_qinfo) { 2098 mrioc->req_qinfo = kcalloc(num_queues, 2099 sizeof(struct op_req_qinfo), GFP_KERNEL); 2100 if (!mrioc->req_qinfo) { 2101 retval = -1; 2102 goto out_failed; 2103 } 2104 2105 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2106 num_queues, GFP_KERNEL); 2107 if (!mrioc->op_reply_qinfo) { 2108 retval = -1; 2109 goto out_failed; 2110 } 2111 } 2112 2113 if (mrioc->enable_segqueue) 2114 ioc_info(mrioc, 2115 "allocating operational queues through segmented queues\n"); 2116 2117 for (i = 0; i < num_queues; i++) { 2118 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2119 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2120 break; 2121 } 2122 if (mpi3mr_create_op_req_q(mrioc, i, 2123 mrioc->op_reply_qinfo[i].qid)) { 2124 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2125 mpi3mr_delete_op_reply_q(mrioc, i); 2126 break; 2127 } 2128 } 2129 2130 if (i == 0) { 2131 /* Not even one queue is created successfully*/ 2132 retval = -1; 2133 goto out_failed; 2134 } 2135 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2136 ioc_info(mrioc, 2137 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2138 mrioc->num_op_reply_q, mrioc->default_qcount, 2139 mrioc->active_poll_qcount); 2140 2141 return retval; 2142 out_failed: 2143 kfree(mrioc->req_qinfo); 2144 mrioc->req_qinfo = NULL; 2145 2146 kfree(mrioc->op_reply_qinfo); 2147 mrioc->op_reply_qinfo = NULL; 2148 2149 return retval; 2150 } 2151 2152 /** 2153 * mpi3mr_op_request_post - Post request to operational queue 2154 * @mrioc: Adapter reference 2155 * @op_req_q: Operational request queue info 2156 * @req: MPI3 request 2157 * 2158 * Post the MPI3 request into operational request queue and 2159 * inform the controller, if the queue is full return 2160 * appropriate error. 2161 * 2162 * Return: 0 on success, non-zero on failure. 2163 */ 2164 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2165 struct op_req_qinfo *op_req_q, u8 *req) 2166 { 2167 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2168 int retval = 0; 2169 unsigned long flags; 2170 u8 *req_entry; 2171 void *segment_base_addr; 2172 u16 req_sz = mrioc->facts.op_req_sz; 2173 struct segments *segments = op_req_q->q_segments; 2174 2175 reply_qidx = op_req_q->reply_qid - 1; 2176 2177 if (mrioc->unrecoverable) 2178 return -EFAULT; 2179 2180 spin_lock_irqsave(&op_req_q->q_lock, flags); 2181 pi = op_req_q->pi; 2182 max_entries = op_req_q->num_requests; 2183 2184 if (mpi3mr_check_req_qfull(op_req_q)) { 2185 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2186 reply_qidx, mrioc->op_reply_q_offset); 2187 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2188 2189 if (mpi3mr_check_req_qfull(op_req_q)) { 2190 retval = -EAGAIN; 2191 goto out; 2192 } 2193 } 2194 2195 if (mrioc->reset_in_progress) { 2196 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2197 retval = -EAGAIN; 2198 goto out; 2199 } 2200 2201 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2202 req_entry = (u8 *)segment_base_addr + 2203 ((pi % op_req_q->segment_qd) * req_sz); 2204 2205 memset(req_entry, 0, req_sz); 2206 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2207 2208 if (++pi == max_entries) 2209 pi = 0; 2210 op_req_q->pi = pi; 2211 2212 #ifndef CONFIG_PREEMPT_RT 2213 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2214 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2215 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2216 #else 2217 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios); 2218 #endif 2219 2220 writel(op_req_q->pi, 2221 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2222 2223 out: 2224 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2225 return retval; 2226 } 2227 2228 /** 2229 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2230 * controller 2231 * @mrioc: Adapter instance reference 2232 * @reason_code: reason code for the fault. 2233 * 2234 * This routine will save snapdump and fault the controller with 2235 * the given reason code if it is not already in the fault or 2236 * not asynchronosuly reset. This will be used to handle 2237 * initilaization time faults/resets/timeout as in those cases 2238 * immediate soft reset invocation is not required. 2239 * 2240 * Return: None. 2241 */ 2242 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2243 { 2244 u32 ioc_status, host_diagnostic, timeout; 2245 2246 if (mrioc->unrecoverable) { 2247 ioc_err(mrioc, "controller is unrecoverable\n"); 2248 return; 2249 } 2250 2251 if (!pci_device_is_present(mrioc->pdev)) { 2252 mrioc->unrecoverable = 1; 2253 ioc_err(mrioc, "controller is not present\n"); 2254 return; 2255 } 2256 2257 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2258 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 2259 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 2260 mpi3mr_print_fault_info(mrioc); 2261 return; 2262 } 2263 mpi3mr_set_diagsave(mrioc); 2264 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2265 reason_code); 2266 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2267 do { 2268 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2269 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2270 break; 2271 msleep(100); 2272 } while (--timeout); 2273 } 2274 2275 /** 2276 * mpi3mr_sync_timestamp - Issue time stamp sync request 2277 * @mrioc: Adapter reference 2278 * 2279 * Issue IO unit control MPI request to synchornize firmware 2280 * timestamp with host time. 2281 * 2282 * Return: 0 on success, non-zero on failure. 2283 */ 2284 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2285 { 2286 ktime_t current_time; 2287 struct mpi3_iounit_control_request iou_ctrl; 2288 int retval = 0; 2289 2290 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2291 mutex_lock(&mrioc->init_cmds.mutex); 2292 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2293 retval = -1; 2294 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2295 mutex_unlock(&mrioc->init_cmds.mutex); 2296 goto out; 2297 } 2298 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2299 mrioc->init_cmds.is_waiting = 1; 2300 mrioc->init_cmds.callback = NULL; 2301 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2302 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2303 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2304 current_time = ktime_get_real(); 2305 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2306 2307 init_completion(&mrioc->init_cmds.done); 2308 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2309 sizeof(iou_ctrl), 0); 2310 if (retval) { 2311 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2312 goto out_unlock; 2313 } 2314 2315 wait_for_completion_timeout(&mrioc->init_cmds.done, 2316 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2317 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2318 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2319 mrioc->init_cmds.is_waiting = 0; 2320 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2321 mpi3mr_soft_reset_handler(mrioc, 2322 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1); 2323 retval = -1; 2324 goto out_unlock; 2325 } 2326 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2327 != MPI3_IOCSTATUS_SUCCESS) { 2328 ioc_err(mrioc, 2329 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2330 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2331 mrioc->init_cmds.ioc_loginfo); 2332 retval = -1; 2333 goto out_unlock; 2334 } 2335 2336 out_unlock: 2337 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2338 mutex_unlock(&mrioc->init_cmds.mutex); 2339 2340 out: 2341 return retval; 2342 } 2343 2344 /** 2345 * mpi3mr_print_pkg_ver - display controller fw package version 2346 * @mrioc: Adapter reference 2347 * 2348 * Retrieve firmware package version from the component image 2349 * header of the controller flash and display it. 2350 * 2351 * Return: 0 on success and non-zero on failure. 2352 */ 2353 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2354 { 2355 struct mpi3_ci_upload_request ci_upload; 2356 int retval = -1; 2357 void *data = NULL; 2358 dma_addr_t data_dma; 2359 struct mpi3_ci_manifest_mpi *manifest; 2360 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2361 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2362 2363 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2364 GFP_KERNEL); 2365 if (!data) 2366 return -ENOMEM; 2367 2368 memset(&ci_upload, 0, sizeof(ci_upload)); 2369 mutex_lock(&mrioc->init_cmds.mutex); 2370 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2371 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2372 mutex_unlock(&mrioc->init_cmds.mutex); 2373 goto out; 2374 } 2375 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2376 mrioc->init_cmds.is_waiting = 1; 2377 mrioc->init_cmds.callback = NULL; 2378 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2379 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2380 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2381 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2382 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2383 ci_upload.segment_size = cpu_to_le32(data_len); 2384 2385 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2386 data_dma); 2387 init_completion(&mrioc->init_cmds.done); 2388 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2389 sizeof(ci_upload), 1); 2390 if (retval) { 2391 ioc_err(mrioc, "posting get package version failed\n"); 2392 goto out_unlock; 2393 } 2394 wait_for_completion_timeout(&mrioc->init_cmds.done, 2395 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2396 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2397 ioc_err(mrioc, "get package version timed out\n"); 2398 mpi3mr_check_rh_fault_ioc(mrioc, 2399 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2400 retval = -1; 2401 goto out_unlock; 2402 } 2403 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2404 == MPI3_IOCSTATUS_SUCCESS) { 2405 manifest = (struct mpi3_ci_manifest_mpi *) data; 2406 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2407 ioc_info(mrioc, 2408 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2409 manifest->package_version.gen_major, 2410 manifest->package_version.gen_minor, 2411 manifest->package_version.phase_major, 2412 manifest->package_version.phase_minor, 2413 manifest->package_version.customer_id, 2414 manifest->package_version.build_num); 2415 } 2416 } 2417 retval = 0; 2418 out_unlock: 2419 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2420 mutex_unlock(&mrioc->init_cmds.mutex); 2421 2422 out: 2423 if (data) 2424 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2425 data_dma); 2426 return retval; 2427 } 2428 2429 /** 2430 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2431 * @work: work struct 2432 * 2433 * Watch dog work periodically executed (1 second interval) to 2434 * monitor firmware fault and to issue periodic timer sync to 2435 * the firmware. 2436 * 2437 * Return: Nothing. 2438 */ 2439 static void mpi3mr_watchdog_work(struct work_struct *work) 2440 { 2441 struct mpi3mr_ioc *mrioc = 2442 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2443 unsigned long flags; 2444 enum mpi3mr_iocstate ioc_state; 2445 u32 fault, host_diagnostic, ioc_status; 2446 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2447 2448 if (mrioc->reset_in_progress) 2449 return; 2450 2451 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) { 2452 ioc_err(mrioc, "watchdog could not detect the controller\n"); 2453 mrioc->unrecoverable = 1; 2454 } 2455 2456 if (mrioc->unrecoverable) { 2457 ioc_err(mrioc, 2458 "flush pending commands for unrecoverable controller\n"); 2459 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 2460 return; 2461 } 2462 2463 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) { 2464 mrioc->ts_update_counter = 0; 2465 mpi3mr_sync_timestamp(mrioc); 2466 } 2467 2468 if ((mrioc->prepare_for_reset) && 2469 ((mrioc->prepare_for_reset_timeout_counter++) >= 2470 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2471 mpi3mr_soft_reset_handler(mrioc, 2472 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2473 return; 2474 } 2475 2476 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2477 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2478 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2479 return; 2480 } 2481 2482 /*Check for fault state every one second and issue Soft reset*/ 2483 ioc_state = mpi3mr_get_iocstate(mrioc); 2484 if (ioc_state != MRIOC_STATE_FAULT) 2485 goto schedule_work; 2486 2487 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2488 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2489 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2490 if (!mrioc->diagsave_timeout) { 2491 mpi3mr_print_fault_info(mrioc); 2492 ioc_warn(mrioc, "diag save in progress\n"); 2493 } 2494 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2495 goto schedule_work; 2496 } 2497 2498 mpi3mr_print_fault_info(mrioc); 2499 mrioc->diagsave_timeout = 0; 2500 2501 switch (fault) { 2502 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED: 2503 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2504 ioc_warn(mrioc, 2505 "controller requires system power cycle, marking controller as unrecoverable\n"); 2506 mrioc->unrecoverable = 1; 2507 goto schedule_work; 2508 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2509 return; 2510 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2511 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2512 break; 2513 default: 2514 break; 2515 } 2516 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2517 return; 2518 2519 schedule_work: 2520 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2521 if (mrioc->watchdog_work_q) 2522 queue_delayed_work(mrioc->watchdog_work_q, 2523 &mrioc->watchdog_work, 2524 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2525 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2526 return; 2527 } 2528 2529 /** 2530 * mpi3mr_start_watchdog - Start watchdog 2531 * @mrioc: Adapter instance reference 2532 * 2533 * Create and start the watchdog thread to monitor controller 2534 * faults. 2535 * 2536 * Return: Nothing. 2537 */ 2538 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2539 { 2540 if (mrioc->watchdog_work_q) 2541 return; 2542 2543 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2544 snprintf(mrioc->watchdog_work_q_name, 2545 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2546 mrioc->id); 2547 mrioc->watchdog_work_q = 2548 create_singlethread_workqueue(mrioc->watchdog_work_q_name); 2549 if (!mrioc->watchdog_work_q) { 2550 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2551 return; 2552 } 2553 2554 if (mrioc->watchdog_work_q) 2555 queue_delayed_work(mrioc->watchdog_work_q, 2556 &mrioc->watchdog_work, 2557 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2558 } 2559 2560 /** 2561 * mpi3mr_stop_watchdog - Stop watchdog 2562 * @mrioc: Adapter instance reference 2563 * 2564 * Stop the watchdog thread created to monitor controller 2565 * faults. 2566 * 2567 * Return: Nothing. 2568 */ 2569 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2570 { 2571 unsigned long flags; 2572 struct workqueue_struct *wq; 2573 2574 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2575 wq = mrioc->watchdog_work_q; 2576 mrioc->watchdog_work_q = NULL; 2577 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2578 if (wq) { 2579 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2580 flush_workqueue(wq); 2581 destroy_workqueue(wq); 2582 } 2583 } 2584 2585 /** 2586 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2587 * @mrioc: Adapter instance reference 2588 * 2589 * Allocate memory for admin queue pair if required and register 2590 * the admin queue with the controller. 2591 * 2592 * Return: 0 on success, non-zero on failures. 2593 */ 2594 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2595 { 2596 int retval = 0; 2597 u32 num_admin_entries = 0; 2598 2599 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2600 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2601 MPI3MR_ADMIN_REQ_FRAME_SZ; 2602 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2603 mrioc->admin_req_base = NULL; 2604 2605 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2606 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2607 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2608 mrioc->admin_reply_ci = 0; 2609 mrioc->admin_reply_ephase = 1; 2610 mrioc->admin_reply_base = NULL; 2611 2612 if (!mrioc->admin_req_base) { 2613 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2614 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2615 2616 if (!mrioc->admin_req_base) { 2617 retval = -1; 2618 goto out_failed; 2619 } 2620 2621 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2622 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2623 GFP_KERNEL); 2624 2625 if (!mrioc->admin_reply_base) { 2626 retval = -1; 2627 goto out_failed; 2628 } 2629 } 2630 2631 num_admin_entries = (mrioc->num_admin_replies << 16) | 2632 (mrioc->num_admin_req); 2633 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2634 mpi3mr_writeq(mrioc->admin_req_dma, 2635 &mrioc->sysif_regs->admin_request_queue_address); 2636 mpi3mr_writeq(mrioc->admin_reply_dma, 2637 &mrioc->sysif_regs->admin_reply_queue_address); 2638 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2639 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2640 return retval; 2641 2642 out_failed: 2643 2644 if (mrioc->admin_reply_base) { 2645 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2646 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2647 mrioc->admin_reply_base = NULL; 2648 } 2649 if (mrioc->admin_req_base) { 2650 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2651 mrioc->admin_req_base, mrioc->admin_req_dma); 2652 mrioc->admin_req_base = NULL; 2653 } 2654 return retval; 2655 } 2656 2657 /** 2658 * mpi3mr_issue_iocfacts - Send IOC Facts 2659 * @mrioc: Adapter instance reference 2660 * @facts_data: Cached IOC facts data 2661 * 2662 * Issue IOC Facts MPI request through admin queue and wait for 2663 * the completion of it or time out. 2664 * 2665 * Return: 0 on success, non-zero on failures. 2666 */ 2667 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 2668 struct mpi3_ioc_facts_data *facts_data) 2669 { 2670 struct mpi3_ioc_facts_request iocfacts_req; 2671 void *data = NULL; 2672 dma_addr_t data_dma; 2673 u32 data_len = sizeof(*facts_data); 2674 int retval = 0; 2675 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2676 2677 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2678 GFP_KERNEL); 2679 2680 if (!data) { 2681 retval = -1; 2682 goto out; 2683 } 2684 2685 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 2686 mutex_lock(&mrioc->init_cmds.mutex); 2687 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2688 retval = -1; 2689 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 2690 mutex_unlock(&mrioc->init_cmds.mutex); 2691 goto out; 2692 } 2693 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2694 mrioc->init_cmds.is_waiting = 1; 2695 mrioc->init_cmds.callback = NULL; 2696 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2697 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 2698 2699 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 2700 data_dma); 2701 2702 init_completion(&mrioc->init_cmds.done); 2703 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 2704 sizeof(iocfacts_req), 1); 2705 if (retval) { 2706 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 2707 goto out_unlock; 2708 } 2709 wait_for_completion_timeout(&mrioc->init_cmds.done, 2710 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2711 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2712 ioc_err(mrioc, "ioc_facts timed out\n"); 2713 mpi3mr_check_rh_fault_ioc(mrioc, 2714 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 2715 retval = -1; 2716 goto out_unlock; 2717 } 2718 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2719 != MPI3_IOCSTATUS_SUCCESS) { 2720 ioc_err(mrioc, 2721 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2722 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2723 mrioc->init_cmds.ioc_loginfo); 2724 retval = -1; 2725 goto out_unlock; 2726 } 2727 memcpy(facts_data, (u8 *)data, data_len); 2728 mpi3mr_process_factsdata(mrioc, facts_data); 2729 out_unlock: 2730 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2731 mutex_unlock(&mrioc->init_cmds.mutex); 2732 2733 out: 2734 if (data) 2735 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 2736 2737 return retval; 2738 } 2739 2740 /** 2741 * mpi3mr_check_reset_dma_mask - Process IOC facts data 2742 * @mrioc: Adapter instance reference 2743 * 2744 * Check whether the new DMA mask requested through IOCFacts by 2745 * firmware needs to be set, if so set it . 2746 * 2747 * Return: 0 on success, non-zero on failure. 2748 */ 2749 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 2750 { 2751 struct pci_dev *pdev = mrioc->pdev; 2752 int r; 2753 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 2754 2755 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 2756 return 0; 2757 2758 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 2759 mrioc->dma_mask, facts_dma_mask); 2760 2761 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 2762 if (r) { 2763 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 2764 facts_dma_mask, r); 2765 return r; 2766 } 2767 mrioc->dma_mask = facts_dma_mask; 2768 return r; 2769 } 2770 2771 /** 2772 * mpi3mr_process_factsdata - Process IOC facts data 2773 * @mrioc: Adapter instance reference 2774 * @facts_data: Cached IOC facts data 2775 * 2776 * Convert IOC facts data into cpu endianness and cache it in 2777 * the driver . 2778 * 2779 * Return: Nothing. 2780 */ 2781 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 2782 struct mpi3_ioc_facts_data *facts_data) 2783 { 2784 u32 ioc_config, req_sz, facts_flags; 2785 2786 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 2787 (sizeof(*facts_data) / 4)) { 2788 ioc_warn(mrioc, 2789 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 2790 sizeof(*facts_data), 2791 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 2792 } 2793 2794 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2795 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 2796 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 2797 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 2798 ioc_err(mrioc, 2799 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 2800 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 2801 } 2802 2803 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 2804 2805 facts_flags = le32_to_cpu(facts_data->flags); 2806 mrioc->facts.op_req_sz = req_sz; 2807 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 2808 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 2809 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 2810 2811 mrioc->facts.ioc_num = facts_data->ioc_number; 2812 mrioc->facts.who_init = facts_data->who_init; 2813 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 2814 mrioc->facts.personality = (facts_flags & 2815 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 2816 mrioc->facts.dma_mask = (facts_flags & 2817 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 2818 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 2819 mrioc->facts.protocol_flags = facts_data->protocol_flags; 2820 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 2821 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 2822 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 2823 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 2824 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 2825 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 2826 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 2827 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 2828 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 2829 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 2830 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 2831 mrioc->facts.max_pcie_switches = 2832 le16_to_cpu(facts_data->max_pcie_switches); 2833 mrioc->facts.max_sasexpanders = 2834 le16_to_cpu(facts_data->max_sas_expanders); 2835 mrioc->facts.max_sasinitiators = 2836 le16_to_cpu(facts_data->max_sas_initiators); 2837 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 2838 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 2839 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 2840 mrioc->facts.max_op_req_q = 2841 le16_to_cpu(facts_data->max_operational_request_queues); 2842 mrioc->facts.max_op_reply_q = 2843 le16_to_cpu(facts_data->max_operational_reply_queues); 2844 mrioc->facts.ioc_capabilities = 2845 le32_to_cpu(facts_data->ioc_capabilities); 2846 mrioc->facts.fw_ver.build_num = 2847 le16_to_cpu(facts_data->fw_version.build_num); 2848 mrioc->facts.fw_ver.cust_id = 2849 le16_to_cpu(facts_data->fw_version.customer_id); 2850 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 2851 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 2852 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 2853 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 2854 mrioc->msix_count = min_t(int, mrioc->msix_count, 2855 mrioc->facts.max_msix_vectors); 2856 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 2857 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 2858 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 2859 mrioc->facts.shutdown_timeout = 2860 le16_to_cpu(facts_data->shutdown_timeout); 2861 2862 mrioc->facts.max_dev_per_tg = 2863 facts_data->max_devices_per_throttle_group; 2864 mrioc->facts.io_throttle_data_length = 2865 le16_to_cpu(facts_data->io_throttle_data_length); 2866 mrioc->facts.max_io_throttle_group = 2867 le16_to_cpu(facts_data->max_io_throttle_group); 2868 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low); 2869 mrioc->facts.io_throttle_high = 2870 le16_to_cpu(facts_data->io_throttle_high); 2871 2872 /* Store in 512b block count */ 2873 if (mrioc->facts.io_throttle_data_length) 2874 mrioc->io_throttle_data_length = 2875 (mrioc->facts.io_throttle_data_length * 2 * 4); 2876 else 2877 /* set the length to 1MB + 1K to disable throttle */ 2878 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2; 2879 2880 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024); 2881 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024); 2882 2883 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 2884 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 2885 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 2886 ioc_info(mrioc, 2887 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 2888 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 2889 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 2890 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 2891 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 2892 mrioc->facts.sge_mod_shift); 2893 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n", 2894 mrioc->facts.dma_mask, (facts_flags & 2895 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK)); 2896 ioc_info(mrioc, 2897 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n", 2898 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group); 2899 ioc_info(mrioc, 2900 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 2901 mrioc->facts.io_throttle_data_length * 4, 2902 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low); 2903 } 2904 2905 /** 2906 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 2907 * @mrioc: Adapter instance reference 2908 * 2909 * Allocate and initialize the reply free buffers, sense 2910 * buffers, reply free queue and sense buffer queue. 2911 * 2912 * Return: 0 on success, non-zero on failures. 2913 */ 2914 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 2915 { 2916 int retval = 0; 2917 u32 sz, i; 2918 2919 if (mrioc->init_cmds.reply) 2920 return retval; 2921 2922 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2923 if (!mrioc->init_cmds.reply) 2924 goto out_failed; 2925 2926 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2927 if (!mrioc->bsg_cmds.reply) 2928 goto out_failed; 2929 2930 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2931 if (!mrioc->transport_cmds.reply) 2932 goto out_failed; 2933 2934 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2935 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 2936 GFP_KERNEL); 2937 if (!mrioc->dev_rmhs_cmds[i].reply) 2938 goto out_failed; 2939 } 2940 2941 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 2942 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 2943 GFP_KERNEL); 2944 if (!mrioc->evtack_cmds[i].reply) 2945 goto out_failed; 2946 } 2947 2948 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2949 if (!mrioc->host_tm_cmds.reply) 2950 goto out_failed; 2951 2952 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2953 if (!mrioc->pel_cmds.reply) 2954 goto out_failed; 2955 2956 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2957 if (!mrioc->pel_abort_cmd.reply) 2958 goto out_failed; 2959 2960 mrioc->dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8; 2961 if (mrioc->facts.max_devhandle % 8) 2962 mrioc->dev_handle_bitmap_sz++; 2963 mrioc->removepend_bitmap = kzalloc(mrioc->dev_handle_bitmap_sz, 2964 GFP_KERNEL); 2965 if (!mrioc->removepend_bitmap) 2966 goto out_failed; 2967 2968 mrioc->devrem_bitmap_sz = MPI3MR_NUM_DEVRMCMD / 8; 2969 if (MPI3MR_NUM_DEVRMCMD % 8) 2970 mrioc->devrem_bitmap_sz++; 2971 mrioc->devrem_bitmap = kzalloc(mrioc->devrem_bitmap_sz, 2972 GFP_KERNEL); 2973 if (!mrioc->devrem_bitmap) 2974 goto out_failed; 2975 2976 mrioc->evtack_cmds_bitmap_sz = MPI3MR_NUM_EVTACKCMD / 8; 2977 if (MPI3MR_NUM_EVTACKCMD % 8) 2978 mrioc->evtack_cmds_bitmap_sz++; 2979 mrioc->evtack_cmds_bitmap = kzalloc(mrioc->evtack_cmds_bitmap_sz, 2980 GFP_KERNEL); 2981 if (!mrioc->evtack_cmds_bitmap) 2982 goto out_failed; 2983 2984 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 2985 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 2986 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 2987 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 2988 2989 /* reply buffer pool, 16 byte align */ 2990 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 2991 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 2992 &mrioc->pdev->dev, sz, 16, 0); 2993 if (!mrioc->reply_buf_pool) { 2994 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 2995 goto out_failed; 2996 } 2997 2998 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 2999 &mrioc->reply_buf_dma); 3000 if (!mrioc->reply_buf) 3001 goto out_failed; 3002 3003 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 3004 3005 /* reply free queue, 8 byte align */ 3006 sz = mrioc->reply_free_qsz * 8; 3007 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 3008 &mrioc->pdev->dev, sz, 8, 0); 3009 if (!mrioc->reply_free_q_pool) { 3010 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 3011 goto out_failed; 3012 } 3013 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 3014 GFP_KERNEL, &mrioc->reply_free_q_dma); 3015 if (!mrioc->reply_free_q) 3016 goto out_failed; 3017 3018 /* sense buffer pool, 4 byte align */ 3019 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3020 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 3021 &mrioc->pdev->dev, sz, 4, 0); 3022 if (!mrioc->sense_buf_pool) { 3023 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 3024 goto out_failed; 3025 } 3026 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 3027 &mrioc->sense_buf_dma); 3028 if (!mrioc->sense_buf) 3029 goto out_failed; 3030 3031 /* sense buffer queue, 8 byte align */ 3032 sz = mrioc->sense_buf_q_sz * 8; 3033 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 3034 &mrioc->pdev->dev, sz, 8, 0); 3035 if (!mrioc->sense_buf_q_pool) { 3036 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 3037 goto out_failed; 3038 } 3039 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 3040 GFP_KERNEL, &mrioc->sense_buf_q_dma); 3041 if (!mrioc->sense_buf_q) 3042 goto out_failed; 3043 3044 return retval; 3045 3046 out_failed: 3047 retval = -1; 3048 return retval; 3049 } 3050 3051 /** 3052 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 3053 * buffers 3054 * @mrioc: Adapter instance reference 3055 * 3056 * Helper function to initialize reply and sense buffers along 3057 * with some debug prints. 3058 * 3059 * Return: None. 3060 */ 3061 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 3062 { 3063 u32 sz, i; 3064 dma_addr_t phy_addr; 3065 3066 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 3067 ioc_info(mrioc, 3068 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3069 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 3070 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 3071 sz = mrioc->reply_free_qsz * 8; 3072 ioc_info(mrioc, 3073 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 3074 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 3075 (unsigned long long)mrioc->reply_free_q_dma); 3076 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 3077 ioc_info(mrioc, 3078 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3079 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 3080 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 3081 sz = mrioc->sense_buf_q_sz * 8; 3082 ioc_info(mrioc, 3083 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 3084 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 3085 (unsigned long long)mrioc->sense_buf_q_dma); 3086 3087 /* initialize Reply buffer Queue */ 3088 for (i = 0, phy_addr = mrioc->reply_buf_dma; 3089 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 3090 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 3091 mrioc->reply_free_q[i] = cpu_to_le64(0); 3092 3093 /* initialize Sense Buffer Queue */ 3094 for (i = 0, phy_addr = mrioc->sense_buf_dma; 3095 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 3096 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 3097 mrioc->sense_buf_q[i] = cpu_to_le64(0); 3098 } 3099 3100 /** 3101 * mpi3mr_issue_iocinit - Send IOC Init 3102 * @mrioc: Adapter instance reference 3103 * 3104 * Issue IOC Init MPI request through admin queue and wait for 3105 * the completion of it or time out. 3106 * 3107 * Return: 0 on success, non-zero on failures. 3108 */ 3109 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 3110 { 3111 struct mpi3_ioc_init_request iocinit_req; 3112 struct mpi3_driver_info_layout *drv_info; 3113 dma_addr_t data_dma; 3114 u32 data_len = sizeof(*drv_info); 3115 int retval = 0; 3116 ktime_t current_time; 3117 3118 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 3119 GFP_KERNEL); 3120 if (!drv_info) { 3121 retval = -1; 3122 goto out; 3123 } 3124 mpimr_initialize_reply_sbuf_queues(mrioc); 3125 3126 drv_info->information_length = cpu_to_le32(data_len); 3127 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3128 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3129 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3130 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3131 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3132 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3133 sizeof(drv_info->driver_release_date)); 3134 drv_info->driver_capabilities = 0; 3135 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3136 sizeof(mrioc->driver_info)); 3137 3138 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3139 mutex_lock(&mrioc->init_cmds.mutex); 3140 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3141 retval = -1; 3142 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3143 mutex_unlock(&mrioc->init_cmds.mutex); 3144 goto out; 3145 } 3146 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3147 mrioc->init_cmds.is_waiting = 1; 3148 mrioc->init_cmds.callback = NULL; 3149 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3150 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3151 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3152 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3153 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3154 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3155 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3156 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3157 iocinit_req.reply_free_queue_address = 3158 cpu_to_le64(mrioc->reply_free_q_dma); 3159 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3160 iocinit_req.sense_buffer_free_queue_depth = 3161 cpu_to_le16(mrioc->sense_buf_q_sz); 3162 iocinit_req.sense_buffer_free_queue_address = 3163 cpu_to_le64(mrioc->sense_buf_q_dma); 3164 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3165 3166 current_time = ktime_get_real(); 3167 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3168 3169 init_completion(&mrioc->init_cmds.done); 3170 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3171 sizeof(iocinit_req), 1); 3172 if (retval) { 3173 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3174 goto out_unlock; 3175 } 3176 wait_for_completion_timeout(&mrioc->init_cmds.done, 3177 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3178 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3179 mpi3mr_check_rh_fault_ioc(mrioc, 3180 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3181 ioc_err(mrioc, "ioc_init timed out\n"); 3182 retval = -1; 3183 goto out_unlock; 3184 } 3185 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3186 != MPI3_IOCSTATUS_SUCCESS) { 3187 ioc_err(mrioc, 3188 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3189 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3190 mrioc->init_cmds.ioc_loginfo); 3191 retval = -1; 3192 goto out_unlock; 3193 } 3194 3195 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3196 writel(mrioc->reply_free_queue_host_index, 3197 &mrioc->sysif_regs->reply_free_host_index); 3198 3199 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3200 writel(mrioc->sbq_host_index, 3201 &mrioc->sysif_regs->sense_buffer_free_host_index); 3202 out_unlock: 3203 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3204 mutex_unlock(&mrioc->init_cmds.mutex); 3205 3206 out: 3207 if (drv_info) 3208 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3209 data_dma); 3210 3211 return retval; 3212 } 3213 3214 /** 3215 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3216 * @mrioc: Adapter instance reference 3217 * @event: MPI event ID 3218 * 3219 * Un mask the specific event by resetting the event_mask 3220 * bitmap. 3221 * 3222 * Return: 0 on success, non-zero on failures. 3223 */ 3224 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3225 { 3226 u32 desired_event; 3227 u8 word; 3228 3229 if (event >= 128) 3230 return; 3231 3232 desired_event = (1 << (event % 32)); 3233 word = event / 32; 3234 3235 mrioc->event_masks[word] &= ~desired_event; 3236 } 3237 3238 /** 3239 * mpi3mr_issue_event_notification - Send event notification 3240 * @mrioc: Adapter instance reference 3241 * 3242 * Issue event notification MPI request through admin queue and 3243 * wait for the completion of it or time out. 3244 * 3245 * Return: 0 on success, non-zero on failures. 3246 */ 3247 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3248 { 3249 struct mpi3_event_notification_request evtnotify_req; 3250 int retval = 0; 3251 u8 i; 3252 3253 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3254 mutex_lock(&mrioc->init_cmds.mutex); 3255 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3256 retval = -1; 3257 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3258 mutex_unlock(&mrioc->init_cmds.mutex); 3259 goto out; 3260 } 3261 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3262 mrioc->init_cmds.is_waiting = 1; 3263 mrioc->init_cmds.callback = NULL; 3264 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3265 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3266 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3267 evtnotify_req.event_masks[i] = 3268 cpu_to_le32(mrioc->event_masks[i]); 3269 init_completion(&mrioc->init_cmds.done); 3270 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3271 sizeof(evtnotify_req), 1); 3272 if (retval) { 3273 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3274 goto out_unlock; 3275 } 3276 wait_for_completion_timeout(&mrioc->init_cmds.done, 3277 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3278 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3279 ioc_err(mrioc, "event notification timed out\n"); 3280 mpi3mr_check_rh_fault_ioc(mrioc, 3281 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3282 retval = -1; 3283 goto out_unlock; 3284 } 3285 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3286 != MPI3_IOCSTATUS_SUCCESS) { 3287 ioc_err(mrioc, 3288 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3289 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3290 mrioc->init_cmds.ioc_loginfo); 3291 retval = -1; 3292 goto out_unlock; 3293 } 3294 3295 out_unlock: 3296 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3297 mutex_unlock(&mrioc->init_cmds.mutex); 3298 out: 3299 return retval; 3300 } 3301 3302 /** 3303 * mpi3mr_process_event_ack - Process event acknowledgment 3304 * @mrioc: Adapter instance reference 3305 * @event: MPI3 event ID 3306 * @event_ctx: event context 3307 * 3308 * Send event acknowledgment through admin queue and wait for 3309 * it to complete. 3310 * 3311 * Return: 0 on success, non-zero on failures. 3312 */ 3313 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3314 u32 event_ctx) 3315 { 3316 struct mpi3_event_ack_request evtack_req; 3317 int retval = 0; 3318 3319 memset(&evtack_req, 0, sizeof(evtack_req)); 3320 mutex_lock(&mrioc->init_cmds.mutex); 3321 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3322 retval = -1; 3323 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3324 mutex_unlock(&mrioc->init_cmds.mutex); 3325 goto out; 3326 } 3327 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3328 mrioc->init_cmds.is_waiting = 1; 3329 mrioc->init_cmds.callback = NULL; 3330 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3331 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3332 evtack_req.event = event; 3333 evtack_req.event_context = cpu_to_le32(event_ctx); 3334 3335 init_completion(&mrioc->init_cmds.done); 3336 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3337 sizeof(evtack_req), 1); 3338 if (retval) { 3339 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3340 goto out_unlock; 3341 } 3342 wait_for_completion_timeout(&mrioc->init_cmds.done, 3343 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3344 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3345 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3346 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3347 mpi3mr_soft_reset_handler(mrioc, 3348 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1); 3349 retval = -1; 3350 goto out_unlock; 3351 } 3352 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3353 != MPI3_IOCSTATUS_SUCCESS) { 3354 ioc_err(mrioc, 3355 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3356 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3357 mrioc->init_cmds.ioc_loginfo); 3358 retval = -1; 3359 goto out_unlock; 3360 } 3361 3362 out_unlock: 3363 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3364 mutex_unlock(&mrioc->init_cmds.mutex); 3365 out: 3366 return retval; 3367 } 3368 3369 /** 3370 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3371 * @mrioc: Adapter instance reference 3372 * 3373 * Allocate chain buffers and set a bitmap to indicate free 3374 * chain buffers. Chain buffers are used to pass the SGE 3375 * information along with MPI3 SCSI IO requests for host I/O. 3376 * 3377 * Return: 0 on success, non-zero on failure 3378 */ 3379 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3380 { 3381 int retval = 0; 3382 u32 sz, i; 3383 u16 num_chains; 3384 3385 if (mrioc->chain_sgl_list) 3386 return retval; 3387 3388 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3389 3390 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3391 | SHOST_DIX_TYPE1_PROTECTION 3392 | SHOST_DIX_TYPE2_PROTECTION 3393 | SHOST_DIX_TYPE3_PROTECTION)) 3394 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3395 3396 mrioc->chain_buf_count = num_chains; 3397 sz = sizeof(struct chain_element) * num_chains; 3398 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3399 if (!mrioc->chain_sgl_list) 3400 goto out_failed; 3401 3402 sz = MPI3MR_PAGE_SIZE_4K; 3403 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3404 &mrioc->pdev->dev, sz, 16, 0); 3405 if (!mrioc->chain_buf_pool) { 3406 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3407 goto out_failed; 3408 } 3409 3410 for (i = 0; i < num_chains; i++) { 3411 mrioc->chain_sgl_list[i].addr = 3412 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3413 &mrioc->chain_sgl_list[i].dma_addr); 3414 3415 if (!mrioc->chain_sgl_list[i].addr) 3416 goto out_failed; 3417 } 3418 mrioc->chain_bitmap_sz = num_chains / 8; 3419 if (num_chains % 8) 3420 mrioc->chain_bitmap_sz++; 3421 mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL); 3422 if (!mrioc->chain_bitmap) 3423 goto out_failed; 3424 return retval; 3425 out_failed: 3426 retval = -1; 3427 return retval; 3428 } 3429 3430 /** 3431 * mpi3mr_port_enable_complete - Mark port enable complete 3432 * @mrioc: Adapter instance reference 3433 * @drv_cmd: Internal command tracker 3434 * 3435 * Call back for asynchronous port enable request sets the 3436 * driver command to indicate port enable request is complete. 3437 * 3438 * Return: Nothing 3439 */ 3440 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3441 struct mpi3mr_drv_cmd *drv_cmd) 3442 { 3443 drv_cmd->callback = NULL; 3444 mrioc->scan_started = 0; 3445 if (drv_cmd->state & MPI3MR_CMD_RESET) 3446 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 3447 else 3448 mrioc->scan_failed = drv_cmd->ioc_status; 3449 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3450 } 3451 3452 /** 3453 * mpi3mr_issue_port_enable - Issue Port Enable 3454 * @mrioc: Adapter instance reference 3455 * @async: Flag to wait for completion or not 3456 * 3457 * Issue Port Enable MPI request through admin queue and if the 3458 * async flag is not set wait for the completion of the port 3459 * enable or time out. 3460 * 3461 * Return: 0 on success, non-zero on failures. 3462 */ 3463 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3464 { 3465 struct mpi3_port_enable_request pe_req; 3466 int retval = 0; 3467 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3468 3469 memset(&pe_req, 0, sizeof(pe_req)); 3470 mutex_lock(&mrioc->init_cmds.mutex); 3471 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3472 retval = -1; 3473 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3474 mutex_unlock(&mrioc->init_cmds.mutex); 3475 goto out; 3476 } 3477 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3478 if (async) { 3479 mrioc->init_cmds.is_waiting = 0; 3480 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3481 } else { 3482 mrioc->init_cmds.is_waiting = 1; 3483 mrioc->init_cmds.callback = NULL; 3484 init_completion(&mrioc->init_cmds.done); 3485 } 3486 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3487 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3488 3489 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3490 if (retval) { 3491 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3492 goto out_unlock; 3493 } 3494 if (async) { 3495 mutex_unlock(&mrioc->init_cmds.mutex); 3496 goto out; 3497 } 3498 3499 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3500 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3501 ioc_err(mrioc, "port enable timed out\n"); 3502 retval = -1; 3503 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3504 goto out_unlock; 3505 } 3506 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3507 3508 out_unlock: 3509 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3510 mutex_unlock(&mrioc->init_cmds.mutex); 3511 out: 3512 return retval; 3513 } 3514 3515 /* Protocol type to name mapper structure */ 3516 static const struct { 3517 u8 protocol; 3518 char *name; 3519 } mpi3mr_protocols[] = { 3520 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3521 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3522 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3523 }; 3524 3525 /* Capability to name mapper structure*/ 3526 static const struct { 3527 u32 capability; 3528 char *name; 3529 } mpi3mr_capabilities[] = { 3530 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" }, 3531 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" }, 3532 }; 3533 3534 /** 3535 * mpi3mr_print_ioc_info - Display controller information 3536 * @mrioc: Adapter instance reference 3537 * 3538 * Display controller personalit, capability, supported 3539 * protocols etc. 3540 * 3541 * Return: Nothing 3542 */ 3543 static void 3544 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 3545 { 3546 int i = 0, bytes_written = 0; 3547 char personality[16]; 3548 char protocol[50] = {0}; 3549 char capabilities[100] = {0}; 3550 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 3551 3552 switch (mrioc->facts.personality) { 3553 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 3554 strncpy(personality, "Enhanced HBA", sizeof(personality)); 3555 break; 3556 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 3557 strncpy(personality, "RAID", sizeof(personality)); 3558 break; 3559 default: 3560 strncpy(personality, "Unknown", sizeof(personality)); 3561 break; 3562 } 3563 3564 ioc_info(mrioc, "Running in %s Personality", personality); 3565 3566 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 3567 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 3568 fwver->ph_minor, fwver->cust_id, fwver->build_num); 3569 3570 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 3571 if (mrioc->facts.protocol_flags & 3572 mpi3mr_protocols[i].protocol) { 3573 bytes_written += scnprintf(protocol + bytes_written, 3574 sizeof(protocol) - bytes_written, "%s%s", 3575 bytes_written ? "," : "", 3576 mpi3mr_protocols[i].name); 3577 } 3578 } 3579 3580 bytes_written = 0; 3581 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 3582 if (mrioc->facts.protocol_flags & 3583 mpi3mr_capabilities[i].capability) { 3584 bytes_written += scnprintf(capabilities + bytes_written, 3585 sizeof(capabilities) - bytes_written, "%s%s", 3586 bytes_written ? "," : "", 3587 mpi3mr_capabilities[i].name); 3588 } 3589 } 3590 3591 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 3592 protocol, capabilities); 3593 } 3594 3595 /** 3596 * mpi3mr_cleanup_resources - Free PCI resources 3597 * @mrioc: Adapter instance reference 3598 * 3599 * Unmap PCI device memory and disable PCI device. 3600 * 3601 * Return: 0 on success and non-zero on failure. 3602 */ 3603 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 3604 { 3605 struct pci_dev *pdev = mrioc->pdev; 3606 3607 mpi3mr_cleanup_isr(mrioc); 3608 3609 if (mrioc->sysif_regs) { 3610 iounmap((void __iomem *)mrioc->sysif_regs); 3611 mrioc->sysif_regs = NULL; 3612 } 3613 3614 if (pci_is_enabled(pdev)) { 3615 if (mrioc->bars) 3616 pci_release_selected_regions(pdev, mrioc->bars); 3617 pci_disable_device(pdev); 3618 } 3619 } 3620 3621 /** 3622 * mpi3mr_setup_resources - Enable PCI resources 3623 * @mrioc: Adapter instance reference 3624 * 3625 * Enable PCI device memory, MSI-x registers and set DMA mask. 3626 * 3627 * Return: 0 on success and non-zero on failure. 3628 */ 3629 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 3630 { 3631 struct pci_dev *pdev = mrioc->pdev; 3632 u32 memap_sz = 0; 3633 int i, retval = 0, capb = 0; 3634 u16 message_control; 3635 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 3636 (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) && 3637 (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 3638 3639 if (pci_enable_device_mem(pdev)) { 3640 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 3641 retval = -ENODEV; 3642 goto out_failed; 3643 } 3644 3645 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 3646 if (!capb) { 3647 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 3648 retval = -ENODEV; 3649 goto out_failed; 3650 } 3651 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3652 3653 if (pci_request_selected_regions(pdev, mrioc->bars, 3654 mrioc->driver_name)) { 3655 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 3656 retval = -ENODEV; 3657 goto out_failed; 3658 } 3659 3660 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 3661 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3662 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 3663 memap_sz = pci_resource_len(pdev, i); 3664 mrioc->sysif_regs = 3665 ioremap(mrioc->sysif_regs_phys, memap_sz); 3666 break; 3667 } 3668 } 3669 3670 pci_set_master(pdev); 3671 3672 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 3673 if (retval) { 3674 if (dma_mask != DMA_BIT_MASK(32)) { 3675 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 3676 dma_mask = DMA_BIT_MASK(32); 3677 retval = dma_set_mask_and_coherent(&pdev->dev, 3678 dma_mask); 3679 } 3680 if (retval) { 3681 mrioc->dma_mask = 0; 3682 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 3683 goto out_failed; 3684 } 3685 } 3686 mrioc->dma_mask = dma_mask; 3687 3688 if (!mrioc->sysif_regs) { 3689 ioc_err(mrioc, 3690 "Unable to map adapter memory or resource not found\n"); 3691 retval = -EINVAL; 3692 goto out_failed; 3693 } 3694 3695 pci_read_config_word(pdev, capb + 2, &message_control); 3696 mrioc->msix_count = (message_control & 0x3FF) + 1; 3697 3698 pci_save_state(pdev); 3699 3700 pci_set_drvdata(pdev, mrioc->shost); 3701 3702 mpi3mr_ioc_disable_intr(mrioc); 3703 3704 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 3705 (unsigned long long)mrioc->sysif_regs_phys, 3706 mrioc->sysif_regs, memap_sz); 3707 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 3708 mrioc->msix_count); 3709 3710 if (!reset_devices && poll_queues > 0) 3711 mrioc->requested_poll_qcount = min_t(int, poll_queues, 3712 mrioc->msix_count - 2); 3713 return retval; 3714 3715 out_failed: 3716 mpi3mr_cleanup_resources(mrioc); 3717 return retval; 3718 } 3719 3720 /** 3721 * mpi3mr_enable_events - Enable required events 3722 * @mrioc: Adapter instance reference 3723 * 3724 * This routine unmasks the events required by the driver by 3725 * sennding appropriate event mask bitmapt through an event 3726 * notification request. 3727 * 3728 * Return: 0 on success and non-zero on failure. 3729 */ 3730 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 3731 { 3732 int retval = 0; 3733 u32 i; 3734 3735 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3736 mrioc->event_masks[i] = -1; 3737 3738 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 3739 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 3740 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 3741 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 3742 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED); 3743 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 3744 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 3745 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 3746 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 3747 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 3748 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 3749 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 3750 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 3751 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 3752 3753 retval = mpi3mr_issue_event_notification(mrioc); 3754 if (retval) 3755 ioc_err(mrioc, "failed to issue event notification %d\n", 3756 retval); 3757 return retval; 3758 } 3759 3760 /** 3761 * mpi3mr_init_ioc - Initialize the controller 3762 * @mrioc: Adapter instance reference 3763 * 3764 * This the controller initialization routine, executed either 3765 * after soft reset or from pci probe callback. 3766 * Setup the required resources, memory map the controller 3767 * registers, create admin and operational reply queue pairs, 3768 * allocate required memory for reply pool, sense buffer pool, 3769 * issue IOC init request to the firmware, unmask the events and 3770 * issue port enable to discover SAS/SATA/NVMe devies and RAID 3771 * volumes. 3772 * 3773 * Return: 0 on success and non-zero on failure. 3774 */ 3775 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 3776 { 3777 int retval = 0; 3778 u8 retry = 0; 3779 struct mpi3_ioc_facts_data facts_data; 3780 u32 sz; 3781 3782 retry_init: 3783 retval = mpi3mr_bring_ioc_ready(mrioc); 3784 if (retval) { 3785 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 3786 retval); 3787 goto out_failed_noretry; 3788 } 3789 3790 retval = mpi3mr_setup_isr(mrioc, 1); 3791 if (retval) { 3792 ioc_err(mrioc, "Failed to setup ISR error %d\n", 3793 retval); 3794 goto out_failed_noretry; 3795 } 3796 3797 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3798 if (retval) { 3799 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 3800 retval); 3801 goto out_failed; 3802 } 3803 3804 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 3805 3806 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group; 3807 atomic_set(&mrioc->pend_large_data_sz, 0); 3808 3809 if (reset_devices) 3810 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 3811 MPI3MR_HOST_IOS_KDUMP); 3812 3813 if (!(mrioc->facts.ioc_capabilities & 3814 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) { 3815 mrioc->sas_transport_enabled = 1; 3816 mrioc->scsi_device_channel = 1; 3817 mrioc->shost->max_channel = 1; 3818 mrioc->shost->transportt = mpi3mr_transport_template; 3819 } 3820 3821 mrioc->reply_sz = mrioc->facts.reply_sz; 3822 3823 retval = mpi3mr_check_reset_dma_mask(mrioc); 3824 if (retval) { 3825 ioc_err(mrioc, "Resetting dma mask failed %d\n", 3826 retval); 3827 goto out_failed_noretry; 3828 } 3829 3830 mpi3mr_print_ioc_info(mrioc); 3831 3832 dprint_init(mrioc, "allocating config page buffers\n"); 3833 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev, 3834 MPI3MR_DEFAULT_CFG_PAGE_SZ, &mrioc->cfg_page_dma, GFP_KERNEL); 3835 if (!mrioc->cfg_page) 3836 goto out_failed_noretry; 3837 3838 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ; 3839 3840 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 3841 if (retval) { 3842 ioc_err(mrioc, 3843 "%s :Failed to allocated reply sense buffers %d\n", 3844 __func__, retval); 3845 goto out_failed_noretry; 3846 } 3847 3848 retval = mpi3mr_alloc_chain_bufs(mrioc); 3849 if (retval) { 3850 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 3851 retval); 3852 goto out_failed_noretry; 3853 } 3854 3855 retval = mpi3mr_issue_iocinit(mrioc); 3856 if (retval) { 3857 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 3858 retval); 3859 goto out_failed; 3860 } 3861 3862 retval = mpi3mr_print_pkg_ver(mrioc); 3863 if (retval) { 3864 ioc_err(mrioc, "failed to get package version\n"); 3865 goto out_failed; 3866 } 3867 3868 retval = mpi3mr_setup_isr(mrioc, 0); 3869 if (retval) { 3870 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 3871 retval); 3872 goto out_failed_noretry; 3873 } 3874 3875 retval = mpi3mr_create_op_queues(mrioc); 3876 if (retval) { 3877 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 3878 retval); 3879 goto out_failed; 3880 } 3881 3882 if (!mrioc->pel_seqnum_virt) { 3883 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n"); 3884 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 3885 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 3886 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 3887 GFP_KERNEL); 3888 if (!mrioc->pel_seqnum_virt) { 3889 retval = -ENOMEM; 3890 goto out_failed_noretry; 3891 } 3892 } 3893 3894 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) { 3895 dprint_init(mrioc, "allocating memory for throttle groups\n"); 3896 sz = sizeof(struct mpi3mr_throttle_group_info); 3897 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL); 3898 if (!mrioc->throttle_groups) 3899 goto out_failed_noretry; 3900 } 3901 3902 retval = mpi3mr_enable_events(mrioc); 3903 if (retval) { 3904 ioc_err(mrioc, "failed to enable events %d\n", 3905 retval); 3906 goto out_failed; 3907 } 3908 3909 ioc_info(mrioc, "controller initialization completed successfully\n"); 3910 return retval; 3911 out_failed: 3912 if (retry < 2) { 3913 retry++; 3914 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 3915 retry); 3916 mpi3mr_memset_buffers(mrioc); 3917 goto retry_init; 3918 } 3919 out_failed_noretry: 3920 ioc_err(mrioc, "controller initialization failed\n"); 3921 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 3922 MPI3MR_RESET_FROM_CTLR_CLEANUP); 3923 mrioc->unrecoverable = 1; 3924 return retval; 3925 } 3926 3927 /** 3928 * mpi3mr_reinit_ioc - Re-Initialize the controller 3929 * @mrioc: Adapter instance reference 3930 * @is_resume: Called from resume or reset path 3931 * 3932 * This the controller re-initialization routine, executed from 3933 * the soft reset handler or resume callback. Creates 3934 * operational reply queue pairs, allocate required memory for 3935 * reply pool, sense buffer pool, issue IOC init request to the 3936 * firmware, unmask the events and issue port enable to discover 3937 * SAS/SATA/NVMe devices and RAID volumes. 3938 * 3939 * Return: 0 on success and non-zero on failure. 3940 */ 3941 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 3942 { 3943 int retval = 0; 3944 u8 retry = 0; 3945 struct mpi3_ioc_facts_data facts_data; 3946 u32 pe_timeout, ioc_status; 3947 3948 retry_init: 3949 pe_timeout = 3950 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL); 3951 3952 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 3953 retval = mpi3mr_bring_ioc_ready(mrioc); 3954 if (retval) { 3955 ioc_err(mrioc, "failed to bring to ready state\n"); 3956 goto out_failed_noretry; 3957 } 3958 3959 if (is_resume) { 3960 dprint_reset(mrioc, "setting up single ISR\n"); 3961 retval = mpi3mr_setup_isr(mrioc, 1); 3962 if (retval) { 3963 ioc_err(mrioc, "failed to setup ISR\n"); 3964 goto out_failed_noretry; 3965 } 3966 } else 3967 mpi3mr_ioc_enable_intr(mrioc); 3968 3969 dprint_reset(mrioc, "getting ioc_facts\n"); 3970 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3971 if (retval) { 3972 ioc_err(mrioc, "failed to get ioc_facts\n"); 3973 goto out_failed; 3974 } 3975 3976 dprint_reset(mrioc, "validating ioc_facts\n"); 3977 retval = mpi3mr_revalidate_factsdata(mrioc); 3978 if (retval) { 3979 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 3980 goto out_failed_noretry; 3981 } 3982 3983 mpi3mr_print_ioc_info(mrioc); 3984 3985 dprint_reset(mrioc, "sending ioc_init\n"); 3986 retval = mpi3mr_issue_iocinit(mrioc); 3987 if (retval) { 3988 ioc_err(mrioc, "failed to send ioc_init\n"); 3989 goto out_failed; 3990 } 3991 3992 dprint_reset(mrioc, "getting package version\n"); 3993 retval = mpi3mr_print_pkg_ver(mrioc); 3994 if (retval) { 3995 ioc_err(mrioc, "failed to get package version\n"); 3996 goto out_failed; 3997 } 3998 3999 if (is_resume) { 4000 dprint_reset(mrioc, "setting up multiple ISR\n"); 4001 retval = mpi3mr_setup_isr(mrioc, 0); 4002 if (retval) { 4003 ioc_err(mrioc, "failed to re-setup ISR\n"); 4004 goto out_failed_noretry; 4005 } 4006 } 4007 4008 dprint_reset(mrioc, "creating operational queue pairs\n"); 4009 retval = mpi3mr_create_op_queues(mrioc); 4010 if (retval) { 4011 ioc_err(mrioc, "failed to create operational queue pairs\n"); 4012 goto out_failed; 4013 } 4014 4015 if (!mrioc->pel_seqnum_virt) { 4016 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n"); 4017 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq); 4018 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev, 4019 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma, 4020 GFP_KERNEL); 4021 if (!mrioc->pel_seqnum_virt) { 4022 retval = -ENOMEM; 4023 goto out_failed_noretry; 4024 } 4025 } 4026 4027 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 4028 ioc_err(mrioc, 4029 "cannot create minimum number of operational queues expected:%d created:%d\n", 4030 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 4031 goto out_failed_noretry; 4032 } 4033 4034 dprint_reset(mrioc, "enabling events\n"); 4035 retval = mpi3mr_enable_events(mrioc); 4036 if (retval) { 4037 ioc_err(mrioc, "failed to enable events\n"); 4038 goto out_failed; 4039 } 4040 4041 mrioc->device_refresh_on = 1; 4042 mpi3mr_add_event_wait_for_device_refresh(mrioc); 4043 4044 ioc_info(mrioc, "sending port enable\n"); 4045 retval = mpi3mr_issue_port_enable(mrioc, 1); 4046 if (retval) { 4047 ioc_err(mrioc, "failed to issue port enable\n"); 4048 goto out_failed; 4049 } 4050 do { 4051 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL); 4052 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED) 4053 break; 4054 if (!pci_device_is_present(mrioc->pdev)) 4055 mrioc->unrecoverable = 1; 4056 if (mrioc->unrecoverable) { 4057 retval = -1; 4058 goto out_failed_noretry; 4059 } 4060 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4061 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 4062 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 4063 mpi3mr_print_fault_info(mrioc); 4064 mrioc->init_cmds.is_waiting = 0; 4065 mrioc->init_cmds.callback = NULL; 4066 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4067 goto out_failed; 4068 } 4069 } while (--pe_timeout); 4070 4071 if (!pe_timeout) { 4072 ioc_err(mrioc, "port enable timed out\n"); 4073 mpi3mr_check_rh_fault_ioc(mrioc, 4074 MPI3MR_RESET_FROM_PE_TIMEOUT); 4075 mrioc->init_cmds.is_waiting = 0; 4076 mrioc->init_cmds.callback = NULL; 4077 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 4078 goto out_failed; 4079 } else if (mrioc->scan_failed) { 4080 ioc_err(mrioc, 4081 "port enable failed with status=0x%04x\n", 4082 mrioc->scan_failed); 4083 } else 4084 ioc_info(mrioc, "port enable completed successfully\n"); 4085 4086 ioc_info(mrioc, "controller %s completed successfully\n", 4087 (is_resume)?"resume":"re-initialization"); 4088 return retval; 4089 out_failed: 4090 if (retry < 2) { 4091 retry++; 4092 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 4093 (is_resume)?"resume":"re-initialization", retry); 4094 mpi3mr_memset_buffers(mrioc); 4095 goto retry_init; 4096 } 4097 out_failed_noretry: 4098 ioc_err(mrioc, "controller %s is failed\n", 4099 (is_resume)?"resume":"re-initialization"); 4100 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 4101 MPI3MR_RESET_FROM_CTLR_CLEANUP); 4102 mrioc->unrecoverable = 1; 4103 return retval; 4104 } 4105 4106 /** 4107 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 4108 * segments 4109 * @mrioc: Adapter instance reference 4110 * @qidx: Operational reply queue index 4111 * 4112 * Return: Nothing. 4113 */ 4114 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4115 { 4116 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 4117 struct segments *segments; 4118 int i, size; 4119 4120 if (!op_reply_q->q_segments) 4121 return; 4122 4123 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 4124 segments = op_reply_q->q_segments; 4125 for (i = 0; i < op_reply_q->num_segments; i++) 4126 memset(segments[i].segment, 0, size); 4127 } 4128 4129 /** 4130 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 4131 * segments 4132 * @mrioc: Adapter instance reference 4133 * @qidx: Operational request queue index 4134 * 4135 * Return: Nothing. 4136 */ 4137 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 4138 { 4139 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 4140 struct segments *segments; 4141 int i, size; 4142 4143 if (!op_req_q->q_segments) 4144 return; 4145 4146 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 4147 segments = op_req_q->q_segments; 4148 for (i = 0; i < op_req_q->num_segments; i++) 4149 memset(segments[i].segment, 0, size); 4150 } 4151 4152 /** 4153 * mpi3mr_memset_buffers - memset memory for a controller 4154 * @mrioc: Adapter instance reference 4155 * 4156 * clear all the memory allocated for a controller, typically 4157 * called post reset to reuse the memory allocated during the 4158 * controller init. 4159 * 4160 * Return: Nothing. 4161 */ 4162 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 4163 { 4164 u16 i; 4165 struct mpi3mr_throttle_group_info *tg; 4166 4167 mrioc->change_count = 0; 4168 mrioc->active_poll_qcount = 0; 4169 mrioc->default_qcount = 0; 4170 if (mrioc->admin_req_base) 4171 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 4172 if (mrioc->admin_reply_base) 4173 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 4174 4175 if (mrioc->init_cmds.reply) { 4176 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 4177 memset(mrioc->bsg_cmds.reply, 0, 4178 sizeof(*mrioc->bsg_cmds.reply)); 4179 memset(mrioc->host_tm_cmds.reply, 0, 4180 sizeof(*mrioc->host_tm_cmds.reply)); 4181 memset(mrioc->pel_cmds.reply, 0, 4182 sizeof(*mrioc->pel_cmds.reply)); 4183 memset(mrioc->pel_abort_cmd.reply, 0, 4184 sizeof(*mrioc->pel_abort_cmd.reply)); 4185 memset(mrioc->transport_cmds.reply, 0, 4186 sizeof(*mrioc->transport_cmds.reply)); 4187 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 4188 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 4189 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 4190 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 4191 memset(mrioc->evtack_cmds[i].reply, 0, 4192 sizeof(*mrioc->evtack_cmds[i].reply)); 4193 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz); 4194 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz); 4195 memset(mrioc->evtack_cmds_bitmap, 0, 4196 mrioc->evtack_cmds_bitmap_sz); 4197 } 4198 4199 for (i = 0; i < mrioc->num_queues; i++) { 4200 mrioc->op_reply_qinfo[i].qid = 0; 4201 mrioc->op_reply_qinfo[i].ci = 0; 4202 mrioc->op_reply_qinfo[i].num_replies = 0; 4203 mrioc->op_reply_qinfo[i].ephase = 0; 4204 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 4205 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 4206 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 4207 4208 mrioc->req_qinfo[i].ci = 0; 4209 mrioc->req_qinfo[i].pi = 0; 4210 mrioc->req_qinfo[i].num_requests = 0; 4211 mrioc->req_qinfo[i].qid = 0; 4212 mrioc->req_qinfo[i].reply_qid = 0; 4213 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 4214 mpi3mr_memset_op_req_q_buffers(mrioc, i); 4215 } 4216 4217 atomic_set(&mrioc->pend_large_data_sz, 0); 4218 if (mrioc->throttle_groups) { 4219 tg = mrioc->throttle_groups; 4220 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) { 4221 tg->id = 0; 4222 tg->fw_qd = 0; 4223 tg->modified_qd = 0; 4224 tg->io_divert = 0; 4225 tg->need_qd_reduction = 0; 4226 tg->high = 0; 4227 tg->low = 0; 4228 tg->qd_reduction = 0; 4229 atomic_set(&tg->pend_large_data_sz, 0); 4230 } 4231 } 4232 } 4233 4234 /** 4235 * mpi3mr_free_mem - Free memory allocated for a controller 4236 * @mrioc: Adapter instance reference 4237 * 4238 * Free all the memory allocated for a controller. 4239 * 4240 * Return: Nothing. 4241 */ 4242 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 4243 { 4244 u16 i; 4245 struct mpi3mr_intr_info *intr_info; 4246 4247 mpi3mr_free_enclosure_list(mrioc); 4248 4249 if (mrioc->sense_buf_pool) { 4250 if (mrioc->sense_buf) 4251 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4252 mrioc->sense_buf_dma); 4253 dma_pool_destroy(mrioc->sense_buf_pool); 4254 mrioc->sense_buf = NULL; 4255 mrioc->sense_buf_pool = NULL; 4256 } 4257 if (mrioc->sense_buf_q_pool) { 4258 if (mrioc->sense_buf_q) 4259 dma_pool_free(mrioc->sense_buf_q_pool, 4260 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4261 dma_pool_destroy(mrioc->sense_buf_q_pool); 4262 mrioc->sense_buf_q = NULL; 4263 mrioc->sense_buf_q_pool = NULL; 4264 } 4265 4266 if (mrioc->reply_buf_pool) { 4267 if (mrioc->reply_buf) 4268 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4269 mrioc->reply_buf_dma); 4270 dma_pool_destroy(mrioc->reply_buf_pool); 4271 mrioc->reply_buf = NULL; 4272 mrioc->reply_buf_pool = NULL; 4273 } 4274 if (mrioc->reply_free_q_pool) { 4275 if (mrioc->reply_free_q) 4276 dma_pool_free(mrioc->reply_free_q_pool, 4277 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4278 dma_pool_destroy(mrioc->reply_free_q_pool); 4279 mrioc->reply_free_q = NULL; 4280 mrioc->reply_free_q_pool = NULL; 4281 } 4282 4283 for (i = 0; i < mrioc->num_op_req_q; i++) 4284 mpi3mr_free_op_req_q_segments(mrioc, i); 4285 4286 for (i = 0; i < mrioc->num_op_reply_q; i++) 4287 mpi3mr_free_op_reply_q_segments(mrioc, i); 4288 4289 for (i = 0; i < mrioc->intr_info_count; i++) { 4290 intr_info = mrioc->intr_info + i; 4291 intr_info->op_reply_q = NULL; 4292 } 4293 4294 kfree(mrioc->req_qinfo); 4295 mrioc->req_qinfo = NULL; 4296 mrioc->num_op_req_q = 0; 4297 4298 kfree(mrioc->op_reply_qinfo); 4299 mrioc->op_reply_qinfo = NULL; 4300 mrioc->num_op_reply_q = 0; 4301 4302 kfree(mrioc->init_cmds.reply); 4303 mrioc->init_cmds.reply = NULL; 4304 4305 kfree(mrioc->bsg_cmds.reply); 4306 mrioc->bsg_cmds.reply = NULL; 4307 4308 kfree(mrioc->host_tm_cmds.reply); 4309 mrioc->host_tm_cmds.reply = NULL; 4310 4311 kfree(mrioc->pel_cmds.reply); 4312 mrioc->pel_cmds.reply = NULL; 4313 4314 kfree(mrioc->pel_abort_cmd.reply); 4315 mrioc->pel_abort_cmd.reply = NULL; 4316 4317 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4318 kfree(mrioc->evtack_cmds[i].reply); 4319 mrioc->evtack_cmds[i].reply = NULL; 4320 } 4321 4322 kfree(mrioc->removepend_bitmap); 4323 mrioc->removepend_bitmap = NULL; 4324 4325 kfree(mrioc->devrem_bitmap); 4326 mrioc->devrem_bitmap = NULL; 4327 4328 kfree(mrioc->evtack_cmds_bitmap); 4329 mrioc->evtack_cmds_bitmap = NULL; 4330 4331 kfree(mrioc->chain_bitmap); 4332 mrioc->chain_bitmap = NULL; 4333 4334 kfree(mrioc->transport_cmds.reply); 4335 mrioc->transport_cmds.reply = NULL; 4336 4337 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4338 kfree(mrioc->dev_rmhs_cmds[i].reply); 4339 mrioc->dev_rmhs_cmds[i].reply = NULL; 4340 } 4341 4342 if (mrioc->chain_buf_pool) { 4343 for (i = 0; i < mrioc->chain_buf_count; i++) { 4344 if (mrioc->chain_sgl_list[i].addr) { 4345 dma_pool_free(mrioc->chain_buf_pool, 4346 mrioc->chain_sgl_list[i].addr, 4347 mrioc->chain_sgl_list[i].dma_addr); 4348 mrioc->chain_sgl_list[i].addr = NULL; 4349 } 4350 } 4351 dma_pool_destroy(mrioc->chain_buf_pool); 4352 mrioc->chain_buf_pool = NULL; 4353 } 4354 4355 kfree(mrioc->chain_sgl_list); 4356 mrioc->chain_sgl_list = NULL; 4357 4358 if (mrioc->admin_reply_base) { 4359 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4360 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4361 mrioc->admin_reply_base = NULL; 4362 } 4363 if (mrioc->admin_req_base) { 4364 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4365 mrioc->admin_req_base, mrioc->admin_req_dma); 4366 mrioc->admin_req_base = NULL; 4367 } 4368 4369 if (mrioc->pel_seqnum_virt) { 4370 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz, 4371 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma); 4372 mrioc->pel_seqnum_virt = NULL; 4373 } 4374 4375 kfree(mrioc->logdata_buf); 4376 mrioc->logdata_buf = NULL; 4377 4378 } 4379 4380 /** 4381 * mpi3mr_issue_ioc_shutdown - shutdown controller 4382 * @mrioc: Adapter instance reference 4383 * 4384 * Send shutodwn notification to the controller and wait for the 4385 * shutdown_timeout for it to be completed. 4386 * 4387 * Return: Nothing. 4388 */ 4389 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4390 { 4391 u32 ioc_config, ioc_status; 4392 u8 retval = 1; 4393 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4394 4395 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4396 if (mrioc->unrecoverable) { 4397 ioc_warn(mrioc, 4398 "IOC is unrecoverable shutdown is not issued\n"); 4399 return; 4400 } 4401 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4402 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4403 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4404 ioc_info(mrioc, "shutdown already in progress\n"); 4405 return; 4406 } 4407 4408 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4409 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4410 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4411 4412 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4413 4414 if (mrioc->facts.shutdown_timeout) 4415 timeout = mrioc->facts.shutdown_timeout * 10; 4416 4417 do { 4418 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4419 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4420 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4421 retval = 0; 4422 break; 4423 } 4424 msleep(100); 4425 } while (--timeout); 4426 4427 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4428 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4429 4430 if (retval) { 4431 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4432 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4433 ioc_warn(mrioc, 4434 "shutdown still in progress after timeout\n"); 4435 } 4436 4437 ioc_info(mrioc, 4438 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 4439 (!retval) ? "successful" : "failed", ioc_status, 4440 ioc_config); 4441 } 4442 4443 /** 4444 * mpi3mr_cleanup_ioc - Cleanup controller 4445 * @mrioc: Adapter instance reference 4446 * 4447 * controller cleanup handler, Message unit reset or soft reset 4448 * and shutdown notification is issued to the controller. 4449 * 4450 * Return: Nothing. 4451 */ 4452 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4453 { 4454 enum mpi3mr_iocstate ioc_state; 4455 4456 dprint_exit(mrioc, "cleaning up the controller\n"); 4457 mpi3mr_ioc_disable_intr(mrioc); 4458 4459 ioc_state = mpi3mr_get_iocstate(mrioc); 4460 4461 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) && 4462 (ioc_state == MRIOC_STATE_READY)) { 4463 if (mpi3mr_issue_and_process_mur(mrioc, 4464 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 4465 mpi3mr_issue_reset(mrioc, 4466 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 4467 MPI3MR_RESET_FROM_MUR_FAILURE); 4468 mpi3mr_issue_ioc_shutdown(mrioc); 4469 } 4470 dprint_exit(mrioc, "controller cleanup completed\n"); 4471 } 4472 4473 /** 4474 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 4475 * @mrioc: Adapter instance reference 4476 * @cmdptr: Internal command tracker 4477 * 4478 * Complete an internal driver commands with state indicating it 4479 * is completed due to reset. 4480 * 4481 * Return: Nothing. 4482 */ 4483 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 4484 struct mpi3mr_drv_cmd *cmdptr) 4485 { 4486 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4487 cmdptr->state |= MPI3MR_CMD_RESET; 4488 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4489 if (cmdptr->is_waiting) { 4490 complete(&cmdptr->done); 4491 cmdptr->is_waiting = 0; 4492 } else if (cmdptr->callback) 4493 cmdptr->callback(mrioc, cmdptr); 4494 } 4495 } 4496 4497 /** 4498 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 4499 * @mrioc: Adapter instance reference 4500 * 4501 * Flush all internal driver commands post reset 4502 * 4503 * Return: Nothing. 4504 */ 4505 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 4506 { 4507 struct mpi3mr_drv_cmd *cmdptr; 4508 u8 i; 4509 4510 cmdptr = &mrioc->init_cmds; 4511 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4512 4513 cmdptr = &mrioc->cfg_cmds; 4514 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4515 4516 cmdptr = &mrioc->bsg_cmds; 4517 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4518 cmdptr = &mrioc->host_tm_cmds; 4519 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4520 4521 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4522 cmdptr = &mrioc->dev_rmhs_cmds[i]; 4523 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4524 } 4525 4526 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4527 cmdptr = &mrioc->evtack_cmds[i]; 4528 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4529 } 4530 4531 cmdptr = &mrioc->pel_cmds; 4532 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4533 4534 cmdptr = &mrioc->pel_abort_cmd; 4535 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4536 4537 cmdptr = &mrioc->transport_cmds; 4538 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4539 } 4540 4541 /** 4542 * mpi3mr_pel_wait_post - Issue PEL Wait 4543 * @mrioc: Adapter instance reference 4544 * @drv_cmd: Internal command tracker 4545 * 4546 * Issue PEL Wait MPI request through admin queue and return. 4547 * 4548 * Return: Nothing. 4549 */ 4550 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc, 4551 struct mpi3mr_drv_cmd *drv_cmd) 4552 { 4553 struct mpi3_pel_req_action_wait pel_wait; 4554 4555 mrioc->pel_abort_requested = false; 4556 4557 memset(&pel_wait, 0, sizeof(pel_wait)); 4558 drv_cmd->state = MPI3MR_CMD_PENDING; 4559 drv_cmd->is_waiting = 0; 4560 drv_cmd->callback = mpi3mr_pel_wait_complete; 4561 drv_cmd->ioc_status = 0; 4562 drv_cmd->ioc_loginfo = 0; 4563 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4564 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4565 pel_wait.action = MPI3_PEL_ACTION_WAIT; 4566 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum); 4567 pel_wait.locale = cpu_to_le16(mrioc->pel_locale); 4568 pel_wait.class = cpu_to_le16(mrioc->pel_class); 4569 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT; 4570 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n", 4571 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale); 4572 4573 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) { 4574 dprint_bsg_err(mrioc, 4575 "Issuing PELWait: Admin post failed\n"); 4576 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4577 drv_cmd->callback = NULL; 4578 drv_cmd->retry_count = 0; 4579 mrioc->pel_enabled = false; 4580 } 4581 } 4582 4583 /** 4584 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number 4585 * @mrioc: Adapter instance reference 4586 * @drv_cmd: Internal command tracker 4587 * 4588 * Issue PEL get sequence number MPI request through admin queue 4589 * and return. 4590 * 4591 * Return: 0 on success, non-zero on failure. 4592 */ 4593 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 4594 struct mpi3mr_drv_cmd *drv_cmd) 4595 { 4596 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req; 4597 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 4598 int retval = 0; 4599 4600 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req)); 4601 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING; 4602 mrioc->pel_cmds.is_waiting = 0; 4603 mrioc->pel_cmds.ioc_status = 0; 4604 mrioc->pel_cmds.ioc_loginfo = 0; 4605 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete; 4606 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT); 4607 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG; 4608 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM; 4609 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags, 4610 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma); 4611 4612 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req, 4613 sizeof(pel_getseq_req), 0); 4614 if (retval) { 4615 if (drv_cmd) { 4616 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4617 drv_cmd->callback = NULL; 4618 drv_cmd->retry_count = 0; 4619 } 4620 mrioc->pel_enabled = false; 4621 } 4622 4623 return retval; 4624 } 4625 4626 /** 4627 * mpi3mr_pel_wait_complete - PELWait Completion callback 4628 * @mrioc: Adapter instance reference 4629 * @drv_cmd: Internal command tracker 4630 * 4631 * This is a callback handler for the PELWait request and 4632 * firmware completes a PELWait request when it is aborted or a 4633 * new PEL entry is available. This sends AEN to the application 4634 * and if the PELwait completion is not due to PELAbort then 4635 * this will send a request for new PEL Sequence number 4636 * 4637 * Return: Nothing. 4638 */ 4639 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc, 4640 struct mpi3mr_drv_cmd *drv_cmd) 4641 { 4642 struct mpi3_pel_reply *pel_reply = NULL; 4643 u16 ioc_status, pe_log_status; 4644 bool do_retry = false; 4645 4646 if (drv_cmd->state & MPI3MR_CMD_RESET) 4647 goto cleanup_drv_cmd; 4648 4649 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4650 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4651 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 4652 __func__, ioc_status, drv_cmd->ioc_loginfo); 4653 dprint_bsg_err(mrioc, 4654 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4655 ioc_status, drv_cmd->ioc_loginfo); 4656 do_retry = true; 4657 } 4658 4659 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4660 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4661 4662 if (!pel_reply) { 4663 dprint_bsg_err(mrioc, 4664 "pel_wait: failed due to no reply\n"); 4665 goto out_failed; 4666 } 4667 4668 pe_log_status = le16_to_cpu(pel_reply->pe_log_status); 4669 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) && 4670 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) { 4671 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n", 4672 __func__, pe_log_status); 4673 dprint_bsg_err(mrioc, 4674 "pel_wait: failed due to pel_log_status(0x%04x)\n", 4675 pe_log_status); 4676 do_retry = true; 4677 } 4678 4679 if (do_retry) { 4680 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4681 drv_cmd->retry_count++; 4682 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n", 4683 drv_cmd->retry_count); 4684 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4685 return; 4686 } 4687 dprint_bsg_err(mrioc, 4688 "pel_wait: failed after all retries(%d)\n", 4689 drv_cmd->retry_count); 4690 goto out_failed; 4691 } 4692 atomic64_inc(&event_counter); 4693 if (!mrioc->pel_abort_requested) { 4694 mrioc->pel_cmds.retry_count = 0; 4695 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds); 4696 } 4697 4698 return; 4699 out_failed: 4700 mrioc->pel_enabled = false; 4701 cleanup_drv_cmd: 4702 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4703 drv_cmd->callback = NULL; 4704 drv_cmd->retry_count = 0; 4705 } 4706 4707 /** 4708 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback 4709 * @mrioc: Adapter instance reference 4710 * @drv_cmd: Internal command tracker 4711 * 4712 * This is a callback handler for the PEL get sequence number 4713 * request and a new PEL wait request will be issued to the 4714 * firmware from this 4715 * 4716 * Return: Nothing. 4717 */ 4718 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 4719 struct mpi3mr_drv_cmd *drv_cmd) 4720 { 4721 struct mpi3_pel_reply *pel_reply = NULL; 4722 struct mpi3_pel_seq *pel_seqnum_virt; 4723 u16 ioc_status; 4724 bool do_retry = false; 4725 4726 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt; 4727 4728 if (drv_cmd->state & MPI3MR_CMD_RESET) 4729 goto cleanup_drv_cmd; 4730 4731 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 4732 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 4733 dprint_bsg_err(mrioc, 4734 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n", 4735 ioc_status, drv_cmd->ioc_loginfo); 4736 do_retry = true; 4737 } 4738 4739 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID) 4740 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply; 4741 if (!pel_reply) { 4742 dprint_bsg_err(mrioc, 4743 "pel_get_seqnum: failed due to no reply\n"); 4744 goto out_failed; 4745 } 4746 4747 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) { 4748 dprint_bsg_err(mrioc, 4749 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n", 4750 le16_to_cpu(pel_reply->pe_log_status)); 4751 do_retry = true; 4752 } 4753 4754 if (do_retry) { 4755 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) { 4756 drv_cmd->retry_count++; 4757 dprint_bsg_err(mrioc, 4758 "pel_get_seqnum: retrying(%d)\n", 4759 drv_cmd->retry_count); 4760 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd); 4761 return; 4762 } 4763 4764 dprint_bsg_err(mrioc, 4765 "pel_get_seqnum: failed after all retries(%d)\n", 4766 drv_cmd->retry_count); 4767 goto out_failed; 4768 } 4769 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1; 4770 drv_cmd->retry_count = 0; 4771 mpi3mr_pel_wait_post(mrioc, drv_cmd); 4772 4773 return; 4774 out_failed: 4775 mrioc->pel_enabled = false; 4776 cleanup_drv_cmd: 4777 drv_cmd->state = MPI3MR_CMD_NOTUSED; 4778 drv_cmd->callback = NULL; 4779 drv_cmd->retry_count = 0; 4780 } 4781 4782 /** 4783 * mpi3mr_soft_reset_handler - Reset the controller 4784 * @mrioc: Adapter instance reference 4785 * @reset_reason: Reset reason code 4786 * @snapdump: Flag to generate snapdump in firmware or not 4787 * 4788 * This is an handler for recovering controller by issuing soft 4789 * reset are diag fault reset. This is a blocking function and 4790 * when one reset is executed if any other resets they will be 4791 * blocked. All BSG requests will be blocked during the reset. If 4792 * controller reset is successful then the controller will be 4793 * reinitalized, otherwise the controller will be marked as not 4794 * recoverable 4795 * 4796 * In snapdump bit is set, the controller is issued with diag 4797 * fault reset so that the firmware can create a snap dump and 4798 * post that the firmware will result in F000 fault and the 4799 * driver will issue soft reset to recover from that. 4800 * 4801 * Return: 0 on success, non-zero on failure. 4802 */ 4803 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 4804 u32 reset_reason, u8 snapdump) 4805 { 4806 int retval = 0, i; 4807 unsigned long flags; 4808 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 4809 4810 /* Block the reset handler until diag save in progress*/ 4811 dprint_reset(mrioc, 4812 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 4813 mrioc->diagsave_timeout); 4814 while (mrioc->diagsave_timeout) 4815 ssleep(1); 4816 /* 4817 * Block new resets until the currently executing one is finished and 4818 * return the status of the existing reset for all blocked resets 4819 */ 4820 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 4821 if (!mutex_trylock(&mrioc->reset_mutex)) { 4822 ioc_info(mrioc, 4823 "controller reset triggered by %s is blocked due to another reset in progress\n", 4824 mpi3mr_reset_rc_name(reset_reason)); 4825 do { 4826 ssleep(1); 4827 } while (mrioc->reset_in_progress == 1); 4828 ioc_info(mrioc, 4829 "returning previous reset result(%d) for the reset triggered by %s\n", 4830 mrioc->prev_reset_result, 4831 mpi3mr_reset_rc_name(reset_reason)); 4832 return mrioc->prev_reset_result; 4833 } 4834 ioc_info(mrioc, "controller reset is triggered by %s\n", 4835 mpi3mr_reset_rc_name(reset_reason)); 4836 4837 mrioc->device_refresh_on = 0; 4838 mrioc->reset_in_progress = 1; 4839 mrioc->stop_bsgs = 1; 4840 mrioc->prev_reset_result = -1; 4841 4842 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 4843 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 4844 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 4845 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4846 mrioc->event_masks[i] = -1; 4847 4848 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 4849 mpi3mr_issue_event_notification(mrioc); 4850 } 4851 4852 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 4853 4854 mpi3mr_ioc_disable_intr(mrioc); 4855 4856 if (snapdump) { 4857 mpi3mr_set_diagsave(mrioc); 4858 retval = mpi3mr_issue_reset(mrioc, 4859 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4860 if (!retval) { 4861 do { 4862 host_diagnostic = 4863 readl(&mrioc->sysif_regs->host_diagnostic); 4864 if (!(host_diagnostic & 4865 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 4866 break; 4867 msleep(100); 4868 } while (--timeout); 4869 } 4870 } 4871 4872 retval = mpi3mr_issue_reset(mrioc, 4873 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 4874 if (retval) { 4875 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 4876 goto out; 4877 } 4878 if (mrioc->num_io_throttle_group != 4879 mrioc->facts.max_io_throttle_group) { 4880 ioc_err(mrioc, 4881 "max io throttle group doesn't match old(%d), new(%d)\n", 4882 mrioc->num_io_throttle_group, 4883 mrioc->facts.max_io_throttle_group); 4884 retval = -EPERM; 4885 goto out; 4886 } 4887 4888 mpi3mr_flush_delayed_cmd_lists(mrioc); 4889 mpi3mr_flush_drv_cmds(mrioc); 4890 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz); 4891 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz); 4892 memset(mrioc->evtack_cmds_bitmap, 0, mrioc->evtack_cmds_bitmap_sz); 4893 mpi3mr_flush_host_io(mrioc); 4894 mpi3mr_cleanup_fwevt_list(mrioc); 4895 mpi3mr_invalidate_devhandles(mrioc); 4896 mpi3mr_free_enclosure_list(mrioc); 4897 4898 if (mrioc->prepare_for_reset) { 4899 mrioc->prepare_for_reset = 0; 4900 mrioc->prepare_for_reset_timeout_counter = 0; 4901 } 4902 mpi3mr_memset_buffers(mrioc); 4903 retval = mpi3mr_reinit_ioc(mrioc, 0); 4904 if (retval) { 4905 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 4906 mrioc->name, reset_reason); 4907 goto out; 4908 } 4909 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME); 4910 4911 out: 4912 if (!retval) { 4913 mrioc->diagsave_timeout = 0; 4914 mrioc->reset_in_progress = 0; 4915 mrioc->pel_abort_requested = 0; 4916 if (mrioc->pel_enabled) { 4917 mrioc->pel_cmds.retry_count = 0; 4918 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds); 4919 } 4920 4921 mrioc->device_refresh_on = 0; 4922 4923 mrioc->ts_update_counter = 0; 4924 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 4925 if (mrioc->watchdog_work_q) 4926 queue_delayed_work(mrioc->watchdog_work_q, 4927 &mrioc->watchdog_work, 4928 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 4929 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 4930 mrioc->stop_bsgs = 0; 4931 if (mrioc->pel_enabled) 4932 atomic64_inc(&event_counter); 4933 } else { 4934 mpi3mr_issue_reset(mrioc, 4935 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4936 mrioc->device_refresh_on = 0; 4937 mrioc->unrecoverable = 1; 4938 mrioc->reset_in_progress = 0; 4939 retval = -1; 4940 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); 4941 } 4942 mrioc->prev_reset_result = retval; 4943 mutex_unlock(&mrioc->reset_mutex); 4944 ioc_info(mrioc, "controller reset is %s\n", 4945 ((retval == 0) ? "successful" : "failed")); 4946 return retval; 4947 } 4948 4949 4950 /** 4951 * mpi3mr_free_config_dma_memory - free memory for config page 4952 * @mrioc: Adapter instance reference 4953 * @mem_desc: memory descriptor structure 4954 * 4955 * Check whether the size of the buffer specified by the memory 4956 * descriptor is greater than the default page size if so then 4957 * free the memory pointed by the descriptor. 4958 * 4959 * Return: Nothing. 4960 */ 4961 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc, 4962 struct dma_memory_desc *mem_desc) 4963 { 4964 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) { 4965 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size, 4966 mem_desc->addr, mem_desc->dma_addr); 4967 mem_desc->addr = NULL; 4968 } 4969 } 4970 4971 /** 4972 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page 4973 * @mrioc: Adapter instance reference 4974 * @mem_desc: Memory descriptor to hold dma memory info 4975 * 4976 * This function allocates new dmaable memory or provides the 4977 * default config page dmaable memory based on the memory size 4978 * described by the descriptor. 4979 * 4980 * Return: 0 on success, non-zero on failure. 4981 */ 4982 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc, 4983 struct dma_memory_desc *mem_desc) 4984 { 4985 if (mem_desc->size > mrioc->cfg_page_sz) { 4986 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev, 4987 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL); 4988 if (!mem_desc->addr) 4989 return -ENOMEM; 4990 } else { 4991 mem_desc->addr = mrioc->cfg_page; 4992 mem_desc->dma_addr = mrioc->cfg_page_dma; 4993 memset(mem_desc->addr, 0, mrioc->cfg_page_sz); 4994 } 4995 return 0; 4996 } 4997 4998 /** 4999 * mpi3mr_post_cfg_req - Issue config requests and wait 5000 * @mrioc: Adapter instance reference 5001 * @cfg_req: Configuration request 5002 * @timeout: Timeout in seconds 5003 * @ioc_status: Pointer to return ioc status 5004 * 5005 * A generic function for posting MPI3 configuration request to 5006 * the firmware. This blocks for the completion of request for 5007 * timeout seconds and if the request times out this function 5008 * faults the controller with proper reason code. 5009 * 5010 * On successful completion of the request this function returns 5011 * appropriate ioc status from the firmware back to the caller. 5012 * 5013 * Return: 0 on success, non-zero on failure. 5014 */ 5015 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc, 5016 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status) 5017 { 5018 int retval = 0; 5019 5020 mutex_lock(&mrioc->cfg_cmds.mutex); 5021 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) { 5022 retval = -1; 5023 ioc_err(mrioc, "sending config request failed due to command in use\n"); 5024 mutex_unlock(&mrioc->cfg_cmds.mutex); 5025 goto out; 5026 } 5027 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING; 5028 mrioc->cfg_cmds.is_waiting = 1; 5029 mrioc->cfg_cmds.callback = NULL; 5030 mrioc->cfg_cmds.ioc_status = 0; 5031 mrioc->cfg_cmds.ioc_loginfo = 0; 5032 5033 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS); 5034 cfg_req->function = MPI3_FUNCTION_CONFIG; 5035 5036 init_completion(&mrioc->cfg_cmds.done); 5037 dprint_cfg_info(mrioc, "posting config request\n"); 5038 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5039 dprint_dump(cfg_req, sizeof(struct mpi3_config_request), 5040 "mpi3_cfg_req"); 5041 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1); 5042 if (retval) { 5043 ioc_err(mrioc, "posting config request failed\n"); 5044 goto out_unlock; 5045 } 5046 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ)); 5047 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { 5048 mpi3mr_check_rh_fault_ioc(mrioc, 5049 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); 5050 ioc_err(mrioc, "config request timed out\n"); 5051 retval = -1; 5052 goto out_unlock; 5053 } 5054 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK; 5055 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS) 5056 dprint_cfg_err(mrioc, 5057 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n", 5058 *ioc_status, mrioc->cfg_cmds.ioc_loginfo); 5059 5060 out_unlock: 5061 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; 5062 mutex_unlock(&mrioc->cfg_cmds.mutex); 5063 5064 out: 5065 return retval; 5066 } 5067 5068 /** 5069 * mpi3mr_process_cfg_req - config page request processor 5070 * @mrioc: Adapter instance reference 5071 * @cfg_req: Configuration request 5072 * @cfg_hdr: Configuration page header 5073 * @timeout: Timeout in seconds 5074 * @ioc_status: Pointer to return ioc status 5075 * @cfg_buf: Memory pointer to copy config page or header 5076 * @cfg_buf_sz: Size of the memory to get config page or header 5077 * 5078 * This is handler for config page read, write and config page 5079 * header read operations. 5080 * 5081 * This function expects the cfg_req to be populated with page 5082 * type, page number, action for the header read and with page 5083 * address for all other operations. 5084 * 5085 * The cfg_hdr can be passed as null for reading required header 5086 * details for read/write pages the cfg_hdr should point valid 5087 * configuration page header. 5088 * 5089 * This allocates dmaable memory based on the size of the config 5090 * buffer and set the SGE of the cfg_req. 5091 * 5092 * For write actions, the config page data has to be passed in 5093 * the cfg_buf and size of the data has to be mentioned in the 5094 * cfg_buf_sz. 5095 * 5096 * For read/header actions, on successful completion of the 5097 * request with successful ioc_status the data will be copied 5098 * into the cfg_buf limited to a minimum of actual page size and 5099 * cfg_buf_sz 5100 * 5101 * 5102 * Return: 0 on success, non-zero on failure. 5103 */ 5104 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc, 5105 struct mpi3_config_request *cfg_req, 5106 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status, 5107 void *cfg_buf, u32 cfg_buf_sz) 5108 { 5109 struct dma_memory_desc mem_desc; 5110 int retval = -1; 5111 u8 invalid_action = 0; 5112 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 5113 5114 memset(&mem_desc, 0, sizeof(struct dma_memory_desc)); 5115 5116 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER) 5117 mem_desc.size = sizeof(struct mpi3_config_page_header); 5118 else { 5119 if (!cfg_hdr) { 5120 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n", 5121 cfg_req->action, cfg_req->page_type, 5122 cfg_req->page_number); 5123 goto out; 5124 } 5125 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) { 5126 case MPI3_CONFIG_PAGEATTR_READ_ONLY: 5127 if (cfg_req->action 5128 != MPI3_CONFIG_ACTION_READ_CURRENT) 5129 invalid_action = 1; 5130 break; 5131 case MPI3_CONFIG_PAGEATTR_CHANGEABLE: 5132 if ((cfg_req->action == 5133 MPI3_CONFIG_ACTION_READ_PERSISTENT) || 5134 (cfg_req->action == 5135 MPI3_CONFIG_ACTION_WRITE_PERSISTENT)) 5136 invalid_action = 1; 5137 break; 5138 case MPI3_CONFIG_PAGEATTR_PERSISTENT: 5139 default: 5140 break; 5141 } 5142 if (invalid_action) { 5143 ioc_err(mrioc, 5144 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n", 5145 cfg_req->action, cfg_req->page_type, 5146 cfg_req->page_number, cfg_hdr->page_attribute); 5147 goto out; 5148 } 5149 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4; 5150 cfg_req->page_length = cfg_hdr->page_length; 5151 cfg_req->page_version = cfg_hdr->page_version; 5152 } 5153 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc)) 5154 goto out; 5155 5156 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size, 5157 mem_desc.dma_addr); 5158 5159 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) || 5160 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5161 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size, 5162 cfg_buf_sz)); 5163 dprint_cfg_info(mrioc, "config buffer to be written\n"); 5164 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5165 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5166 } 5167 5168 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status)) 5169 goto out; 5170 5171 retval = 0; 5172 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) && 5173 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) && 5174 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) { 5175 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size, 5176 cfg_buf_sz)); 5177 dprint_cfg_info(mrioc, "config buffer read\n"); 5178 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO) 5179 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf"); 5180 } 5181 5182 out: 5183 mpi3mr_free_config_dma_memory(mrioc, &mem_desc); 5184 return retval; 5185 } 5186 5187 /** 5188 * mpi3mr_cfg_get_dev_pg0 - Read current device page0 5189 * @mrioc: Adapter instance reference 5190 * @ioc_status: Pointer to return ioc status 5191 * @dev_pg0: Pointer to return device page 0 5192 * @pg_sz: Size of the memory allocated to the page pointer 5193 * @form: The form to be used for addressing the page 5194 * @form_spec: Form specific information like device handle 5195 * 5196 * This is handler for config page read for a specific device 5197 * page0. The ioc_status has the controller returned ioc_status. 5198 * This routine doesn't check ioc_status to decide whether the 5199 * page read is success or not and it is the callers 5200 * responsibility. 5201 * 5202 * Return: 0 on success, non-zero on failure. 5203 */ 5204 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5205 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec) 5206 { 5207 struct mpi3_config_page_header cfg_hdr; 5208 struct mpi3_config_request cfg_req; 5209 u32 page_address; 5210 5211 memset(dev_pg0, 0, pg_sz); 5212 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5213 memset(&cfg_req, 0, sizeof(cfg_req)); 5214 5215 cfg_req.function = MPI3_FUNCTION_CONFIG; 5216 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5217 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE; 5218 cfg_req.page_number = 0; 5219 cfg_req.page_address = 0; 5220 5221 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5222 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5223 ioc_err(mrioc, "device page0 header read failed\n"); 5224 goto out_failed; 5225 } 5226 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5227 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n", 5228 *ioc_status); 5229 goto out_failed; 5230 } 5231 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5232 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) | 5233 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK)); 5234 cfg_req.page_address = cpu_to_le32(page_address); 5235 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5236 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) { 5237 ioc_err(mrioc, "device page0 read failed\n"); 5238 goto out_failed; 5239 } 5240 return 0; 5241 out_failed: 5242 return -1; 5243 } 5244 5245 5246 /** 5247 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0 5248 * @mrioc: Adapter instance reference 5249 * @ioc_status: Pointer to return ioc status 5250 * @phy_pg0: Pointer to return SAS Phy page 0 5251 * @pg_sz: Size of the memory allocated to the page pointer 5252 * @form: The form to be used for addressing the page 5253 * @form_spec: Form specific information like phy number 5254 * 5255 * This is handler for config page read for a specific SAS Phy 5256 * page0. The ioc_status has the controller returned ioc_status. 5257 * This routine doesn't check ioc_status to decide whether the 5258 * page read is success or not and it is the callers 5259 * responsibility. 5260 * 5261 * Return: 0 on success, non-zero on failure. 5262 */ 5263 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5264 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 5265 u32 form_spec) 5266 { 5267 struct mpi3_config_page_header cfg_hdr; 5268 struct mpi3_config_request cfg_req; 5269 u32 page_address; 5270 5271 memset(phy_pg0, 0, pg_sz); 5272 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5273 memset(&cfg_req, 0, sizeof(cfg_req)); 5274 5275 cfg_req.function = MPI3_FUNCTION_CONFIG; 5276 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5277 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5278 cfg_req.page_number = 0; 5279 cfg_req.page_address = 0; 5280 5281 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5282 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5283 ioc_err(mrioc, "sas phy page0 header read failed\n"); 5284 goto out_failed; 5285 } 5286 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5287 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n", 5288 *ioc_status); 5289 goto out_failed; 5290 } 5291 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5292 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5293 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5294 cfg_req.page_address = cpu_to_le32(page_address); 5295 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5296 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) { 5297 ioc_err(mrioc, "sas phy page0 read failed\n"); 5298 goto out_failed; 5299 } 5300 return 0; 5301 out_failed: 5302 return -1; 5303 } 5304 5305 /** 5306 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1 5307 * @mrioc: Adapter instance reference 5308 * @ioc_status: Pointer to return ioc status 5309 * @phy_pg1: Pointer to return SAS Phy page 1 5310 * @pg_sz: Size of the memory allocated to the page pointer 5311 * @form: The form to be used for addressing the page 5312 * @form_spec: Form specific information like phy number 5313 * 5314 * This is handler for config page read for a specific SAS Phy 5315 * page1. The ioc_status has the controller returned ioc_status. 5316 * This routine doesn't check ioc_status to decide whether the 5317 * page read is success or not and it is the callers 5318 * responsibility. 5319 * 5320 * Return: 0 on success, non-zero on failure. 5321 */ 5322 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5323 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 5324 u32 form_spec) 5325 { 5326 struct mpi3_config_page_header cfg_hdr; 5327 struct mpi3_config_request cfg_req; 5328 u32 page_address; 5329 5330 memset(phy_pg1, 0, pg_sz); 5331 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5332 memset(&cfg_req, 0, sizeof(cfg_req)); 5333 5334 cfg_req.function = MPI3_FUNCTION_CONFIG; 5335 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5336 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY; 5337 cfg_req.page_number = 1; 5338 cfg_req.page_address = 0; 5339 5340 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5341 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5342 ioc_err(mrioc, "sas phy page1 header read failed\n"); 5343 goto out_failed; 5344 } 5345 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5346 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n", 5347 *ioc_status); 5348 goto out_failed; 5349 } 5350 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5351 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) | 5352 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK)); 5353 cfg_req.page_address = cpu_to_le32(page_address); 5354 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5355 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) { 5356 ioc_err(mrioc, "sas phy page1 read failed\n"); 5357 goto out_failed; 5358 } 5359 return 0; 5360 out_failed: 5361 return -1; 5362 } 5363 5364 5365 /** 5366 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0 5367 * @mrioc: Adapter instance reference 5368 * @ioc_status: Pointer to return ioc status 5369 * @exp_pg0: Pointer to return SAS Expander page 0 5370 * @pg_sz: Size of the memory allocated to the page pointer 5371 * @form: The form to be used for addressing the page 5372 * @form_spec: Form specific information like device handle 5373 * 5374 * This is handler for config page read for a specific SAS 5375 * Expander page0. The ioc_status has the controller returned 5376 * ioc_status. This routine doesn't check ioc_status to decide 5377 * whether the page read is success or not and it is the callers 5378 * responsibility. 5379 * 5380 * Return: 0 on success, non-zero on failure. 5381 */ 5382 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5383 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 5384 u32 form_spec) 5385 { 5386 struct mpi3_config_page_header cfg_hdr; 5387 struct mpi3_config_request cfg_req; 5388 u32 page_address; 5389 5390 memset(exp_pg0, 0, pg_sz); 5391 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5392 memset(&cfg_req, 0, sizeof(cfg_req)); 5393 5394 cfg_req.function = MPI3_FUNCTION_CONFIG; 5395 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5396 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5397 cfg_req.page_number = 0; 5398 cfg_req.page_address = 0; 5399 5400 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5401 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5402 ioc_err(mrioc, "expander page0 header read failed\n"); 5403 goto out_failed; 5404 } 5405 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5406 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n", 5407 *ioc_status); 5408 goto out_failed; 5409 } 5410 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5411 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5412 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5413 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5414 cfg_req.page_address = cpu_to_le32(page_address); 5415 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5416 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) { 5417 ioc_err(mrioc, "expander page0 read failed\n"); 5418 goto out_failed; 5419 } 5420 return 0; 5421 out_failed: 5422 return -1; 5423 } 5424 5425 /** 5426 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1 5427 * @mrioc: Adapter instance reference 5428 * @ioc_status: Pointer to return ioc status 5429 * @exp_pg1: Pointer to return SAS Expander page 1 5430 * @pg_sz: Size of the memory allocated to the page pointer 5431 * @form: The form to be used for addressing the page 5432 * @form_spec: Form specific information like phy number 5433 * 5434 * This is handler for config page read for a specific SAS 5435 * Expander page1. The ioc_status has the controller returned 5436 * ioc_status. This routine doesn't check ioc_status to decide 5437 * whether the page read is success or not and it is the callers 5438 * responsibility. 5439 * 5440 * Return: 0 on success, non-zero on failure. 5441 */ 5442 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5443 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 5444 u32 form_spec) 5445 { 5446 struct mpi3_config_page_header cfg_hdr; 5447 struct mpi3_config_request cfg_req; 5448 u32 page_address; 5449 5450 memset(exp_pg1, 0, pg_sz); 5451 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5452 memset(&cfg_req, 0, sizeof(cfg_req)); 5453 5454 cfg_req.function = MPI3_FUNCTION_CONFIG; 5455 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5456 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER; 5457 cfg_req.page_number = 1; 5458 cfg_req.page_address = 0; 5459 5460 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5461 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5462 ioc_err(mrioc, "expander page1 header read failed\n"); 5463 goto out_failed; 5464 } 5465 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5466 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n", 5467 *ioc_status); 5468 goto out_failed; 5469 } 5470 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5471 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) | 5472 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK | 5473 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK))); 5474 cfg_req.page_address = cpu_to_le32(page_address); 5475 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5476 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) { 5477 ioc_err(mrioc, "expander page1 read failed\n"); 5478 goto out_failed; 5479 } 5480 return 0; 5481 out_failed: 5482 return -1; 5483 } 5484 5485 /** 5486 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0 5487 * @mrioc: Adapter instance reference 5488 * @ioc_status: Pointer to return ioc status 5489 * @encl_pg0: Pointer to return Enclosure page 0 5490 * @pg_sz: Size of the memory allocated to the page pointer 5491 * @form: The form to be used for addressing the page 5492 * @form_spec: Form specific information like device handle 5493 * 5494 * This is handler for config page read for a specific Enclosure 5495 * page0. The ioc_status has the controller returned ioc_status. 5496 * This routine doesn't check ioc_status to decide whether the 5497 * page read is success or not and it is the callers 5498 * responsibility. 5499 * 5500 * Return: 0 on success, non-zero on failure. 5501 */ 5502 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 5503 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 5504 u32 form_spec) 5505 { 5506 struct mpi3_config_page_header cfg_hdr; 5507 struct mpi3_config_request cfg_req; 5508 u32 page_address; 5509 5510 memset(encl_pg0, 0, pg_sz); 5511 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5512 memset(&cfg_req, 0, sizeof(cfg_req)); 5513 5514 cfg_req.function = MPI3_FUNCTION_CONFIG; 5515 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5516 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE; 5517 cfg_req.page_number = 0; 5518 cfg_req.page_address = 0; 5519 5520 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5521 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5522 ioc_err(mrioc, "enclosure page0 header read failed\n"); 5523 goto out_failed; 5524 } 5525 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5526 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n", 5527 *ioc_status); 5528 goto out_failed; 5529 } 5530 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5531 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) | 5532 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK)); 5533 cfg_req.page_address = cpu_to_le32(page_address); 5534 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5535 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) { 5536 ioc_err(mrioc, "enclosure page0 read failed\n"); 5537 goto out_failed; 5538 } 5539 return 0; 5540 out_failed: 5541 return -1; 5542 } 5543 5544 5545 /** 5546 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0 5547 * @mrioc: Adapter instance reference 5548 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0 5549 * @pg_sz: Size of the memory allocated to the page pointer 5550 * 5551 * This is handler for config page read for the SAS IO Unit 5552 * page0. This routine checks ioc_status to decide whether the 5553 * page read is success or not. 5554 * 5555 * Return: 0 on success, non-zero on failure. 5556 */ 5557 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 5558 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz) 5559 { 5560 struct mpi3_config_page_header cfg_hdr; 5561 struct mpi3_config_request cfg_req; 5562 u16 ioc_status = 0; 5563 5564 memset(sas_io_unit_pg0, 0, pg_sz); 5565 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5566 memset(&cfg_req, 0, sizeof(cfg_req)); 5567 5568 cfg_req.function = MPI3_FUNCTION_CONFIG; 5569 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5570 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5571 cfg_req.page_number = 0; 5572 cfg_req.page_address = 0; 5573 5574 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5575 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5576 ioc_err(mrioc, "sas io unit page0 header read failed\n"); 5577 goto out_failed; 5578 } 5579 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5580 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n", 5581 ioc_status); 5582 goto out_failed; 5583 } 5584 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5585 5586 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5587 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) { 5588 ioc_err(mrioc, "sas io unit page0 read failed\n"); 5589 goto out_failed; 5590 } 5591 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5592 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n", 5593 ioc_status); 5594 goto out_failed; 5595 } 5596 return 0; 5597 out_failed: 5598 return -1; 5599 } 5600 5601 /** 5602 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1 5603 * @mrioc: Adapter instance reference 5604 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1 5605 * @pg_sz: Size of the memory allocated to the page pointer 5606 * 5607 * This is handler for config page read for the SAS IO Unit 5608 * page1. This routine checks ioc_status to decide whether the 5609 * page read is success or not. 5610 * 5611 * Return: 0 on success, non-zero on failure. 5612 */ 5613 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5614 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5615 { 5616 struct mpi3_config_page_header cfg_hdr; 5617 struct mpi3_config_request cfg_req; 5618 u16 ioc_status = 0; 5619 5620 memset(sas_io_unit_pg1, 0, pg_sz); 5621 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5622 memset(&cfg_req, 0, sizeof(cfg_req)); 5623 5624 cfg_req.function = MPI3_FUNCTION_CONFIG; 5625 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5626 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5627 cfg_req.page_number = 1; 5628 cfg_req.page_address = 0; 5629 5630 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5631 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5632 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5633 goto out_failed; 5634 } 5635 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5636 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5637 ioc_status); 5638 goto out_failed; 5639 } 5640 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5641 5642 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5643 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5644 ioc_err(mrioc, "sas io unit page1 read failed\n"); 5645 goto out_failed; 5646 } 5647 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5648 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n", 5649 ioc_status); 5650 goto out_failed; 5651 } 5652 return 0; 5653 out_failed: 5654 return -1; 5655 } 5656 5657 /** 5658 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1 5659 * @mrioc: Adapter instance reference 5660 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write 5661 * @pg_sz: Size of the memory allocated to the page pointer 5662 * 5663 * This is handler for config page write for the SAS IO Unit 5664 * page1. This routine checks ioc_status to decide whether the 5665 * page read is success or not. This will modify both current 5666 * and persistent page. 5667 * 5668 * Return: 0 on success, non-zero on failure. 5669 */ 5670 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 5671 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz) 5672 { 5673 struct mpi3_config_page_header cfg_hdr; 5674 struct mpi3_config_request cfg_req; 5675 u16 ioc_status = 0; 5676 5677 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5678 memset(&cfg_req, 0, sizeof(cfg_req)); 5679 5680 cfg_req.function = MPI3_FUNCTION_CONFIG; 5681 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5682 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT; 5683 cfg_req.page_number = 1; 5684 cfg_req.page_address = 0; 5685 5686 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5687 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5688 ioc_err(mrioc, "sas io unit page1 header read failed\n"); 5689 goto out_failed; 5690 } 5691 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5692 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n", 5693 ioc_status); 5694 goto out_failed; 5695 } 5696 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT; 5697 5698 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5699 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5700 ioc_err(mrioc, "sas io unit page1 write current failed\n"); 5701 goto out_failed; 5702 } 5703 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5704 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n", 5705 ioc_status); 5706 goto out_failed; 5707 } 5708 5709 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT; 5710 5711 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5712 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) { 5713 ioc_err(mrioc, "sas io unit page1 write persistent failed\n"); 5714 goto out_failed; 5715 } 5716 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5717 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n", 5718 ioc_status); 5719 goto out_failed; 5720 } 5721 return 0; 5722 out_failed: 5723 return -1; 5724 } 5725 5726 /** 5727 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1 5728 * @mrioc: Adapter instance reference 5729 * @driver_pg1: Pointer to return Driver page 1 5730 * @pg_sz: Size of the memory allocated to the page pointer 5731 * 5732 * This is handler for config page read for the Driver page1. 5733 * This routine checks ioc_status to decide whether the page 5734 * read is success or not. 5735 * 5736 * Return: 0 on success, non-zero on failure. 5737 */ 5738 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 5739 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz) 5740 { 5741 struct mpi3_config_page_header cfg_hdr; 5742 struct mpi3_config_request cfg_req; 5743 u16 ioc_status = 0; 5744 5745 memset(driver_pg1, 0, pg_sz); 5746 memset(&cfg_hdr, 0, sizeof(cfg_hdr)); 5747 memset(&cfg_req, 0, sizeof(cfg_req)); 5748 5749 cfg_req.function = MPI3_FUNCTION_CONFIG; 5750 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER; 5751 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER; 5752 cfg_req.page_number = 1; 5753 cfg_req.page_address = 0; 5754 5755 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL, 5756 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) { 5757 ioc_err(mrioc, "driver page1 header read failed\n"); 5758 goto out_failed; 5759 } 5760 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5761 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n", 5762 ioc_status); 5763 goto out_failed; 5764 } 5765 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT; 5766 5767 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr, 5768 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) { 5769 ioc_err(mrioc, "driver page1 read failed\n"); 5770 goto out_failed; 5771 } 5772 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) { 5773 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n", 5774 ioc_status); 5775 goto out_failed; 5776 } 5777 return 0; 5778 out_failed: 5779 return -1; 5780 } 5781