1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 #if defined(writeq) && defined(CONFIG_64BIT) 14 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 15 { 16 writeq(b, addr); 17 } 18 #else 19 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 20 { 21 __u64 data_out = b; 22 23 writel((u32)(data_out), addr); 24 writel((u32)(data_out >> 32), (addr + 4)); 25 } 26 #endif 27 28 static inline bool 29 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 30 { 31 u16 pi, ci, max_entries; 32 bool is_qfull = false; 33 34 pi = op_req_q->pi; 35 ci = READ_ONCE(op_req_q->ci); 36 max_entries = op_req_q->num_requests; 37 38 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 39 is_qfull = true; 40 41 return is_qfull; 42 } 43 44 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 45 { 46 u16 i, max_vectors; 47 48 max_vectors = mrioc->intr_info_count; 49 50 for (i = 0; i < max_vectors; i++) 51 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 52 } 53 54 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 55 { 56 mrioc->intr_enabled = 0; 57 mpi3mr_sync_irqs(mrioc); 58 } 59 60 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 61 { 62 mrioc->intr_enabled = 1; 63 } 64 65 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 66 { 67 u16 i; 68 69 mpi3mr_ioc_disable_intr(mrioc); 70 71 if (!mrioc->intr_info) 72 return; 73 74 for (i = 0; i < mrioc->intr_info_count; i++) 75 free_irq(pci_irq_vector(mrioc->pdev, i), 76 (mrioc->intr_info + i)); 77 78 kfree(mrioc->intr_info); 79 mrioc->intr_info = NULL; 80 mrioc->intr_info_count = 0; 81 pci_free_irq_vectors(mrioc->pdev); 82 } 83 84 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 85 dma_addr_t dma_addr) 86 { 87 struct mpi3_sge_common *sgel = paddr; 88 89 sgel->flags = flags; 90 sgel->length = cpu_to_le32(length); 91 sgel->address = cpu_to_le64(dma_addr); 92 } 93 94 void mpi3mr_build_zero_len_sge(void *paddr) 95 { 96 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 97 98 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 99 } 100 101 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 102 dma_addr_t phys_addr) 103 { 104 if (!phys_addr) 105 return NULL; 106 107 if ((phys_addr < mrioc->reply_buf_dma) || 108 (phys_addr > mrioc->reply_buf_dma_max_address)) 109 return NULL; 110 111 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 112 } 113 114 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 115 dma_addr_t phys_addr) 116 { 117 if (!phys_addr) 118 return NULL; 119 120 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 121 } 122 123 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 124 u64 reply_dma) 125 { 126 u32 old_idx = 0; 127 128 spin_lock(&mrioc->reply_free_queue_lock); 129 old_idx = mrioc->reply_free_queue_host_index; 130 mrioc->reply_free_queue_host_index = ( 131 (mrioc->reply_free_queue_host_index == 132 (mrioc->reply_free_qsz - 1)) ? 0 : 133 (mrioc->reply_free_queue_host_index + 1)); 134 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 135 writel(mrioc->reply_free_queue_host_index, 136 &mrioc->sysif_regs->reply_free_host_index); 137 spin_unlock(&mrioc->reply_free_queue_lock); 138 } 139 140 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 141 u64 sense_buf_dma) 142 { 143 u32 old_idx = 0; 144 145 spin_lock(&mrioc->sbq_lock); 146 old_idx = mrioc->sbq_host_index; 147 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 148 (mrioc->sense_buf_q_sz - 1)) ? 0 : 149 (mrioc->sbq_host_index + 1)); 150 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 151 writel(mrioc->sbq_host_index, 152 &mrioc->sysif_regs->sense_buffer_free_host_index); 153 spin_unlock(&mrioc->sbq_lock); 154 } 155 156 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 157 struct mpi3_default_reply *def_reply) 158 { 159 struct mpi3_event_notification_reply *event_reply = 160 (struct mpi3_event_notification_reply *)def_reply; 161 162 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 163 mpi3mr_os_handle_events(mrioc, event_reply); 164 } 165 166 static struct mpi3mr_drv_cmd * 167 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 168 struct mpi3_default_reply *def_reply) 169 { 170 u16 idx; 171 172 switch (host_tag) { 173 case MPI3MR_HOSTTAG_INITCMDS: 174 return &mrioc->init_cmds; 175 case MPI3MR_HOSTTAG_INVALID: 176 if (def_reply && def_reply->function == 177 MPI3_FUNCTION_EVENT_NOTIFICATION) 178 mpi3mr_handle_events(mrioc, def_reply); 179 return NULL; 180 default: 181 break; 182 } 183 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 184 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 185 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 186 return &mrioc->dev_rmhs_cmds[idx]; 187 } 188 189 return NULL; 190 } 191 192 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 193 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 194 { 195 u16 reply_desc_type, host_tag = 0; 196 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 197 u32 ioc_loginfo = 0; 198 struct mpi3_status_reply_descriptor *status_desc; 199 struct mpi3_address_reply_descriptor *addr_desc; 200 struct mpi3_success_reply_descriptor *success_desc; 201 struct mpi3_default_reply *def_reply = NULL; 202 struct mpi3mr_drv_cmd *cmdptr = NULL; 203 struct mpi3_scsi_io_reply *scsi_reply; 204 u8 *sense_buf = NULL; 205 206 *reply_dma = 0; 207 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 208 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 209 switch (reply_desc_type) { 210 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 211 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 212 host_tag = le16_to_cpu(status_desc->host_tag); 213 ioc_status = le16_to_cpu(status_desc->ioc_status); 214 if (ioc_status & 215 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 216 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 217 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 218 break; 219 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 220 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 221 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 222 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 223 if (!def_reply) 224 goto out; 225 host_tag = le16_to_cpu(def_reply->host_tag); 226 ioc_status = le16_to_cpu(def_reply->ioc_status); 227 if (ioc_status & 228 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 229 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 230 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 231 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 232 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 233 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 234 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 235 } 236 break; 237 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 238 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 239 host_tag = le16_to_cpu(success_desc->host_tag); 240 break; 241 default: 242 break; 243 } 244 245 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 246 if (cmdptr) { 247 if (cmdptr->state & MPI3MR_CMD_PENDING) { 248 cmdptr->state |= MPI3MR_CMD_COMPLETE; 249 cmdptr->ioc_loginfo = ioc_loginfo; 250 cmdptr->ioc_status = ioc_status; 251 cmdptr->state &= ~MPI3MR_CMD_PENDING; 252 if (def_reply) { 253 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 254 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 255 mrioc->facts.reply_sz); 256 } 257 if (cmdptr->is_waiting) { 258 complete(&cmdptr->done); 259 cmdptr->is_waiting = 0; 260 } else if (cmdptr->callback) 261 cmdptr->callback(mrioc, cmdptr); 262 } 263 } 264 out: 265 if (sense_buf) 266 mpi3mr_repost_sense_buf(mrioc, 267 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 268 } 269 270 static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 271 { 272 u32 exp_phase = mrioc->admin_reply_ephase; 273 u32 admin_reply_ci = mrioc->admin_reply_ci; 274 u32 num_admin_replies = 0; 275 u64 reply_dma = 0; 276 struct mpi3_default_reply_descriptor *reply_desc; 277 278 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 279 admin_reply_ci; 280 281 if ((le16_to_cpu(reply_desc->reply_flags) & 282 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 283 return 0; 284 285 do { 286 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 287 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 288 if (reply_dma) 289 mpi3mr_repost_reply_buf(mrioc, reply_dma); 290 num_admin_replies++; 291 if (++admin_reply_ci == mrioc->num_admin_replies) { 292 admin_reply_ci = 0; 293 exp_phase ^= 1; 294 } 295 reply_desc = 296 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 297 admin_reply_ci; 298 if ((le16_to_cpu(reply_desc->reply_flags) & 299 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 300 break; 301 } while (1); 302 303 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 304 mrioc->admin_reply_ci = admin_reply_ci; 305 mrioc->admin_reply_ephase = exp_phase; 306 307 return num_admin_replies; 308 } 309 310 /** 311 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 312 * queue's consumer index from operational reply descriptor queue. 313 * @op_reply_q: op_reply_qinfo object 314 * @reply_ci: operational reply descriptor's queue consumer index 315 * 316 * Returns reply descriptor frame address 317 */ 318 static inline struct mpi3_default_reply_descriptor * 319 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 320 { 321 void *segment_base_addr; 322 struct segments *segments = op_reply_q->q_segments; 323 struct mpi3_default_reply_descriptor *reply_desc = NULL; 324 325 segment_base_addr = 326 segments[reply_ci / op_reply_q->segment_qd].segment; 327 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 328 (reply_ci % op_reply_q->segment_qd); 329 return reply_desc; 330 } 331 332 static int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 333 struct mpi3mr_intr_info *intr_info) 334 { 335 struct op_reply_qinfo *op_reply_q = intr_info->op_reply_q; 336 struct op_req_qinfo *op_req_q; 337 u32 exp_phase; 338 u32 reply_ci; 339 u32 num_op_reply = 0; 340 u64 reply_dma = 0; 341 struct mpi3_default_reply_descriptor *reply_desc; 342 u16 req_q_idx = 0, reply_qidx; 343 344 reply_qidx = op_reply_q->qid - 1; 345 346 exp_phase = op_reply_q->ephase; 347 reply_ci = op_reply_q->ci; 348 349 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 350 if ((le16_to_cpu(reply_desc->reply_flags) & 351 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 352 return 0; 353 } 354 355 do { 356 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 357 op_req_q = &mrioc->req_qinfo[req_q_idx]; 358 359 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 360 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 361 reply_qidx); 362 if (reply_dma) 363 mpi3mr_repost_reply_buf(mrioc, reply_dma); 364 num_op_reply++; 365 366 if (++reply_ci == op_reply_q->num_replies) { 367 reply_ci = 0; 368 exp_phase ^= 1; 369 } 370 371 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 372 373 if ((le16_to_cpu(reply_desc->reply_flags) & 374 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 375 break; 376 377 } while (1); 378 379 writel(reply_ci, 380 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 381 op_reply_q->ci = reply_ci; 382 op_reply_q->ephase = exp_phase; 383 384 return num_op_reply; 385 } 386 387 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 388 { 389 struct mpi3mr_intr_info *intr_info = privdata; 390 struct mpi3mr_ioc *mrioc; 391 u16 midx; 392 u32 num_admin_replies = 0; 393 394 if (!intr_info) 395 return IRQ_NONE; 396 397 mrioc = intr_info->mrioc; 398 399 if (!mrioc->intr_enabled) 400 return IRQ_NONE; 401 402 midx = intr_info->msix_index; 403 404 if (!midx) 405 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 406 407 if (num_admin_replies) 408 return IRQ_HANDLED; 409 else 410 return IRQ_NONE; 411 } 412 413 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 414 { 415 struct mpi3mr_intr_info *intr_info = privdata; 416 int ret; 417 418 if (!intr_info) 419 return IRQ_NONE; 420 421 /* Call primary ISR routine */ 422 ret = mpi3mr_isr_primary(irq, privdata); 423 424 return ret; 425 } 426 427 /** 428 * mpi3mr_isr_poll - Reply queue polling routine 429 * @irq: IRQ 430 * @privdata: Interrupt info 431 * 432 * poll for pending I/O completions in a loop until pending I/Os 433 * present or controller queue depth I/Os are processed. 434 * 435 * Return: IRQ_NONE or IRQ_HANDLED 436 */ 437 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 438 { 439 return IRQ_HANDLED; 440 } 441 442 /** 443 * mpi3mr_request_irq - Request IRQ and register ISR 444 * @mrioc: Adapter instance reference 445 * @index: IRQ vector index 446 * 447 * Request threaded ISR with primary ISR and secondary 448 * 449 * Return: 0 on success and non zero on failures. 450 */ 451 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 452 { 453 struct pci_dev *pdev = mrioc->pdev; 454 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 455 int retval = 0; 456 457 intr_info->mrioc = mrioc; 458 intr_info->msix_index = index; 459 intr_info->op_reply_q = NULL; 460 461 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 462 mrioc->driver_name, mrioc->id, index); 463 464 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 465 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 466 if (retval) { 467 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 468 intr_info->name, pci_irq_vector(pdev, index)); 469 return retval; 470 } 471 472 return retval; 473 } 474 475 /** 476 * mpi3mr_setup_isr - Setup ISR for the controller 477 * @mrioc: Adapter instance reference 478 * @setup_one: Request one IRQ or more 479 * 480 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 481 * 482 * Return: 0 on success and non zero on failures. 483 */ 484 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 485 { 486 unsigned int irq_flags = PCI_IRQ_MSIX; 487 u16 max_vectors = 0, i; 488 int retval = 0; 489 struct irq_affinity desc = { .pre_vectors = 1}; 490 491 mpi3mr_cleanup_isr(mrioc); 492 493 if (setup_one || reset_devices) 494 max_vectors = 1; 495 else { 496 max_vectors = 497 min_t(int, mrioc->cpu_count + 1, mrioc->msix_count); 498 499 ioc_info(mrioc, 500 "MSI-X vectors supported: %d, no of cores: %d,", 501 mrioc->msix_count, mrioc->cpu_count); 502 ioc_info(mrioc, 503 "MSI-x vectors requested: %d\n", max_vectors); 504 } 505 506 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 507 508 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 509 i = pci_alloc_irq_vectors_affinity(mrioc->pdev, 510 1, max_vectors, irq_flags, &desc); 511 if (i <= 0) { 512 ioc_err(mrioc, "Cannot alloc irq vectors\n"); 513 goto out_failed; 514 } 515 if (i != max_vectors) { 516 ioc_info(mrioc, 517 "allocated vectors (%d) are less than configured (%d)\n", 518 i, max_vectors); 519 /* 520 * If only one MSI-x is allocated, then MSI-x 0 will be shared 521 * between Admin queue and operational queue 522 */ 523 if (i == 1) 524 mrioc->op_reply_q_offset = 0; 525 526 max_vectors = i; 527 } 528 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 529 GFP_KERNEL); 530 if (!mrioc->intr_info) { 531 retval = -1; 532 pci_free_irq_vectors(mrioc->pdev); 533 goto out_failed; 534 } 535 for (i = 0; i < max_vectors; i++) { 536 retval = mpi3mr_request_irq(mrioc, i); 537 if (retval) { 538 mrioc->intr_info_count = i; 539 goto out_failed; 540 } 541 } 542 mrioc->intr_info_count = max_vectors; 543 mpi3mr_ioc_enable_intr(mrioc); 544 return retval; 545 out_failed: 546 mpi3mr_cleanup_isr(mrioc); 547 548 return retval; 549 } 550 551 static const struct { 552 enum mpi3mr_iocstate value; 553 char *name; 554 } mrioc_states[] = { 555 { MRIOC_STATE_READY, "ready" }, 556 { MRIOC_STATE_FAULT, "fault" }, 557 { MRIOC_STATE_RESET, "reset" }, 558 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 559 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 560 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 561 }; 562 563 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 564 { 565 int i; 566 char *name = NULL; 567 568 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 569 if (mrioc_states[i].value == mrioc_state) { 570 name = mrioc_states[i].name; 571 break; 572 } 573 } 574 return name; 575 } 576 577 /** 578 * mpi3mr_print_fault_info - Display fault information 579 * @mrioc: Adapter instance reference 580 * 581 * Display the controller fault information if there is a 582 * controller fault. 583 * 584 * Return: Nothing. 585 */ 586 static void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 587 { 588 u32 ioc_status, code, code1, code2, code3; 589 590 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 591 592 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 593 code = readl(&mrioc->sysif_regs->fault); 594 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 595 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 596 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 597 598 ioc_info(mrioc, 599 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 600 code, code1, code2, code3); 601 } 602 } 603 604 /** 605 * mpi3mr_get_iocstate - Get IOC State 606 * @mrioc: Adapter instance reference 607 * 608 * Return a proper IOC state enum based on the IOC status and 609 * IOC configuration and unrcoverable state of the controller. 610 * 611 * Return: Current IOC state. 612 */ 613 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 614 { 615 u32 ioc_status, ioc_config; 616 u8 ready, enabled; 617 618 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 619 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 620 621 if (mrioc->unrecoverable) 622 return MRIOC_STATE_UNRECOVERABLE; 623 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 624 return MRIOC_STATE_FAULT; 625 626 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 627 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 628 629 if (ready && enabled) 630 return MRIOC_STATE_READY; 631 if ((!ready) && (!enabled)) 632 return MRIOC_STATE_RESET; 633 if ((!ready) && (enabled)) 634 return MRIOC_STATE_BECOMING_READY; 635 636 return MRIOC_STATE_RESET_REQUESTED; 637 } 638 639 /** 640 * mpi3mr_clear_reset_history - clear reset history 641 * @mrioc: Adapter instance reference 642 * 643 * Write the reset history bit in IOC status to clear the bit, 644 * if it is already set. 645 * 646 * Return: Nothing. 647 */ 648 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 649 { 650 u32 ioc_status; 651 652 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 653 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 654 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 655 } 656 657 /** 658 * mpi3mr_issue_and_process_mur - Message unit Reset handler 659 * @mrioc: Adapter instance reference 660 * @reset_reason: Reset reason code 661 * 662 * Issue Message unit Reset to the controller and wait for it to 663 * be complete. 664 * 665 * Return: 0 on success, -1 on failure. 666 */ 667 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 668 u32 reset_reason) 669 { 670 u32 ioc_config, timeout, ioc_status; 671 int retval = -1; 672 673 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 674 if (mrioc->unrecoverable) { 675 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 676 return retval; 677 } 678 mpi3mr_clear_reset_history(mrioc); 679 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 680 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 681 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 682 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 683 684 timeout = mrioc->ready_timeout * 10; 685 do { 686 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 687 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 688 mpi3mr_clear_reset_history(mrioc); 689 ioc_config = 690 readl(&mrioc->sysif_regs->ioc_configuration); 691 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 692 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 693 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) { 694 retval = 0; 695 break; 696 } 697 } 698 msleep(100); 699 } while (--timeout); 700 701 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 702 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 703 704 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 705 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 706 return retval; 707 } 708 709 /** 710 * mpi3mr_bring_ioc_ready - Bring controller to ready state 711 * @mrioc: Adapter instance reference 712 * 713 * Set Enable IOC bit in IOC configuration register and wait for 714 * the controller to become ready. 715 * 716 * Return: 0 on success, -1 on failure. 717 */ 718 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 719 { 720 u32 ioc_config, timeout; 721 enum mpi3mr_iocstate current_state; 722 723 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 724 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 725 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 726 727 timeout = mrioc->ready_timeout * 10; 728 do { 729 current_state = mpi3mr_get_iocstate(mrioc); 730 if (current_state == MRIOC_STATE_READY) 731 return 0; 732 msleep(100); 733 } while (--timeout); 734 735 return -1; 736 } 737 738 /** 739 * mpi3mr_set_diagsave - Set diag save bit for snapdump 740 * @mrioc: Adapter reference 741 * 742 * Set diag save bit in IOC configuration register to enable 743 * snapdump. 744 * 745 * Return: Nothing. 746 */ 747 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 748 { 749 u32 ioc_config; 750 751 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 752 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 753 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 754 } 755 756 /** 757 * mpi3mr_issue_reset - Issue reset to the controller 758 * @mrioc: Adapter reference 759 * @reset_type: Reset type 760 * @reset_reason: Reset reason code 761 * 762 * TBD 763 * 764 * Return: 0 on success, non-zero on failure. 765 */ 766 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 767 u32 reset_reason) 768 { 769 return 0; 770 } 771 772 /** 773 * mpi3mr_admin_request_post - Post request to admin queue 774 * @mrioc: Adapter reference 775 * @admin_req: MPI3 request 776 * @admin_req_sz: Request size 777 * @ignore_reset: Ignore reset in process 778 * 779 * Post the MPI3 request into admin request queue and 780 * inform the controller, if the queue is full return 781 * appropriate error. 782 * 783 * Return: 0 on success, non-zero on failure. 784 */ 785 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 786 u16 admin_req_sz, u8 ignore_reset) 787 { 788 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 789 int retval = 0; 790 unsigned long flags; 791 u8 *areq_entry; 792 793 if (mrioc->unrecoverable) { 794 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 795 return -EFAULT; 796 } 797 798 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 799 areq_pi = mrioc->admin_req_pi; 800 areq_ci = mrioc->admin_req_ci; 801 max_entries = mrioc->num_admin_req; 802 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 803 (areq_pi == (max_entries - 1)))) { 804 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 805 retval = -EAGAIN; 806 goto out; 807 } 808 if (!ignore_reset && mrioc->reset_in_progress) { 809 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 810 retval = -EAGAIN; 811 goto out; 812 } 813 areq_entry = (u8 *)mrioc->admin_req_base + 814 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 815 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 816 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 817 818 if (++areq_pi == max_entries) 819 areq_pi = 0; 820 mrioc->admin_req_pi = areq_pi; 821 822 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 823 824 out: 825 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 826 827 return retval; 828 } 829 830 /** 831 * mpi3mr_free_op_req_q_segments - free request memory segments 832 * @mrioc: Adapter instance reference 833 * @q_idx: operational request queue index 834 * 835 * Free memory segments allocated for operational request queue 836 * 837 * Return: Nothing. 838 */ 839 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 840 { 841 u16 j; 842 int size; 843 struct segments *segments; 844 845 segments = mrioc->req_qinfo[q_idx].q_segments; 846 if (!segments) 847 return; 848 849 if (mrioc->enable_segqueue) { 850 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 851 if (mrioc->req_qinfo[q_idx].q_segment_list) { 852 dma_free_coherent(&mrioc->pdev->dev, 853 MPI3MR_MAX_SEG_LIST_SIZE, 854 mrioc->req_qinfo[q_idx].q_segment_list, 855 mrioc->req_qinfo[q_idx].q_segment_list_dma); 856 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 857 } 858 } else 859 size = mrioc->req_qinfo[q_idx].num_requests * 860 mrioc->facts.op_req_sz; 861 862 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 863 if (!segments[j].segment) 864 continue; 865 dma_free_coherent(&mrioc->pdev->dev, 866 size, segments[j].segment, segments[j].segment_dma); 867 segments[j].segment = NULL; 868 } 869 kfree(mrioc->req_qinfo[q_idx].q_segments); 870 mrioc->req_qinfo[q_idx].q_segments = NULL; 871 mrioc->req_qinfo[q_idx].qid = 0; 872 } 873 874 /** 875 * mpi3mr_free_op_reply_q_segments - free reply memory segments 876 * @mrioc: Adapter instance reference 877 * @q_idx: operational reply queue index 878 * 879 * Free memory segments allocated for operational reply queue 880 * 881 * Return: Nothing. 882 */ 883 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 884 { 885 u16 j; 886 int size; 887 struct segments *segments; 888 889 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 890 if (!segments) 891 return; 892 893 if (mrioc->enable_segqueue) { 894 size = MPI3MR_OP_REP_Q_SEG_SIZE; 895 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 896 dma_free_coherent(&mrioc->pdev->dev, 897 MPI3MR_MAX_SEG_LIST_SIZE, 898 mrioc->op_reply_qinfo[q_idx].q_segment_list, 899 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 900 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 901 } 902 } else 903 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 904 mrioc->op_reply_desc_sz; 905 906 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 907 if (!segments[j].segment) 908 continue; 909 dma_free_coherent(&mrioc->pdev->dev, 910 size, segments[j].segment, segments[j].segment_dma); 911 segments[j].segment = NULL; 912 } 913 914 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 915 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 916 mrioc->op_reply_qinfo[q_idx].qid = 0; 917 } 918 919 /** 920 * mpi3mr_delete_op_reply_q - delete operational reply queue 921 * @mrioc: Adapter instance reference 922 * @qidx: operational reply queue index 923 * 924 * Delete operatinal reply queue by issuing MPI request 925 * through admin queue. 926 * 927 * Return: 0 on success, non-zero on failure. 928 */ 929 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 930 { 931 struct mpi3_delete_reply_queue_request delq_req; 932 int retval = 0; 933 u16 reply_qid = 0, midx; 934 935 reply_qid = mrioc->op_reply_qinfo[qidx].qid; 936 937 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 938 939 if (!reply_qid) { 940 retval = -1; 941 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 942 goto out; 943 } 944 945 memset(&delq_req, 0, sizeof(delq_req)); 946 mutex_lock(&mrioc->init_cmds.mutex); 947 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 948 retval = -1; 949 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 950 mutex_unlock(&mrioc->init_cmds.mutex); 951 goto out; 952 } 953 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 954 mrioc->init_cmds.is_waiting = 1; 955 mrioc->init_cmds.callback = NULL; 956 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 957 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 958 delq_req.queue_id = cpu_to_le16(reply_qid); 959 960 init_completion(&mrioc->init_cmds.done); 961 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 962 1); 963 if (retval) { 964 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 965 goto out_unlock; 966 } 967 wait_for_completion_timeout(&mrioc->init_cmds.done, 968 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 969 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 970 ioc_err(mrioc, "Issue DelRepQ: command timed out\n"); 971 mpi3mr_set_diagsave(mrioc); 972 mpi3mr_issue_reset(mrioc, 973 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 974 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 975 mrioc->unrecoverable = 1; 976 977 retval = -1; 978 goto out_unlock; 979 } 980 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 981 != MPI3_IOCSTATUS_SUCCESS) { 982 ioc_err(mrioc, 983 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 984 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 985 mrioc->init_cmds.ioc_loginfo); 986 retval = -1; 987 goto out_unlock; 988 } 989 mrioc->intr_info[midx].op_reply_q = NULL; 990 991 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 992 out_unlock: 993 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 994 mutex_unlock(&mrioc->init_cmds.mutex); 995 out: 996 997 return retval; 998 } 999 1000 /** 1001 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1002 * @mrioc: Adapter instance reference 1003 * @qidx: request queue index 1004 * 1005 * Allocate segmented memory pools for operational reply 1006 * queue. 1007 * 1008 * Return: 0 on success, non-zero on failure. 1009 */ 1010 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1011 { 1012 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1013 int i, size; 1014 u64 *q_segment_list_entry = NULL; 1015 struct segments *segments; 1016 1017 if (mrioc->enable_segqueue) { 1018 op_reply_q->segment_qd = 1019 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1020 1021 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1022 1023 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1024 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1025 GFP_KERNEL); 1026 if (!op_reply_q->q_segment_list) 1027 return -ENOMEM; 1028 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1029 } else { 1030 op_reply_q->segment_qd = op_reply_q->num_replies; 1031 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1032 } 1033 1034 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1035 op_reply_q->segment_qd); 1036 1037 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1038 sizeof(struct segments), GFP_KERNEL); 1039 if (!op_reply_q->q_segments) 1040 return -ENOMEM; 1041 1042 segments = op_reply_q->q_segments; 1043 for (i = 0; i < op_reply_q->num_segments; i++) { 1044 segments[i].segment = 1045 dma_alloc_coherent(&mrioc->pdev->dev, 1046 size, &segments[i].segment_dma, GFP_KERNEL); 1047 if (!segments[i].segment) 1048 return -ENOMEM; 1049 if (mrioc->enable_segqueue) 1050 q_segment_list_entry[i] = 1051 (unsigned long)segments[i].segment_dma; 1052 } 1053 1054 return 0; 1055 } 1056 1057 /** 1058 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1059 * @mrioc: Adapter instance reference 1060 * @qidx: request queue index 1061 * 1062 * Allocate segmented memory pools for operational request 1063 * queue. 1064 * 1065 * Return: 0 on success, non-zero on failure. 1066 */ 1067 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1068 { 1069 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1070 int i, size; 1071 u64 *q_segment_list_entry = NULL; 1072 struct segments *segments; 1073 1074 if (mrioc->enable_segqueue) { 1075 op_req_q->segment_qd = 1076 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1077 1078 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1079 1080 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1081 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1082 GFP_KERNEL); 1083 if (!op_req_q->q_segment_list) 1084 return -ENOMEM; 1085 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1086 1087 } else { 1088 op_req_q->segment_qd = op_req_q->num_requests; 1089 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1090 } 1091 1092 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 1093 op_req_q->segment_qd); 1094 1095 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 1096 sizeof(struct segments), GFP_KERNEL); 1097 if (!op_req_q->q_segments) 1098 return -ENOMEM; 1099 1100 segments = op_req_q->q_segments; 1101 for (i = 0; i < op_req_q->num_segments; i++) { 1102 segments[i].segment = 1103 dma_alloc_coherent(&mrioc->pdev->dev, 1104 size, &segments[i].segment_dma, GFP_KERNEL); 1105 if (!segments[i].segment) 1106 return -ENOMEM; 1107 if (mrioc->enable_segqueue) 1108 q_segment_list_entry[i] = 1109 (unsigned long)segments[i].segment_dma; 1110 } 1111 1112 return 0; 1113 } 1114 1115 /** 1116 * mpi3mr_create_op_reply_q - create operational reply queue 1117 * @mrioc: Adapter instance reference 1118 * @qidx: operational reply queue index 1119 * 1120 * Create operatinal reply queue by issuing MPI request 1121 * through admin queue. 1122 * 1123 * Return: 0 on success, non-zero on failure. 1124 */ 1125 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1126 { 1127 struct mpi3_create_reply_queue_request create_req; 1128 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1129 int retval = 0; 1130 u16 reply_qid = 0, midx; 1131 1132 reply_qid = op_reply_q->qid; 1133 1134 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1135 1136 if (reply_qid) { 1137 retval = -1; 1138 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 1139 reply_qid); 1140 1141 return retval; 1142 } 1143 1144 reply_qid = qidx + 1; 1145 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 1146 op_reply_q->ci = 0; 1147 op_reply_q->ephase = 1; 1148 1149 if (!op_reply_q->q_segments) { 1150 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 1151 if (retval) { 1152 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1153 goto out; 1154 } 1155 } 1156 1157 memset(&create_req, 0, sizeof(create_req)); 1158 mutex_lock(&mrioc->init_cmds.mutex); 1159 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1160 retval = -1; 1161 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 1162 goto out; 1163 } 1164 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1165 mrioc->init_cmds.is_waiting = 1; 1166 mrioc->init_cmds.callback = NULL; 1167 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1168 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 1169 create_req.queue_id = cpu_to_le16(reply_qid); 1170 create_req.flags = MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 1171 create_req.msix_index = cpu_to_le16(mrioc->intr_info[midx].msix_index); 1172 if (mrioc->enable_segqueue) { 1173 create_req.flags |= 1174 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1175 create_req.base_address = cpu_to_le64( 1176 op_reply_q->q_segment_list_dma); 1177 } else 1178 create_req.base_address = cpu_to_le64( 1179 op_reply_q->q_segments[0].segment_dma); 1180 1181 create_req.size = cpu_to_le16(op_reply_q->num_replies); 1182 1183 init_completion(&mrioc->init_cmds.done); 1184 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1185 sizeof(create_req), 1); 1186 if (retval) { 1187 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 1188 goto out_unlock; 1189 } 1190 wait_for_completion_timeout(&mrioc->init_cmds.done, 1191 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1192 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1193 ioc_err(mrioc, "CreateRepQ: command timed out\n"); 1194 mpi3mr_set_diagsave(mrioc); 1195 mpi3mr_issue_reset(mrioc, 1196 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 1197 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 1198 mrioc->unrecoverable = 1; 1199 retval = -1; 1200 goto out_unlock; 1201 } 1202 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1203 != MPI3_IOCSTATUS_SUCCESS) { 1204 ioc_err(mrioc, 1205 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1206 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1207 mrioc->init_cmds.ioc_loginfo); 1208 retval = -1; 1209 goto out_unlock; 1210 } 1211 op_reply_q->qid = reply_qid; 1212 mrioc->intr_info[midx].op_reply_q = op_reply_q; 1213 1214 out_unlock: 1215 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1216 mutex_unlock(&mrioc->init_cmds.mutex); 1217 out: 1218 1219 return retval; 1220 } 1221 1222 /** 1223 * mpi3mr_create_op_req_q - create operational request queue 1224 * @mrioc: Adapter instance reference 1225 * @idx: operational request queue index 1226 * @reply_qid: Reply queue ID 1227 * 1228 * Create operatinal request queue by issuing MPI request 1229 * through admin queue. 1230 * 1231 * Return: 0 on success, non-zero on failure. 1232 */ 1233 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 1234 u16 reply_qid) 1235 { 1236 struct mpi3_create_request_queue_request create_req; 1237 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 1238 int retval = 0; 1239 u16 req_qid = 0; 1240 1241 req_qid = op_req_q->qid; 1242 1243 if (req_qid) { 1244 retval = -1; 1245 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 1246 req_qid); 1247 1248 return retval; 1249 } 1250 req_qid = idx + 1; 1251 1252 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 1253 op_req_q->ci = 0; 1254 op_req_q->pi = 0; 1255 op_req_q->reply_qid = reply_qid; 1256 spin_lock_init(&op_req_q->q_lock); 1257 1258 if (!op_req_q->q_segments) { 1259 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 1260 if (retval) { 1261 mpi3mr_free_op_req_q_segments(mrioc, idx); 1262 goto out; 1263 } 1264 } 1265 1266 memset(&create_req, 0, sizeof(create_req)); 1267 mutex_lock(&mrioc->init_cmds.mutex); 1268 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1269 retval = -1; 1270 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 1271 goto out; 1272 } 1273 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1274 mrioc->init_cmds.is_waiting = 1; 1275 mrioc->init_cmds.callback = NULL; 1276 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1277 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 1278 create_req.queue_id = cpu_to_le16(req_qid); 1279 if (mrioc->enable_segqueue) { 1280 create_req.flags = 1281 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1282 create_req.base_address = cpu_to_le64( 1283 op_req_q->q_segment_list_dma); 1284 } else 1285 create_req.base_address = cpu_to_le64( 1286 op_req_q->q_segments[0].segment_dma); 1287 create_req.reply_queue_id = cpu_to_le16(reply_qid); 1288 create_req.size = cpu_to_le16(op_req_q->num_requests); 1289 1290 init_completion(&mrioc->init_cmds.done); 1291 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1292 sizeof(create_req), 1); 1293 if (retval) { 1294 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 1295 goto out_unlock; 1296 } 1297 wait_for_completion_timeout(&mrioc->init_cmds.done, 1298 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1299 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1300 ioc_err(mrioc, "CreateReqQ: command timed out\n"); 1301 mpi3mr_set_diagsave(mrioc); 1302 if (mpi3mr_issue_reset(mrioc, 1303 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 1304 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT)) 1305 mrioc->unrecoverable = 1; 1306 retval = -1; 1307 goto out_unlock; 1308 } 1309 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1310 != MPI3_IOCSTATUS_SUCCESS) { 1311 ioc_err(mrioc, 1312 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1313 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1314 mrioc->init_cmds.ioc_loginfo); 1315 retval = -1; 1316 goto out_unlock; 1317 } 1318 op_req_q->qid = req_qid; 1319 1320 out_unlock: 1321 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1322 mutex_unlock(&mrioc->init_cmds.mutex); 1323 out: 1324 1325 return retval; 1326 } 1327 1328 /** 1329 * mpi3mr_create_op_queues - create operational queue pairs 1330 * @mrioc: Adapter instance reference 1331 * 1332 * Allocate memory for operational queue meta data and call 1333 * create request and reply queue functions. 1334 * 1335 * Return: 0 on success, non-zero on failures. 1336 */ 1337 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 1338 { 1339 int retval = 0; 1340 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 1341 1342 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 1343 mrioc->facts.max_op_req_q); 1344 1345 msix_count_op_q = 1346 mrioc->intr_info_count - mrioc->op_reply_q_offset; 1347 if (!mrioc->num_queues) 1348 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 1349 num_queues = mrioc->num_queues; 1350 ioc_info(mrioc, "Trying to create %d Operational Q pairs\n", 1351 num_queues); 1352 1353 if (!mrioc->req_qinfo) { 1354 mrioc->req_qinfo = kcalloc(num_queues, 1355 sizeof(struct op_req_qinfo), GFP_KERNEL); 1356 if (!mrioc->req_qinfo) { 1357 retval = -1; 1358 goto out_failed; 1359 } 1360 1361 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 1362 num_queues, GFP_KERNEL); 1363 if (!mrioc->op_reply_qinfo) { 1364 retval = -1; 1365 goto out_failed; 1366 } 1367 } 1368 1369 if (mrioc->enable_segqueue) 1370 ioc_info(mrioc, 1371 "allocating operational queues through segmented queues\n"); 1372 1373 for (i = 0; i < num_queues; i++) { 1374 if (mpi3mr_create_op_reply_q(mrioc, i)) { 1375 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 1376 break; 1377 } 1378 if (mpi3mr_create_op_req_q(mrioc, i, 1379 mrioc->op_reply_qinfo[i].qid)) { 1380 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 1381 mpi3mr_delete_op_reply_q(mrioc, i); 1382 break; 1383 } 1384 } 1385 1386 if (i == 0) { 1387 /* Not even one queue is created successfully*/ 1388 retval = -1; 1389 goto out_failed; 1390 } 1391 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 1392 ioc_info(mrioc, "Successfully created %d Operational Q pairs\n", 1393 mrioc->num_op_reply_q); 1394 1395 return retval; 1396 out_failed: 1397 kfree(mrioc->req_qinfo); 1398 mrioc->req_qinfo = NULL; 1399 1400 kfree(mrioc->op_reply_qinfo); 1401 mrioc->op_reply_qinfo = NULL; 1402 1403 return retval; 1404 } 1405 1406 /** 1407 * mpi3mr_op_request_post - Post request to operational queue 1408 * @mrioc: Adapter reference 1409 * @op_req_q: Operational request queue info 1410 * @req: MPI3 request 1411 * 1412 * Post the MPI3 request into operational request queue and 1413 * inform the controller, if the queue is full return 1414 * appropriate error. 1415 * 1416 * Return: 0 on success, non-zero on failure. 1417 */ 1418 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1419 struct op_req_qinfo *op_req_q, u8 *req) 1420 { 1421 u16 pi = 0, max_entries, reply_qidx = 0, midx; 1422 int retval = 0; 1423 unsigned long flags; 1424 u8 *req_entry; 1425 void *segment_base_addr; 1426 u16 req_sz = mrioc->facts.op_req_sz; 1427 struct segments *segments = op_req_q->q_segments; 1428 1429 reply_qidx = op_req_q->reply_qid - 1; 1430 1431 if (mrioc->unrecoverable) 1432 return -EFAULT; 1433 1434 spin_lock_irqsave(&op_req_q->q_lock, flags); 1435 pi = op_req_q->pi; 1436 max_entries = op_req_q->num_requests; 1437 1438 if (mpi3mr_check_req_qfull(op_req_q)) { 1439 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 1440 reply_qidx, mrioc->op_reply_q_offset); 1441 mpi3mr_process_op_reply_q(mrioc, &mrioc->intr_info[midx]); 1442 1443 if (mpi3mr_check_req_qfull(op_req_q)) { 1444 retval = -EAGAIN; 1445 goto out; 1446 } 1447 } 1448 1449 if (mrioc->reset_in_progress) { 1450 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 1451 retval = -EAGAIN; 1452 goto out; 1453 } 1454 1455 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 1456 req_entry = (u8 *)segment_base_addr + 1457 ((pi % op_req_q->segment_qd) * req_sz); 1458 1459 memset(req_entry, 0, req_sz); 1460 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 1461 1462 if (++pi == max_entries) 1463 pi = 0; 1464 op_req_q->pi = pi; 1465 1466 writel(op_req_q->pi, 1467 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 1468 1469 out: 1470 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 1471 return retval; 1472 } 1473 1474 /** 1475 * mpi3mr_watchdog_work - watchdog thread to monitor faults 1476 * @work: work struct 1477 * 1478 * Watch dog work periodically executed (1 second interval) to 1479 * monitor firmware fault and to issue periodic timer sync to 1480 * the firmware. 1481 * 1482 * Return: Nothing. 1483 */ 1484 static void mpi3mr_watchdog_work(struct work_struct *work) 1485 { 1486 struct mpi3mr_ioc *mrioc = 1487 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 1488 unsigned long flags; 1489 enum mpi3mr_iocstate ioc_state; 1490 u32 fault, host_diagnostic; 1491 1492 /*Check for fault state every one second and issue Soft reset*/ 1493 ioc_state = mpi3mr_get_iocstate(mrioc); 1494 if (ioc_state == MRIOC_STATE_FAULT) { 1495 fault = readl(&mrioc->sysif_regs->fault) & 1496 MPI3_SYSIF_FAULT_CODE_MASK; 1497 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1498 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 1499 if (!mrioc->diagsave_timeout) { 1500 mpi3mr_print_fault_info(mrioc); 1501 ioc_warn(mrioc, "Diag save in progress\n"); 1502 } 1503 if ((mrioc->diagsave_timeout++) <= 1504 MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 1505 goto schedule_work; 1506 } else 1507 mpi3mr_print_fault_info(mrioc); 1508 mrioc->diagsave_timeout = 0; 1509 1510 if (fault == MPI3_SYSIF_FAULT_CODE_FACTORY_RESET) { 1511 ioc_info(mrioc, 1512 "Factory Reset fault occurred marking controller as unrecoverable" 1513 ); 1514 mrioc->unrecoverable = 1; 1515 goto out; 1516 } 1517 1518 if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) || 1519 (fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) || 1520 (mrioc->reset_in_progress)) 1521 goto out; 1522 if (fault == MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET) 1523 mpi3mr_soft_reset_handler(mrioc, 1524 MPI3MR_RESET_FROM_CIACTIV_FAULT, 0); 1525 else 1526 mpi3mr_soft_reset_handler(mrioc, 1527 MPI3MR_RESET_FROM_FAULT_WATCH, 0); 1528 } 1529 1530 schedule_work: 1531 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 1532 if (mrioc->watchdog_work_q) 1533 queue_delayed_work(mrioc->watchdog_work_q, 1534 &mrioc->watchdog_work, 1535 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 1536 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 1537 out: 1538 return; 1539 } 1540 1541 /** 1542 * mpi3mr_start_watchdog - Start watchdog 1543 * @mrioc: Adapter instance reference 1544 * 1545 * Create and start the watchdog thread to monitor controller 1546 * faults. 1547 * 1548 * Return: Nothing. 1549 */ 1550 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 1551 { 1552 if (mrioc->watchdog_work_q) 1553 return; 1554 1555 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 1556 snprintf(mrioc->watchdog_work_q_name, 1557 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 1558 mrioc->id); 1559 mrioc->watchdog_work_q = 1560 create_singlethread_workqueue(mrioc->watchdog_work_q_name); 1561 if (!mrioc->watchdog_work_q) { 1562 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 1563 return; 1564 } 1565 1566 if (mrioc->watchdog_work_q) 1567 queue_delayed_work(mrioc->watchdog_work_q, 1568 &mrioc->watchdog_work, 1569 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 1570 } 1571 1572 /** 1573 * mpi3mr_stop_watchdog - Stop watchdog 1574 * @mrioc: Adapter instance reference 1575 * 1576 * Stop the watchdog thread created to monitor controller 1577 * faults. 1578 * 1579 * Return: Nothing. 1580 */ 1581 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 1582 { 1583 unsigned long flags; 1584 struct workqueue_struct *wq; 1585 1586 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 1587 wq = mrioc->watchdog_work_q; 1588 mrioc->watchdog_work_q = NULL; 1589 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 1590 if (wq) { 1591 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 1592 flush_workqueue(wq); 1593 destroy_workqueue(wq); 1594 } 1595 } 1596 1597 /** 1598 * mpi3mr_setup_admin_qpair - Setup admin queue pair 1599 * @mrioc: Adapter instance reference 1600 * 1601 * Allocate memory for admin queue pair if required and register 1602 * the admin queue with the controller. 1603 * 1604 * Return: 0 on success, non-zero on failures. 1605 */ 1606 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 1607 { 1608 int retval = 0; 1609 u32 num_admin_entries = 0; 1610 1611 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 1612 mrioc->num_admin_req = mrioc->admin_req_q_sz / 1613 MPI3MR_ADMIN_REQ_FRAME_SZ; 1614 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 1615 mrioc->admin_req_base = NULL; 1616 1617 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 1618 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 1619 MPI3MR_ADMIN_REPLY_FRAME_SZ; 1620 mrioc->admin_reply_ci = 0; 1621 mrioc->admin_reply_ephase = 1; 1622 mrioc->admin_reply_base = NULL; 1623 1624 if (!mrioc->admin_req_base) { 1625 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 1626 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 1627 1628 if (!mrioc->admin_req_base) { 1629 retval = -1; 1630 goto out_failed; 1631 } 1632 1633 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 1634 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 1635 GFP_KERNEL); 1636 1637 if (!mrioc->admin_reply_base) { 1638 retval = -1; 1639 goto out_failed; 1640 } 1641 } 1642 1643 num_admin_entries = (mrioc->num_admin_replies << 16) | 1644 (mrioc->num_admin_req); 1645 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 1646 mpi3mr_writeq(mrioc->admin_req_dma, 1647 &mrioc->sysif_regs->admin_request_queue_address); 1648 mpi3mr_writeq(mrioc->admin_reply_dma, 1649 &mrioc->sysif_regs->admin_reply_queue_address); 1650 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1651 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 1652 return retval; 1653 1654 out_failed: 1655 1656 if (mrioc->admin_reply_base) { 1657 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 1658 mrioc->admin_reply_base, mrioc->admin_reply_dma); 1659 mrioc->admin_reply_base = NULL; 1660 } 1661 if (mrioc->admin_req_base) { 1662 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 1663 mrioc->admin_req_base, mrioc->admin_req_dma); 1664 mrioc->admin_req_base = NULL; 1665 } 1666 return retval; 1667 } 1668 1669 /** 1670 * mpi3mr_issue_iocfacts - Send IOC Facts 1671 * @mrioc: Adapter instance reference 1672 * @facts_data: Cached IOC facts data 1673 * 1674 * Issue IOC Facts MPI request through admin queue and wait for 1675 * the completion of it or time out. 1676 * 1677 * Return: 0 on success, non-zero on failures. 1678 */ 1679 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 1680 struct mpi3_ioc_facts_data *facts_data) 1681 { 1682 struct mpi3_ioc_facts_request iocfacts_req; 1683 void *data = NULL; 1684 dma_addr_t data_dma; 1685 u32 data_len = sizeof(*facts_data); 1686 int retval = 0; 1687 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 1688 1689 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 1690 GFP_KERNEL); 1691 1692 if (!data) { 1693 retval = -1; 1694 goto out; 1695 } 1696 1697 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 1698 mutex_lock(&mrioc->init_cmds.mutex); 1699 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1700 retval = -1; 1701 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 1702 mutex_unlock(&mrioc->init_cmds.mutex); 1703 goto out; 1704 } 1705 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1706 mrioc->init_cmds.is_waiting = 1; 1707 mrioc->init_cmds.callback = NULL; 1708 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1709 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 1710 1711 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 1712 data_dma); 1713 1714 init_completion(&mrioc->init_cmds.done); 1715 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 1716 sizeof(iocfacts_req), 1); 1717 if (retval) { 1718 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 1719 goto out_unlock; 1720 } 1721 wait_for_completion_timeout(&mrioc->init_cmds.done, 1722 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1723 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1724 ioc_err(mrioc, "Issue IOCFacts: command timed out\n"); 1725 mpi3mr_set_diagsave(mrioc); 1726 mpi3mr_issue_reset(mrioc, 1727 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 1728 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 1729 mrioc->unrecoverable = 1; 1730 retval = -1; 1731 goto out_unlock; 1732 } 1733 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1734 != MPI3_IOCSTATUS_SUCCESS) { 1735 ioc_err(mrioc, 1736 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1737 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1738 mrioc->init_cmds.ioc_loginfo); 1739 retval = -1; 1740 goto out_unlock; 1741 } 1742 memcpy(facts_data, (u8 *)data, data_len); 1743 out_unlock: 1744 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1745 mutex_unlock(&mrioc->init_cmds.mutex); 1746 1747 out: 1748 if (data) 1749 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 1750 1751 return retval; 1752 } 1753 1754 /** 1755 * mpi3mr_check_reset_dma_mask - Process IOC facts data 1756 * @mrioc: Adapter instance reference 1757 * 1758 * Check whether the new DMA mask requested through IOCFacts by 1759 * firmware needs to be set, if so set it . 1760 * 1761 * Return: 0 on success, non-zero on failure. 1762 */ 1763 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 1764 { 1765 struct pci_dev *pdev = mrioc->pdev; 1766 int r; 1767 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 1768 1769 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 1770 return 0; 1771 1772 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 1773 mrioc->dma_mask, facts_dma_mask); 1774 1775 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 1776 if (r) { 1777 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 1778 facts_dma_mask, r); 1779 return r; 1780 } 1781 mrioc->dma_mask = facts_dma_mask; 1782 return r; 1783 } 1784 1785 /** 1786 * mpi3mr_process_factsdata - Process IOC facts data 1787 * @mrioc: Adapter instance reference 1788 * @facts_data: Cached IOC facts data 1789 * 1790 * Convert IOC facts data into cpu endianness and cache it in 1791 * the driver . 1792 * 1793 * Return: Nothing. 1794 */ 1795 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 1796 struct mpi3_ioc_facts_data *facts_data) 1797 { 1798 u32 ioc_config, req_sz, facts_flags; 1799 1800 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 1801 (sizeof(*facts_data) / 4)) { 1802 ioc_warn(mrioc, 1803 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 1804 sizeof(*facts_data), 1805 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 1806 } 1807 1808 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1809 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 1810 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 1811 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 1812 ioc_err(mrioc, 1813 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 1814 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 1815 } 1816 1817 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 1818 1819 facts_flags = le32_to_cpu(facts_data->flags); 1820 mrioc->facts.op_req_sz = req_sz; 1821 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 1822 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 1823 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 1824 1825 mrioc->facts.ioc_num = facts_data->ioc_number; 1826 mrioc->facts.who_init = facts_data->who_init; 1827 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 1828 mrioc->facts.personality = (facts_flags & 1829 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 1830 mrioc->facts.dma_mask = (facts_flags & 1831 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 1832 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 1833 mrioc->facts.protocol_flags = facts_data->protocol_flags; 1834 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 1835 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_request); 1836 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 1837 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 1838 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 1839 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 1840 mrioc->facts.max_pds = le16_to_cpu(facts_data->max_pds); 1841 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 1842 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 1843 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_advanced_host_pds); 1844 mrioc->facts.max_raidpds = le16_to_cpu(facts_data->max_raid_pds); 1845 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 1846 mrioc->facts.max_pcie_switches = 1847 le16_to_cpu(facts_data->max_pc_ie_switches); 1848 mrioc->facts.max_sasexpanders = 1849 le16_to_cpu(facts_data->max_sas_expanders); 1850 mrioc->facts.max_sasinitiators = 1851 le16_to_cpu(facts_data->max_sas_initiators); 1852 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 1853 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 1854 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 1855 mrioc->facts.max_op_req_q = 1856 le16_to_cpu(facts_data->max_operational_request_queues); 1857 mrioc->facts.max_op_reply_q = 1858 le16_to_cpu(facts_data->max_operational_reply_queues); 1859 mrioc->facts.ioc_capabilities = 1860 le32_to_cpu(facts_data->ioc_capabilities); 1861 mrioc->facts.fw_ver.build_num = 1862 le16_to_cpu(facts_data->fw_version.build_num); 1863 mrioc->facts.fw_ver.cust_id = 1864 le16_to_cpu(facts_data->fw_version.customer_id); 1865 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 1866 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 1867 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 1868 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 1869 mrioc->msix_count = min_t(int, mrioc->msix_count, 1870 mrioc->facts.max_msix_vectors); 1871 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 1872 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 1873 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 1874 mrioc->facts.shutdown_timeout = 1875 le16_to_cpu(facts_data->shutdown_timeout); 1876 1877 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 1878 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 1879 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 1880 ioc_info(mrioc, 1881 "maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n", 1882 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 1883 mrioc->facts.max_pds, mrioc->facts.max_msix_vectors, 1884 mrioc->facts.max_perids); 1885 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 1886 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 1887 mrioc->facts.sge_mod_shift); 1888 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n", 1889 mrioc->facts.dma_mask, (facts_flags & 1890 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK)); 1891 1892 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 1893 1894 if (reset_devices) 1895 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 1896 MPI3MR_HOST_IOS_KDUMP); 1897 } 1898 1899 /** 1900 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 1901 * @mrioc: Adapter instance reference 1902 * 1903 * Allocate and initialize the reply free buffers, sense 1904 * buffers, reply free queue and sense buffer queue. 1905 * 1906 * Return: 0 on success, non-zero on failures. 1907 */ 1908 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 1909 { 1910 int retval = 0; 1911 u32 sz, i; 1912 dma_addr_t phy_addr; 1913 1914 if (mrioc->init_cmds.reply) 1915 goto post_reply_sbuf; 1916 1917 mrioc->init_cmds.reply = kzalloc(mrioc->facts.reply_sz, GFP_KERNEL); 1918 if (!mrioc->init_cmds.reply) 1919 goto out_failed; 1920 1921 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 1922 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->facts.reply_sz, 1923 GFP_KERNEL); 1924 if (!mrioc->dev_rmhs_cmds[i].reply) 1925 goto out_failed; 1926 } 1927 1928 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 1929 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 1930 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 1931 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 1932 1933 /* reply buffer pool, 16 byte align */ 1934 sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz; 1935 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 1936 &mrioc->pdev->dev, sz, 16, 0); 1937 if (!mrioc->reply_buf_pool) { 1938 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 1939 goto out_failed; 1940 } 1941 1942 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 1943 &mrioc->reply_buf_dma); 1944 if (!mrioc->reply_buf) 1945 goto out_failed; 1946 1947 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 1948 1949 /* reply free queue, 8 byte align */ 1950 sz = mrioc->reply_free_qsz * 8; 1951 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 1952 &mrioc->pdev->dev, sz, 8, 0); 1953 if (!mrioc->reply_free_q_pool) { 1954 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 1955 goto out_failed; 1956 } 1957 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 1958 GFP_KERNEL, &mrioc->reply_free_q_dma); 1959 if (!mrioc->reply_free_q) 1960 goto out_failed; 1961 1962 /* sense buffer pool, 4 byte align */ 1963 sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; 1964 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 1965 &mrioc->pdev->dev, sz, 4, 0); 1966 if (!mrioc->sense_buf_pool) { 1967 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 1968 goto out_failed; 1969 } 1970 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 1971 &mrioc->sense_buf_dma); 1972 if (!mrioc->sense_buf) 1973 goto out_failed; 1974 1975 /* sense buffer queue, 8 byte align */ 1976 sz = mrioc->sense_buf_q_sz * 8; 1977 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 1978 &mrioc->pdev->dev, sz, 8, 0); 1979 if (!mrioc->sense_buf_q_pool) { 1980 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 1981 goto out_failed; 1982 } 1983 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 1984 GFP_KERNEL, &mrioc->sense_buf_q_dma); 1985 if (!mrioc->sense_buf_q) 1986 goto out_failed; 1987 1988 post_reply_sbuf: 1989 sz = mrioc->num_reply_bufs * mrioc->facts.reply_sz; 1990 ioc_info(mrioc, 1991 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 1992 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->facts.reply_sz, 1993 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 1994 sz = mrioc->reply_free_qsz * 8; 1995 ioc_info(mrioc, 1996 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 1997 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 1998 (unsigned long long)mrioc->reply_free_q_dma); 1999 sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; 2000 ioc_info(mrioc, 2001 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 2002 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSEBUF_SZ, 2003 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 2004 sz = mrioc->sense_buf_q_sz * 8; 2005 ioc_info(mrioc, 2006 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 2007 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 2008 (unsigned long long)mrioc->sense_buf_q_dma); 2009 2010 /* initialize Reply buffer Queue */ 2011 for (i = 0, phy_addr = mrioc->reply_buf_dma; 2012 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->facts.reply_sz) 2013 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 2014 mrioc->reply_free_q[i] = cpu_to_le64(0); 2015 2016 /* initialize Sense Buffer Queue */ 2017 for (i = 0, phy_addr = mrioc->sense_buf_dma; 2018 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSEBUF_SZ) 2019 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 2020 mrioc->sense_buf_q[i] = cpu_to_le64(0); 2021 return retval; 2022 2023 out_failed: 2024 retval = -1; 2025 return retval; 2026 } 2027 2028 /** 2029 * mpi3mr_issue_iocinit - Send IOC Init 2030 * @mrioc: Adapter instance reference 2031 * 2032 * Issue IOC Init MPI request through admin queue and wait for 2033 * the completion of it or time out. 2034 * 2035 * Return: 0 on success, non-zero on failures. 2036 */ 2037 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 2038 { 2039 struct mpi3_ioc_init_request iocinit_req; 2040 struct mpi3_driver_info_layout *drv_info; 2041 dma_addr_t data_dma; 2042 u32 data_len = sizeof(*drv_info); 2043 int retval = 0; 2044 ktime_t current_time; 2045 2046 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2047 GFP_KERNEL); 2048 if (!drv_info) { 2049 retval = -1; 2050 goto out; 2051 } 2052 drv_info->information_length = cpu_to_le32(data_len); 2053 strncpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 2054 strncpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 2055 drv_info->os_name[sizeof(drv_info->os_name) - 1] = 0; 2056 strncpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 2057 drv_info->os_version[sizeof(drv_info->os_version) - 1] = 0; 2058 strncpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 2059 strncpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 2060 strncpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, sizeof(drv_info->driver_release_date)); 2061 drv_info->driver_capabilities = 0; 2062 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 2063 sizeof(mrioc->driver_info)); 2064 2065 memset(&iocinit_req, 0, sizeof(iocinit_req)); 2066 mutex_lock(&mrioc->init_cmds.mutex); 2067 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2068 retval = -1; 2069 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 2070 mutex_unlock(&mrioc->init_cmds.mutex); 2071 goto out; 2072 } 2073 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2074 mrioc->init_cmds.is_waiting = 1; 2075 mrioc->init_cmds.callback = NULL; 2076 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2077 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 2078 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 2079 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 2080 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 2081 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 2082 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 2083 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 2084 iocinit_req.reply_free_queue_address = 2085 cpu_to_le64(mrioc->reply_free_q_dma); 2086 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSEBUF_SZ); 2087 iocinit_req.sense_buffer_free_queue_depth = 2088 cpu_to_le16(mrioc->sense_buf_q_sz); 2089 iocinit_req.sense_buffer_free_queue_address = 2090 cpu_to_le64(mrioc->sense_buf_q_dma); 2091 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 2092 2093 current_time = ktime_get_real(); 2094 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 2095 2096 init_completion(&mrioc->init_cmds.done); 2097 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 2098 sizeof(iocinit_req), 1); 2099 if (retval) { 2100 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 2101 goto out_unlock; 2102 } 2103 wait_for_completion_timeout(&mrioc->init_cmds.done, 2104 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2105 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2106 mpi3mr_set_diagsave(mrioc); 2107 mpi3mr_issue_reset(mrioc, 2108 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2109 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 2110 mrioc->unrecoverable = 1; 2111 ioc_err(mrioc, "Issue IOCInit: command timed out\n"); 2112 retval = -1; 2113 goto out_unlock; 2114 } 2115 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2116 != MPI3_IOCSTATUS_SUCCESS) { 2117 ioc_err(mrioc, 2118 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2119 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2120 mrioc->init_cmds.ioc_loginfo); 2121 retval = -1; 2122 goto out_unlock; 2123 } 2124 2125 out_unlock: 2126 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2127 mutex_unlock(&mrioc->init_cmds.mutex); 2128 2129 out: 2130 if (drv_info) 2131 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 2132 data_dma); 2133 2134 return retval; 2135 } 2136 2137 /** 2138 * mpi3mr_unmask_events - Unmask events in event mask bitmap 2139 * @mrioc: Adapter instance reference 2140 * @event: MPI event ID 2141 * 2142 * Un mask the specific event by resetting the event_mask 2143 * bitmap. 2144 * 2145 * Return: 0 on success, non-zero on failures. 2146 */ 2147 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 2148 { 2149 u32 desired_event; 2150 u8 word; 2151 2152 if (event >= 128) 2153 return; 2154 2155 desired_event = (1 << (event % 32)); 2156 word = event / 32; 2157 2158 mrioc->event_masks[word] &= ~desired_event; 2159 } 2160 2161 /** 2162 * mpi3mr_issue_event_notification - Send event notification 2163 * @mrioc: Adapter instance reference 2164 * 2165 * Issue event notification MPI request through admin queue and 2166 * wait for the completion of it or time out. 2167 * 2168 * Return: 0 on success, non-zero on failures. 2169 */ 2170 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 2171 { 2172 struct mpi3_event_notification_request evtnotify_req; 2173 int retval = 0; 2174 u8 i; 2175 2176 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 2177 mutex_lock(&mrioc->init_cmds.mutex); 2178 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2179 retval = -1; 2180 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 2181 mutex_unlock(&mrioc->init_cmds.mutex); 2182 goto out; 2183 } 2184 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2185 mrioc->init_cmds.is_waiting = 1; 2186 mrioc->init_cmds.callback = NULL; 2187 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2188 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 2189 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2190 evtnotify_req.event_masks[i] = 2191 cpu_to_le32(mrioc->event_masks[i]); 2192 init_completion(&mrioc->init_cmds.done); 2193 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 2194 sizeof(evtnotify_req), 1); 2195 if (retval) { 2196 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 2197 goto out_unlock; 2198 } 2199 wait_for_completion_timeout(&mrioc->init_cmds.done, 2200 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2201 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2202 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 2203 mpi3mr_set_diagsave(mrioc); 2204 mpi3mr_issue_reset(mrioc, 2205 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2206 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 2207 mrioc->unrecoverable = 1; 2208 retval = -1; 2209 goto out_unlock; 2210 } 2211 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2212 != MPI3_IOCSTATUS_SUCCESS) { 2213 ioc_err(mrioc, 2214 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2215 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2216 mrioc->init_cmds.ioc_loginfo); 2217 retval = -1; 2218 goto out_unlock; 2219 } 2220 2221 out_unlock: 2222 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2223 mutex_unlock(&mrioc->init_cmds.mutex); 2224 out: 2225 return retval; 2226 } 2227 2228 /** 2229 * mpi3mr_send_event_ack - Send event acknowledgment 2230 * @mrioc: Adapter instance reference 2231 * @event: MPI3 event ID 2232 * @event_ctx: Event context 2233 * 2234 * Send event acknowledgment through admin queue and wait for 2235 * it to complete. 2236 * 2237 * Return: 0 on success, non-zero on failures. 2238 */ 2239 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 2240 u32 event_ctx) 2241 { 2242 struct mpi3_event_ack_request evtack_req; 2243 int retval = 0; 2244 2245 memset(&evtack_req, 0, sizeof(evtack_req)); 2246 mutex_lock(&mrioc->init_cmds.mutex); 2247 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2248 retval = -1; 2249 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 2250 mutex_unlock(&mrioc->init_cmds.mutex); 2251 goto out; 2252 } 2253 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2254 mrioc->init_cmds.is_waiting = 1; 2255 mrioc->init_cmds.callback = NULL; 2256 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2257 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 2258 evtack_req.event = event; 2259 evtack_req.event_context = cpu_to_le32(event_ctx); 2260 2261 init_completion(&mrioc->init_cmds.done); 2262 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 2263 sizeof(evtack_req), 1); 2264 if (retval) { 2265 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 2266 goto out_unlock; 2267 } 2268 wait_for_completion_timeout(&mrioc->init_cmds.done, 2269 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2270 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2271 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 2272 mpi3mr_soft_reset_handler(mrioc, 2273 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1); 2274 retval = -1; 2275 goto out_unlock; 2276 } 2277 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2278 != MPI3_IOCSTATUS_SUCCESS) { 2279 ioc_err(mrioc, 2280 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2281 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2282 mrioc->init_cmds.ioc_loginfo); 2283 retval = -1; 2284 goto out_unlock; 2285 } 2286 2287 out_unlock: 2288 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2289 mutex_unlock(&mrioc->init_cmds.mutex); 2290 out: 2291 return retval; 2292 } 2293 2294 /** 2295 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 2296 * @mrioc: Adapter instance reference 2297 * 2298 * Allocate chain buffers and set a bitmap to indicate free 2299 * chain buffers. Chain buffers are used to pass the SGE 2300 * information along with MPI3 SCSI IO requests for host I/O. 2301 * 2302 * Return: 0 on success, non-zero on failure 2303 */ 2304 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 2305 { 2306 int retval = 0; 2307 u32 sz, i; 2308 u16 num_chains; 2309 2310 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 2311 2312 mrioc->chain_buf_count = num_chains; 2313 sz = sizeof(struct chain_element) * num_chains; 2314 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 2315 if (!mrioc->chain_sgl_list) 2316 goto out_failed; 2317 2318 sz = MPI3MR_PAGE_SIZE_4K; 2319 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 2320 &mrioc->pdev->dev, sz, 16, 0); 2321 if (!mrioc->chain_buf_pool) { 2322 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 2323 goto out_failed; 2324 } 2325 2326 for (i = 0; i < num_chains; i++) { 2327 mrioc->chain_sgl_list[i].addr = 2328 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 2329 &mrioc->chain_sgl_list[i].dma_addr); 2330 2331 if (!mrioc->chain_sgl_list[i].addr) 2332 goto out_failed; 2333 } 2334 mrioc->chain_bitmap_sz = num_chains / 8; 2335 if (num_chains % 8) 2336 mrioc->chain_bitmap_sz++; 2337 mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL); 2338 if (!mrioc->chain_bitmap) 2339 goto out_failed; 2340 return retval; 2341 out_failed: 2342 retval = -1; 2343 return retval; 2344 } 2345 2346 /** 2347 * mpi3mr_port_enable_complete - Mark port enable complete 2348 * @mrioc: Adapter instance reference 2349 * @drv_cmd: Internal command tracker 2350 * 2351 * Call back for asynchronous port enable request sets the 2352 * driver command to indicate port enable request is complete. 2353 * 2354 * Return: Nothing 2355 */ 2356 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 2357 struct mpi3mr_drv_cmd *drv_cmd) 2358 { 2359 drv_cmd->state = MPI3MR_CMD_NOTUSED; 2360 drv_cmd->callback = NULL; 2361 mrioc->scan_failed = drv_cmd->ioc_status; 2362 mrioc->scan_started = 0; 2363 } 2364 2365 /** 2366 * mpi3mr_issue_port_enable - Issue Port Enable 2367 * @mrioc: Adapter instance reference 2368 * @async: Flag to wait for completion or not 2369 * 2370 * Issue Port Enable MPI request through admin queue and if the 2371 * async flag is not set wait for the completion of the port 2372 * enable or time out. 2373 * 2374 * Return: 0 on success, non-zero on failures. 2375 */ 2376 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 2377 { 2378 struct mpi3_port_enable_request pe_req; 2379 int retval = 0; 2380 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 2381 2382 memset(&pe_req, 0, sizeof(pe_req)); 2383 mutex_lock(&mrioc->init_cmds.mutex); 2384 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2385 retval = -1; 2386 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 2387 mutex_unlock(&mrioc->init_cmds.mutex); 2388 goto out; 2389 } 2390 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2391 if (async) { 2392 mrioc->init_cmds.is_waiting = 0; 2393 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 2394 } else { 2395 mrioc->init_cmds.is_waiting = 1; 2396 mrioc->init_cmds.callback = NULL; 2397 init_completion(&mrioc->init_cmds.done); 2398 } 2399 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2400 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 2401 2402 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 2403 if (retval) { 2404 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 2405 goto out_unlock; 2406 } 2407 if (!async) { 2408 wait_for_completion_timeout(&mrioc->init_cmds.done, 2409 (pe_timeout * HZ)); 2410 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2411 ioc_err(mrioc, "Issue PortEnable: command timed out\n"); 2412 retval = -1; 2413 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR; 2414 mpi3mr_set_diagsave(mrioc); 2415 mpi3mr_issue_reset(mrioc, 2416 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2417 MPI3MR_RESET_FROM_PE_TIMEOUT); 2418 mrioc->unrecoverable = 1; 2419 goto out_unlock; 2420 } 2421 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 2422 } 2423 out_unlock: 2424 mutex_unlock(&mrioc->init_cmds.mutex); 2425 out: 2426 return retval; 2427 } 2428 2429 /** 2430 * mpi3mr_cleanup_resources - Free PCI resources 2431 * @mrioc: Adapter instance reference 2432 * 2433 * Unmap PCI device memory and disable PCI device. 2434 * 2435 * Return: 0 on success and non-zero on failure. 2436 */ 2437 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 2438 { 2439 struct pci_dev *pdev = mrioc->pdev; 2440 2441 mpi3mr_cleanup_isr(mrioc); 2442 2443 if (mrioc->sysif_regs) { 2444 iounmap((void __iomem *)mrioc->sysif_regs); 2445 mrioc->sysif_regs = NULL; 2446 } 2447 2448 if (pci_is_enabled(pdev)) { 2449 if (mrioc->bars) 2450 pci_release_selected_regions(pdev, mrioc->bars); 2451 pci_disable_device(pdev); 2452 } 2453 } 2454 2455 /** 2456 * mpi3mr_setup_resources - Enable PCI resources 2457 * @mrioc: Adapter instance reference 2458 * 2459 * Enable PCI device memory, MSI-x registers and set DMA mask. 2460 * 2461 * Return: 0 on success and non-zero on failure. 2462 */ 2463 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 2464 { 2465 struct pci_dev *pdev = mrioc->pdev; 2466 u32 memap_sz = 0; 2467 int i, retval = 0, capb = 0; 2468 u16 message_control; 2469 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 2470 (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) && 2471 (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 2472 2473 if (pci_enable_device_mem(pdev)) { 2474 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 2475 retval = -ENODEV; 2476 goto out_failed; 2477 } 2478 2479 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 2480 if (!capb) { 2481 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 2482 retval = -ENODEV; 2483 goto out_failed; 2484 } 2485 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 2486 2487 if (pci_request_selected_regions(pdev, mrioc->bars, 2488 mrioc->driver_name)) { 2489 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 2490 retval = -ENODEV; 2491 goto out_failed; 2492 } 2493 2494 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 2495 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 2496 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 2497 memap_sz = pci_resource_len(pdev, i); 2498 mrioc->sysif_regs = 2499 ioremap(mrioc->sysif_regs_phys, memap_sz); 2500 break; 2501 } 2502 } 2503 2504 pci_set_master(pdev); 2505 2506 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 2507 if (retval) { 2508 if (dma_mask != DMA_BIT_MASK(32)) { 2509 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 2510 dma_mask = DMA_BIT_MASK(32); 2511 retval = dma_set_mask_and_coherent(&pdev->dev, 2512 dma_mask); 2513 } 2514 if (retval) { 2515 mrioc->dma_mask = 0; 2516 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 2517 goto out_failed; 2518 } 2519 } 2520 mrioc->dma_mask = dma_mask; 2521 2522 if (!mrioc->sysif_regs) { 2523 ioc_err(mrioc, 2524 "Unable to map adapter memory or resource not found\n"); 2525 retval = -EINVAL; 2526 goto out_failed; 2527 } 2528 2529 pci_read_config_word(pdev, capb + 2, &message_control); 2530 mrioc->msix_count = (message_control & 0x3FF) + 1; 2531 2532 pci_save_state(pdev); 2533 2534 pci_set_drvdata(pdev, mrioc->shost); 2535 2536 mpi3mr_ioc_disable_intr(mrioc); 2537 2538 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 2539 (unsigned long long)mrioc->sysif_regs_phys, 2540 mrioc->sysif_regs, memap_sz); 2541 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 2542 mrioc->msix_count); 2543 return retval; 2544 2545 out_failed: 2546 mpi3mr_cleanup_resources(mrioc); 2547 return retval; 2548 } 2549 2550 /** 2551 * mpi3mr_init_ioc - Initialize the controller 2552 * @mrioc: Adapter instance reference 2553 * 2554 * This the controller initialization routine, executed either 2555 * after soft reset or from pci probe callback. 2556 * Setup the required resources, memory map the controller 2557 * registers, create admin and operational reply queue pairs, 2558 * allocate required memory for reply pool, sense buffer pool, 2559 * issue IOC init request to the firmware, unmask the events and 2560 * issue port enable to discover SAS/SATA/NVMe devies and RAID 2561 * volumes. 2562 * 2563 * Return: 0 on success and non-zero on failure. 2564 */ 2565 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 2566 { 2567 int retval = 0; 2568 enum mpi3mr_iocstate ioc_state; 2569 u64 base_info; 2570 u32 timeout; 2571 u32 ioc_status, ioc_config, i; 2572 struct mpi3_ioc_facts_data facts_data; 2573 2574 mrioc->change_count = 0; 2575 mrioc->cpu_count = num_online_cpus(); 2576 retval = mpi3mr_setup_resources(mrioc); 2577 if (retval) { 2578 ioc_err(mrioc, "Failed to setup resources:error %d\n", 2579 retval); 2580 goto out_nocleanup; 2581 } 2582 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2583 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2584 2585 ioc_info(mrioc, "SOD status %x configuration %x\n", 2586 ioc_status, ioc_config); 2587 2588 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 2589 ioc_info(mrioc, "SOD base_info %llx\n", base_info); 2590 2591 /*The timeout value is in 2sec unit, changing it to seconds*/ 2592 mrioc->ready_timeout = 2593 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 2594 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 2595 2596 ioc_info(mrioc, "IOC ready timeout %d\n", mrioc->ready_timeout); 2597 2598 ioc_state = mpi3mr_get_iocstate(mrioc); 2599 ioc_info(mrioc, "IOC in %s state during detection\n", 2600 mpi3mr_iocstate_name(ioc_state)); 2601 2602 if (ioc_state == MRIOC_STATE_BECOMING_READY || 2603 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 2604 timeout = mrioc->ready_timeout * 10; 2605 do { 2606 msleep(100); 2607 } while (--timeout); 2608 2609 ioc_state = mpi3mr_get_iocstate(mrioc); 2610 ioc_info(mrioc, 2611 "IOC in %s state after waiting for reset time\n", 2612 mpi3mr_iocstate_name(ioc_state)); 2613 } 2614 2615 if (ioc_state == MRIOC_STATE_READY) { 2616 retval = mpi3mr_issue_and_process_mur(mrioc, 2617 MPI3MR_RESET_FROM_BRINGUP); 2618 if (retval) { 2619 ioc_err(mrioc, "Failed to MU reset IOC error %d\n", 2620 retval); 2621 } 2622 ioc_state = mpi3mr_get_iocstate(mrioc); 2623 } 2624 if (ioc_state != MRIOC_STATE_RESET) { 2625 mpi3mr_print_fault_info(mrioc); 2626 retval = mpi3mr_issue_reset(mrioc, 2627 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 2628 MPI3MR_RESET_FROM_BRINGUP); 2629 if (retval) { 2630 ioc_err(mrioc, 2631 "%s :Failed to soft reset IOC error %d\n", 2632 __func__, retval); 2633 goto out_failed; 2634 } 2635 } 2636 ioc_state = mpi3mr_get_iocstate(mrioc); 2637 if (ioc_state != MRIOC_STATE_RESET) { 2638 ioc_err(mrioc, "Cannot bring IOC to reset state\n"); 2639 goto out_failed; 2640 } 2641 2642 retval = mpi3mr_setup_admin_qpair(mrioc); 2643 if (retval) { 2644 ioc_err(mrioc, "Failed to setup admin Qs: error %d\n", 2645 retval); 2646 goto out_failed; 2647 } 2648 2649 retval = mpi3mr_bring_ioc_ready(mrioc); 2650 if (retval) { 2651 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 2652 retval); 2653 goto out_failed; 2654 } 2655 2656 retval = mpi3mr_setup_isr(mrioc, 1); 2657 if (retval) { 2658 ioc_err(mrioc, "Failed to setup ISR error %d\n", 2659 retval); 2660 goto out_failed; 2661 } 2662 2663 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 2664 if (retval) { 2665 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 2666 retval); 2667 goto out_failed; 2668 } 2669 2670 mpi3mr_process_factsdata(mrioc, &facts_data); 2671 retval = mpi3mr_check_reset_dma_mask(mrioc); 2672 if (retval) { 2673 ioc_err(mrioc, "Resetting dma mask failed %d\n", 2674 retval); 2675 goto out_failed; 2676 } 2677 2678 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 2679 if (retval) { 2680 ioc_err(mrioc, 2681 "%s :Failed to allocated reply sense buffers %d\n", 2682 __func__, retval); 2683 goto out_failed; 2684 } 2685 2686 retval = mpi3mr_alloc_chain_bufs(mrioc); 2687 if (retval) { 2688 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 2689 retval); 2690 goto out_failed; 2691 } 2692 2693 retval = mpi3mr_issue_iocinit(mrioc); 2694 if (retval) { 2695 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 2696 retval); 2697 goto out_failed; 2698 } 2699 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 2700 writel(mrioc->reply_free_queue_host_index, 2701 &mrioc->sysif_regs->reply_free_host_index); 2702 2703 mrioc->sbq_host_index = mrioc->num_sense_bufs; 2704 writel(mrioc->sbq_host_index, 2705 &mrioc->sysif_regs->sense_buffer_free_host_index); 2706 2707 retval = mpi3mr_setup_isr(mrioc, 0); 2708 if (retval) { 2709 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 2710 retval); 2711 goto out_failed; 2712 } 2713 2714 retval = mpi3mr_create_op_queues(mrioc); 2715 if (retval) { 2716 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 2717 retval); 2718 goto out_failed; 2719 } 2720 2721 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2722 mrioc->event_masks[i] = -1; 2723 2724 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 2725 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 2726 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 2727 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 2728 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 2729 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 2730 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 2731 2732 retval = mpi3mr_issue_event_notification(mrioc); 2733 if (retval) { 2734 ioc_err(mrioc, "Failed to issue event notification %d\n", 2735 retval); 2736 goto out_failed; 2737 } 2738 2739 return retval; 2740 2741 out_failed: 2742 mpi3mr_cleanup_ioc(mrioc); 2743 out_nocleanup: 2744 return retval; 2745 } 2746 2747 /** 2748 * mpi3mr_free_mem - Free memory allocated for a controller 2749 * @mrioc: Adapter instance reference 2750 * 2751 * Free all the memory allocated for a controller. 2752 * 2753 * Return: Nothing. 2754 */ 2755 static void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 2756 { 2757 u16 i; 2758 struct mpi3mr_intr_info *intr_info; 2759 2760 if (mrioc->sense_buf_pool) { 2761 if (mrioc->sense_buf) 2762 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 2763 mrioc->sense_buf_dma); 2764 dma_pool_destroy(mrioc->sense_buf_pool); 2765 mrioc->sense_buf = NULL; 2766 mrioc->sense_buf_pool = NULL; 2767 } 2768 if (mrioc->sense_buf_q_pool) { 2769 if (mrioc->sense_buf_q) 2770 dma_pool_free(mrioc->sense_buf_q_pool, 2771 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 2772 dma_pool_destroy(mrioc->sense_buf_q_pool); 2773 mrioc->sense_buf_q = NULL; 2774 mrioc->sense_buf_q_pool = NULL; 2775 } 2776 2777 if (mrioc->reply_buf_pool) { 2778 if (mrioc->reply_buf) 2779 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 2780 mrioc->reply_buf_dma); 2781 dma_pool_destroy(mrioc->reply_buf_pool); 2782 mrioc->reply_buf = NULL; 2783 mrioc->reply_buf_pool = NULL; 2784 } 2785 if (mrioc->reply_free_q_pool) { 2786 if (mrioc->reply_free_q) 2787 dma_pool_free(mrioc->reply_free_q_pool, 2788 mrioc->reply_free_q, mrioc->reply_free_q_dma); 2789 dma_pool_destroy(mrioc->reply_free_q_pool); 2790 mrioc->reply_free_q = NULL; 2791 mrioc->reply_free_q_pool = NULL; 2792 } 2793 2794 for (i = 0; i < mrioc->num_op_req_q; i++) 2795 mpi3mr_free_op_req_q_segments(mrioc, i); 2796 2797 for (i = 0; i < mrioc->num_op_reply_q; i++) 2798 mpi3mr_free_op_reply_q_segments(mrioc, i); 2799 2800 for (i = 0; i < mrioc->intr_info_count; i++) { 2801 intr_info = mrioc->intr_info + i; 2802 if (intr_info) 2803 intr_info->op_reply_q = NULL; 2804 } 2805 2806 kfree(mrioc->req_qinfo); 2807 mrioc->req_qinfo = NULL; 2808 mrioc->num_op_req_q = 0; 2809 2810 kfree(mrioc->op_reply_qinfo); 2811 mrioc->op_reply_qinfo = NULL; 2812 mrioc->num_op_reply_q = 0; 2813 2814 kfree(mrioc->init_cmds.reply); 2815 mrioc->init_cmds.reply = NULL; 2816 2817 kfree(mrioc->chain_bitmap); 2818 mrioc->chain_bitmap = NULL; 2819 2820 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2821 kfree(mrioc->dev_rmhs_cmds[i].reply); 2822 mrioc->dev_rmhs_cmds[i].reply = NULL; 2823 } 2824 2825 if (mrioc->chain_buf_pool) { 2826 for (i = 0; i < mrioc->chain_buf_count; i++) { 2827 if (mrioc->chain_sgl_list[i].addr) { 2828 dma_pool_free(mrioc->chain_buf_pool, 2829 mrioc->chain_sgl_list[i].addr, 2830 mrioc->chain_sgl_list[i].dma_addr); 2831 mrioc->chain_sgl_list[i].addr = NULL; 2832 } 2833 } 2834 dma_pool_destroy(mrioc->chain_buf_pool); 2835 mrioc->chain_buf_pool = NULL; 2836 } 2837 2838 kfree(mrioc->chain_sgl_list); 2839 mrioc->chain_sgl_list = NULL; 2840 2841 if (mrioc->admin_reply_base) { 2842 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2843 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2844 mrioc->admin_reply_base = NULL; 2845 } 2846 if (mrioc->admin_req_base) { 2847 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2848 mrioc->admin_req_base, mrioc->admin_req_dma); 2849 mrioc->admin_req_base = NULL; 2850 } 2851 } 2852 2853 /** 2854 * mpi3mr_issue_ioc_shutdown - shutdown controller 2855 * @mrioc: Adapter instance reference 2856 * 2857 * Send shutodwn notification to the controller and wait for the 2858 * shutdown_timeout for it to be completed. 2859 * 2860 * Return: Nothing. 2861 */ 2862 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 2863 { 2864 u32 ioc_config, ioc_status; 2865 u8 retval = 1; 2866 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 2867 2868 ioc_info(mrioc, "Issuing shutdown Notification\n"); 2869 if (mrioc->unrecoverable) { 2870 ioc_warn(mrioc, 2871 "IOC is unrecoverable shutdown is not issued\n"); 2872 return; 2873 } 2874 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2875 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 2876 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 2877 ioc_info(mrioc, "shutdown already in progress\n"); 2878 return; 2879 } 2880 2881 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2882 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 2883 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN; 2884 2885 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 2886 2887 if (mrioc->facts.shutdown_timeout) 2888 timeout = mrioc->facts.shutdown_timeout * 10; 2889 2890 do { 2891 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2892 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 2893 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 2894 retval = 0; 2895 break; 2896 } 2897 msleep(100); 2898 } while (--timeout); 2899 2900 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2901 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2902 2903 if (retval) { 2904 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 2905 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 2906 ioc_warn(mrioc, 2907 "shutdown still in progress after timeout\n"); 2908 } 2909 2910 ioc_info(mrioc, 2911 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 2912 (!retval) ? "successful" : "failed", ioc_status, 2913 ioc_config); 2914 } 2915 2916 /** 2917 * mpi3mr_cleanup_ioc - Cleanup controller 2918 * @mrioc: Adapter instance reference 2919 * 2920 * controller cleanup handler, Message unit reset or soft reset 2921 * and shutdown notification is issued to the controller and the 2922 * associated memory resources are freed. 2923 * 2924 * Return: Nothing. 2925 */ 2926 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 2927 { 2928 enum mpi3mr_iocstate ioc_state; 2929 2930 mpi3mr_stop_watchdog(mrioc); 2931 2932 mpi3mr_ioc_disable_intr(mrioc); 2933 2934 ioc_state = mpi3mr_get_iocstate(mrioc); 2935 2936 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) && 2937 (ioc_state == MRIOC_STATE_READY)) { 2938 if (mpi3mr_issue_and_process_mur(mrioc, 2939 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 2940 mpi3mr_issue_reset(mrioc, 2941 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 2942 MPI3MR_RESET_FROM_MUR_FAILURE); 2943 2944 mpi3mr_issue_ioc_shutdown(mrioc); 2945 } 2946 2947 mpi3mr_free_mem(mrioc); 2948 mpi3mr_cleanup_resources(mrioc); 2949 } 2950 2951 /** 2952 * mpi3mr_soft_reset_handler - Reset the controller 2953 * @mrioc: Adapter instance reference 2954 * @reset_reason: Reset reason code 2955 * @snapdump: Flag to generate snapdump in firmware or not 2956 * 2957 * TBD 2958 * 2959 * Return: 0 on success, non-zero on failure. 2960 */ 2961 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 2962 u32 reset_reason, u8 snapdump) 2963 { 2964 return 0; 2965 } 2966