1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #include "mpi3mr.h" 11 #include <linux/io-64-nonatomic-lo-hi.h> 12 13 static int 14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason); 15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); 16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 17 struct mpi3_ioc_facts_data *facts_data); 18 19 static int poll_queues; 20 module_param(poll_queues, int, 0444); 21 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); 22 23 #if defined(writeq) && defined(CONFIG_64BIT) 24 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 25 { 26 writeq(b, addr); 27 } 28 #else 29 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) 30 { 31 __u64 data_out = b; 32 33 writel((u32)(data_out), addr); 34 writel((u32)(data_out >> 32), (addr + 4)); 35 } 36 #endif 37 38 static inline bool 39 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q) 40 { 41 u16 pi, ci, max_entries; 42 bool is_qfull = false; 43 44 pi = op_req_q->pi; 45 ci = READ_ONCE(op_req_q->ci); 46 max_entries = op_req_q->num_requests; 47 48 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 49 is_qfull = true; 50 51 return is_qfull; 52 } 53 54 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc) 55 { 56 u16 i, max_vectors; 57 58 max_vectors = mrioc->intr_info_count; 59 60 for (i = 0; i < max_vectors; i++) 61 synchronize_irq(pci_irq_vector(mrioc->pdev, i)); 62 } 63 64 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc) 65 { 66 mrioc->intr_enabled = 0; 67 mpi3mr_sync_irqs(mrioc); 68 } 69 70 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc) 71 { 72 mrioc->intr_enabled = 1; 73 } 74 75 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc) 76 { 77 u16 i; 78 79 mpi3mr_ioc_disable_intr(mrioc); 80 81 if (!mrioc->intr_info) 82 return; 83 84 for (i = 0; i < mrioc->intr_info_count; i++) 85 free_irq(pci_irq_vector(mrioc->pdev, i), 86 (mrioc->intr_info + i)); 87 88 kfree(mrioc->intr_info); 89 mrioc->intr_info = NULL; 90 mrioc->intr_info_count = 0; 91 mrioc->is_intr_info_set = false; 92 pci_free_irq_vectors(mrioc->pdev); 93 } 94 95 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 96 dma_addr_t dma_addr) 97 { 98 struct mpi3_sge_common *sgel = paddr; 99 100 sgel->flags = flags; 101 sgel->length = cpu_to_le32(length); 102 sgel->address = cpu_to_le64(dma_addr); 103 } 104 105 void mpi3mr_build_zero_len_sge(void *paddr) 106 { 107 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 108 109 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 110 } 111 112 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 113 dma_addr_t phys_addr) 114 { 115 if (!phys_addr) 116 return NULL; 117 118 if ((phys_addr < mrioc->reply_buf_dma) || 119 (phys_addr > mrioc->reply_buf_dma_max_address)) 120 return NULL; 121 122 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma); 123 } 124 125 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 126 dma_addr_t phys_addr) 127 { 128 if (!phys_addr) 129 return NULL; 130 131 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma); 132 } 133 134 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc, 135 u64 reply_dma) 136 { 137 u32 old_idx = 0; 138 unsigned long flags; 139 140 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags); 141 old_idx = mrioc->reply_free_queue_host_index; 142 mrioc->reply_free_queue_host_index = ( 143 (mrioc->reply_free_queue_host_index == 144 (mrioc->reply_free_qsz - 1)) ? 0 : 145 (mrioc->reply_free_queue_host_index + 1)); 146 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma); 147 writel(mrioc->reply_free_queue_host_index, 148 &mrioc->sysif_regs->reply_free_host_index); 149 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags); 150 } 151 152 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 153 u64 sense_buf_dma) 154 { 155 u32 old_idx = 0; 156 unsigned long flags; 157 158 spin_lock_irqsave(&mrioc->sbq_lock, flags); 159 old_idx = mrioc->sbq_host_index; 160 mrioc->sbq_host_index = ((mrioc->sbq_host_index == 161 (mrioc->sense_buf_q_sz - 1)) ? 0 : 162 (mrioc->sbq_host_index + 1)); 163 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma); 164 writel(mrioc->sbq_host_index, 165 &mrioc->sysif_regs->sense_buffer_free_host_index); 166 spin_unlock_irqrestore(&mrioc->sbq_lock, flags); 167 } 168 169 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc, 170 struct mpi3_event_notification_reply *event_reply) 171 { 172 char *desc = NULL; 173 u16 event; 174 175 event = event_reply->event; 176 177 switch (event) { 178 case MPI3_EVENT_LOG_DATA: 179 desc = "Log Data"; 180 break; 181 case MPI3_EVENT_CHANGE: 182 desc = "Event Change"; 183 break; 184 case MPI3_EVENT_GPIO_INTERRUPT: 185 desc = "GPIO Interrupt"; 186 break; 187 case MPI3_EVENT_CABLE_MGMT: 188 desc = "Cable Management"; 189 break; 190 case MPI3_EVENT_ENERGY_PACK_CHANGE: 191 desc = "Energy Pack Change"; 192 break; 193 case MPI3_EVENT_DEVICE_ADDED: 194 { 195 struct mpi3_device_page0 *event_data = 196 (struct mpi3_device_page0 *)event_reply->event_data; 197 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n", 198 event_data->dev_handle, event_data->device_form); 199 return; 200 } 201 case MPI3_EVENT_DEVICE_INFO_CHANGED: 202 { 203 struct mpi3_device_page0 *event_data = 204 (struct mpi3_device_page0 *)event_reply->event_data; 205 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n", 206 event_data->dev_handle, event_data->device_form); 207 return; 208 } 209 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 210 { 211 struct mpi3_event_data_device_status_change *event_data = 212 (struct mpi3_event_data_device_status_change *)event_reply->event_data; 213 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n", 214 event_data->dev_handle, event_data->reason_code); 215 return; 216 } 217 case MPI3_EVENT_SAS_DISCOVERY: 218 { 219 struct mpi3_event_data_sas_discovery *event_data = 220 (struct mpi3_event_data_sas_discovery *)event_reply->event_data; 221 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n", 222 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 223 "start" : "stop", 224 le32_to_cpu(event_data->discovery_status)); 225 return; 226 } 227 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 228 desc = "SAS Broadcast Primitive"; 229 break; 230 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 231 desc = "SAS Notify Primitive"; 232 break; 233 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 234 desc = "SAS Init Device Status Change"; 235 break; 236 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 237 desc = "SAS Init Table Overflow"; 238 break; 239 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 240 desc = "SAS Topology Change List"; 241 break; 242 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 243 desc = "Enclosure Device Status Change"; 244 break; 245 case MPI3_EVENT_HARD_RESET_RECEIVED: 246 desc = "Hard Reset Received"; 247 break; 248 case MPI3_EVENT_SAS_PHY_COUNTER: 249 desc = "SAS PHY Counter"; 250 break; 251 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 252 desc = "SAS Device Discovery Error"; 253 break; 254 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 255 desc = "PCIE Topology Change List"; 256 break; 257 case MPI3_EVENT_PCIE_ENUMERATION: 258 { 259 struct mpi3_event_data_pcie_enumeration *event_data = 260 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data; 261 ioc_info(mrioc, "PCIE Enumeration: (%s)", 262 (event_data->reason_code == 263 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop"); 264 if (event_data->enumeration_status) 265 ioc_info(mrioc, "enumeration_status(0x%08x)\n", 266 le32_to_cpu(event_data->enumeration_status)); 267 return; 268 } 269 case MPI3_EVENT_PREPARE_FOR_RESET: 270 desc = "Prepare For Reset"; 271 break; 272 } 273 274 if (!desc) 275 return; 276 277 ioc_info(mrioc, "%s\n", desc); 278 } 279 280 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc, 281 struct mpi3_default_reply *def_reply) 282 { 283 struct mpi3_event_notification_reply *event_reply = 284 (struct mpi3_event_notification_reply *)def_reply; 285 286 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count); 287 mpi3mr_print_event_data(mrioc, event_reply); 288 mpi3mr_os_handle_events(mrioc, event_reply); 289 } 290 291 static struct mpi3mr_drv_cmd * 292 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag, 293 struct mpi3_default_reply *def_reply) 294 { 295 u16 idx; 296 297 switch (host_tag) { 298 case MPI3MR_HOSTTAG_INITCMDS: 299 return &mrioc->init_cmds; 300 case MPI3MR_HOSTTAG_BLK_TMS: 301 return &mrioc->host_tm_cmds; 302 case MPI3MR_HOSTTAG_INVALID: 303 if (def_reply && def_reply->function == 304 MPI3_FUNCTION_EVENT_NOTIFICATION) 305 mpi3mr_handle_events(mrioc, def_reply); 306 return NULL; 307 default: 308 break; 309 } 310 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 311 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) { 312 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 313 return &mrioc->dev_rmhs_cmds[idx]; 314 } 315 316 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 317 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 318 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 319 return &mrioc->evtack_cmds[idx]; 320 } 321 322 return NULL; 323 } 324 325 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc, 326 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma) 327 { 328 u16 reply_desc_type, host_tag = 0; 329 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 330 u32 ioc_loginfo = 0; 331 struct mpi3_status_reply_descriptor *status_desc; 332 struct mpi3_address_reply_descriptor *addr_desc; 333 struct mpi3_success_reply_descriptor *success_desc; 334 struct mpi3_default_reply *def_reply = NULL; 335 struct mpi3mr_drv_cmd *cmdptr = NULL; 336 struct mpi3_scsi_io_reply *scsi_reply; 337 u8 *sense_buf = NULL; 338 339 *reply_dma = 0; 340 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) & 341 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 342 switch (reply_desc_type) { 343 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 344 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc; 345 host_tag = le16_to_cpu(status_desc->host_tag); 346 ioc_status = le16_to_cpu(status_desc->ioc_status); 347 if (ioc_status & 348 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 349 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info); 350 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 351 break; 352 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 353 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc; 354 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address); 355 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma); 356 if (!def_reply) 357 goto out; 358 host_tag = le16_to_cpu(def_reply->host_tag); 359 ioc_status = le16_to_cpu(def_reply->ioc_status); 360 if (ioc_status & 361 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 362 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info); 363 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 364 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) { 365 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply; 366 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc, 367 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 368 } 369 break; 370 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 371 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc; 372 host_tag = le16_to_cpu(success_desc->host_tag); 373 break; 374 default: 375 break; 376 } 377 378 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply); 379 if (cmdptr) { 380 if (cmdptr->state & MPI3MR_CMD_PENDING) { 381 cmdptr->state |= MPI3MR_CMD_COMPLETE; 382 cmdptr->ioc_loginfo = ioc_loginfo; 383 cmdptr->ioc_status = ioc_status; 384 cmdptr->state &= ~MPI3MR_CMD_PENDING; 385 if (def_reply) { 386 cmdptr->state |= MPI3MR_CMD_REPLY_VALID; 387 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply, 388 mrioc->reply_sz); 389 } 390 if (cmdptr->is_waiting) { 391 complete(&cmdptr->done); 392 cmdptr->is_waiting = 0; 393 } else if (cmdptr->callback) 394 cmdptr->callback(mrioc, cmdptr); 395 } 396 } 397 out: 398 if (sense_buf) 399 mpi3mr_repost_sense_buf(mrioc, 400 le64_to_cpu(scsi_reply->sense_data_buffer_address)); 401 } 402 403 static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc) 404 { 405 u32 exp_phase = mrioc->admin_reply_ephase; 406 u32 admin_reply_ci = mrioc->admin_reply_ci; 407 u32 num_admin_replies = 0; 408 u64 reply_dma = 0; 409 struct mpi3_default_reply_descriptor *reply_desc; 410 411 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 412 admin_reply_ci; 413 414 if ((le16_to_cpu(reply_desc->reply_flags) & 415 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 416 return 0; 417 418 do { 419 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci); 420 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma); 421 if (reply_dma) 422 mpi3mr_repost_reply_buf(mrioc, reply_dma); 423 num_admin_replies++; 424 if (++admin_reply_ci == mrioc->num_admin_replies) { 425 admin_reply_ci = 0; 426 exp_phase ^= 1; 427 } 428 reply_desc = 429 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base + 430 admin_reply_ci; 431 if ((le16_to_cpu(reply_desc->reply_flags) & 432 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 433 break; 434 } while (1); 435 436 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 437 mrioc->admin_reply_ci = admin_reply_ci; 438 mrioc->admin_reply_ephase = exp_phase; 439 440 return num_admin_replies; 441 } 442 443 /** 444 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to 445 * queue's consumer index from operational reply descriptor queue. 446 * @op_reply_q: op_reply_qinfo object 447 * @reply_ci: operational reply descriptor's queue consumer index 448 * 449 * Returns reply descriptor frame address 450 */ 451 static inline struct mpi3_default_reply_descriptor * 452 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci) 453 { 454 void *segment_base_addr; 455 struct segments *segments = op_reply_q->q_segments; 456 struct mpi3_default_reply_descriptor *reply_desc = NULL; 457 458 segment_base_addr = 459 segments[reply_ci / op_reply_q->segment_qd].segment; 460 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr + 461 (reply_ci % op_reply_q->segment_qd); 462 return reply_desc; 463 } 464 465 /** 466 * mpi3mr_process_op_reply_q - Operational reply queue handler 467 * @mrioc: Adapter instance reference 468 * @op_reply_q: Operational reply queue info 469 * 470 * Checks the specific operational reply queue and drains the 471 * reply queue entries until the queue is empty and process the 472 * individual reply descriptors. 473 * 474 * Return: 0 if queue is already processed,or number of reply 475 * descriptors processed. 476 */ 477 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 478 struct op_reply_qinfo *op_reply_q) 479 { 480 struct op_req_qinfo *op_req_q; 481 u32 exp_phase; 482 u32 reply_ci; 483 u32 num_op_reply = 0; 484 u64 reply_dma = 0; 485 struct mpi3_default_reply_descriptor *reply_desc; 486 u16 req_q_idx = 0, reply_qidx; 487 488 reply_qidx = op_reply_q->qid - 1; 489 490 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1)) 491 return 0; 492 493 exp_phase = op_reply_q->ephase; 494 reply_ci = op_reply_q->ci; 495 496 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 497 if ((le16_to_cpu(reply_desc->reply_flags) & 498 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 499 atomic_dec(&op_reply_q->in_use); 500 return 0; 501 } 502 503 do { 504 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1; 505 op_req_q = &mrioc->req_qinfo[req_q_idx]; 506 507 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci)); 508 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma, 509 reply_qidx); 510 atomic_dec(&op_reply_q->pend_ios); 511 if (reply_dma) 512 mpi3mr_repost_reply_buf(mrioc, reply_dma); 513 num_op_reply++; 514 515 if (++reply_ci == op_reply_q->num_replies) { 516 reply_ci = 0; 517 exp_phase ^= 1; 518 } 519 520 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci); 521 522 if ((le16_to_cpu(reply_desc->reply_flags) & 523 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 524 break; 525 /* 526 * Exit completion loop to avoid CPU lockup 527 * Ensure remaining completion happens from threaded ISR. 528 */ 529 if (num_op_reply > mrioc->max_host_ios) { 530 op_reply_q->enable_irq_poll = true; 531 break; 532 } 533 534 } while (1); 535 536 writel(reply_ci, 537 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index); 538 op_reply_q->ci = reply_ci; 539 op_reply_q->ephase = exp_phase; 540 541 atomic_dec(&op_reply_q->in_use); 542 return num_op_reply; 543 } 544 545 /** 546 * mpi3mr_blk_mq_poll - Operational reply queue handler 547 * @shost: SCSI Host reference 548 * @queue_num: Request queue number (w.r.t OS it is hardware context number) 549 * 550 * Checks the specific operational reply queue and drains the 551 * reply queue entries until the queue is empty and process the 552 * individual reply descriptors. 553 * 554 * Return: 0 if queue is already processed,or number of reply 555 * descriptors processed. 556 */ 557 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) 558 { 559 int num_entries = 0; 560 struct mpi3mr_ioc *mrioc; 561 562 mrioc = (struct mpi3mr_ioc *)shost->hostdata; 563 564 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset)) 565 return 0; 566 567 num_entries = mpi3mr_process_op_reply_q(mrioc, 568 &mrioc->op_reply_qinfo[queue_num]); 569 570 return num_entries; 571 } 572 573 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata) 574 { 575 struct mpi3mr_intr_info *intr_info = privdata; 576 struct mpi3mr_ioc *mrioc; 577 u16 midx; 578 u32 num_admin_replies = 0, num_op_reply = 0; 579 580 if (!intr_info) 581 return IRQ_NONE; 582 583 mrioc = intr_info->mrioc; 584 585 if (!mrioc->intr_enabled) 586 return IRQ_NONE; 587 588 midx = intr_info->msix_index; 589 590 if (!midx) 591 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc); 592 if (intr_info->op_reply_q) 593 num_op_reply = mpi3mr_process_op_reply_q(mrioc, 594 intr_info->op_reply_q); 595 596 if (num_admin_replies || num_op_reply) 597 return IRQ_HANDLED; 598 else 599 return IRQ_NONE; 600 } 601 602 static irqreturn_t mpi3mr_isr(int irq, void *privdata) 603 { 604 struct mpi3mr_intr_info *intr_info = privdata; 605 struct mpi3mr_ioc *mrioc; 606 u16 midx; 607 int ret; 608 609 if (!intr_info) 610 return IRQ_NONE; 611 612 mrioc = intr_info->mrioc; 613 midx = intr_info->msix_index; 614 /* Call primary ISR routine */ 615 ret = mpi3mr_isr_primary(irq, privdata); 616 617 /* 618 * If more IOs are expected, schedule IRQ polling thread. 619 * Otherwise exit from ISR. 620 */ 621 if (!intr_info->op_reply_q) 622 return ret; 623 624 if (!intr_info->op_reply_q->enable_irq_poll || 625 !atomic_read(&intr_info->op_reply_q->pend_ios)) 626 return ret; 627 628 disable_irq_nosync(pci_irq_vector(mrioc->pdev, midx)); 629 630 return IRQ_WAKE_THREAD; 631 } 632 633 /** 634 * mpi3mr_isr_poll - Reply queue polling routine 635 * @irq: IRQ 636 * @privdata: Interrupt info 637 * 638 * poll for pending I/O completions in a loop until pending I/Os 639 * present or controller queue depth I/Os are processed. 640 * 641 * Return: IRQ_NONE or IRQ_HANDLED 642 */ 643 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata) 644 { 645 struct mpi3mr_intr_info *intr_info = privdata; 646 struct mpi3mr_ioc *mrioc; 647 u16 midx; 648 u32 num_op_reply = 0; 649 650 if (!intr_info || !intr_info->op_reply_q) 651 return IRQ_NONE; 652 653 mrioc = intr_info->mrioc; 654 midx = intr_info->msix_index; 655 656 /* Poll for pending IOs completions */ 657 do { 658 if (!mrioc->intr_enabled) 659 break; 660 661 if (!midx) 662 mpi3mr_process_admin_reply_q(mrioc); 663 if (intr_info->op_reply_q) 664 num_op_reply += 665 mpi3mr_process_op_reply_q(mrioc, 666 intr_info->op_reply_q); 667 668 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP); 669 670 } while (atomic_read(&intr_info->op_reply_q->pend_ios) && 671 (num_op_reply < mrioc->max_host_ios)); 672 673 intr_info->op_reply_q->enable_irq_poll = false; 674 enable_irq(pci_irq_vector(mrioc->pdev, midx)); 675 676 return IRQ_HANDLED; 677 } 678 679 /** 680 * mpi3mr_request_irq - Request IRQ and register ISR 681 * @mrioc: Adapter instance reference 682 * @index: IRQ vector index 683 * 684 * Request threaded ISR with primary ISR and secondary 685 * 686 * Return: 0 on success and non zero on failures. 687 */ 688 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index) 689 { 690 struct pci_dev *pdev = mrioc->pdev; 691 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index; 692 int retval = 0; 693 694 intr_info->mrioc = mrioc; 695 intr_info->msix_index = index; 696 intr_info->op_reply_q = NULL; 697 698 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d", 699 mrioc->driver_name, mrioc->id, index); 700 701 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr, 702 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info); 703 if (retval) { 704 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n", 705 intr_info->name, pci_irq_vector(pdev, index)); 706 return retval; 707 } 708 709 return retval; 710 } 711 712 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors) 713 { 714 if (!mrioc->requested_poll_qcount) 715 return; 716 717 /* Reserved for Admin and Default Queue */ 718 if (max_vectors > 2 && 719 (mrioc->requested_poll_qcount < max_vectors - 2)) { 720 ioc_info(mrioc, 721 "enabled polled queues (%d) msix (%d)\n", 722 mrioc->requested_poll_qcount, max_vectors); 723 } else { 724 ioc_info(mrioc, 725 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n", 726 mrioc->requested_poll_qcount, max_vectors); 727 mrioc->requested_poll_qcount = 0; 728 } 729 } 730 731 /** 732 * mpi3mr_setup_isr - Setup ISR for the controller 733 * @mrioc: Adapter instance reference 734 * @setup_one: Request one IRQ or more 735 * 736 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR 737 * 738 * Return: 0 on success and non zero on failures. 739 */ 740 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one) 741 { 742 unsigned int irq_flags = PCI_IRQ_MSIX; 743 int max_vectors, min_vec; 744 int retval; 745 int i; 746 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 }; 747 748 if (mrioc->is_intr_info_set) 749 return 0; 750 751 mpi3mr_cleanup_isr(mrioc); 752 753 if (setup_one || reset_devices) { 754 max_vectors = 1; 755 retval = pci_alloc_irq_vectors(mrioc->pdev, 756 1, max_vectors, irq_flags); 757 if (retval < 0) { 758 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 759 retval); 760 goto out_failed; 761 } 762 } else { 763 max_vectors = 764 min_t(int, mrioc->cpu_count + 1 + 765 mrioc->requested_poll_qcount, mrioc->msix_count); 766 767 mpi3mr_calc_poll_queues(mrioc, max_vectors); 768 769 ioc_info(mrioc, 770 "MSI-X vectors supported: %d, no of cores: %d,", 771 mrioc->msix_count, mrioc->cpu_count); 772 ioc_info(mrioc, 773 "MSI-x vectors requested: %d poll_queues %d\n", 774 max_vectors, mrioc->requested_poll_qcount); 775 776 desc.post_vectors = mrioc->requested_poll_qcount; 777 min_vec = desc.pre_vectors + desc.post_vectors; 778 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; 779 780 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev, 781 min_vec, max_vectors, irq_flags, &desc); 782 783 if (retval < 0) { 784 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n", 785 retval); 786 goto out_failed; 787 } 788 789 790 /* 791 * If only one MSI-x is allocated, then MSI-x 0 will be shared 792 * between Admin queue and operational queue 793 */ 794 if (retval == min_vec) 795 mrioc->op_reply_q_offset = 0; 796 else if (retval != (max_vectors)) { 797 ioc_info(mrioc, 798 "allocated vectors (%d) are less than configured (%d)\n", 799 retval, max_vectors); 800 } 801 802 max_vectors = retval; 803 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0; 804 805 mpi3mr_calc_poll_queues(mrioc, max_vectors); 806 807 } 808 809 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors, 810 GFP_KERNEL); 811 if (!mrioc->intr_info) { 812 retval = -ENOMEM; 813 pci_free_irq_vectors(mrioc->pdev); 814 goto out_failed; 815 } 816 for (i = 0; i < max_vectors; i++) { 817 retval = mpi3mr_request_irq(mrioc, i); 818 if (retval) { 819 mrioc->intr_info_count = i; 820 goto out_failed; 821 } 822 } 823 if (reset_devices || !setup_one) 824 mrioc->is_intr_info_set = true; 825 mrioc->intr_info_count = max_vectors; 826 mpi3mr_ioc_enable_intr(mrioc); 827 return 0; 828 829 out_failed: 830 mpi3mr_cleanup_isr(mrioc); 831 832 return retval; 833 } 834 835 static const struct { 836 enum mpi3mr_iocstate value; 837 char *name; 838 } mrioc_states[] = { 839 { MRIOC_STATE_READY, "ready" }, 840 { MRIOC_STATE_FAULT, "fault" }, 841 { MRIOC_STATE_RESET, "reset" }, 842 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 843 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 844 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" }, 845 }; 846 847 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 848 { 849 int i; 850 char *name = NULL; 851 852 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) { 853 if (mrioc_states[i].value == mrioc_state) { 854 name = mrioc_states[i].name; 855 break; 856 } 857 } 858 return name; 859 } 860 861 /* Reset reason to name mapper structure*/ 862 static const struct { 863 enum mpi3mr_reset_reason value; 864 char *name; 865 } mpi3mr_reset_reason_codes[] = { 866 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 867 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 868 { MPI3MR_RESET_FROM_IOCTL, "application invocation" }, 869 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 870 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 871 { MPI3MR_RESET_FROM_IOCTL_TIMEOUT, "IOCTL timeout" }, 872 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 873 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 874 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 875 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 876 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 877 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 878 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 879 { 880 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 881 "create request queue timeout" 882 }, 883 { 884 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 885 "create reply queue timeout" 886 }, 887 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 888 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 889 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 890 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 891 { 892 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 893 "component image activation timeout" 894 }, 895 { 896 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 897 "get package version timeout" 898 }, 899 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 900 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 901 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" }, 902 }; 903 904 /** 905 * mpi3mr_reset_rc_name - get reset reason code name 906 * @reason_code: reset reason code value 907 * 908 * Map reset reason to an NULL terminated ASCII string 909 * 910 * Return: name corresponding to reset reason value or NULL. 911 */ 912 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 913 { 914 int i; 915 char *name = NULL; 916 917 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) { 918 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 919 name = mpi3mr_reset_reason_codes[i].name; 920 break; 921 } 922 } 923 return name; 924 } 925 926 /* Reset type to name mapper structure*/ 927 static const struct { 928 u16 reset_type; 929 char *name; 930 } mpi3mr_reset_types[] = { 931 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 932 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 933 }; 934 935 /** 936 * mpi3mr_reset_type_name - get reset type name 937 * @reset_type: reset type value 938 * 939 * Map reset type to an NULL terminated ASCII string 940 * 941 * Return: name corresponding to reset type value or NULL. 942 */ 943 static const char *mpi3mr_reset_type_name(u16 reset_type) 944 { 945 int i; 946 char *name = NULL; 947 948 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) { 949 if (mpi3mr_reset_types[i].reset_type == reset_type) { 950 name = mpi3mr_reset_types[i].name; 951 break; 952 } 953 } 954 return name; 955 } 956 957 /** 958 * mpi3mr_print_fault_info - Display fault information 959 * @mrioc: Adapter instance reference 960 * 961 * Display the controller fault information if there is a 962 * controller fault. 963 * 964 * Return: Nothing. 965 */ 966 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc) 967 { 968 u32 ioc_status, code, code1, code2, code3; 969 970 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 971 972 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 973 code = readl(&mrioc->sysif_regs->fault); 974 code1 = readl(&mrioc->sysif_regs->fault_info[0]); 975 code2 = readl(&mrioc->sysif_regs->fault_info[1]); 976 code3 = readl(&mrioc->sysif_regs->fault_info[2]); 977 978 ioc_info(mrioc, 979 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n", 980 code, code1, code2, code3); 981 } 982 } 983 984 /** 985 * mpi3mr_get_iocstate - Get IOC State 986 * @mrioc: Adapter instance reference 987 * 988 * Return a proper IOC state enum based on the IOC status and 989 * IOC configuration and unrcoverable state of the controller. 990 * 991 * Return: Current IOC state. 992 */ 993 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc) 994 { 995 u32 ioc_status, ioc_config; 996 u8 ready, enabled; 997 998 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 999 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1000 1001 if (mrioc->unrecoverable) 1002 return MRIOC_STATE_UNRECOVERABLE; 1003 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1004 return MRIOC_STATE_FAULT; 1005 1006 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1007 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1008 1009 if (ready && enabled) 1010 return MRIOC_STATE_READY; 1011 if ((!ready) && (!enabled)) 1012 return MRIOC_STATE_RESET; 1013 if ((!ready) && (enabled)) 1014 return MRIOC_STATE_BECOMING_READY; 1015 1016 return MRIOC_STATE_RESET_REQUESTED; 1017 } 1018 1019 /** 1020 * mpi3mr_clear_reset_history - clear reset history 1021 * @mrioc: Adapter instance reference 1022 * 1023 * Write the reset history bit in IOC status to clear the bit, 1024 * if it is already set. 1025 * 1026 * Return: Nothing. 1027 */ 1028 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) 1029 { 1030 u32 ioc_status; 1031 1032 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1033 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1034 writel(ioc_status, &mrioc->sysif_regs->ioc_status); 1035 } 1036 1037 /** 1038 * mpi3mr_issue_and_process_mur - Message unit Reset handler 1039 * @mrioc: Adapter instance reference 1040 * @reset_reason: Reset reason code 1041 * 1042 * Issue Message unit Reset to the controller and wait for it to 1043 * be complete. 1044 * 1045 * Return: 0 on success, -1 on failure. 1046 */ 1047 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, 1048 u32 reset_reason) 1049 { 1050 u32 ioc_config, timeout, ioc_status; 1051 int retval = -1; 1052 1053 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); 1054 if (mrioc->unrecoverable) { 1055 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n"); 1056 return retval; 1057 } 1058 mpi3mr_clear_reset_history(mrioc); 1059 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1060 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1061 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1062 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1063 1064 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1065 do { 1066 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1067 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1068 mpi3mr_clear_reset_history(mrioc); 1069 break; 1070 } 1071 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1072 mpi3mr_print_fault_info(mrioc); 1073 break; 1074 } 1075 msleep(100); 1076 } while (--timeout); 1077 1078 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1079 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1080 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1081 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1082 retval = 0; 1083 1084 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n", 1085 (!retval) ? "successful" : "failed", ioc_status, ioc_config); 1086 return retval; 1087 } 1088 1089 /** 1090 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters 1091 * during reset/resume 1092 * @mrioc: Adapter instance reference 1093 * 1094 * Return zero if the new IOCFacts parameters value is compatible with 1095 * older values else return -EPERM 1096 */ 1097 static int 1098 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) 1099 { 1100 u16 dev_handle_bitmap_sz; 1101 void *removepend_bitmap; 1102 1103 if (mrioc->facts.reply_sz > mrioc->reply_sz) { 1104 ioc_err(mrioc, 1105 "cannot increase reply size from %d to %d\n", 1106 mrioc->reply_sz, mrioc->facts.reply_sz); 1107 return -EPERM; 1108 } 1109 1110 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) { 1111 ioc_err(mrioc, 1112 "cannot reduce number of operational reply queues from %d to %d\n", 1113 mrioc->num_op_reply_q, 1114 mrioc->facts.max_op_reply_q); 1115 return -EPERM; 1116 } 1117 1118 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) { 1119 ioc_err(mrioc, 1120 "cannot reduce number of operational request queues from %d to %d\n", 1121 mrioc->num_op_req_q, mrioc->facts.max_op_req_q); 1122 return -EPERM; 1123 } 1124 1125 dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8; 1126 if (mrioc->facts.max_devhandle % 8) 1127 dev_handle_bitmap_sz++; 1128 if (dev_handle_bitmap_sz > mrioc->dev_handle_bitmap_sz) { 1129 removepend_bitmap = krealloc(mrioc->removepend_bitmap, 1130 dev_handle_bitmap_sz, GFP_KERNEL); 1131 if (!removepend_bitmap) { 1132 ioc_err(mrioc, 1133 "failed to increase removepend_bitmap sz from: %d to %d\n", 1134 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 1135 return -EPERM; 1136 } 1137 memset(removepend_bitmap + mrioc->dev_handle_bitmap_sz, 0, 1138 dev_handle_bitmap_sz - mrioc->dev_handle_bitmap_sz); 1139 mrioc->removepend_bitmap = removepend_bitmap; 1140 ioc_info(mrioc, 1141 "increased dev_handle_bitmap_sz from %d to %d\n", 1142 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 1143 mrioc->dev_handle_bitmap_sz = dev_handle_bitmap_sz; 1144 } 1145 1146 return 0; 1147 } 1148 1149 /** 1150 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1151 * @mrioc: Adapter instance reference 1152 * 1153 * Set Enable IOC bit in IOC configuration register and wait for 1154 * the controller to become ready. 1155 * 1156 * Return: 0 on success, appropriate error on failure. 1157 */ 1158 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc) 1159 { 1160 u32 ioc_config, ioc_status, timeout; 1161 int retval = 0; 1162 enum mpi3mr_iocstate ioc_state; 1163 u64 base_info; 1164 1165 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1166 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1167 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information); 1168 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n", 1169 ioc_status, ioc_config, base_info); 1170 1171 /*The timeout value is in 2sec unit, changing it to seconds*/ 1172 mrioc->ready_timeout = 1173 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 1174 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 1175 1176 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout); 1177 1178 ioc_state = mpi3mr_get_iocstate(mrioc); 1179 ioc_info(mrioc, "controller is in %s state during detection\n", 1180 mpi3mr_iocstate_name(ioc_state)); 1181 1182 if (ioc_state == MRIOC_STATE_BECOMING_READY || 1183 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 1184 timeout = mrioc->ready_timeout * 10; 1185 do { 1186 msleep(100); 1187 } while (--timeout); 1188 1189 ioc_state = mpi3mr_get_iocstate(mrioc); 1190 ioc_info(mrioc, 1191 "controller is in %s state after waiting to reset\n", 1192 mpi3mr_iocstate_name(ioc_state)); 1193 } 1194 1195 if (ioc_state == MRIOC_STATE_READY) { 1196 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n"); 1197 retval = mpi3mr_issue_and_process_mur(mrioc, 1198 MPI3MR_RESET_FROM_BRINGUP); 1199 ioc_state = mpi3mr_get_iocstate(mrioc); 1200 if (retval) 1201 ioc_err(mrioc, 1202 "message unit reset failed with error %d current state %s\n", 1203 retval, mpi3mr_iocstate_name(ioc_state)); 1204 } 1205 if (ioc_state != MRIOC_STATE_RESET) { 1206 mpi3mr_print_fault_info(mrioc); 1207 ioc_info(mrioc, "issuing soft reset to bring to reset state\n"); 1208 retval = mpi3mr_issue_reset(mrioc, 1209 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 1210 MPI3MR_RESET_FROM_BRINGUP); 1211 if (retval) { 1212 ioc_err(mrioc, 1213 "soft reset failed with error %d\n", retval); 1214 goto out_failed; 1215 } 1216 } 1217 ioc_state = mpi3mr_get_iocstate(mrioc); 1218 if (ioc_state != MRIOC_STATE_RESET) { 1219 ioc_err(mrioc, 1220 "cannot bring controller to reset state, current state: %s\n", 1221 mpi3mr_iocstate_name(ioc_state)); 1222 goto out_failed; 1223 } 1224 mpi3mr_clear_reset_history(mrioc); 1225 retval = mpi3mr_setup_admin_qpair(mrioc); 1226 if (retval) { 1227 ioc_err(mrioc, "failed to setup admin queues: error %d\n", 1228 retval); 1229 goto out_failed; 1230 } 1231 1232 ioc_info(mrioc, "bringing controller to ready state\n"); 1233 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1234 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1235 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1236 1237 timeout = mrioc->ready_timeout * 10; 1238 do { 1239 ioc_state = mpi3mr_get_iocstate(mrioc); 1240 if (ioc_state == MRIOC_STATE_READY) { 1241 ioc_info(mrioc, 1242 "successfully transitioned to %s state\n", 1243 mpi3mr_iocstate_name(ioc_state)); 1244 return 0; 1245 } 1246 msleep(100); 1247 } while (--timeout); 1248 1249 out_failed: 1250 ioc_state = mpi3mr_get_iocstate(mrioc); 1251 ioc_err(mrioc, 1252 "failed to bring to ready state, current state: %s\n", 1253 mpi3mr_iocstate_name(ioc_state)); 1254 return retval; 1255 } 1256 1257 /** 1258 * mpi3mr_soft_reset_success - Check softreset is success or not 1259 * @ioc_status: IOC status register value 1260 * @ioc_config: IOC config register value 1261 * 1262 * Check whether the soft reset is successful or not based on 1263 * IOC status and IOC config register values. 1264 * 1265 * Return: True when the soft reset is success, false otherwise. 1266 */ 1267 static inline bool 1268 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config) 1269 { 1270 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1271 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1272 return true; 1273 return false; 1274 } 1275 1276 /** 1277 * mpi3mr_diagfault_success - Check diag fault is success or not 1278 * @mrioc: Adapter reference 1279 * @ioc_status: IOC status register value 1280 * 1281 * Check whether the controller hit diag reset fault code. 1282 * 1283 * Return: True when there is diag fault, false otherwise. 1284 */ 1285 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc, 1286 u32 ioc_status) 1287 { 1288 u32 fault; 1289 1290 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1291 return false; 1292 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 1293 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) { 1294 mpi3mr_print_fault_info(mrioc); 1295 return true; 1296 } 1297 return false; 1298 } 1299 1300 /** 1301 * mpi3mr_set_diagsave - Set diag save bit for snapdump 1302 * @mrioc: Adapter reference 1303 * 1304 * Set diag save bit in IOC configuration register to enable 1305 * snapdump. 1306 * 1307 * Return: Nothing. 1308 */ 1309 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) 1310 { 1311 u32 ioc_config; 1312 1313 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1314 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 1315 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 1316 } 1317 1318 /** 1319 * mpi3mr_issue_reset - Issue reset to the controller 1320 * @mrioc: Adapter reference 1321 * @reset_type: Reset type 1322 * @reset_reason: Reset reason code 1323 * 1324 * Unlock the host diagnostic registers and write the specific 1325 * reset type to that, wait for reset acknowledgment from the 1326 * controller, if the reset is not successful retry for the 1327 * predefined number of times. 1328 * 1329 * Return: 0 on success, non-zero on failure. 1330 */ 1331 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, 1332 u32 reset_reason) 1333 { 1334 int retval = -1; 1335 u8 unlock_retry_count = 0; 1336 u32 host_diagnostic, ioc_status, ioc_config; 1337 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 1338 1339 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 1340 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 1341 return retval; 1342 if (mrioc->unrecoverable) 1343 return retval; 1344 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 1345 retval = 0; 1346 return retval; 1347 } 1348 1349 ioc_info(mrioc, "%s reset due to %s(0x%x)\n", 1350 mpi3mr_reset_type_name(reset_type), 1351 mpi3mr_reset_rc_name(reset_reason), reset_reason); 1352 1353 mpi3mr_clear_reset_history(mrioc); 1354 do { 1355 ioc_info(mrioc, 1356 "Write magic sequence to unlock host diag register (retry=%d)\n", 1357 ++unlock_retry_count); 1358 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 1359 ioc_err(mrioc, 1360 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n", 1361 mpi3mr_reset_type_name(reset_type), 1362 host_diagnostic); 1363 mrioc->unrecoverable = 1; 1364 return retval; 1365 } 1366 1367 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH, 1368 &mrioc->sysif_regs->write_sequence); 1369 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST, 1370 &mrioc->sysif_regs->write_sequence); 1371 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1372 &mrioc->sysif_regs->write_sequence); 1373 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD, 1374 &mrioc->sysif_regs->write_sequence); 1375 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH, 1376 &mrioc->sysif_regs->write_sequence); 1377 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH, 1378 &mrioc->sysif_regs->write_sequence); 1379 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH, 1380 &mrioc->sysif_regs->write_sequence); 1381 usleep_range(1000, 1100); 1382 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 1383 ioc_info(mrioc, 1384 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 1385 unlock_retry_count, host_diagnostic); 1386 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 1387 1388 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); 1389 writel(host_diagnostic | reset_type, 1390 &mrioc->sysif_regs->host_diagnostic); 1391 switch (reset_type) { 1392 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET: 1393 do { 1394 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1395 ioc_config = 1396 readl(&mrioc->sysif_regs->ioc_configuration); 1397 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1398 && mpi3mr_soft_reset_success(ioc_status, ioc_config) 1399 ) { 1400 mpi3mr_clear_reset_history(mrioc); 1401 retval = 0; 1402 break; 1403 } 1404 msleep(100); 1405 } while (--timeout); 1406 mpi3mr_print_fault_info(mrioc); 1407 break; 1408 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT: 1409 do { 1410 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1411 if (mpi3mr_diagfault_success(mrioc, ioc_status)) { 1412 retval = 0; 1413 break; 1414 } 1415 msleep(100); 1416 } while (--timeout); 1417 break; 1418 default: 1419 break; 1420 } 1421 1422 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND, 1423 &mrioc->sysif_regs->write_sequence); 1424 1425 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 1426 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 1427 ioc_info(mrioc, 1428 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n", 1429 (!retval)?"successful":"failed", ioc_status, 1430 ioc_config); 1431 if (retval) 1432 mrioc->unrecoverable = 1; 1433 return retval; 1434 } 1435 1436 /** 1437 * mpi3mr_admin_request_post - Post request to admin queue 1438 * @mrioc: Adapter reference 1439 * @admin_req: MPI3 request 1440 * @admin_req_sz: Request size 1441 * @ignore_reset: Ignore reset in process 1442 * 1443 * Post the MPI3 request into admin request queue and 1444 * inform the controller, if the queue is full return 1445 * appropriate error. 1446 * 1447 * Return: 0 on success, non-zero on failure. 1448 */ 1449 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1450 u16 admin_req_sz, u8 ignore_reset) 1451 { 1452 u16 areq_pi = 0, areq_ci = 0, max_entries = 0; 1453 int retval = 0; 1454 unsigned long flags; 1455 u8 *areq_entry; 1456 1457 if (mrioc->unrecoverable) { 1458 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__); 1459 return -EFAULT; 1460 } 1461 1462 spin_lock_irqsave(&mrioc->admin_req_lock, flags); 1463 areq_pi = mrioc->admin_req_pi; 1464 areq_ci = mrioc->admin_req_ci; 1465 max_entries = mrioc->num_admin_req; 1466 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 1467 (areq_pi == (max_entries - 1)))) { 1468 ioc_err(mrioc, "AdminReqQ full condition detected\n"); 1469 retval = -EAGAIN; 1470 goto out; 1471 } 1472 if (!ignore_reset && mrioc->reset_in_progress) { 1473 ioc_err(mrioc, "AdminReqQ submit reset in progress\n"); 1474 retval = -EAGAIN; 1475 goto out; 1476 } 1477 areq_entry = (u8 *)mrioc->admin_req_base + 1478 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ); 1479 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ); 1480 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz); 1481 1482 if (++areq_pi == max_entries) 1483 areq_pi = 0; 1484 mrioc->admin_req_pi = areq_pi; 1485 1486 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 1487 1488 out: 1489 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags); 1490 1491 return retval; 1492 } 1493 1494 /** 1495 * mpi3mr_free_op_req_q_segments - free request memory segments 1496 * @mrioc: Adapter instance reference 1497 * @q_idx: operational request queue index 1498 * 1499 * Free memory segments allocated for operational request queue 1500 * 1501 * Return: Nothing. 1502 */ 1503 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1504 { 1505 u16 j; 1506 int size; 1507 struct segments *segments; 1508 1509 segments = mrioc->req_qinfo[q_idx].q_segments; 1510 if (!segments) 1511 return; 1512 1513 if (mrioc->enable_segqueue) { 1514 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1515 if (mrioc->req_qinfo[q_idx].q_segment_list) { 1516 dma_free_coherent(&mrioc->pdev->dev, 1517 MPI3MR_MAX_SEG_LIST_SIZE, 1518 mrioc->req_qinfo[q_idx].q_segment_list, 1519 mrioc->req_qinfo[q_idx].q_segment_list_dma); 1520 mrioc->req_qinfo[q_idx].q_segment_list = NULL; 1521 } 1522 } else 1523 size = mrioc->req_qinfo[q_idx].segment_qd * 1524 mrioc->facts.op_req_sz; 1525 1526 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) { 1527 if (!segments[j].segment) 1528 continue; 1529 dma_free_coherent(&mrioc->pdev->dev, 1530 size, segments[j].segment, segments[j].segment_dma); 1531 segments[j].segment = NULL; 1532 } 1533 kfree(mrioc->req_qinfo[q_idx].q_segments); 1534 mrioc->req_qinfo[q_idx].q_segments = NULL; 1535 mrioc->req_qinfo[q_idx].qid = 0; 1536 } 1537 1538 /** 1539 * mpi3mr_free_op_reply_q_segments - free reply memory segments 1540 * @mrioc: Adapter instance reference 1541 * @q_idx: operational reply queue index 1542 * 1543 * Free memory segments allocated for operational reply queue 1544 * 1545 * Return: Nothing. 1546 */ 1547 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx) 1548 { 1549 u16 j; 1550 int size; 1551 struct segments *segments; 1552 1553 segments = mrioc->op_reply_qinfo[q_idx].q_segments; 1554 if (!segments) 1555 return; 1556 1557 if (mrioc->enable_segqueue) { 1558 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1559 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) { 1560 dma_free_coherent(&mrioc->pdev->dev, 1561 MPI3MR_MAX_SEG_LIST_SIZE, 1562 mrioc->op_reply_qinfo[q_idx].q_segment_list, 1563 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma); 1564 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL; 1565 } 1566 } else 1567 size = mrioc->op_reply_qinfo[q_idx].segment_qd * 1568 mrioc->op_reply_desc_sz; 1569 1570 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) { 1571 if (!segments[j].segment) 1572 continue; 1573 dma_free_coherent(&mrioc->pdev->dev, 1574 size, segments[j].segment, segments[j].segment_dma); 1575 segments[j].segment = NULL; 1576 } 1577 1578 kfree(mrioc->op_reply_qinfo[q_idx].q_segments); 1579 mrioc->op_reply_qinfo[q_idx].q_segments = NULL; 1580 mrioc->op_reply_qinfo[q_idx].qid = 0; 1581 } 1582 1583 /** 1584 * mpi3mr_delete_op_reply_q - delete operational reply queue 1585 * @mrioc: Adapter instance reference 1586 * @qidx: operational reply queue index 1587 * 1588 * Delete operatinal reply queue by issuing MPI request 1589 * through admin queue. 1590 * 1591 * Return: 0 on success, non-zero on failure. 1592 */ 1593 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1594 { 1595 struct mpi3_delete_reply_queue_request delq_req; 1596 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1597 int retval = 0; 1598 u16 reply_qid = 0, midx; 1599 1600 reply_qid = op_reply_q->qid; 1601 1602 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1603 1604 if (!reply_qid) { 1605 retval = -1; 1606 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n"); 1607 goto out; 1608 } 1609 1610 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- : 1611 mrioc->active_poll_qcount--; 1612 1613 memset(&delq_req, 0, sizeof(delq_req)); 1614 mutex_lock(&mrioc->init_cmds.mutex); 1615 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1616 retval = -1; 1617 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n"); 1618 mutex_unlock(&mrioc->init_cmds.mutex); 1619 goto out; 1620 } 1621 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1622 mrioc->init_cmds.is_waiting = 1; 1623 mrioc->init_cmds.callback = NULL; 1624 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1625 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 1626 delq_req.queue_id = cpu_to_le16(reply_qid); 1627 1628 init_completion(&mrioc->init_cmds.done); 1629 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req), 1630 1); 1631 if (retval) { 1632 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n"); 1633 goto out_unlock; 1634 } 1635 wait_for_completion_timeout(&mrioc->init_cmds.done, 1636 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1637 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1638 ioc_err(mrioc, "delete reply queue timed out\n"); 1639 mpi3mr_check_rh_fault_ioc(mrioc, 1640 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 1641 retval = -1; 1642 goto out_unlock; 1643 } 1644 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1645 != MPI3_IOCSTATUS_SUCCESS) { 1646 ioc_err(mrioc, 1647 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1648 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1649 mrioc->init_cmds.ioc_loginfo); 1650 retval = -1; 1651 goto out_unlock; 1652 } 1653 mrioc->intr_info[midx].op_reply_q = NULL; 1654 1655 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1656 out_unlock: 1657 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1658 mutex_unlock(&mrioc->init_cmds.mutex); 1659 out: 1660 1661 return retval; 1662 } 1663 1664 /** 1665 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool 1666 * @mrioc: Adapter instance reference 1667 * @qidx: request queue index 1668 * 1669 * Allocate segmented memory pools for operational reply 1670 * queue. 1671 * 1672 * Return: 0 on success, non-zero on failure. 1673 */ 1674 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1675 { 1676 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1677 int i, size; 1678 u64 *q_segment_list_entry = NULL; 1679 struct segments *segments; 1680 1681 if (mrioc->enable_segqueue) { 1682 op_reply_q->segment_qd = 1683 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz; 1684 1685 size = MPI3MR_OP_REP_Q_SEG_SIZE; 1686 1687 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1688 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma, 1689 GFP_KERNEL); 1690 if (!op_reply_q->q_segment_list) 1691 return -ENOMEM; 1692 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list; 1693 } else { 1694 op_reply_q->segment_qd = op_reply_q->num_replies; 1695 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz; 1696 } 1697 1698 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies, 1699 op_reply_q->segment_qd); 1700 1701 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments, 1702 sizeof(struct segments), GFP_KERNEL); 1703 if (!op_reply_q->q_segments) 1704 return -ENOMEM; 1705 1706 segments = op_reply_q->q_segments; 1707 for (i = 0; i < op_reply_q->num_segments; i++) { 1708 segments[i].segment = 1709 dma_alloc_coherent(&mrioc->pdev->dev, 1710 size, &segments[i].segment_dma, GFP_KERNEL); 1711 if (!segments[i].segment) 1712 return -ENOMEM; 1713 if (mrioc->enable_segqueue) 1714 q_segment_list_entry[i] = 1715 (unsigned long)segments[i].segment_dma; 1716 } 1717 1718 return 0; 1719 } 1720 1721 /** 1722 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool. 1723 * @mrioc: Adapter instance reference 1724 * @qidx: request queue index 1725 * 1726 * Allocate segmented memory pools for operational request 1727 * queue. 1728 * 1729 * Return: 0 on success, non-zero on failure. 1730 */ 1731 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx) 1732 { 1733 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 1734 int i, size; 1735 u64 *q_segment_list_entry = NULL; 1736 struct segments *segments; 1737 1738 if (mrioc->enable_segqueue) { 1739 op_req_q->segment_qd = 1740 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz; 1741 1742 size = MPI3MR_OP_REQ_Q_SEG_SIZE; 1743 1744 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev, 1745 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma, 1746 GFP_KERNEL); 1747 if (!op_req_q->q_segment_list) 1748 return -ENOMEM; 1749 q_segment_list_entry = (u64 *)op_req_q->q_segment_list; 1750 1751 } else { 1752 op_req_q->segment_qd = op_req_q->num_requests; 1753 size = op_req_q->num_requests * mrioc->facts.op_req_sz; 1754 } 1755 1756 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests, 1757 op_req_q->segment_qd); 1758 1759 op_req_q->q_segments = kcalloc(op_req_q->num_segments, 1760 sizeof(struct segments), GFP_KERNEL); 1761 if (!op_req_q->q_segments) 1762 return -ENOMEM; 1763 1764 segments = op_req_q->q_segments; 1765 for (i = 0; i < op_req_q->num_segments; i++) { 1766 segments[i].segment = 1767 dma_alloc_coherent(&mrioc->pdev->dev, 1768 size, &segments[i].segment_dma, GFP_KERNEL); 1769 if (!segments[i].segment) 1770 return -ENOMEM; 1771 if (mrioc->enable_segqueue) 1772 q_segment_list_entry[i] = 1773 (unsigned long)segments[i].segment_dma; 1774 } 1775 1776 return 0; 1777 } 1778 1779 /** 1780 * mpi3mr_create_op_reply_q - create operational reply queue 1781 * @mrioc: Adapter instance reference 1782 * @qidx: operational reply queue index 1783 * 1784 * Create operatinal reply queue by issuing MPI request 1785 * through admin queue. 1786 * 1787 * Return: 0 on success, non-zero on failure. 1788 */ 1789 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx) 1790 { 1791 struct mpi3_create_reply_queue_request create_req; 1792 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 1793 int retval = 0; 1794 u16 reply_qid = 0, midx; 1795 1796 reply_qid = op_reply_q->qid; 1797 1798 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset); 1799 1800 if (reply_qid) { 1801 retval = -1; 1802 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n", 1803 reply_qid); 1804 1805 return retval; 1806 } 1807 1808 reply_qid = qidx + 1; 1809 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 1810 if (!mrioc->pdev->revision) 1811 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K; 1812 op_reply_q->ci = 0; 1813 op_reply_q->ephase = 1; 1814 atomic_set(&op_reply_q->pend_ios, 0); 1815 atomic_set(&op_reply_q->in_use, 0); 1816 op_reply_q->enable_irq_poll = false; 1817 1818 if (!op_reply_q->q_segments) { 1819 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx); 1820 if (retval) { 1821 mpi3mr_free_op_reply_q_segments(mrioc, qidx); 1822 goto out; 1823 } 1824 } 1825 1826 memset(&create_req, 0, sizeof(create_req)); 1827 mutex_lock(&mrioc->init_cmds.mutex); 1828 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1829 retval = -1; 1830 ioc_err(mrioc, "CreateRepQ: Init command is in use\n"); 1831 goto out_unlock; 1832 } 1833 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1834 mrioc->init_cmds.is_waiting = 1; 1835 mrioc->init_cmds.callback = NULL; 1836 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1837 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 1838 create_req.queue_id = cpu_to_le16(reply_qid); 1839 1840 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount)) 1841 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE; 1842 else 1843 op_reply_q->qtype = MPI3MR_POLL_QUEUE; 1844 1845 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) { 1846 create_req.flags = 1847 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 1848 create_req.msix_index = 1849 cpu_to_le16(mrioc->intr_info[midx].msix_index); 1850 } else { 1851 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1); 1852 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n", 1853 reply_qid, midx); 1854 if (!mrioc->active_poll_qcount) 1855 disable_irq_nosync(pci_irq_vector(mrioc->pdev, 1856 mrioc->intr_info_count - 1)); 1857 } 1858 1859 if (mrioc->enable_segqueue) { 1860 create_req.flags |= 1861 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1862 create_req.base_address = cpu_to_le64( 1863 op_reply_q->q_segment_list_dma); 1864 } else 1865 create_req.base_address = cpu_to_le64( 1866 op_reply_q->q_segments[0].segment_dma); 1867 1868 create_req.size = cpu_to_le16(op_reply_q->num_replies); 1869 1870 init_completion(&mrioc->init_cmds.done); 1871 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1872 sizeof(create_req), 1); 1873 if (retval) { 1874 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n"); 1875 goto out_unlock; 1876 } 1877 wait_for_completion_timeout(&mrioc->init_cmds.done, 1878 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1879 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1880 ioc_err(mrioc, "create reply queue timed out\n"); 1881 mpi3mr_check_rh_fault_ioc(mrioc, 1882 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 1883 retval = -1; 1884 goto out_unlock; 1885 } 1886 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1887 != MPI3_IOCSTATUS_SUCCESS) { 1888 ioc_err(mrioc, 1889 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1890 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1891 mrioc->init_cmds.ioc_loginfo); 1892 retval = -1; 1893 goto out_unlock; 1894 } 1895 op_reply_q->qid = reply_qid; 1896 if (midx < mrioc->intr_info_count) 1897 mrioc->intr_info[midx].op_reply_q = op_reply_q; 1898 1899 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ : 1900 mrioc->active_poll_qcount++; 1901 1902 out_unlock: 1903 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1904 mutex_unlock(&mrioc->init_cmds.mutex); 1905 out: 1906 1907 return retval; 1908 } 1909 1910 /** 1911 * mpi3mr_create_op_req_q - create operational request queue 1912 * @mrioc: Adapter instance reference 1913 * @idx: operational request queue index 1914 * @reply_qid: Reply queue ID 1915 * 1916 * Create operatinal request queue by issuing MPI request 1917 * through admin queue. 1918 * 1919 * Return: 0 on success, non-zero on failure. 1920 */ 1921 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx, 1922 u16 reply_qid) 1923 { 1924 struct mpi3_create_request_queue_request create_req; 1925 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx; 1926 int retval = 0; 1927 u16 req_qid = 0; 1928 1929 req_qid = op_req_q->qid; 1930 1931 if (req_qid) { 1932 retval = -1; 1933 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n", 1934 req_qid); 1935 1936 return retval; 1937 } 1938 req_qid = idx + 1; 1939 1940 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD; 1941 op_req_q->ci = 0; 1942 op_req_q->pi = 0; 1943 op_req_q->reply_qid = reply_qid; 1944 spin_lock_init(&op_req_q->q_lock); 1945 1946 if (!op_req_q->q_segments) { 1947 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx); 1948 if (retval) { 1949 mpi3mr_free_op_req_q_segments(mrioc, idx); 1950 goto out; 1951 } 1952 } 1953 1954 memset(&create_req, 0, sizeof(create_req)); 1955 mutex_lock(&mrioc->init_cmds.mutex); 1956 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 1957 retval = -1; 1958 ioc_err(mrioc, "CreateReqQ: Init command is in use\n"); 1959 goto out_unlock; 1960 } 1961 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 1962 mrioc->init_cmds.is_waiting = 1; 1963 mrioc->init_cmds.callback = NULL; 1964 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 1965 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 1966 create_req.queue_id = cpu_to_le16(req_qid); 1967 if (mrioc->enable_segqueue) { 1968 create_req.flags = 1969 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED; 1970 create_req.base_address = cpu_to_le64( 1971 op_req_q->q_segment_list_dma); 1972 } else 1973 create_req.base_address = cpu_to_le64( 1974 op_req_q->q_segments[0].segment_dma); 1975 create_req.reply_queue_id = cpu_to_le16(reply_qid); 1976 create_req.size = cpu_to_le16(op_req_q->num_requests); 1977 1978 init_completion(&mrioc->init_cmds.done); 1979 retval = mpi3mr_admin_request_post(mrioc, &create_req, 1980 sizeof(create_req), 1); 1981 if (retval) { 1982 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n"); 1983 goto out_unlock; 1984 } 1985 wait_for_completion_timeout(&mrioc->init_cmds.done, 1986 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 1987 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1988 ioc_err(mrioc, "create request queue timed out\n"); 1989 mpi3mr_check_rh_fault_ioc(mrioc, 1990 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 1991 retval = -1; 1992 goto out_unlock; 1993 } 1994 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1995 != MPI3_IOCSTATUS_SUCCESS) { 1996 ioc_err(mrioc, 1997 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 1998 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1999 mrioc->init_cmds.ioc_loginfo); 2000 retval = -1; 2001 goto out_unlock; 2002 } 2003 op_req_q->qid = req_qid; 2004 2005 out_unlock: 2006 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2007 mutex_unlock(&mrioc->init_cmds.mutex); 2008 out: 2009 2010 return retval; 2011 } 2012 2013 /** 2014 * mpi3mr_create_op_queues - create operational queue pairs 2015 * @mrioc: Adapter instance reference 2016 * 2017 * Allocate memory for operational queue meta data and call 2018 * create request and reply queue functions. 2019 * 2020 * Return: 0 on success, non-zero on failures. 2021 */ 2022 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc) 2023 { 2024 int retval = 0; 2025 u16 num_queues = 0, i = 0, msix_count_op_q = 1; 2026 2027 num_queues = min_t(int, mrioc->facts.max_op_reply_q, 2028 mrioc->facts.max_op_req_q); 2029 2030 msix_count_op_q = 2031 mrioc->intr_info_count - mrioc->op_reply_q_offset; 2032 if (!mrioc->num_queues) 2033 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q); 2034 /* 2035 * During reset set the num_queues to the number of queues 2036 * that was set before the reset. 2037 */ 2038 num_queues = mrioc->num_op_reply_q ? 2039 mrioc->num_op_reply_q : mrioc->num_queues; 2040 ioc_info(mrioc, "trying to create %d operational queue pairs\n", 2041 num_queues); 2042 2043 if (!mrioc->req_qinfo) { 2044 mrioc->req_qinfo = kcalloc(num_queues, 2045 sizeof(struct op_req_qinfo), GFP_KERNEL); 2046 if (!mrioc->req_qinfo) { 2047 retval = -1; 2048 goto out_failed; 2049 } 2050 2051 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) * 2052 num_queues, GFP_KERNEL); 2053 if (!mrioc->op_reply_qinfo) { 2054 retval = -1; 2055 goto out_failed; 2056 } 2057 } 2058 2059 if (mrioc->enable_segqueue) 2060 ioc_info(mrioc, 2061 "allocating operational queues through segmented queues\n"); 2062 2063 for (i = 0; i < num_queues; i++) { 2064 if (mpi3mr_create_op_reply_q(mrioc, i)) { 2065 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i); 2066 break; 2067 } 2068 if (mpi3mr_create_op_req_q(mrioc, i, 2069 mrioc->op_reply_qinfo[i].qid)) { 2070 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i); 2071 mpi3mr_delete_op_reply_q(mrioc, i); 2072 break; 2073 } 2074 } 2075 2076 if (i == 0) { 2077 /* Not even one queue is created successfully*/ 2078 retval = -1; 2079 goto out_failed; 2080 } 2081 mrioc->num_op_reply_q = mrioc->num_op_req_q = i; 2082 ioc_info(mrioc, 2083 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n", 2084 mrioc->num_op_reply_q, mrioc->default_qcount, 2085 mrioc->active_poll_qcount); 2086 2087 return retval; 2088 out_failed: 2089 kfree(mrioc->req_qinfo); 2090 mrioc->req_qinfo = NULL; 2091 2092 kfree(mrioc->op_reply_qinfo); 2093 mrioc->op_reply_qinfo = NULL; 2094 2095 return retval; 2096 } 2097 2098 /** 2099 * mpi3mr_op_request_post - Post request to operational queue 2100 * @mrioc: Adapter reference 2101 * @op_req_q: Operational request queue info 2102 * @req: MPI3 request 2103 * 2104 * Post the MPI3 request into operational request queue and 2105 * inform the controller, if the queue is full return 2106 * appropriate error. 2107 * 2108 * Return: 0 on success, non-zero on failure. 2109 */ 2110 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 2111 struct op_req_qinfo *op_req_q, u8 *req) 2112 { 2113 u16 pi = 0, max_entries, reply_qidx = 0, midx; 2114 int retval = 0; 2115 unsigned long flags; 2116 u8 *req_entry; 2117 void *segment_base_addr; 2118 u16 req_sz = mrioc->facts.op_req_sz; 2119 struct segments *segments = op_req_q->q_segments; 2120 2121 reply_qidx = op_req_q->reply_qid - 1; 2122 2123 if (mrioc->unrecoverable) 2124 return -EFAULT; 2125 2126 spin_lock_irqsave(&op_req_q->q_lock, flags); 2127 pi = op_req_q->pi; 2128 max_entries = op_req_q->num_requests; 2129 2130 if (mpi3mr_check_req_qfull(op_req_q)) { 2131 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX( 2132 reply_qidx, mrioc->op_reply_q_offset); 2133 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q); 2134 2135 if (mpi3mr_check_req_qfull(op_req_q)) { 2136 retval = -EAGAIN; 2137 goto out; 2138 } 2139 } 2140 2141 if (mrioc->reset_in_progress) { 2142 ioc_err(mrioc, "OpReqQ submit reset in progress\n"); 2143 retval = -EAGAIN; 2144 goto out; 2145 } 2146 2147 segment_base_addr = segments[pi / op_req_q->segment_qd].segment; 2148 req_entry = (u8 *)segment_base_addr + 2149 ((pi % op_req_q->segment_qd) * req_sz); 2150 2151 memset(req_entry, 0, req_sz); 2152 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ); 2153 2154 if (++pi == max_entries) 2155 pi = 0; 2156 op_req_q->pi = pi; 2157 2158 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios) 2159 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT) 2160 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true; 2161 2162 writel(op_req_q->pi, 2163 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index); 2164 2165 out: 2166 spin_unlock_irqrestore(&op_req_q->q_lock, flags); 2167 return retval; 2168 } 2169 2170 /** 2171 * mpi3mr_check_rh_fault_ioc - check reset history and fault 2172 * controller 2173 * @mrioc: Adapter instance reference 2174 * @reason_code: reason code for the fault. 2175 * 2176 * This routine will save snapdump and fault the controller with 2177 * the given reason code if it is not already in the fault or 2178 * not asynchronosuly reset. This will be used to handle 2179 * initilaization time faults/resets/timeout as in those cases 2180 * immediate soft reset invocation is not required. 2181 * 2182 * Return: None. 2183 */ 2184 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code) 2185 { 2186 u32 ioc_status, host_diagnostic, timeout; 2187 2188 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2189 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 2190 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 2191 mpi3mr_print_fault_info(mrioc); 2192 return; 2193 } 2194 mpi3mr_set_diagsave(mrioc); 2195 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 2196 reason_code); 2197 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 2198 do { 2199 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2200 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 2201 break; 2202 msleep(100); 2203 } while (--timeout); 2204 } 2205 2206 /** 2207 * mpi3mr_sync_timestamp - Issue time stamp sync request 2208 * @mrioc: Adapter reference 2209 * 2210 * Issue IO unit control MPI request to synchornize firmware 2211 * timestamp with host time. 2212 * 2213 * Return: 0 on success, non-zero on failure. 2214 */ 2215 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc) 2216 { 2217 ktime_t current_time; 2218 struct mpi3_iounit_control_request iou_ctrl; 2219 int retval = 0; 2220 2221 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 2222 mutex_lock(&mrioc->init_cmds.mutex); 2223 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2224 retval = -1; 2225 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n"); 2226 mutex_unlock(&mrioc->init_cmds.mutex); 2227 goto out; 2228 } 2229 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2230 mrioc->init_cmds.is_waiting = 1; 2231 mrioc->init_cmds.callback = NULL; 2232 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2233 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL; 2234 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; 2235 current_time = ktime_get_real(); 2236 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time)); 2237 2238 init_completion(&mrioc->init_cmds.done); 2239 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, 2240 sizeof(iou_ctrl), 0); 2241 if (retval) { 2242 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n"); 2243 goto out_unlock; 2244 } 2245 2246 wait_for_completion_timeout(&mrioc->init_cmds.done, 2247 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2248 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2249 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n"); 2250 mrioc->init_cmds.is_waiting = 0; 2251 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 2252 mpi3mr_soft_reset_handler(mrioc, 2253 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1); 2254 retval = -1; 2255 goto out_unlock; 2256 } 2257 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2258 != MPI3_IOCSTATUS_SUCCESS) { 2259 ioc_err(mrioc, 2260 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2261 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2262 mrioc->init_cmds.ioc_loginfo); 2263 retval = -1; 2264 goto out_unlock; 2265 } 2266 2267 out_unlock: 2268 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2269 mutex_unlock(&mrioc->init_cmds.mutex); 2270 2271 out: 2272 return retval; 2273 } 2274 2275 /** 2276 * mpi3mr_print_pkg_ver - display controller fw package version 2277 * @mrioc: Adapter reference 2278 * 2279 * Retrieve firmware package version from the component image 2280 * header of the controller flash and display it. 2281 * 2282 * Return: 0 on success and non-zero on failure. 2283 */ 2284 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc) 2285 { 2286 struct mpi3_ci_upload_request ci_upload; 2287 int retval = -1; 2288 void *data = NULL; 2289 dma_addr_t data_dma; 2290 struct mpi3_ci_manifest_mpi *manifest; 2291 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi); 2292 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2293 2294 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2295 GFP_KERNEL); 2296 if (!data) 2297 return -ENOMEM; 2298 2299 memset(&ci_upload, 0, sizeof(ci_upload)); 2300 mutex_lock(&mrioc->init_cmds.mutex); 2301 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2302 ioc_err(mrioc, "sending get package version failed due to command in use\n"); 2303 mutex_unlock(&mrioc->init_cmds.mutex); 2304 goto out; 2305 } 2306 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2307 mrioc->init_cmds.is_waiting = 1; 2308 mrioc->init_cmds.callback = NULL; 2309 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2310 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD; 2311 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2312 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST); 2313 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE); 2314 ci_upload.segment_size = cpu_to_le32(data_len); 2315 2316 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len, 2317 data_dma); 2318 init_completion(&mrioc->init_cmds.done); 2319 retval = mpi3mr_admin_request_post(mrioc, &ci_upload, 2320 sizeof(ci_upload), 1); 2321 if (retval) { 2322 ioc_err(mrioc, "posting get package version failed\n"); 2323 goto out_unlock; 2324 } 2325 wait_for_completion_timeout(&mrioc->init_cmds.done, 2326 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2327 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2328 ioc_err(mrioc, "get package version timed out\n"); 2329 mpi3mr_check_rh_fault_ioc(mrioc, 2330 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2331 retval = -1; 2332 goto out_unlock; 2333 } 2334 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2335 == MPI3_IOCSTATUS_SUCCESS) { 2336 manifest = (struct mpi3_ci_manifest_mpi *) data; 2337 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) { 2338 ioc_info(mrioc, 2339 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n", 2340 manifest->package_version.gen_major, 2341 manifest->package_version.gen_minor, 2342 manifest->package_version.phase_major, 2343 manifest->package_version.phase_minor, 2344 manifest->package_version.customer_id, 2345 manifest->package_version.build_num); 2346 } 2347 } 2348 retval = 0; 2349 out_unlock: 2350 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2351 mutex_unlock(&mrioc->init_cmds.mutex); 2352 2353 out: 2354 if (data) 2355 dma_free_coherent(&mrioc->pdev->dev, data_len, data, 2356 data_dma); 2357 return retval; 2358 } 2359 2360 /** 2361 * mpi3mr_watchdog_work - watchdog thread to monitor faults 2362 * @work: work struct 2363 * 2364 * Watch dog work periodically executed (1 second interval) to 2365 * monitor firmware fault and to issue periodic timer sync to 2366 * the firmware. 2367 * 2368 * Return: Nothing. 2369 */ 2370 static void mpi3mr_watchdog_work(struct work_struct *work) 2371 { 2372 struct mpi3mr_ioc *mrioc = 2373 container_of(work, struct mpi3mr_ioc, watchdog_work.work); 2374 unsigned long flags; 2375 enum mpi3mr_iocstate ioc_state; 2376 u32 fault, host_diagnostic, ioc_status; 2377 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; 2378 2379 if (mrioc->reset_in_progress || mrioc->unrecoverable) 2380 return; 2381 2382 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) { 2383 mrioc->ts_update_counter = 0; 2384 mpi3mr_sync_timestamp(mrioc); 2385 } 2386 2387 if ((mrioc->prepare_for_reset) && 2388 ((mrioc->prepare_for_reset_timeout_counter++) >= 2389 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 2390 mpi3mr_soft_reset_handler(mrioc, 2391 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 2392 return; 2393 } 2394 2395 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 2396 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 2397 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0); 2398 return; 2399 } 2400 2401 /*Check for fault state every one second and issue Soft reset*/ 2402 ioc_state = mpi3mr_get_iocstate(mrioc); 2403 if (ioc_state != MRIOC_STATE_FAULT) 2404 goto schedule_work; 2405 2406 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK; 2407 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic); 2408 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 2409 if (!mrioc->diagsave_timeout) { 2410 mpi3mr_print_fault_info(mrioc); 2411 ioc_warn(mrioc, "diag save in progress\n"); 2412 } 2413 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 2414 goto schedule_work; 2415 } 2416 2417 mpi3mr_print_fault_info(mrioc); 2418 mrioc->diagsave_timeout = 0; 2419 2420 switch (fault) { 2421 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED: 2422 ioc_info(mrioc, 2423 "controller requires system power cycle, marking controller as unrecoverable\n"); 2424 mrioc->unrecoverable = 1; 2425 return; 2426 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS: 2427 return; 2428 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET: 2429 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT; 2430 break; 2431 default: 2432 break; 2433 } 2434 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0); 2435 return; 2436 2437 schedule_work: 2438 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2439 if (mrioc->watchdog_work_q) 2440 queue_delayed_work(mrioc->watchdog_work_q, 2441 &mrioc->watchdog_work, 2442 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2443 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2444 return; 2445 } 2446 2447 /** 2448 * mpi3mr_start_watchdog - Start watchdog 2449 * @mrioc: Adapter instance reference 2450 * 2451 * Create and start the watchdog thread to monitor controller 2452 * faults. 2453 * 2454 * Return: Nothing. 2455 */ 2456 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc) 2457 { 2458 if (mrioc->watchdog_work_q) 2459 return; 2460 2461 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work); 2462 snprintf(mrioc->watchdog_work_q_name, 2463 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name, 2464 mrioc->id); 2465 mrioc->watchdog_work_q = 2466 create_singlethread_workqueue(mrioc->watchdog_work_q_name); 2467 if (!mrioc->watchdog_work_q) { 2468 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__); 2469 return; 2470 } 2471 2472 if (mrioc->watchdog_work_q) 2473 queue_delayed_work(mrioc->watchdog_work_q, 2474 &mrioc->watchdog_work, 2475 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 2476 } 2477 2478 /** 2479 * mpi3mr_stop_watchdog - Stop watchdog 2480 * @mrioc: Adapter instance reference 2481 * 2482 * Stop the watchdog thread created to monitor controller 2483 * faults. 2484 * 2485 * Return: Nothing. 2486 */ 2487 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc) 2488 { 2489 unsigned long flags; 2490 struct workqueue_struct *wq; 2491 2492 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 2493 wq = mrioc->watchdog_work_q; 2494 mrioc->watchdog_work_q = NULL; 2495 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 2496 if (wq) { 2497 if (!cancel_delayed_work_sync(&mrioc->watchdog_work)) 2498 flush_workqueue(wq); 2499 destroy_workqueue(wq); 2500 } 2501 } 2502 2503 /** 2504 * mpi3mr_setup_admin_qpair - Setup admin queue pair 2505 * @mrioc: Adapter instance reference 2506 * 2507 * Allocate memory for admin queue pair if required and register 2508 * the admin queue with the controller. 2509 * 2510 * Return: 0 on success, non-zero on failures. 2511 */ 2512 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc) 2513 { 2514 int retval = 0; 2515 u32 num_admin_entries = 0; 2516 2517 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE; 2518 mrioc->num_admin_req = mrioc->admin_req_q_sz / 2519 MPI3MR_ADMIN_REQ_FRAME_SZ; 2520 mrioc->admin_req_ci = mrioc->admin_req_pi = 0; 2521 mrioc->admin_req_base = NULL; 2522 2523 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE; 2524 mrioc->num_admin_replies = mrioc->admin_reply_q_sz / 2525 MPI3MR_ADMIN_REPLY_FRAME_SZ; 2526 mrioc->admin_reply_ci = 0; 2527 mrioc->admin_reply_ephase = 1; 2528 mrioc->admin_reply_base = NULL; 2529 2530 if (!mrioc->admin_req_base) { 2531 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev, 2532 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL); 2533 2534 if (!mrioc->admin_req_base) { 2535 retval = -1; 2536 goto out_failed; 2537 } 2538 2539 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev, 2540 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma, 2541 GFP_KERNEL); 2542 2543 if (!mrioc->admin_reply_base) { 2544 retval = -1; 2545 goto out_failed; 2546 } 2547 } 2548 2549 num_admin_entries = (mrioc->num_admin_replies << 16) | 2550 (mrioc->num_admin_req); 2551 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); 2552 mpi3mr_writeq(mrioc->admin_req_dma, 2553 &mrioc->sysif_regs->admin_request_queue_address); 2554 mpi3mr_writeq(mrioc->admin_reply_dma, 2555 &mrioc->sysif_regs->admin_reply_queue_address); 2556 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); 2557 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); 2558 return retval; 2559 2560 out_failed: 2561 2562 if (mrioc->admin_reply_base) { 2563 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 2564 mrioc->admin_reply_base, mrioc->admin_reply_dma); 2565 mrioc->admin_reply_base = NULL; 2566 } 2567 if (mrioc->admin_req_base) { 2568 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 2569 mrioc->admin_req_base, mrioc->admin_req_dma); 2570 mrioc->admin_req_base = NULL; 2571 } 2572 return retval; 2573 } 2574 2575 /** 2576 * mpi3mr_issue_iocfacts - Send IOC Facts 2577 * @mrioc: Adapter instance reference 2578 * @facts_data: Cached IOC facts data 2579 * 2580 * Issue IOC Facts MPI request through admin queue and wait for 2581 * the completion of it or time out. 2582 * 2583 * Return: 0 on success, non-zero on failures. 2584 */ 2585 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc, 2586 struct mpi3_ioc_facts_data *facts_data) 2587 { 2588 struct mpi3_ioc_facts_request iocfacts_req; 2589 void *data = NULL; 2590 dma_addr_t data_dma; 2591 u32 data_len = sizeof(*facts_data); 2592 int retval = 0; 2593 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 2594 2595 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2596 GFP_KERNEL); 2597 2598 if (!data) { 2599 retval = -1; 2600 goto out; 2601 } 2602 2603 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 2604 mutex_lock(&mrioc->init_cmds.mutex); 2605 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 2606 retval = -1; 2607 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n"); 2608 mutex_unlock(&mrioc->init_cmds.mutex); 2609 goto out; 2610 } 2611 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 2612 mrioc->init_cmds.is_waiting = 1; 2613 mrioc->init_cmds.callback = NULL; 2614 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 2615 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS; 2616 2617 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len, 2618 data_dma); 2619 2620 init_completion(&mrioc->init_cmds.done); 2621 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req, 2622 sizeof(iocfacts_req), 1); 2623 if (retval) { 2624 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n"); 2625 goto out_unlock; 2626 } 2627 wait_for_completion_timeout(&mrioc->init_cmds.done, 2628 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 2629 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2630 ioc_err(mrioc, "ioc_facts timed out\n"); 2631 mpi3mr_check_rh_fault_ioc(mrioc, 2632 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 2633 retval = -1; 2634 goto out_unlock; 2635 } 2636 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2637 != MPI3_IOCSTATUS_SUCCESS) { 2638 ioc_err(mrioc, 2639 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 2640 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2641 mrioc->init_cmds.ioc_loginfo); 2642 retval = -1; 2643 goto out_unlock; 2644 } 2645 memcpy(facts_data, (u8 *)data, data_len); 2646 mpi3mr_process_factsdata(mrioc, facts_data); 2647 out_unlock: 2648 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2649 mutex_unlock(&mrioc->init_cmds.mutex); 2650 2651 out: 2652 if (data) 2653 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma); 2654 2655 return retval; 2656 } 2657 2658 /** 2659 * mpi3mr_check_reset_dma_mask - Process IOC facts data 2660 * @mrioc: Adapter instance reference 2661 * 2662 * Check whether the new DMA mask requested through IOCFacts by 2663 * firmware needs to be set, if so set it . 2664 * 2665 * Return: 0 on success, non-zero on failure. 2666 */ 2667 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc) 2668 { 2669 struct pci_dev *pdev = mrioc->pdev; 2670 int r; 2671 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask); 2672 2673 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask)) 2674 return 0; 2675 2676 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n", 2677 mrioc->dma_mask, facts_dma_mask); 2678 2679 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask); 2680 if (r) { 2681 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n", 2682 facts_dma_mask, r); 2683 return r; 2684 } 2685 mrioc->dma_mask = facts_dma_mask; 2686 return r; 2687 } 2688 2689 /** 2690 * mpi3mr_process_factsdata - Process IOC facts data 2691 * @mrioc: Adapter instance reference 2692 * @facts_data: Cached IOC facts data 2693 * 2694 * Convert IOC facts data into cpu endianness and cache it in 2695 * the driver . 2696 * 2697 * Return: Nothing. 2698 */ 2699 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, 2700 struct mpi3_ioc_facts_data *facts_data) 2701 { 2702 u32 ioc_config, req_sz, facts_flags; 2703 2704 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) != 2705 (sizeof(*facts_data) / 4)) { 2706 ioc_warn(mrioc, 2707 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n", 2708 sizeof(*facts_data), 2709 le16_to_cpu(facts_data->ioc_facts_data_length) * 4); 2710 } 2711 2712 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 2713 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 2714 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 2715 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) { 2716 ioc_err(mrioc, 2717 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n", 2718 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size)); 2719 } 2720 2721 memset(&mrioc->facts, 0, sizeof(mrioc->facts)); 2722 2723 facts_flags = le32_to_cpu(facts_data->flags); 2724 mrioc->facts.op_req_sz = req_sz; 2725 mrioc->op_reply_desc_sz = 1 << ((ioc_config & 2726 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 2727 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 2728 2729 mrioc->facts.ioc_num = facts_data->ioc_number; 2730 mrioc->facts.who_init = facts_data->who_init; 2731 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors); 2732 mrioc->facts.personality = (facts_flags & 2733 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 2734 mrioc->facts.dma_mask = (facts_flags & 2735 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 2736 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 2737 mrioc->facts.protocol_flags = facts_data->protocol_flags; 2738 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word); 2739 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests); 2740 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id); 2741 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; 2742 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); 2743 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); 2744 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); 2745 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); 2746 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds); 2747 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds); 2748 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); 2749 mrioc->facts.max_pcie_switches = 2750 le16_to_cpu(facts_data->max_pcie_switches); 2751 mrioc->facts.max_sasexpanders = 2752 le16_to_cpu(facts_data->max_sas_expanders); 2753 mrioc->facts.max_sasinitiators = 2754 le16_to_cpu(facts_data->max_sas_initiators); 2755 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures); 2756 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle); 2757 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle); 2758 mrioc->facts.max_op_req_q = 2759 le16_to_cpu(facts_data->max_operational_request_queues); 2760 mrioc->facts.max_op_reply_q = 2761 le16_to_cpu(facts_data->max_operational_reply_queues); 2762 mrioc->facts.ioc_capabilities = 2763 le32_to_cpu(facts_data->ioc_capabilities); 2764 mrioc->facts.fw_ver.build_num = 2765 le16_to_cpu(facts_data->fw_version.build_num); 2766 mrioc->facts.fw_ver.cust_id = 2767 le16_to_cpu(facts_data->fw_version.customer_id); 2768 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor; 2769 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major; 2770 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor; 2771 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major; 2772 mrioc->msix_count = min_t(int, mrioc->msix_count, 2773 mrioc->facts.max_msix_vectors); 2774 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask; 2775 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value; 2776 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift; 2777 mrioc->facts.shutdown_timeout = 2778 le16_to_cpu(facts_data->shutdown_timeout); 2779 2780 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),", 2781 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, 2782 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); 2783 ioc_info(mrioc, 2784 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n", 2785 mrioc->facts.max_reqs, mrioc->facts.min_devhandle, 2786 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids); 2787 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", 2788 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, 2789 mrioc->facts.sge_mod_shift); 2790 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n", 2791 mrioc->facts.dma_mask, (facts_flags & 2792 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK)); 2793 } 2794 2795 /** 2796 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init 2797 * @mrioc: Adapter instance reference 2798 * 2799 * Allocate and initialize the reply free buffers, sense 2800 * buffers, reply free queue and sense buffer queue. 2801 * 2802 * Return: 0 on success, non-zero on failures. 2803 */ 2804 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) 2805 { 2806 int retval = 0; 2807 u32 sz, i; 2808 2809 if (mrioc->init_cmds.reply) 2810 return retval; 2811 2812 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2813 if (!mrioc->init_cmds.reply) 2814 goto out_failed; 2815 2816 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2817 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz, 2818 GFP_KERNEL); 2819 if (!mrioc->dev_rmhs_cmds[i].reply) 2820 goto out_failed; 2821 } 2822 2823 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 2824 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz, 2825 GFP_KERNEL); 2826 if (!mrioc->evtack_cmds[i].reply) 2827 goto out_failed; 2828 } 2829 2830 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL); 2831 if (!mrioc->host_tm_cmds.reply) 2832 goto out_failed; 2833 2834 mrioc->dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8; 2835 if (mrioc->facts.max_devhandle % 8) 2836 mrioc->dev_handle_bitmap_sz++; 2837 mrioc->removepend_bitmap = kzalloc(mrioc->dev_handle_bitmap_sz, 2838 GFP_KERNEL); 2839 if (!mrioc->removepend_bitmap) 2840 goto out_failed; 2841 2842 mrioc->devrem_bitmap_sz = MPI3MR_NUM_DEVRMCMD / 8; 2843 if (MPI3MR_NUM_DEVRMCMD % 8) 2844 mrioc->devrem_bitmap_sz++; 2845 mrioc->devrem_bitmap = kzalloc(mrioc->devrem_bitmap_sz, 2846 GFP_KERNEL); 2847 if (!mrioc->devrem_bitmap) 2848 goto out_failed; 2849 2850 mrioc->evtack_cmds_bitmap_sz = MPI3MR_NUM_EVTACKCMD / 8; 2851 if (MPI3MR_NUM_EVTACKCMD % 8) 2852 mrioc->evtack_cmds_bitmap_sz++; 2853 mrioc->evtack_cmds_bitmap = kzalloc(mrioc->evtack_cmds_bitmap_sz, 2854 GFP_KERNEL); 2855 if (!mrioc->evtack_cmds_bitmap) 2856 goto out_failed; 2857 2858 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES; 2859 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1; 2860 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 2861 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1; 2862 2863 /* reply buffer pool, 16 byte align */ 2864 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 2865 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool", 2866 &mrioc->pdev->dev, sz, 16, 0); 2867 if (!mrioc->reply_buf_pool) { 2868 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n"); 2869 goto out_failed; 2870 } 2871 2872 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL, 2873 &mrioc->reply_buf_dma); 2874 if (!mrioc->reply_buf) 2875 goto out_failed; 2876 2877 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz; 2878 2879 /* reply free queue, 8 byte align */ 2880 sz = mrioc->reply_free_qsz * 8; 2881 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool", 2882 &mrioc->pdev->dev, sz, 8, 0); 2883 if (!mrioc->reply_free_q_pool) { 2884 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n"); 2885 goto out_failed; 2886 } 2887 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool, 2888 GFP_KERNEL, &mrioc->reply_free_q_dma); 2889 if (!mrioc->reply_free_q) 2890 goto out_failed; 2891 2892 /* sense buffer pool, 4 byte align */ 2893 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 2894 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", 2895 &mrioc->pdev->dev, sz, 4, 0); 2896 if (!mrioc->sense_buf_pool) { 2897 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n"); 2898 goto out_failed; 2899 } 2900 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL, 2901 &mrioc->sense_buf_dma); 2902 if (!mrioc->sense_buf) 2903 goto out_failed; 2904 2905 /* sense buffer queue, 8 byte align */ 2906 sz = mrioc->sense_buf_q_sz * 8; 2907 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool", 2908 &mrioc->pdev->dev, sz, 8, 0); 2909 if (!mrioc->sense_buf_q_pool) { 2910 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n"); 2911 goto out_failed; 2912 } 2913 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool, 2914 GFP_KERNEL, &mrioc->sense_buf_q_dma); 2915 if (!mrioc->sense_buf_q) 2916 goto out_failed; 2917 2918 return retval; 2919 2920 out_failed: 2921 retval = -1; 2922 return retval; 2923 } 2924 2925 /** 2926 * mpimr_initialize_reply_sbuf_queues - initialize reply sense 2927 * buffers 2928 * @mrioc: Adapter instance reference 2929 * 2930 * Helper function to initialize reply and sense buffers along 2931 * with some debug prints. 2932 * 2933 * Return: None. 2934 */ 2935 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc) 2936 { 2937 u32 sz, i; 2938 dma_addr_t phy_addr; 2939 2940 sz = mrioc->num_reply_bufs * mrioc->reply_sz; 2941 ioc_info(mrioc, 2942 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 2943 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz, 2944 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma); 2945 sz = mrioc->reply_free_qsz * 8; 2946 ioc_info(mrioc, 2947 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", 2948 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), 2949 (unsigned long long)mrioc->reply_free_q_dma); 2950 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ; 2951 ioc_info(mrioc, 2952 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 2953 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ, 2954 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma); 2955 sz = mrioc->sense_buf_q_sz * 8; 2956 ioc_info(mrioc, 2957 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", 2958 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024), 2959 (unsigned long long)mrioc->sense_buf_q_dma); 2960 2961 /* initialize Reply buffer Queue */ 2962 for (i = 0, phy_addr = mrioc->reply_buf_dma; 2963 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz) 2964 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr); 2965 mrioc->reply_free_q[i] = cpu_to_le64(0); 2966 2967 /* initialize Sense Buffer Queue */ 2968 for (i = 0, phy_addr = mrioc->sense_buf_dma; 2969 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ) 2970 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); 2971 mrioc->sense_buf_q[i] = cpu_to_le64(0); 2972 } 2973 2974 /** 2975 * mpi3mr_issue_iocinit - Send IOC Init 2976 * @mrioc: Adapter instance reference 2977 * 2978 * Issue IOC Init MPI request through admin queue and wait for 2979 * the completion of it or time out. 2980 * 2981 * Return: 0 on success, non-zero on failures. 2982 */ 2983 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) 2984 { 2985 struct mpi3_ioc_init_request iocinit_req; 2986 struct mpi3_driver_info_layout *drv_info; 2987 dma_addr_t data_dma; 2988 u32 data_len = sizeof(*drv_info); 2989 int retval = 0; 2990 ktime_t current_time; 2991 2992 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma, 2993 GFP_KERNEL); 2994 if (!drv_info) { 2995 retval = -1; 2996 goto out; 2997 } 2998 mpimr_initialize_reply_sbuf_queues(mrioc); 2999 3000 drv_info->information_length = cpu_to_le32(data_len); 3001 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature)); 3002 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name)); 3003 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version)); 3004 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name)); 3005 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version)); 3006 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE, 3007 sizeof(drv_info->driver_release_date)); 3008 drv_info->driver_capabilities = 0; 3009 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info, 3010 sizeof(mrioc->driver_info)); 3011 3012 memset(&iocinit_req, 0, sizeof(iocinit_req)); 3013 mutex_lock(&mrioc->init_cmds.mutex); 3014 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3015 retval = -1; 3016 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n"); 3017 mutex_unlock(&mrioc->init_cmds.mutex); 3018 goto out; 3019 } 3020 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3021 mrioc->init_cmds.is_waiting = 1; 3022 mrioc->init_cmds.callback = NULL; 3023 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3024 iocinit_req.function = MPI3_FUNCTION_IOC_INIT; 3025 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV; 3026 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT; 3027 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR; 3028 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR; 3029 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER; 3030 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); 3031 iocinit_req.reply_free_queue_address = 3032 cpu_to_le64(mrioc->reply_free_q_dma); 3033 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ); 3034 iocinit_req.sense_buffer_free_queue_depth = 3035 cpu_to_le16(mrioc->sense_buf_q_sz); 3036 iocinit_req.sense_buffer_free_queue_address = 3037 cpu_to_le64(mrioc->sense_buf_q_dma); 3038 iocinit_req.driver_information_address = cpu_to_le64(data_dma); 3039 3040 current_time = ktime_get_real(); 3041 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time)); 3042 3043 init_completion(&mrioc->init_cmds.done); 3044 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, 3045 sizeof(iocinit_req), 1); 3046 if (retval) { 3047 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n"); 3048 goto out_unlock; 3049 } 3050 wait_for_completion_timeout(&mrioc->init_cmds.done, 3051 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3052 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3053 mpi3mr_check_rh_fault_ioc(mrioc, 3054 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 3055 ioc_err(mrioc, "ioc_init timed out\n"); 3056 retval = -1; 3057 goto out_unlock; 3058 } 3059 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3060 != MPI3_IOCSTATUS_SUCCESS) { 3061 ioc_err(mrioc, 3062 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3063 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3064 mrioc->init_cmds.ioc_loginfo); 3065 retval = -1; 3066 goto out_unlock; 3067 } 3068 3069 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs; 3070 writel(mrioc->reply_free_queue_host_index, 3071 &mrioc->sysif_regs->reply_free_host_index); 3072 3073 mrioc->sbq_host_index = mrioc->num_sense_bufs; 3074 writel(mrioc->sbq_host_index, 3075 &mrioc->sysif_regs->sense_buffer_free_host_index); 3076 out_unlock: 3077 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3078 mutex_unlock(&mrioc->init_cmds.mutex); 3079 3080 out: 3081 if (drv_info) 3082 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info, 3083 data_dma); 3084 3085 return retval; 3086 } 3087 3088 /** 3089 * mpi3mr_unmask_events - Unmask events in event mask bitmap 3090 * @mrioc: Adapter instance reference 3091 * @event: MPI event ID 3092 * 3093 * Un mask the specific event by resetting the event_mask 3094 * bitmap. 3095 * 3096 * Return: 0 on success, non-zero on failures. 3097 */ 3098 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event) 3099 { 3100 u32 desired_event; 3101 u8 word; 3102 3103 if (event >= 128) 3104 return; 3105 3106 desired_event = (1 << (event % 32)); 3107 word = event / 32; 3108 3109 mrioc->event_masks[word] &= ~desired_event; 3110 } 3111 3112 /** 3113 * mpi3mr_issue_event_notification - Send event notification 3114 * @mrioc: Adapter instance reference 3115 * 3116 * Issue event notification MPI request through admin queue and 3117 * wait for the completion of it or time out. 3118 * 3119 * Return: 0 on success, non-zero on failures. 3120 */ 3121 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc) 3122 { 3123 struct mpi3_event_notification_request evtnotify_req; 3124 int retval = 0; 3125 u8 i; 3126 3127 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 3128 mutex_lock(&mrioc->init_cmds.mutex); 3129 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3130 retval = -1; 3131 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n"); 3132 mutex_unlock(&mrioc->init_cmds.mutex); 3133 goto out; 3134 } 3135 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3136 mrioc->init_cmds.is_waiting = 1; 3137 mrioc->init_cmds.callback = NULL; 3138 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3139 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION; 3140 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3141 evtnotify_req.event_masks[i] = 3142 cpu_to_le32(mrioc->event_masks[i]); 3143 init_completion(&mrioc->init_cmds.done); 3144 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req, 3145 sizeof(evtnotify_req), 1); 3146 if (retval) { 3147 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n"); 3148 goto out_unlock; 3149 } 3150 wait_for_completion_timeout(&mrioc->init_cmds.done, 3151 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3152 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3153 ioc_err(mrioc, "event notification timed out\n"); 3154 mpi3mr_check_rh_fault_ioc(mrioc, 3155 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 3156 retval = -1; 3157 goto out_unlock; 3158 } 3159 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3160 != MPI3_IOCSTATUS_SUCCESS) { 3161 ioc_err(mrioc, 3162 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3163 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3164 mrioc->init_cmds.ioc_loginfo); 3165 retval = -1; 3166 goto out_unlock; 3167 } 3168 3169 out_unlock: 3170 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3171 mutex_unlock(&mrioc->init_cmds.mutex); 3172 out: 3173 return retval; 3174 } 3175 3176 /** 3177 * mpi3mr_process_event_ack - Process event acknowledgment 3178 * @mrioc: Adapter instance reference 3179 * @event: MPI3 event ID 3180 * @event_ctx: event context 3181 * 3182 * Send event acknowledgment through admin queue and wait for 3183 * it to complete. 3184 * 3185 * Return: 0 on success, non-zero on failures. 3186 */ 3187 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 3188 u32 event_ctx) 3189 { 3190 struct mpi3_event_ack_request evtack_req; 3191 int retval = 0; 3192 3193 memset(&evtack_req, 0, sizeof(evtack_req)); 3194 mutex_lock(&mrioc->init_cmds.mutex); 3195 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3196 retval = -1; 3197 ioc_err(mrioc, "Send EvtAck: Init command is in use\n"); 3198 mutex_unlock(&mrioc->init_cmds.mutex); 3199 goto out; 3200 } 3201 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3202 mrioc->init_cmds.is_waiting = 1; 3203 mrioc->init_cmds.callback = NULL; 3204 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3205 evtack_req.function = MPI3_FUNCTION_EVENT_ACK; 3206 evtack_req.event = event; 3207 evtack_req.event_context = cpu_to_le32(event_ctx); 3208 3209 init_completion(&mrioc->init_cmds.done); 3210 retval = mpi3mr_admin_request_post(mrioc, &evtack_req, 3211 sizeof(evtack_req), 1); 3212 if (retval) { 3213 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n"); 3214 goto out_unlock; 3215 } 3216 wait_for_completion_timeout(&mrioc->init_cmds.done, 3217 (MPI3MR_INTADMCMD_TIMEOUT * HZ)); 3218 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3219 ioc_err(mrioc, "Issue EvtNotify: command timed out\n"); 3220 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET)) 3221 mpi3mr_soft_reset_handler(mrioc, 3222 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1); 3223 retval = -1; 3224 goto out_unlock; 3225 } 3226 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 3227 != MPI3_IOCSTATUS_SUCCESS) { 3228 ioc_err(mrioc, 3229 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n", 3230 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3231 mrioc->init_cmds.ioc_loginfo); 3232 retval = -1; 3233 goto out_unlock; 3234 } 3235 3236 out_unlock: 3237 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3238 mutex_unlock(&mrioc->init_cmds.mutex); 3239 out: 3240 return retval; 3241 } 3242 3243 /** 3244 * mpi3mr_alloc_chain_bufs - Allocate chain buffers 3245 * @mrioc: Adapter instance reference 3246 * 3247 * Allocate chain buffers and set a bitmap to indicate free 3248 * chain buffers. Chain buffers are used to pass the SGE 3249 * information along with MPI3 SCSI IO requests for host I/O. 3250 * 3251 * Return: 0 on success, non-zero on failure 3252 */ 3253 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc) 3254 { 3255 int retval = 0; 3256 u32 sz, i; 3257 u16 num_chains; 3258 3259 if (mrioc->chain_sgl_list) 3260 return retval; 3261 3262 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR; 3263 3264 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION 3265 | SHOST_DIX_TYPE1_PROTECTION 3266 | SHOST_DIX_TYPE2_PROTECTION 3267 | SHOST_DIX_TYPE3_PROTECTION)) 3268 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR); 3269 3270 mrioc->chain_buf_count = num_chains; 3271 sz = sizeof(struct chain_element) * num_chains; 3272 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL); 3273 if (!mrioc->chain_sgl_list) 3274 goto out_failed; 3275 3276 sz = MPI3MR_PAGE_SIZE_4K; 3277 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool", 3278 &mrioc->pdev->dev, sz, 16, 0); 3279 if (!mrioc->chain_buf_pool) { 3280 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n"); 3281 goto out_failed; 3282 } 3283 3284 for (i = 0; i < num_chains; i++) { 3285 mrioc->chain_sgl_list[i].addr = 3286 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL, 3287 &mrioc->chain_sgl_list[i].dma_addr); 3288 3289 if (!mrioc->chain_sgl_list[i].addr) 3290 goto out_failed; 3291 } 3292 mrioc->chain_bitmap_sz = num_chains / 8; 3293 if (num_chains % 8) 3294 mrioc->chain_bitmap_sz++; 3295 mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL); 3296 if (!mrioc->chain_bitmap) 3297 goto out_failed; 3298 return retval; 3299 out_failed: 3300 retval = -1; 3301 return retval; 3302 } 3303 3304 /** 3305 * mpi3mr_port_enable_complete - Mark port enable complete 3306 * @mrioc: Adapter instance reference 3307 * @drv_cmd: Internal command tracker 3308 * 3309 * Call back for asynchronous port enable request sets the 3310 * driver command to indicate port enable request is complete. 3311 * 3312 * Return: Nothing 3313 */ 3314 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc, 3315 struct mpi3mr_drv_cmd *drv_cmd) 3316 { 3317 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3318 drv_cmd->callback = NULL; 3319 mrioc->scan_failed = drv_cmd->ioc_status; 3320 mrioc->scan_started = 0; 3321 } 3322 3323 /** 3324 * mpi3mr_issue_port_enable - Issue Port Enable 3325 * @mrioc: Adapter instance reference 3326 * @async: Flag to wait for completion or not 3327 * 3328 * Issue Port Enable MPI request through admin queue and if the 3329 * async flag is not set wait for the completion of the port 3330 * enable or time out. 3331 * 3332 * Return: 0 on success, non-zero on failures. 3333 */ 3334 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async) 3335 { 3336 struct mpi3_port_enable_request pe_req; 3337 int retval = 0; 3338 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT; 3339 3340 memset(&pe_req, 0, sizeof(pe_req)); 3341 mutex_lock(&mrioc->init_cmds.mutex); 3342 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) { 3343 retval = -1; 3344 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n"); 3345 mutex_unlock(&mrioc->init_cmds.mutex); 3346 goto out; 3347 } 3348 mrioc->init_cmds.state = MPI3MR_CMD_PENDING; 3349 if (async) { 3350 mrioc->init_cmds.is_waiting = 0; 3351 mrioc->init_cmds.callback = mpi3mr_port_enable_complete; 3352 } else { 3353 mrioc->init_cmds.is_waiting = 1; 3354 mrioc->init_cmds.callback = NULL; 3355 init_completion(&mrioc->init_cmds.done); 3356 } 3357 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS); 3358 pe_req.function = MPI3_FUNCTION_PORT_ENABLE; 3359 3360 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1); 3361 if (retval) { 3362 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n"); 3363 goto out_unlock; 3364 } 3365 if (async) { 3366 mutex_unlock(&mrioc->init_cmds.mutex); 3367 goto out; 3368 } 3369 3370 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ)); 3371 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3372 ioc_err(mrioc, "port enable timed out\n"); 3373 retval = -1; 3374 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3375 goto out_unlock; 3376 } 3377 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds); 3378 3379 out_unlock: 3380 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED; 3381 mutex_unlock(&mrioc->init_cmds.mutex); 3382 out: 3383 return retval; 3384 } 3385 3386 /* Protocol type to name mapper structure */ 3387 static const struct { 3388 u8 protocol; 3389 char *name; 3390 } mpi3mr_protocols[] = { 3391 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" }, 3392 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" }, 3393 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" }, 3394 }; 3395 3396 /* Capability to name mapper structure*/ 3397 static const struct { 3398 u32 capability; 3399 char *name; 3400 } mpi3mr_capabilities[] = { 3401 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" }, 3402 }; 3403 3404 /** 3405 * mpi3mr_print_ioc_info - Display controller information 3406 * @mrioc: Adapter instance reference 3407 * 3408 * Display controller personalit, capability, supported 3409 * protocols etc. 3410 * 3411 * Return: Nothing 3412 */ 3413 static void 3414 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc) 3415 { 3416 int i = 0, bytes_written = 0; 3417 char personality[16]; 3418 char protocol[50] = {0}; 3419 char capabilities[100] = {0}; 3420 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver; 3421 3422 switch (mrioc->facts.personality) { 3423 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 3424 strncpy(personality, "Enhanced HBA", sizeof(personality)); 3425 break; 3426 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 3427 strncpy(personality, "RAID", sizeof(personality)); 3428 break; 3429 default: 3430 strncpy(personality, "Unknown", sizeof(personality)); 3431 break; 3432 } 3433 3434 ioc_info(mrioc, "Running in %s Personality", personality); 3435 3436 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n", 3437 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 3438 fwver->ph_minor, fwver->cust_id, fwver->build_num); 3439 3440 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) { 3441 if (mrioc->facts.protocol_flags & 3442 mpi3mr_protocols[i].protocol) { 3443 bytes_written += scnprintf(protocol + bytes_written, 3444 sizeof(protocol) - bytes_written, "%s%s", 3445 bytes_written ? "," : "", 3446 mpi3mr_protocols[i].name); 3447 } 3448 } 3449 3450 bytes_written = 0; 3451 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) { 3452 if (mrioc->facts.protocol_flags & 3453 mpi3mr_capabilities[i].capability) { 3454 bytes_written += scnprintf(capabilities + bytes_written, 3455 sizeof(capabilities) - bytes_written, "%s%s", 3456 bytes_written ? "," : "", 3457 mpi3mr_capabilities[i].name); 3458 } 3459 } 3460 3461 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n", 3462 protocol, capabilities); 3463 } 3464 3465 /** 3466 * mpi3mr_cleanup_resources - Free PCI resources 3467 * @mrioc: Adapter instance reference 3468 * 3469 * Unmap PCI device memory and disable PCI device. 3470 * 3471 * Return: 0 on success and non-zero on failure. 3472 */ 3473 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc) 3474 { 3475 struct pci_dev *pdev = mrioc->pdev; 3476 3477 mpi3mr_cleanup_isr(mrioc); 3478 3479 if (mrioc->sysif_regs) { 3480 iounmap((void __iomem *)mrioc->sysif_regs); 3481 mrioc->sysif_regs = NULL; 3482 } 3483 3484 if (pci_is_enabled(pdev)) { 3485 if (mrioc->bars) 3486 pci_release_selected_regions(pdev, mrioc->bars); 3487 pci_disable_device(pdev); 3488 } 3489 } 3490 3491 /** 3492 * mpi3mr_setup_resources - Enable PCI resources 3493 * @mrioc: Adapter instance reference 3494 * 3495 * Enable PCI device memory, MSI-x registers and set DMA mask. 3496 * 3497 * Return: 0 on success and non-zero on failure. 3498 */ 3499 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc) 3500 { 3501 struct pci_dev *pdev = mrioc->pdev; 3502 u32 memap_sz = 0; 3503 int i, retval = 0, capb = 0; 3504 u16 message_control; 3505 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask : 3506 (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) && 3507 (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); 3508 3509 if (pci_enable_device_mem(pdev)) { 3510 ioc_err(mrioc, "pci_enable_device_mem: failed\n"); 3511 retval = -ENODEV; 3512 goto out_failed; 3513 } 3514 3515 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 3516 if (!capb) { 3517 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n"); 3518 retval = -ENODEV; 3519 goto out_failed; 3520 } 3521 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 3522 3523 if (pci_request_selected_regions(pdev, mrioc->bars, 3524 mrioc->driver_name)) { 3525 ioc_err(mrioc, "pci_request_selected_regions: failed\n"); 3526 retval = -ENODEV; 3527 goto out_failed; 3528 } 3529 3530 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) { 3531 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 3532 mrioc->sysif_regs_phys = pci_resource_start(pdev, i); 3533 memap_sz = pci_resource_len(pdev, i); 3534 mrioc->sysif_regs = 3535 ioremap(mrioc->sysif_regs_phys, memap_sz); 3536 break; 3537 } 3538 } 3539 3540 pci_set_master(pdev); 3541 3542 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 3543 if (retval) { 3544 if (dma_mask != DMA_BIT_MASK(32)) { 3545 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n"); 3546 dma_mask = DMA_BIT_MASK(32); 3547 retval = dma_set_mask_and_coherent(&pdev->dev, 3548 dma_mask); 3549 } 3550 if (retval) { 3551 mrioc->dma_mask = 0; 3552 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n"); 3553 goto out_failed; 3554 } 3555 } 3556 mrioc->dma_mask = dma_mask; 3557 3558 if (!mrioc->sysif_regs) { 3559 ioc_err(mrioc, 3560 "Unable to map adapter memory or resource not found\n"); 3561 retval = -EINVAL; 3562 goto out_failed; 3563 } 3564 3565 pci_read_config_word(pdev, capb + 2, &message_control); 3566 mrioc->msix_count = (message_control & 0x3FF) + 1; 3567 3568 pci_save_state(pdev); 3569 3570 pci_set_drvdata(pdev, mrioc->shost); 3571 3572 mpi3mr_ioc_disable_intr(mrioc); 3573 3574 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 3575 (unsigned long long)mrioc->sysif_regs_phys, 3576 mrioc->sysif_regs, memap_sz); 3577 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n", 3578 mrioc->msix_count); 3579 3580 if (!reset_devices && poll_queues > 0) 3581 mrioc->requested_poll_qcount = min_t(int, poll_queues, 3582 mrioc->msix_count - 2); 3583 return retval; 3584 3585 out_failed: 3586 mpi3mr_cleanup_resources(mrioc); 3587 return retval; 3588 } 3589 3590 /** 3591 * mpi3mr_enable_events - Enable required events 3592 * @mrioc: Adapter instance reference 3593 * 3594 * This routine unmasks the events required by the driver by 3595 * sennding appropriate event mask bitmapt through an event 3596 * notification request. 3597 * 3598 * Return: 0 on success and non-zero on failure. 3599 */ 3600 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc) 3601 { 3602 int retval = 0; 3603 u32 i; 3604 3605 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 3606 mrioc->event_masks[i] = -1; 3607 3608 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED); 3609 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED); 3610 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 3611 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 3612 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 3613 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY); 3614 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 3615 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 3616 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 3617 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION); 3618 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET); 3619 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT); 3620 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE); 3621 3622 retval = mpi3mr_issue_event_notification(mrioc); 3623 if (retval) 3624 ioc_err(mrioc, "failed to issue event notification %d\n", 3625 retval); 3626 return retval; 3627 } 3628 3629 /** 3630 * mpi3mr_init_ioc - Initialize the controller 3631 * @mrioc: Adapter instance reference 3632 * 3633 * This the controller initialization routine, executed either 3634 * after soft reset or from pci probe callback. 3635 * Setup the required resources, memory map the controller 3636 * registers, create admin and operational reply queue pairs, 3637 * allocate required memory for reply pool, sense buffer pool, 3638 * issue IOC init request to the firmware, unmask the events and 3639 * issue port enable to discover SAS/SATA/NVMe devies and RAID 3640 * volumes. 3641 * 3642 * Return: 0 on success and non-zero on failure. 3643 */ 3644 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) 3645 { 3646 int retval = 0; 3647 u8 retry = 0; 3648 struct mpi3_ioc_facts_data facts_data; 3649 3650 retry_init: 3651 retval = mpi3mr_bring_ioc_ready(mrioc); 3652 if (retval) { 3653 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n", 3654 retval); 3655 goto out_failed_noretry; 3656 } 3657 3658 retval = mpi3mr_setup_isr(mrioc, 1); 3659 if (retval) { 3660 ioc_err(mrioc, "Failed to setup ISR error %d\n", 3661 retval); 3662 goto out_failed_noretry; 3663 } 3664 3665 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3666 if (retval) { 3667 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n", 3668 retval); 3669 goto out_failed; 3670 } 3671 3672 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD; 3673 3674 if (reset_devices) 3675 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios, 3676 MPI3MR_HOST_IOS_KDUMP); 3677 3678 mrioc->reply_sz = mrioc->facts.reply_sz; 3679 3680 retval = mpi3mr_check_reset_dma_mask(mrioc); 3681 if (retval) { 3682 ioc_err(mrioc, "Resetting dma mask failed %d\n", 3683 retval); 3684 goto out_failed_noretry; 3685 } 3686 3687 mpi3mr_print_ioc_info(mrioc); 3688 3689 retval = mpi3mr_alloc_reply_sense_bufs(mrioc); 3690 if (retval) { 3691 ioc_err(mrioc, 3692 "%s :Failed to allocated reply sense buffers %d\n", 3693 __func__, retval); 3694 goto out_failed_noretry; 3695 } 3696 3697 retval = mpi3mr_alloc_chain_bufs(mrioc); 3698 if (retval) { 3699 ioc_err(mrioc, "Failed to allocated chain buffers %d\n", 3700 retval); 3701 goto out_failed_noretry; 3702 } 3703 3704 retval = mpi3mr_issue_iocinit(mrioc); 3705 if (retval) { 3706 ioc_err(mrioc, "Failed to Issue IOC Init %d\n", 3707 retval); 3708 goto out_failed; 3709 } 3710 3711 retval = mpi3mr_print_pkg_ver(mrioc); 3712 if (retval) { 3713 ioc_err(mrioc, "failed to get package version\n"); 3714 goto out_failed; 3715 } 3716 3717 retval = mpi3mr_setup_isr(mrioc, 0); 3718 if (retval) { 3719 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n", 3720 retval); 3721 goto out_failed_noretry; 3722 } 3723 3724 retval = mpi3mr_create_op_queues(mrioc); 3725 if (retval) { 3726 ioc_err(mrioc, "Failed to create OpQueues error %d\n", 3727 retval); 3728 goto out_failed; 3729 } 3730 3731 retval = mpi3mr_enable_events(mrioc); 3732 if (retval) { 3733 ioc_err(mrioc, "failed to enable events %d\n", 3734 retval); 3735 goto out_failed; 3736 } 3737 3738 ioc_info(mrioc, "controller initialization completed successfully\n"); 3739 return retval; 3740 out_failed: 3741 if (retry < 2) { 3742 retry++; 3743 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n", 3744 retry); 3745 mpi3mr_memset_buffers(mrioc); 3746 goto retry_init; 3747 } 3748 out_failed_noretry: 3749 ioc_err(mrioc, "controller initialization failed\n"); 3750 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 3751 MPI3MR_RESET_FROM_CTLR_CLEANUP); 3752 mrioc->unrecoverable = 1; 3753 return retval; 3754 } 3755 3756 /** 3757 * mpi3mr_reinit_ioc - Re-Initialize the controller 3758 * @mrioc: Adapter instance reference 3759 * @is_resume: Called from resume or reset path 3760 * 3761 * This the controller re-initialization routine, executed from 3762 * the soft reset handler or resume callback. Creates 3763 * operational reply queue pairs, allocate required memory for 3764 * reply pool, sense buffer pool, issue IOC init request to the 3765 * firmware, unmask the events and issue port enable to discover 3766 * SAS/SATA/NVMe devices and RAID volumes. 3767 * 3768 * Return: 0 on success and non-zero on failure. 3769 */ 3770 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume) 3771 { 3772 int retval = 0; 3773 u8 retry = 0; 3774 struct mpi3_ioc_facts_data facts_data; 3775 3776 retry_init: 3777 dprint_reset(mrioc, "bringing up the controller to ready state\n"); 3778 retval = mpi3mr_bring_ioc_ready(mrioc); 3779 if (retval) { 3780 ioc_err(mrioc, "failed to bring to ready state\n"); 3781 goto out_failed_noretry; 3782 } 3783 3784 if (is_resume) { 3785 dprint_reset(mrioc, "setting up single ISR\n"); 3786 retval = mpi3mr_setup_isr(mrioc, 1); 3787 if (retval) { 3788 ioc_err(mrioc, "failed to setup ISR\n"); 3789 goto out_failed_noretry; 3790 } 3791 } else 3792 mpi3mr_ioc_enable_intr(mrioc); 3793 3794 dprint_reset(mrioc, "getting ioc_facts\n"); 3795 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data); 3796 if (retval) { 3797 ioc_err(mrioc, "failed to get ioc_facts\n"); 3798 goto out_failed; 3799 } 3800 3801 dprint_reset(mrioc, "validating ioc_facts\n"); 3802 retval = mpi3mr_revalidate_factsdata(mrioc); 3803 if (retval) { 3804 ioc_err(mrioc, "failed to revalidate ioc_facts data\n"); 3805 goto out_failed_noretry; 3806 } 3807 3808 mpi3mr_print_ioc_info(mrioc); 3809 3810 dprint_reset(mrioc, "sending ioc_init\n"); 3811 retval = mpi3mr_issue_iocinit(mrioc); 3812 if (retval) { 3813 ioc_err(mrioc, "failed to send ioc_init\n"); 3814 goto out_failed; 3815 } 3816 3817 dprint_reset(mrioc, "getting package version\n"); 3818 retval = mpi3mr_print_pkg_ver(mrioc); 3819 if (retval) { 3820 ioc_err(mrioc, "failed to get package version\n"); 3821 goto out_failed; 3822 } 3823 3824 if (is_resume) { 3825 dprint_reset(mrioc, "setting up multiple ISR\n"); 3826 retval = mpi3mr_setup_isr(mrioc, 0); 3827 if (retval) { 3828 ioc_err(mrioc, "failed to re-setup ISR\n"); 3829 goto out_failed_noretry; 3830 } 3831 } 3832 3833 dprint_reset(mrioc, "creating operational queue pairs\n"); 3834 retval = mpi3mr_create_op_queues(mrioc); 3835 if (retval) { 3836 ioc_err(mrioc, "failed to create operational queue pairs\n"); 3837 goto out_failed; 3838 } 3839 3840 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) { 3841 ioc_err(mrioc, 3842 "cannot create minimum number of operational queues expected:%d created:%d\n", 3843 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q); 3844 goto out_failed_noretry; 3845 } 3846 3847 dprint_reset(mrioc, "enabling events\n"); 3848 retval = mpi3mr_enable_events(mrioc); 3849 if (retval) { 3850 ioc_err(mrioc, "failed to enable events\n"); 3851 goto out_failed; 3852 } 3853 3854 ioc_info(mrioc, "sending port enable\n"); 3855 retval = mpi3mr_issue_port_enable(mrioc, 0); 3856 if (retval) { 3857 ioc_err(mrioc, "failed to issue port enable\n"); 3858 goto out_failed; 3859 } 3860 3861 ioc_info(mrioc, "controller %s completed successfully\n", 3862 (is_resume)?"resume":"re-initialization"); 3863 return retval; 3864 out_failed: 3865 if (retry < 2) { 3866 retry++; 3867 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n", 3868 (is_resume)?"resume":"re-initialization", retry); 3869 mpi3mr_memset_buffers(mrioc); 3870 goto retry_init; 3871 } 3872 out_failed_noretry: 3873 ioc_err(mrioc, "controller %s is failed\n", 3874 (is_resume)?"resume":"re-initialization"); 3875 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 3876 MPI3MR_RESET_FROM_CTLR_CLEANUP); 3877 mrioc->unrecoverable = 1; 3878 return retval; 3879 } 3880 3881 /** 3882 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's 3883 * segments 3884 * @mrioc: Adapter instance reference 3885 * @qidx: Operational reply queue index 3886 * 3887 * Return: Nothing. 3888 */ 3889 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 3890 { 3891 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx; 3892 struct segments *segments; 3893 int i, size; 3894 3895 if (!op_reply_q->q_segments) 3896 return; 3897 3898 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz; 3899 segments = op_reply_q->q_segments; 3900 for (i = 0; i < op_reply_q->num_segments; i++) 3901 memset(segments[i].segment, 0, size); 3902 } 3903 3904 /** 3905 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's 3906 * segments 3907 * @mrioc: Adapter instance reference 3908 * @qidx: Operational request queue index 3909 * 3910 * Return: Nothing. 3911 */ 3912 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx) 3913 { 3914 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx; 3915 struct segments *segments; 3916 int i, size; 3917 3918 if (!op_req_q->q_segments) 3919 return; 3920 3921 size = op_req_q->segment_qd * mrioc->facts.op_req_sz; 3922 segments = op_req_q->q_segments; 3923 for (i = 0; i < op_req_q->num_segments; i++) 3924 memset(segments[i].segment, 0, size); 3925 } 3926 3927 /** 3928 * mpi3mr_memset_buffers - memset memory for a controller 3929 * @mrioc: Adapter instance reference 3930 * 3931 * clear all the memory allocated for a controller, typically 3932 * called post reset to reuse the memory allocated during the 3933 * controller init. 3934 * 3935 * Return: Nothing. 3936 */ 3937 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc) 3938 { 3939 u16 i; 3940 3941 mrioc->change_count = 0; 3942 mrioc->active_poll_qcount = 0; 3943 mrioc->default_qcount = 0; 3944 if (mrioc->admin_req_base) 3945 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz); 3946 if (mrioc->admin_reply_base) 3947 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz); 3948 3949 if (mrioc->init_cmds.reply) { 3950 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply)); 3951 memset(mrioc->host_tm_cmds.reply, 0, 3952 sizeof(*mrioc->host_tm_cmds.reply)); 3953 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 3954 memset(mrioc->dev_rmhs_cmds[i].reply, 0, 3955 sizeof(*mrioc->dev_rmhs_cmds[i].reply)); 3956 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 3957 memset(mrioc->evtack_cmds[i].reply, 0, 3958 sizeof(*mrioc->evtack_cmds[i].reply)); 3959 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz); 3960 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz); 3961 memset(mrioc->evtack_cmds_bitmap, 0, 3962 mrioc->evtack_cmds_bitmap_sz); 3963 } 3964 3965 for (i = 0; i < mrioc->num_queues; i++) { 3966 mrioc->op_reply_qinfo[i].qid = 0; 3967 mrioc->op_reply_qinfo[i].ci = 0; 3968 mrioc->op_reply_qinfo[i].num_replies = 0; 3969 mrioc->op_reply_qinfo[i].ephase = 0; 3970 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0); 3971 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0); 3972 mpi3mr_memset_op_reply_q_buffers(mrioc, i); 3973 3974 mrioc->req_qinfo[i].ci = 0; 3975 mrioc->req_qinfo[i].pi = 0; 3976 mrioc->req_qinfo[i].num_requests = 0; 3977 mrioc->req_qinfo[i].qid = 0; 3978 mrioc->req_qinfo[i].reply_qid = 0; 3979 spin_lock_init(&mrioc->req_qinfo[i].q_lock); 3980 mpi3mr_memset_op_req_q_buffers(mrioc, i); 3981 } 3982 } 3983 3984 /** 3985 * mpi3mr_free_mem - Free memory allocated for a controller 3986 * @mrioc: Adapter instance reference 3987 * 3988 * Free all the memory allocated for a controller. 3989 * 3990 * Return: Nothing. 3991 */ 3992 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc) 3993 { 3994 u16 i; 3995 struct mpi3mr_intr_info *intr_info; 3996 3997 if (mrioc->sense_buf_pool) { 3998 if (mrioc->sense_buf) 3999 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf, 4000 mrioc->sense_buf_dma); 4001 dma_pool_destroy(mrioc->sense_buf_pool); 4002 mrioc->sense_buf = NULL; 4003 mrioc->sense_buf_pool = NULL; 4004 } 4005 if (mrioc->sense_buf_q_pool) { 4006 if (mrioc->sense_buf_q) 4007 dma_pool_free(mrioc->sense_buf_q_pool, 4008 mrioc->sense_buf_q, mrioc->sense_buf_q_dma); 4009 dma_pool_destroy(mrioc->sense_buf_q_pool); 4010 mrioc->sense_buf_q = NULL; 4011 mrioc->sense_buf_q_pool = NULL; 4012 } 4013 4014 if (mrioc->reply_buf_pool) { 4015 if (mrioc->reply_buf) 4016 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf, 4017 mrioc->reply_buf_dma); 4018 dma_pool_destroy(mrioc->reply_buf_pool); 4019 mrioc->reply_buf = NULL; 4020 mrioc->reply_buf_pool = NULL; 4021 } 4022 if (mrioc->reply_free_q_pool) { 4023 if (mrioc->reply_free_q) 4024 dma_pool_free(mrioc->reply_free_q_pool, 4025 mrioc->reply_free_q, mrioc->reply_free_q_dma); 4026 dma_pool_destroy(mrioc->reply_free_q_pool); 4027 mrioc->reply_free_q = NULL; 4028 mrioc->reply_free_q_pool = NULL; 4029 } 4030 4031 for (i = 0; i < mrioc->num_op_req_q; i++) 4032 mpi3mr_free_op_req_q_segments(mrioc, i); 4033 4034 for (i = 0; i < mrioc->num_op_reply_q; i++) 4035 mpi3mr_free_op_reply_q_segments(mrioc, i); 4036 4037 for (i = 0; i < mrioc->intr_info_count; i++) { 4038 intr_info = mrioc->intr_info + i; 4039 intr_info->op_reply_q = NULL; 4040 } 4041 4042 kfree(mrioc->req_qinfo); 4043 mrioc->req_qinfo = NULL; 4044 mrioc->num_op_req_q = 0; 4045 4046 kfree(mrioc->op_reply_qinfo); 4047 mrioc->op_reply_qinfo = NULL; 4048 mrioc->num_op_reply_q = 0; 4049 4050 kfree(mrioc->init_cmds.reply); 4051 mrioc->init_cmds.reply = NULL; 4052 4053 kfree(mrioc->host_tm_cmds.reply); 4054 mrioc->host_tm_cmds.reply = NULL; 4055 4056 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4057 kfree(mrioc->evtack_cmds[i].reply); 4058 mrioc->evtack_cmds[i].reply = NULL; 4059 } 4060 4061 kfree(mrioc->removepend_bitmap); 4062 mrioc->removepend_bitmap = NULL; 4063 4064 kfree(mrioc->devrem_bitmap); 4065 mrioc->devrem_bitmap = NULL; 4066 4067 kfree(mrioc->evtack_cmds_bitmap); 4068 mrioc->evtack_cmds_bitmap = NULL; 4069 4070 kfree(mrioc->chain_bitmap); 4071 mrioc->chain_bitmap = NULL; 4072 4073 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4074 kfree(mrioc->dev_rmhs_cmds[i].reply); 4075 mrioc->dev_rmhs_cmds[i].reply = NULL; 4076 } 4077 4078 if (mrioc->chain_buf_pool) { 4079 for (i = 0; i < mrioc->chain_buf_count; i++) { 4080 if (mrioc->chain_sgl_list[i].addr) { 4081 dma_pool_free(mrioc->chain_buf_pool, 4082 mrioc->chain_sgl_list[i].addr, 4083 mrioc->chain_sgl_list[i].dma_addr); 4084 mrioc->chain_sgl_list[i].addr = NULL; 4085 } 4086 } 4087 dma_pool_destroy(mrioc->chain_buf_pool); 4088 mrioc->chain_buf_pool = NULL; 4089 } 4090 4091 kfree(mrioc->chain_sgl_list); 4092 mrioc->chain_sgl_list = NULL; 4093 4094 if (mrioc->admin_reply_base) { 4095 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz, 4096 mrioc->admin_reply_base, mrioc->admin_reply_dma); 4097 mrioc->admin_reply_base = NULL; 4098 } 4099 if (mrioc->admin_req_base) { 4100 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz, 4101 mrioc->admin_req_base, mrioc->admin_req_dma); 4102 mrioc->admin_req_base = NULL; 4103 } 4104 } 4105 4106 /** 4107 * mpi3mr_issue_ioc_shutdown - shutdown controller 4108 * @mrioc: Adapter instance reference 4109 * 4110 * Send shutodwn notification to the controller and wait for the 4111 * shutdown_timeout for it to be completed. 4112 * 4113 * Return: Nothing. 4114 */ 4115 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) 4116 { 4117 u32 ioc_config, ioc_status; 4118 u8 retval = 1; 4119 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 4120 4121 ioc_info(mrioc, "Issuing shutdown Notification\n"); 4122 if (mrioc->unrecoverable) { 4123 ioc_warn(mrioc, 4124 "IOC is unrecoverable shutdown is not issued\n"); 4125 return; 4126 } 4127 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4128 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4129 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 4130 ioc_info(mrioc, "shutdown already in progress\n"); 4131 return; 4132 } 4133 4134 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4135 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 4136 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 4137 4138 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); 4139 4140 if (mrioc->facts.shutdown_timeout) 4141 timeout = mrioc->facts.shutdown_timeout * 10; 4142 4143 do { 4144 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4145 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4146 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 4147 retval = 0; 4148 break; 4149 } 4150 msleep(100); 4151 } while (--timeout); 4152 4153 ioc_status = readl(&mrioc->sysif_regs->ioc_status); 4154 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); 4155 4156 if (retval) { 4157 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 4158 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 4159 ioc_warn(mrioc, 4160 "shutdown still in progress after timeout\n"); 4161 } 4162 4163 ioc_info(mrioc, 4164 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n", 4165 (!retval) ? "successful" : "failed", ioc_status, 4166 ioc_config); 4167 } 4168 4169 /** 4170 * mpi3mr_cleanup_ioc - Cleanup controller 4171 * @mrioc: Adapter instance reference 4172 * 4173 * controller cleanup handler, Message unit reset or soft reset 4174 * and shutdown notification is issued to the controller. 4175 * 4176 * Return: Nothing. 4177 */ 4178 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc) 4179 { 4180 enum mpi3mr_iocstate ioc_state; 4181 4182 dprint_exit(mrioc, "cleaning up the controller\n"); 4183 mpi3mr_ioc_disable_intr(mrioc); 4184 4185 ioc_state = mpi3mr_get_iocstate(mrioc); 4186 4187 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) && 4188 (ioc_state == MRIOC_STATE_READY)) { 4189 if (mpi3mr_issue_and_process_mur(mrioc, 4190 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 4191 mpi3mr_issue_reset(mrioc, 4192 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 4193 MPI3MR_RESET_FROM_MUR_FAILURE); 4194 mpi3mr_issue_ioc_shutdown(mrioc); 4195 } 4196 dprint_exit(mrioc, "controller cleanup completed\n"); 4197 } 4198 4199 /** 4200 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 4201 * @mrioc: Adapter instance reference 4202 * @cmdptr: Internal command tracker 4203 * 4204 * Complete an internal driver commands with state indicating it 4205 * is completed due to reset. 4206 * 4207 * Return: Nothing. 4208 */ 4209 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc, 4210 struct mpi3mr_drv_cmd *cmdptr) 4211 { 4212 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4213 cmdptr->state |= MPI3MR_CMD_RESET; 4214 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4215 if (cmdptr->is_waiting) { 4216 complete(&cmdptr->done); 4217 cmdptr->is_waiting = 0; 4218 } else if (cmdptr->callback) 4219 cmdptr->callback(mrioc, cmdptr); 4220 } 4221 } 4222 4223 /** 4224 * mpi3mr_flush_drv_cmds - Flush internaldriver commands 4225 * @mrioc: Adapter instance reference 4226 * 4227 * Flush all internal driver commands post reset 4228 * 4229 * Return: Nothing. 4230 */ 4231 static void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc) 4232 { 4233 struct mpi3mr_drv_cmd *cmdptr; 4234 u8 i; 4235 4236 cmdptr = &mrioc->init_cmds; 4237 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4238 cmdptr = &mrioc->host_tm_cmds; 4239 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4240 4241 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 4242 cmdptr = &mrioc->dev_rmhs_cmds[i]; 4243 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4244 } 4245 4246 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 4247 cmdptr = &mrioc->evtack_cmds[i]; 4248 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr); 4249 } 4250 } 4251 4252 /** 4253 * mpi3mr_soft_reset_handler - Reset the controller 4254 * @mrioc: Adapter instance reference 4255 * @reset_reason: Reset reason code 4256 * @snapdump: Flag to generate snapdump in firmware or not 4257 * 4258 * This is an handler for recovering controller by issuing soft 4259 * reset are diag fault reset. This is a blocking function and 4260 * when one reset is executed if any other resets they will be 4261 * blocked. All IOCTLs/IO will be blocked during the reset. If 4262 * controller reset is successful then the controller will be 4263 * reinitalized, otherwise the controller will be marked as not 4264 * recoverable 4265 * 4266 * In snapdump bit is set, the controller is issued with diag 4267 * fault reset so that the firmware can create a snap dump and 4268 * post that the firmware will result in F000 fault and the 4269 * driver will issue soft reset to recover from that. 4270 * 4271 * Return: 0 on success, non-zero on failure. 4272 */ 4273 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 4274 u32 reset_reason, u8 snapdump) 4275 { 4276 int retval = 0, i; 4277 unsigned long flags; 4278 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 4279 4280 /* Block the reset handler until diag save in progress*/ 4281 dprint_reset(mrioc, 4282 "soft_reset_handler: check and block on diagsave_timeout(%d)\n", 4283 mrioc->diagsave_timeout); 4284 while (mrioc->diagsave_timeout) 4285 ssleep(1); 4286 /* 4287 * Block new resets until the currently executing one is finished and 4288 * return the status of the existing reset for all blocked resets 4289 */ 4290 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n"); 4291 if (!mutex_trylock(&mrioc->reset_mutex)) { 4292 ioc_info(mrioc, 4293 "controller reset triggered by %s is blocked due to another reset in progress\n", 4294 mpi3mr_reset_rc_name(reset_reason)); 4295 do { 4296 ssleep(1); 4297 } while (mrioc->reset_in_progress == 1); 4298 ioc_info(mrioc, 4299 "returning previous reset result(%d) for the reset triggered by %s\n", 4300 mrioc->prev_reset_result, 4301 mpi3mr_reset_rc_name(reset_reason)); 4302 return mrioc->prev_reset_result; 4303 } 4304 ioc_info(mrioc, "controller reset is triggered by %s\n", 4305 mpi3mr_reset_rc_name(reset_reason)); 4306 4307 mrioc->reset_in_progress = 1; 4308 mrioc->prev_reset_result = -1; 4309 4310 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 4311 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 4312 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 4313 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4314 mrioc->event_masks[i] = -1; 4315 4316 dprint_reset(mrioc, "soft_reset_handler: masking events\n"); 4317 mpi3mr_issue_event_notification(mrioc); 4318 } 4319 4320 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT); 4321 4322 mpi3mr_ioc_disable_intr(mrioc); 4323 4324 if (snapdump) { 4325 mpi3mr_set_diagsave(mrioc); 4326 retval = mpi3mr_issue_reset(mrioc, 4327 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4328 if (!retval) { 4329 do { 4330 host_diagnostic = 4331 readl(&mrioc->sysif_regs->host_diagnostic); 4332 if (!(host_diagnostic & 4333 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 4334 break; 4335 msleep(100); 4336 } while (--timeout); 4337 } 4338 } 4339 4340 retval = mpi3mr_issue_reset(mrioc, 4341 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 4342 if (retval) { 4343 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n"); 4344 goto out; 4345 } 4346 4347 mpi3mr_flush_delayed_cmd_lists(mrioc); 4348 mpi3mr_flush_drv_cmds(mrioc); 4349 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz); 4350 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz); 4351 memset(mrioc->evtack_cmds_bitmap, 0, mrioc->evtack_cmds_bitmap_sz); 4352 mpi3mr_flush_host_io(mrioc); 4353 mpi3mr_cleanup_fwevt_list(mrioc); 4354 mpi3mr_invalidate_devhandles(mrioc); 4355 if (mrioc->prepare_for_reset) { 4356 mrioc->prepare_for_reset = 0; 4357 mrioc->prepare_for_reset_timeout_counter = 0; 4358 } 4359 mpi3mr_memset_buffers(mrioc); 4360 retval = mpi3mr_reinit_ioc(mrioc, 0); 4361 if (retval) { 4362 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n", 4363 mrioc->name, reset_reason); 4364 goto out; 4365 } 4366 ssleep(10); 4367 4368 out: 4369 if (!retval) { 4370 mrioc->diagsave_timeout = 0; 4371 mrioc->reset_in_progress = 0; 4372 mpi3mr_rfresh_tgtdevs(mrioc); 4373 mrioc->ts_update_counter = 0; 4374 spin_lock_irqsave(&mrioc->watchdog_lock, flags); 4375 if (mrioc->watchdog_work_q) 4376 queue_delayed_work(mrioc->watchdog_work_q, 4377 &mrioc->watchdog_work, 4378 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL)); 4379 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags); 4380 } else { 4381 mpi3mr_issue_reset(mrioc, 4382 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 4383 mrioc->unrecoverable = 1; 4384 mrioc->reset_in_progress = 0; 4385 retval = -1; 4386 } 4387 mrioc->prev_reset_result = retval; 4388 mutex_unlock(&mrioc->reset_mutex); 4389 ioc_info(mrioc, "controller reset is %s\n", 4390 ((retval == 0) ? "successful" : "failed")); 4391 return retval; 4392 } 4393