1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/workqueue.h> 33 #include <asm/unaligned.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_dbg.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 #include <scsi/scsi_tcq.h> 40 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 41 #include <scsi/scsi_transport_sas.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.4.1.0.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2023" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_MAX_SECTORS 2048 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 74 75 /* Definitions for MAX values for shost */ 76 #define MPI3MR_MAX_CMDS_LUN 128 77 #define MPI3MR_MAX_CDB_LENGTH 32 78 79 /* Admin queue management definitions */ 80 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 81 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 83 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 84 85 /* Operational queue management definitions */ 86 #define MPI3MR_OP_REQ_Q_QD 512 87 #define MPI3MR_OP_REP_Q_QD 1024 88 #define MPI3MR_OP_REP_Q_QD4K 4096 89 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 90 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 91 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 92 93 /* Reserved Host Tag definitions */ 94 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 95 #define MPI3MR_HOSTTAG_INITCMDS 1 96 #define MPI3MR_HOSTTAG_BSG_CMDS 2 97 #define MPI3MR_HOSTTAG_PEL_ABORT 3 98 #define MPI3MR_HOSTTAG_PEL_WAIT 4 99 #define MPI3MR_HOSTTAG_BLK_TMS 5 100 #define MPI3MR_HOSTTAG_CFG_CMDS 6 101 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 102 103 #define MPI3MR_NUM_DEVRMCMD 16 104 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 105 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 106 MPI3MR_NUM_DEVRMCMD - 1) 107 108 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 109 #define MPI3MR_NUM_EVTACKCMD 4 110 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 111 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 112 MPI3MR_NUM_EVTACKCMD - 1) 113 114 /* Reduced resource count definition for crash kernel */ 115 #define MPI3MR_HOST_IOS_KDUMP 128 116 117 /* command/controller interaction timeout definitions in seconds */ 118 #define MPI3MR_INTADMCMD_TIMEOUT 60 119 #define MPI3MR_PORTENABLE_TIMEOUT 300 120 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5 121 #define MPI3MR_ABORTTM_TIMEOUT 60 122 #define MPI3MR_RESETTM_TIMEOUT 60 123 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 124 #define MPI3MR_TSUPDATE_INTERVAL 900 125 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 126 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 127 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 128 #define MPI3MR_RESET_ACK_TIMEOUT 30 129 #define MPI3MR_MUR_TIMEOUT 120 130 131 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 132 133 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 134 135 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 136 137 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 138 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 139 140 /* Internal admin command state definitions*/ 141 #define MPI3MR_CMD_NOTUSED 0x8000 142 #define MPI3MR_CMD_COMPLETE 0x0001 143 #define MPI3MR_CMD_PENDING 0x0002 144 #define MPI3MR_CMD_REPLY_VALID 0x0004 145 #define MPI3MR_CMD_RESET 0x0008 146 147 /* Definitions for Event replies and sense buffer allocated per controller */ 148 #define MPI3MR_NUM_EVT_REPLIES 64 149 #define MPI3MR_SENSE_BUF_SZ 256 150 #define MPI3MR_SENSEBUF_FACTOR 3 151 #define MPI3MR_CHAINBUF_FACTOR 3 152 #define MPI3MR_CHAINBUFDIX_FACTOR 2 153 154 /* Invalid target device handle */ 155 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 156 157 /* Controller Reset related definitions */ 158 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 159 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 160 161 /* ResponseCode definitions */ 162 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 163 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 164 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 165 166 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 167 #define MPI3MR_DEFAULT_PGSZEXP (12) 168 169 /* Command retry count definitions */ 170 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 171 #define MPI3MR_PEL_RETRY_COUNT 3 172 173 /* Default target device queue depth */ 174 #define MPI3MR_DEFAULT_SDEV_QD 32 175 176 /* Definitions for Threaded IRQ poll*/ 177 #define MPI3MR_IRQ_POLL_SLEEP 2 178 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 179 180 /* Definitions for the controller security status*/ 181 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 182 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 183 184 #define MPI3MR_INVALID_DEVICE 0x00 185 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 186 #define MPI3MR_HARD_SECURE_DEVICE 0x08 187 #define MPI3MR_TAMPERED_DEVICE 0x0C 188 189 /* SGE Flag definition */ 190 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 191 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 192 MPI3_SGE_FLAGS_END_OF_LIST) 193 194 /* MSI Index from Reply Queue Index */ 195 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 196 197 /* 198 * Maximum data transfer size definitions for management 199 * application commands 200 */ 201 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 202 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 203 /* 204 * 2048 sectors are for data buffers and additional 512 sectors for 205 * other buffers 206 */ 207 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 208 209 /** 210 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 211 * Encapsulated commands. 212 * 213 * @base_addr: Physical address 214 * @length: SGE length 215 * @rsvd: Reserved 216 * @rsvd1: Reserved 217 * @sgl_type: sgl type 218 */ 219 struct mpi3mr_nvme_pt_sge { 220 u64 base_addr; 221 u32 length; 222 u16 rsvd; 223 u8 rsvd1; 224 u8 sgl_type; 225 }; 226 227 /** 228 * struct mpi3mr_buf_map - local structure to 229 * track kernel and user buffers associated with an BSG 230 * structure. 231 * 232 * @bsg_buf: BSG buffer virtual address 233 * @bsg_buf_len: BSG buffer length 234 * @kern_buf: Kernel buffer virtual address 235 * @kern_buf_len: Kernel buffer length 236 * @kern_buf_dma: Kernel buffer DMA address 237 * @data_dir: Data direction. 238 */ 239 struct mpi3mr_buf_map { 240 void *bsg_buf; 241 u32 bsg_buf_len; 242 void *kern_buf; 243 u32 kern_buf_len; 244 dma_addr_t kern_buf_dma; 245 u8 data_dir; 246 }; 247 248 /* IOC State definitions */ 249 enum mpi3mr_iocstate { 250 MRIOC_STATE_READY = 1, 251 MRIOC_STATE_RESET, 252 MRIOC_STATE_FAULT, 253 MRIOC_STATE_BECOMING_READY, 254 MRIOC_STATE_RESET_REQUESTED, 255 MRIOC_STATE_UNRECOVERABLE, 256 }; 257 258 /* Reset reason code definitions*/ 259 enum mpi3mr_reset_reason { 260 MPI3MR_RESET_FROM_BRINGUP = 1, 261 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 262 MPI3MR_RESET_FROM_APP = 3, 263 MPI3MR_RESET_FROM_EH_HOS = 4, 264 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 265 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 266 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 267 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 268 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 269 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 270 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 271 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 272 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 273 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 274 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 275 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 276 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 277 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 278 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 279 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 280 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 281 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 282 MPI3MR_RESET_FROM_SYSFS = 23, 283 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 284 MPI3MR_RESET_FROM_FIRMWARE = 27, 285 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 286 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 287 }; 288 289 /* Queue type definitions */ 290 enum queue_type { 291 MPI3MR_DEFAULT_QUEUE = 0, 292 MPI3MR_POLL_QUEUE, 293 }; 294 295 /** 296 * struct mpi3mr_compimg_ver - replica of component image 297 * version defined in mpi30_image.h in host endianness 298 * 299 */ 300 struct mpi3mr_compimg_ver { 301 u16 build_num; 302 u16 cust_id; 303 u8 ph_minor; 304 u8 ph_major; 305 u8 gen_minor; 306 u8 gen_major; 307 }; 308 309 /** 310 * struct mpi3mr_ioc_facs - replica of component image version 311 * defined in mpi30_ioc.h in host endianness 312 * 313 */ 314 struct mpi3mr_ioc_facts { 315 u32 ioc_capabilities; 316 struct mpi3mr_compimg_ver fw_ver; 317 u32 mpi_version; 318 u16 max_reqs; 319 u16 product_id; 320 u16 op_req_sz; 321 u16 reply_sz; 322 u16 exceptions; 323 u16 max_perids; 324 u16 max_pds; 325 u16 max_sasexpanders; 326 u16 max_sasinitiators; 327 u16 max_enclosures; 328 u16 max_pcie_switches; 329 u16 max_nvme; 330 u16 max_vds; 331 u16 max_hpds; 332 u16 max_advhpds; 333 u16 max_raid_pds; 334 u16 min_devhandle; 335 u16 max_devhandle; 336 u16 max_op_req_q; 337 u16 max_op_reply_q; 338 u16 shutdown_timeout; 339 u8 ioc_num; 340 u8 who_init; 341 u16 max_msix_vectors; 342 u8 personality; 343 u8 dma_mask; 344 u8 protocol_flags; 345 u8 sge_mod_mask; 346 u8 sge_mod_value; 347 u8 sge_mod_shift; 348 u8 max_dev_per_tg; 349 u16 max_io_throttle_group; 350 u16 io_throttle_data_length; 351 u16 io_throttle_low; 352 u16 io_throttle_high; 353 354 }; 355 356 /** 357 * struct segments - memory descriptor structure to store 358 * virtual and dma addresses for operational queue segments. 359 * 360 * @segment: virtual address 361 * @segment_dma: dma address 362 */ 363 struct segments { 364 void *segment; 365 dma_addr_t segment_dma; 366 }; 367 368 /** 369 * struct op_req_qinfo - Operational Request Queue Information 370 * 371 * @ci: consumer index 372 * @pi: producer index 373 * @num_request: Maximum number of entries in the queue 374 * @qid: Queue Id starting from 1 375 * @reply_qid: Associated reply queue Id 376 * @num_segments: Number of discontiguous memory segments 377 * @segment_qd: Depth of each segments 378 * @q_lock: Concurrent queue access lock 379 * @q_segments: Segment descriptor pointer 380 * @q_segment_list: Segment list base virtual address 381 * @q_segment_list_dma: Segment list base DMA address 382 */ 383 struct op_req_qinfo { 384 u16 ci; 385 u16 pi; 386 u16 num_requests; 387 u16 qid; 388 u16 reply_qid; 389 u16 num_segments; 390 u16 segment_qd; 391 spinlock_t q_lock; 392 struct segments *q_segments; 393 void *q_segment_list; 394 dma_addr_t q_segment_list_dma; 395 }; 396 397 /** 398 * struct op_reply_qinfo - Operational Reply Queue Information 399 * 400 * @ci: consumer index 401 * @qid: Queue Id starting from 1 402 * @num_replies: Maximum number of entries in the queue 403 * @num_segments: Number of discontiguous memory segments 404 * @segment_qd: Depth of each segments 405 * @q_segments: Segment descriptor pointer 406 * @q_segment_list: Segment list base virtual address 407 * @q_segment_list_dma: Segment list base DMA address 408 * @ephase: Expected phased identifier for the reply queue 409 * @pend_ios: Number of IOs pending in HW for this queue 410 * @enable_irq_poll: Flag to indicate polling is enabled 411 * @in_use: Queue is handled by poll/ISR 412 * @qtype: Type of queue (types defined in enum queue_type) 413 */ 414 struct op_reply_qinfo { 415 u16 ci; 416 u16 qid; 417 u16 num_replies; 418 u16 num_segments; 419 u16 segment_qd; 420 struct segments *q_segments; 421 void *q_segment_list; 422 dma_addr_t q_segment_list_dma; 423 u8 ephase; 424 atomic_t pend_ios; 425 bool enable_irq_poll; 426 atomic_t in_use; 427 enum queue_type qtype; 428 }; 429 430 /** 431 * struct mpi3mr_intr_info - Interrupt cookie information 432 * 433 * @mrioc: Adapter instance reference 434 * @os_irq: irq number 435 * @msix_index: MSIx index 436 * @op_reply_q: Associated operational reply queue 437 * @name: Dev name for the irq claiming device 438 */ 439 struct mpi3mr_intr_info { 440 struct mpi3mr_ioc *mrioc; 441 int os_irq; 442 u16 msix_index; 443 struct op_reply_qinfo *op_reply_q; 444 char name[MPI3MR_NAME_LENGTH]; 445 }; 446 447 /** 448 * struct mpi3mr_throttle_group_info - Throttle group info 449 * 450 * @io_divert: Flag indicates io divert is on or off for the TG 451 * @need_qd_reduction: Flag to indicate QD reduction is needed 452 * @qd_reduction: Queue Depth reduction in units of 10% 453 * @fw_qd: QueueDepth value reported by the firmware 454 * @modified_qd: Modified QueueDepth value due to throttling 455 * @id: Throttle Group ID. 456 * @high: High limit to turn on throttling in 512 byte blocks 457 * @low: Low limit to turn off throttling in 512 byte blocks 458 * @pend_large_data_sz: Counter to track pending large data 459 */ 460 struct mpi3mr_throttle_group_info { 461 u8 io_divert; 462 u8 need_qd_reduction; 463 u8 qd_reduction; 464 u16 fw_qd; 465 u16 modified_qd; 466 u16 id; 467 u32 high; 468 u32 low; 469 atomic_t pend_large_data_sz; 470 }; 471 472 /* HBA port flags */ 473 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 474 475 /** 476 * struct mpi3mr_hba_port - HBA's port information 477 * @port_id: Port number 478 * @flags: HBA port flags 479 */ 480 struct mpi3mr_hba_port { 481 struct list_head list; 482 u8 port_id; 483 u8 flags; 484 }; 485 486 /** 487 * struct mpi3mr_sas_port - Internal SAS port information 488 * @port_list: List of ports belonging to a SAS node 489 * @num_phys: Number of phys associated with port 490 * @marked_responding: used while refresing the sas ports 491 * @lowest_phy: lowest phy ID of current sas port 492 * @phy_mask: phy_mask of current sas port 493 * @hba_port: HBA port entry 494 * @remote_identify: Attached device identification 495 * @rphy: SAS transport layer rphy object 496 * @port: SAS transport layer port object 497 * @phy_list: mpi3mr_sas_phy objects belonging to this port 498 */ 499 struct mpi3mr_sas_port { 500 struct list_head port_list; 501 u8 num_phys; 502 u8 marked_responding; 503 int lowest_phy; 504 u32 phy_mask; 505 struct mpi3mr_hba_port *hba_port; 506 struct sas_identify remote_identify; 507 struct sas_rphy *rphy; 508 struct sas_port *port; 509 struct list_head phy_list; 510 }; 511 512 /** 513 * struct mpi3mr_sas_phy - Internal SAS Phy information 514 * @port_siblings: List of phys belonging to a port 515 * @identify: Phy identification 516 * @remote_identify: Attached device identification 517 * @phy: SAS transport layer Phy object 518 * @phy_id: Unique phy id within a port 519 * @handle: Firmware device handle for this phy 520 * @attached_handle: Firmware device handle for attached device 521 * @phy_belongs_to_port: Flag to indicate phy belongs to port 522 @hba_port: HBA port entry 523 */ 524 struct mpi3mr_sas_phy { 525 struct list_head port_siblings; 526 struct sas_identify identify; 527 struct sas_identify remote_identify; 528 struct sas_phy *phy; 529 u8 phy_id; 530 u16 handle; 531 u16 attached_handle; 532 u8 phy_belongs_to_port; 533 struct mpi3mr_hba_port *hba_port; 534 }; 535 536 /** 537 * struct mpi3mr_sas_node - SAS host/expander information 538 * @list: List of sas nodes in a controller 539 * @parent_dev: Parent device class 540 * @num_phys: Number phys belonging to sas_node 541 * @sas_address: SAS address of sas_node 542 * @handle: Firmware device handle for this sas_host/expander 543 * @sas_address_parent: SAS address of parent expander or host 544 * @enclosure_handle: Firmware handle of enclosure of this node 545 * @device_info: Capabilities of this sas_host/expander 546 * @non_responding: used to refresh the expander devices during reset 547 * @host_node: Flag to indicate this is a host_node 548 * @hba_port: HBA port entry 549 * @phy: A list of phys that make up this sas_host/expander 550 * @sas_port_list: List of internal ports of this node 551 * @rphy: sas_rphy object of this expander node 552 */ 553 struct mpi3mr_sas_node { 554 struct list_head list; 555 struct device *parent_dev; 556 u8 num_phys; 557 u64 sas_address; 558 u16 handle; 559 u64 sas_address_parent; 560 u16 enclosure_handle; 561 u64 enclosure_logical_id; 562 u8 non_responding; 563 u8 host_node; 564 struct mpi3mr_hba_port *hba_port; 565 struct mpi3mr_sas_phy *phy; 566 struct list_head sas_port_list; 567 struct sas_rphy *rphy; 568 }; 569 570 /** 571 * struct mpi3mr_enclosure_node - enclosure information 572 * @list: List of enclosures 573 * @pg0: Enclosure page 0; 574 */ 575 struct mpi3mr_enclosure_node { 576 struct list_head list; 577 struct mpi3_enclosure_page0 pg0; 578 }; 579 580 /** 581 * struct tgt_dev_sas_sata - SAS/SATA device specific 582 * information cached from firmware given data 583 * 584 * @sas_address: World wide unique SAS address 585 * @sas_address_parent: Sas address of parent expander or host 586 * @dev_info: Device information bits 587 * @phy_id: Phy identifier provided in device page 0 588 * @attached_phy_id: Attached phy identifier provided in device page 0 589 * @sas_transport_attached: Is this device exposed to transport 590 * @pend_sas_rphy_add: Flag to check device is in process of add 591 * @hba_port: HBA port entry 592 * @rphy: SAS transport layer rphy object 593 */ 594 struct tgt_dev_sas_sata { 595 u64 sas_address; 596 u64 sas_address_parent; 597 u16 dev_info; 598 u8 phy_id; 599 u8 attached_phy_id; 600 u8 sas_transport_attached; 601 u8 pend_sas_rphy_add; 602 struct mpi3mr_hba_port *hba_port; 603 struct sas_rphy *rphy; 604 }; 605 606 /** 607 * struct tgt_dev_pcie - PCIe device specific information cached 608 * from firmware given data 609 * 610 * @mdts: Maximum data transfer size 611 * @capb: Device capabilities 612 * @pgsz: Device page size 613 * @abort_to: Timeout for abort TM 614 * @reset_to: Timeout for Target/LUN reset TM 615 * @dev_info: Device information bits 616 */ 617 struct tgt_dev_pcie { 618 u32 mdts; 619 u16 capb; 620 u8 pgsz; 621 u8 abort_to; 622 u8 reset_to; 623 u16 dev_info; 624 }; 625 626 /** 627 * struct tgt_dev_vd - virtual device specific information 628 * cached from firmware given data 629 * 630 * @state: State of the VD 631 * @tg_qd_reduction: Queue Depth reduction in units of 10% 632 * @tg_id: VDs throttle group ID 633 * @high: High limit to turn on throttling in 512 byte blocks 634 * @low: Low limit to turn off throttling in 512 byte blocks 635 * @tg: Pointer to throttle group info 636 */ 637 struct tgt_dev_vd { 638 u8 state; 639 u8 tg_qd_reduction; 640 u16 tg_id; 641 u32 tg_high; 642 u32 tg_low; 643 struct mpi3mr_throttle_group_info *tg; 644 }; 645 646 647 /** 648 * union _form_spec_inf - union of device specific information 649 */ 650 union _form_spec_inf { 651 struct tgt_dev_sas_sata sas_sata_inf; 652 struct tgt_dev_pcie pcie_inf; 653 struct tgt_dev_vd vd_inf; 654 }; 655 656 enum mpi3mr_dev_state { 657 MPI3MR_DEV_CREATED = 1, 658 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 659 MPI3MR_DEV_DELETED = 3, 660 }; 661 662 /** 663 * struct mpi3mr_tgt_dev - target device data structure 664 * 665 * @list: List pointer 666 * @starget: Scsi_target pointer 667 * @dev_handle: FW device handle 668 * @parent_handle: FW parent device handle 669 * @slot: Slot number 670 * @encl_handle: FW enclosure handle 671 * @perst_id: FW assigned Persistent ID 672 * @devpg0_flag: Device Page0 flag 673 * @dev_type: SAS/SATA/PCIE device type 674 * @is_hidden: Should be exposed to upper layers or not 675 * @host_exposed: Already exposed to host or not 676 * @io_unit_port: IO Unit port ID 677 * @non_stl: Is this device not to be attached with SAS TL 678 * @io_throttle_enabled: I/O throttling needed or not 679 * @q_depth: Device specific Queue Depth 680 * @wwid: World wide ID 681 * @enclosure_logical_id: Enclosure logical identifier 682 * @dev_spec: Device type specific information 683 * @ref_count: Reference count 684 * @state: device state 685 */ 686 struct mpi3mr_tgt_dev { 687 struct list_head list; 688 struct scsi_target *starget; 689 u16 dev_handle; 690 u16 parent_handle; 691 u16 slot; 692 u16 encl_handle; 693 u16 perst_id; 694 u16 devpg0_flag; 695 u8 dev_type; 696 u8 is_hidden; 697 u8 host_exposed; 698 u8 io_unit_port; 699 u8 non_stl; 700 u8 io_throttle_enabled; 701 u16 q_depth; 702 u64 wwid; 703 u64 enclosure_logical_id; 704 union _form_spec_inf dev_spec; 705 struct kref ref_count; 706 enum mpi3mr_dev_state state; 707 }; 708 709 /** 710 * mpi3mr_tgtdev_get - k reference incrementor 711 * @s: Target device reference 712 * 713 * Increment target device reference count. 714 */ 715 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 716 { 717 kref_get(&s->ref_count); 718 } 719 720 /** 721 * mpi3mr_free_tgtdev - target device memory dealloctor 722 * @r: k reference pointer of the target device 723 * 724 * Free target device memory when no reference. 725 */ 726 static inline void mpi3mr_free_tgtdev(struct kref *r) 727 { 728 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 729 } 730 731 /** 732 * mpi3mr_tgtdev_put - k reference decrementor 733 * @s: Target device reference 734 * 735 * Decrement target device reference count. 736 */ 737 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 738 { 739 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 740 } 741 742 743 /** 744 * struct mpi3mr_stgt_priv_data - SCSI target private structure 745 * 746 * @starget: Scsi_target pointer 747 * @dev_handle: FW device handle 748 * @perst_id: FW assigned Persistent ID 749 * @num_luns: Number of Logical Units 750 * @block_io: I/O blocked to the device or not 751 * @dev_removed: Device removed in the Firmware 752 * @dev_removedelay: Device is waiting to be removed in FW 753 * @dev_type: Device type 754 * @io_throttle_enabled: I/O throttling needed or not 755 * @io_divert: Flag indicates io divert is on or off for the dev 756 * @throttle_group: Pointer to throttle group info 757 * @tgt_dev: Internal target device pointer 758 * @pend_count: Counter to track pending I/Os during error 759 * handling 760 */ 761 struct mpi3mr_stgt_priv_data { 762 struct scsi_target *starget; 763 u16 dev_handle; 764 u16 perst_id; 765 u32 num_luns; 766 atomic_t block_io; 767 u8 dev_removed; 768 u8 dev_removedelay; 769 u8 dev_type; 770 u8 io_throttle_enabled; 771 u8 io_divert; 772 struct mpi3mr_throttle_group_info *throttle_group; 773 struct mpi3mr_tgt_dev *tgt_dev; 774 u32 pend_count; 775 }; 776 777 /** 778 * struct mpi3mr_stgt_priv_data - SCSI device private structure 779 * 780 * @tgt_priv_data: Scsi_target private data pointer 781 * @lun_id: LUN ID of the device 782 * @ncq_prio_enable: NCQ priority enable for SATA device 783 * @pend_count: Counter to track pending I/Os during error 784 * handling 785 */ 786 struct mpi3mr_sdev_priv_data { 787 struct mpi3mr_stgt_priv_data *tgt_priv_data; 788 u32 lun_id; 789 u8 ncq_prio_enable; 790 u32 pend_count; 791 }; 792 793 /** 794 * struct mpi3mr_drv_cmd - Internal command tracker 795 * 796 * @mutex: Command mutex 797 * @done: Completeor for wakeup 798 * @reply: Firmware reply for internal commands 799 * @sensebuf: Sensebuf for SCSI IO commands 800 * @iou_rc: IO Unit control reason code 801 * @state: Command State 802 * @dev_handle: Firmware handle for device specific commands 803 * @ioc_status: IOC status from the firmware 804 * @ioc_loginfo:IOC log info from the firmware 805 * @is_waiting: Is the command issued in block mode 806 * @is_sense: Is Sense data present 807 * @retry_count: Retry count for retriable commands 808 * @host_tag: Host tag used by the command 809 * @callback: Callback for non blocking commands 810 */ 811 struct mpi3mr_drv_cmd { 812 struct mutex mutex; 813 struct completion done; 814 void *reply; 815 u8 *sensebuf; 816 u8 iou_rc; 817 u16 state; 818 u16 dev_handle; 819 u16 ioc_status; 820 u32 ioc_loginfo; 821 u8 is_waiting; 822 u8 is_sense; 823 u8 retry_count; 824 u16 host_tag; 825 826 void (*callback)(struct mpi3mr_ioc *mrioc, 827 struct mpi3mr_drv_cmd *drv_cmd); 828 }; 829 830 /** 831 * struct dma_memory_desc - memory descriptor structure to store 832 * virtual address, dma address and size for any generic dma 833 * memory allocations in the driver. 834 * 835 * @size: buffer size 836 * @addr: virtual address 837 * @dma_addr: dma address 838 */ 839 struct dma_memory_desc { 840 u32 size; 841 void *addr; 842 dma_addr_t dma_addr; 843 }; 844 845 846 /** 847 * struct chain_element - memory descriptor structure to store 848 * virtual and dma addresses for chain elements. 849 * 850 * @addr: virtual address 851 * @dma_addr: dma address 852 */ 853 struct chain_element { 854 void *addr; 855 dma_addr_t dma_addr; 856 }; 857 858 /** 859 * struct scmd_priv - SCSI command private data 860 * 861 * @host_tag: Host tag specific to operational queue 862 * @in_lld_scope: Command in LLD scope or not 863 * @meta_sg_valid: DIX command with meta data SGL or not 864 * @scmd: SCSI Command pointer 865 * @req_q_idx: Operational request queue index 866 * @chain_idx: Chain frame index 867 * @meta_chain_idx: Chain frame index of meta data SGL 868 * @mpi3mr_scsiio_req: MPI SCSI IO request 869 */ 870 struct scmd_priv { 871 u16 host_tag; 872 u8 in_lld_scope; 873 u8 meta_sg_valid; 874 struct scsi_cmnd *scmd; 875 u16 req_q_idx; 876 int chain_idx; 877 int meta_chain_idx; 878 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 879 }; 880 881 /** 882 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 883 * private data 884 * 885 * @list: List pointer 886 * @pdev: PCI device pointer 887 * @shost: Scsi_Host pointer 888 * @id: Controller ID 889 * @cpu_count: Number of online CPUs 890 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 891 * @name: Controller ASCII name 892 * @driver_name: Driver ASCII name 893 * @sysif_regs: System interface registers virtual address 894 * @sysif_regs_phys: System interface registers physical address 895 * @bars: PCI BARS 896 * @dma_mask: DMA mask 897 * @msix_count: Number of MSIX vectors used 898 * @intr_enabled: Is interrupts enabled 899 * @num_admin_req: Number of admin requests 900 * @admin_req_q_sz: Admin request queue size 901 * @admin_req_pi: Admin request queue producer index 902 * @admin_req_ci: Admin request queue consumer index 903 * @admin_req_base: Admin request queue base virtual address 904 * @admin_req_dma: Admin request queue base dma address 905 * @admin_req_lock: Admin queue access lock 906 * @num_admin_replies: Number of admin replies 907 * @admin_reply_q_sz: Admin reply queue size 908 * @admin_reply_ci: Admin reply queue consumer index 909 * @admin_reply_ephase:Admin reply queue expected phase 910 * @admin_reply_base: Admin reply queue base virtual address 911 * @admin_reply_dma: Admin reply queue base dma address 912 * @admin_reply_q_in_use: Queue is handled by poll/ISR 913 * @ready_timeout: Controller ready timeout 914 * @intr_info: Interrupt cookie pointer 915 * @intr_info_count: Number of interrupt cookies 916 * @is_intr_info_set: Flag to indicate intr info is setup 917 * @num_queues: Number of operational queues 918 * @num_op_req_q: Number of operational request queues 919 * @req_qinfo: Operational request queue info pointer 920 * @num_op_reply_q: Number of operational reply queues 921 * @op_reply_qinfo: Operational reply queue info pointer 922 * @init_cmds: Command tracker for initialization commands 923 * @cfg_cmds: Command tracker for configuration requests 924 * @facts: Cached IOC facts data 925 * @op_reply_desc_sz: Operational reply descriptor size 926 * @num_reply_bufs: Number of reply buffers allocated 927 * @reply_buf_pool: Reply buffer pool 928 * @reply_buf: Reply buffer base virtual address 929 * @reply_buf_dma: Reply buffer DMA address 930 * @reply_buf_dma_max_address: Reply DMA address max limit 931 * @reply_free_qsz: Reply free queue size 932 * @reply_free_q_pool: Reply free queue pool 933 * @reply_free_q: Reply free queue base virtual address 934 * @reply_free_q_dma: Reply free queue base DMA address 935 * @reply_free_queue_lock: Reply free queue lock 936 * @reply_free_queue_host_index: Reply free queue host index 937 * @num_sense_bufs: Number of sense buffers 938 * @sense_buf_pool: Sense buffer pool 939 * @sense_buf: Sense buffer base virtual address 940 * @sense_buf_dma: Sense buffer base DMA address 941 * @sense_buf_q_sz: Sense buffer queue size 942 * @sense_buf_q_pool: Sense buffer queue pool 943 * @sense_buf_q: Sense buffer queue virtual address 944 * @sense_buf_q_dma: Sense buffer queue DMA address 945 * @sbq_lock: Sense buffer queue lock 946 * @sbq_host_index: Sense buffer queuehost index 947 * @event_masks: Event mask bitmap 948 * @fwevt_worker_name: Firmware event worker thread name 949 * @fwevt_worker_thread: Firmware event worker thread 950 * @fwevt_lock: Firmware event lock 951 * @fwevt_list: Firmware event list 952 * @watchdog_work_q_name: Fault watchdog worker thread name 953 * @watchdog_work_q: Fault watchdog worker thread 954 * @watchdog_work: Fault watchdog work 955 * @watchdog_lock: Fault watchdog lock 956 * @is_driver_loading: Is driver still loading 957 * @scan_started: Async scan started 958 * @scan_failed: Asycn scan failed 959 * @stop_drv_processing: Stop all command processing 960 * @device_refresh_on: Don't process the events until devices are refreshed 961 * @max_host_ios: Maximum host I/O count 962 * @chain_buf_count: Chain buffer count 963 * @chain_buf_pool: Chain buffer pool 964 * @chain_sgl_list: Chain SGL list 965 * @chain_bitmap: Chain buffer allocator bitmap 966 * @chain_buf_lock: Chain buffer list lock 967 * @bsg_cmds: Command tracker for BSG command 968 * @host_tm_cmds: Command tracker for task management commands 969 * @dev_rmhs_cmds: Command tracker for device removal commands 970 * @evtack_cmds: Command tracker for event ack commands 971 * @devrem_bitmap: Device removal bitmap 972 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 973 * @removepend_bitmap: Remove pending bitmap 974 * @delayed_rmhs_list: Delayed device removal list 975 * @evtack_cmds_bitmap: Event Ack bitmap 976 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 977 * @ts_update_counter: Timestamp update counter 978 * @reset_in_progress: Reset in progress flag 979 * @unrecoverable: Controller unrecoverable flag 980 * @prev_reset_result: Result of previous reset 981 * @reset_mutex: Controller reset mutex 982 * @reset_waitq: Controller reset wait queue 983 * @prepare_for_reset: Prepare for reset event received 984 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 985 * @prp_list_virt: NVMe encapsulated PRP list virtual base 986 * @prp_list_dma: NVMe encapsulated PRP list DMA 987 * @prp_sz: NVME encapsulated PRP list size 988 * @diagsave_timeout: Diagnostic information save timeout 989 * @logging_level: Controller debug logging level 990 * @flush_io_count: I/O count to flush after reset 991 * @current_event: Firmware event currently in process 992 * @driver_info: Driver, Kernel, OS information to firmware 993 * @change_count: Topology change count 994 * @pel_enabled: Persistent Event Log(PEL) enabled or not 995 * @pel_abort_requested: PEL abort is requested or not 996 * @pel_class: PEL Class identifier 997 * @pel_locale: PEL Locale identifier 998 * @pel_cmds: Command tracker for PEL wait command 999 * @pel_abort_cmd: Command tracker for PEL abort command 1000 * @pel_newest_seqnum: Newest PEL sequenece number 1001 * @pel_seqnum_virt: PEL sequence number virtual address 1002 * @pel_seqnum_dma: PEL sequence number DMA address 1003 * @pel_seqnum_sz: PEL sequenece number size 1004 * @op_reply_q_offset: Operational reply queue offset with MSIx 1005 * @default_qcount: Total Default queues 1006 * @active_poll_qcount: Currently active poll queue count 1007 * @requested_poll_qcount: User requested poll queue count 1008 * @bsg_dev: BSG device structure 1009 * @bsg_queue: Request queue for BSG device 1010 * @stop_bsgs: Stop BSG request flag 1011 * @logdata_buf: Circular buffer to store log data entries 1012 * @logdata_buf_idx: Index of entry in buffer to store 1013 * @logdata_entry_sz: log data entry size 1014 * @pend_large_data_sz: Counter to track pending large data 1015 * @io_throttle_data_length: I/O size to track in 512b blocks 1016 * @io_throttle_high: I/O size to start throttle in 512b blocks 1017 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1018 * @num_io_throttle_group: Maximum number of throttle groups 1019 * @throttle_groups: Pointer to throttle group info structures 1020 * @cfg_page: Default memory for configuration pages 1021 * @cfg_page_dma: Configuration page DMA address 1022 * @cfg_page_sz: Default configuration page memory size 1023 * @sas_transport_enabled: SAS transport enabled or not 1024 * @scsi_device_channel: Channel ID for SCSI devices 1025 * @transport_cmds: Command tracker for SAS transport commands 1026 * @sas_hba: SAS node for the controller 1027 * @sas_expander_list: SAS node list of expanders 1028 * @sas_node_lock: Lock to protect SAS node list 1029 * @hba_port_table_list: List of HBA Ports 1030 * @enclosure_list: List of Enclosure objects 1031 */ 1032 struct mpi3mr_ioc { 1033 struct list_head list; 1034 struct pci_dev *pdev; 1035 struct Scsi_Host *shost; 1036 u8 id; 1037 int cpu_count; 1038 bool enable_segqueue; 1039 u32 irqpoll_sleep; 1040 1041 char name[MPI3MR_NAME_LENGTH]; 1042 char driver_name[MPI3MR_NAME_LENGTH]; 1043 1044 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1045 resource_size_t sysif_regs_phys; 1046 int bars; 1047 u64 dma_mask; 1048 1049 u16 msix_count; 1050 u8 intr_enabled; 1051 1052 u16 num_admin_req; 1053 u32 admin_req_q_sz; 1054 u16 admin_req_pi; 1055 u16 admin_req_ci; 1056 void *admin_req_base; 1057 dma_addr_t admin_req_dma; 1058 spinlock_t admin_req_lock; 1059 1060 u16 num_admin_replies; 1061 u32 admin_reply_q_sz; 1062 u16 admin_reply_ci; 1063 u8 admin_reply_ephase; 1064 void *admin_reply_base; 1065 dma_addr_t admin_reply_dma; 1066 atomic_t admin_reply_q_in_use; 1067 1068 u32 ready_timeout; 1069 1070 struct mpi3mr_intr_info *intr_info; 1071 u16 intr_info_count; 1072 bool is_intr_info_set; 1073 1074 u16 num_queues; 1075 u16 num_op_req_q; 1076 struct op_req_qinfo *req_qinfo; 1077 1078 u16 num_op_reply_q; 1079 struct op_reply_qinfo *op_reply_qinfo; 1080 1081 struct mpi3mr_drv_cmd init_cmds; 1082 struct mpi3mr_drv_cmd cfg_cmds; 1083 struct mpi3mr_ioc_facts facts; 1084 u16 op_reply_desc_sz; 1085 1086 u32 num_reply_bufs; 1087 struct dma_pool *reply_buf_pool; 1088 u8 *reply_buf; 1089 dma_addr_t reply_buf_dma; 1090 dma_addr_t reply_buf_dma_max_address; 1091 1092 u16 reply_free_qsz; 1093 u16 reply_sz; 1094 struct dma_pool *reply_free_q_pool; 1095 __le64 *reply_free_q; 1096 dma_addr_t reply_free_q_dma; 1097 spinlock_t reply_free_queue_lock; 1098 u32 reply_free_queue_host_index; 1099 1100 u32 num_sense_bufs; 1101 struct dma_pool *sense_buf_pool; 1102 u8 *sense_buf; 1103 dma_addr_t sense_buf_dma; 1104 1105 u16 sense_buf_q_sz; 1106 struct dma_pool *sense_buf_q_pool; 1107 __le64 *sense_buf_q; 1108 dma_addr_t sense_buf_q_dma; 1109 spinlock_t sbq_lock; 1110 u32 sbq_host_index; 1111 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1112 1113 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 1114 struct workqueue_struct *fwevt_worker_thread; 1115 spinlock_t fwevt_lock; 1116 struct list_head fwevt_list; 1117 1118 char watchdog_work_q_name[20]; 1119 struct workqueue_struct *watchdog_work_q; 1120 struct delayed_work watchdog_work; 1121 spinlock_t watchdog_lock; 1122 1123 u8 is_driver_loading; 1124 u8 scan_started; 1125 u16 scan_failed; 1126 u8 stop_drv_processing; 1127 u8 device_refresh_on; 1128 1129 u16 max_host_ios; 1130 spinlock_t tgtdev_lock; 1131 struct list_head tgtdev_list; 1132 1133 u32 chain_buf_count; 1134 struct dma_pool *chain_buf_pool; 1135 struct chain_element *chain_sgl_list; 1136 void *chain_bitmap; 1137 spinlock_t chain_buf_lock; 1138 1139 struct mpi3mr_drv_cmd bsg_cmds; 1140 struct mpi3mr_drv_cmd host_tm_cmds; 1141 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1142 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1143 void *devrem_bitmap; 1144 u16 dev_handle_bitmap_bits; 1145 void *removepend_bitmap; 1146 struct list_head delayed_rmhs_list; 1147 void *evtack_cmds_bitmap; 1148 struct list_head delayed_evtack_cmds_list; 1149 1150 u32 ts_update_counter; 1151 u8 reset_in_progress; 1152 u8 unrecoverable; 1153 int prev_reset_result; 1154 struct mutex reset_mutex; 1155 wait_queue_head_t reset_waitq; 1156 1157 u8 prepare_for_reset; 1158 u16 prepare_for_reset_timeout_counter; 1159 1160 void *prp_list_virt; 1161 dma_addr_t prp_list_dma; 1162 u32 prp_sz; 1163 1164 u16 diagsave_timeout; 1165 int logging_level; 1166 u16 flush_io_count; 1167 1168 struct mpi3mr_fwevt *current_event; 1169 struct mpi3_driver_info_layout driver_info; 1170 u16 change_count; 1171 1172 u8 pel_enabled; 1173 u8 pel_abort_requested; 1174 u8 pel_class; 1175 u16 pel_locale; 1176 struct mpi3mr_drv_cmd pel_cmds; 1177 struct mpi3mr_drv_cmd pel_abort_cmd; 1178 1179 u32 pel_newest_seqnum; 1180 void *pel_seqnum_virt; 1181 dma_addr_t pel_seqnum_dma; 1182 u32 pel_seqnum_sz; 1183 1184 u16 op_reply_q_offset; 1185 u16 default_qcount; 1186 u16 active_poll_qcount; 1187 u16 requested_poll_qcount; 1188 1189 struct device bsg_dev; 1190 struct request_queue *bsg_queue; 1191 u8 stop_bsgs; 1192 u8 *logdata_buf; 1193 u16 logdata_buf_idx; 1194 u16 logdata_entry_sz; 1195 1196 atomic_t pend_large_data_sz; 1197 u32 io_throttle_data_length; 1198 u32 io_throttle_high; 1199 u32 io_throttle_low; 1200 u16 num_io_throttle_group; 1201 struct mpi3mr_throttle_group_info *throttle_groups; 1202 1203 void *cfg_page; 1204 dma_addr_t cfg_page_dma; 1205 u16 cfg_page_sz; 1206 1207 u8 sas_transport_enabled; 1208 u8 scsi_device_channel; 1209 struct mpi3mr_drv_cmd transport_cmds; 1210 struct mpi3mr_sas_node sas_hba; 1211 struct list_head sas_expander_list; 1212 spinlock_t sas_node_lock; 1213 struct list_head hba_port_table_list; 1214 struct list_head enclosure_list; 1215 }; 1216 1217 /** 1218 * struct mpi3mr_fwevt - Firmware event structure. 1219 * 1220 * @list: list head 1221 * @work: Work structure 1222 * @mrioc: Adapter instance reference 1223 * @event_id: MPI3 firmware event ID 1224 * @send_ack: Event acknowledgment required or not 1225 * @process_evt: Bottomhalf processing required or not 1226 * @evt_ctx: Event context to send in Ack 1227 * @event_data_size: size of the event data in bytes 1228 * @pending_at_sml: waiting for device add/remove API to complete 1229 * @discard: discard this event 1230 * @ref_count: kref count 1231 * @event_data: Actual MPI3 event data 1232 */ 1233 struct mpi3mr_fwevt { 1234 struct list_head list; 1235 struct work_struct work; 1236 struct mpi3mr_ioc *mrioc; 1237 u16 event_id; 1238 bool send_ack; 1239 bool process_evt; 1240 u32 evt_ctx; 1241 u16 event_data_size; 1242 bool pending_at_sml; 1243 bool discard; 1244 struct kref ref_count; 1245 char event_data[] __aligned(4); 1246 }; 1247 1248 1249 /** 1250 * struct delayed_dev_rmhs_node - Delayed device removal node 1251 * 1252 * @list: list head 1253 * @handle: Device handle 1254 * @iou_rc: IO Unit Control Reason Code 1255 */ 1256 struct delayed_dev_rmhs_node { 1257 struct list_head list; 1258 u16 handle; 1259 u8 iou_rc; 1260 }; 1261 1262 /** 1263 * struct delayed_evt_ack_node - Delayed event ack node 1264 * @list: list head 1265 * @event: MPI3 event ID 1266 * @event_ctx: event context 1267 */ 1268 struct delayed_evt_ack_node { 1269 struct list_head list; 1270 u8 event; 1271 u32 event_ctx; 1272 }; 1273 1274 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1275 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1276 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1277 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1278 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1279 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1280 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1281 u16 admin_req_sz, u8 ignore_reset); 1282 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1283 struct op_req_qinfo *opreqq, u8 *req); 1284 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1285 dma_addr_t dma_addr); 1286 void mpi3mr_build_zero_len_sge(void *paddr); 1287 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1288 dma_addr_t phys_addr); 1289 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1290 dma_addr_t phys_addr); 1291 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1292 u64 sense_buf_dma); 1293 1294 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1295 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1296 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1297 struct mpi3_event_notification_reply *event_reply); 1298 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1299 struct mpi3_default_reply_descriptor *reply_desc, 1300 u64 *reply_dma, u16 qidx); 1301 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1302 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1303 1304 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1305 u32 reset_reason, u8 snapdump); 1306 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1307 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1308 1309 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1310 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1311 u32 event_ctx); 1312 1313 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1314 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1315 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1316 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1317 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1318 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1319 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1320 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1321 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1322 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1323 struct op_reply_qinfo *op_reply_q); 1324 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1325 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1326 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1327 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1328 u16 handle, uint lun, u16 htag, ulong timeout, 1329 struct mpi3mr_drv_cmd *drv_cmd, 1330 u8 *resp_code, struct scsi_cmnd *scmd); 1331 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1332 struct mpi3mr_ioc *mrioc, u16 handle); 1333 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1334 struct mpi3mr_drv_cmd *drv_cmd); 1335 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1336 struct mpi3mr_drv_cmd *drv_cmd); 1337 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1338 u16 event_data_size); 1339 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1340 struct mpi3mr_ioc *mrioc, u16 handle); 1341 extern const struct attribute_group *mpi3mr_host_groups[]; 1342 extern const struct attribute_group *mpi3mr_dev_groups[]; 1343 1344 extern struct sas_function_template mpi3mr_transport_functions; 1345 extern struct scsi_transport_template *mpi3mr_transport_template; 1346 1347 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1348 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1349 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1350 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1351 u32 form_spec); 1352 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1353 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1354 u32 form_spec); 1355 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1356 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1357 u32 form_spec); 1358 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1359 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1360 u32 form_spec); 1361 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1362 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1363 u32 form_spec); 1364 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1365 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1366 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1367 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1368 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1369 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1370 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1371 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1372 1373 u8 mpi3mr_is_expander_device(u16 device_info); 1374 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1375 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1376 struct mpi3mr_hba_port *hba_port); 1377 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1378 *mrioc, u16 handle); 1379 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1380 u8 port_id); 1381 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1382 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1383 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1384 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1385 struct mpi3mr_hba_port *hba_port); 1386 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1387 struct mpi3mr_tgt_dev *tgtdev); 1388 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1389 struct mpi3mr_tgt_dev *tgtdev); 1390 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1391 struct mpi3mr_tgt_dev *tgtdev); 1392 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1393 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1394 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1395 bool device_add); 1396 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1397 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1398 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1399 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1400 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1401 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1402 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1403 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1404 struct mpi3mr_sas_node *sas_expander); 1405 #endif /*MPI3MR_H_INCLUDED*/ 1406