1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_cnfg.h" 44 #include "mpi/mpi30_image.h" 45 #include "mpi/mpi30_init.h" 46 #include "mpi/mpi30_ioc.h" 47 #include "mpi/mpi30_sas.h" 48 #include "mpi/mpi30_pci.h" 49 #include "mpi3mr_debug.h" 50 51 /* Global list and lock for storing multiple adapters managed by the driver */ 52 extern spinlock_t mrioc_list_lock; 53 extern struct list_head mrioc_list; 54 extern int prot_mask; 55 56 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 57 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 58 59 #define MPI3MR_DRIVER_NAME "mpi3mr" 60 #define MPI3MR_DRIVER_LICENSE "GPL" 61 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 62 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 63 64 #define MPI3MR_NAME_LENGTH 32 65 #define IOCNAME "%s: " 66 67 /* Definitions for internal SGL and Chain SGL buffers */ 68 #define MPI3MR_PAGE_SIZE_4K 4096 69 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 70 71 /* Definitions for MAX values for shost */ 72 #define MPI3MR_MAX_CMDS_LUN 7 73 #define MPI3MR_MAX_CDB_LENGTH 32 74 75 /* Admin queue management definitions */ 76 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 77 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 78 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 79 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 80 81 /* Operational queue management definitions */ 82 #define MPI3MR_OP_REQ_Q_QD 512 83 #define MPI3MR_OP_REP_Q_QD 4096 84 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 85 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 86 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 87 88 /* Reserved Host Tag definitions */ 89 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 90 #define MPI3MR_HOSTTAG_INITCMDS 1 91 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 92 #define MPI3MR_HOSTTAG_BLK_TMS 5 93 94 #define MPI3MR_NUM_DEVRMCMD 16 95 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 96 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 97 MPI3MR_NUM_DEVRMCMD - 1) 98 99 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 100 101 /* Reduced resource count definition for crash kernel */ 102 #define MPI3MR_HOST_IOS_KDUMP 128 103 104 /* command/controller interaction timeout definitions in seconds */ 105 #define MPI3MR_INTADMCMD_TIMEOUT 60 106 #define MPI3MR_PORTENABLE_TIMEOUT 300 107 #define MPI3MR_ABORTTM_TIMEOUT 60 108 #define MPI3MR_RESETTM_TIMEOUT 60 109 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 110 #define MPI3MR_TSUPDATE_INTERVAL 900 111 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 112 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 113 114 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 115 116 /* Internal admin command state definitions*/ 117 #define MPI3MR_CMD_NOTUSED 0x8000 118 #define MPI3MR_CMD_COMPLETE 0x0001 119 #define MPI3MR_CMD_PENDING 0x0002 120 #define MPI3MR_CMD_REPLY_VALID 0x0004 121 #define MPI3MR_CMD_RESET 0x0008 122 123 /* Definitions for Event replies and sense buffer allocated per controller */ 124 #define MPI3MR_NUM_EVT_REPLIES 64 125 #define MPI3MR_SENSE_BUF_SZ 256 126 #define MPI3MR_SENSEBUF_FACTOR 3 127 #define MPI3MR_CHAINBUF_FACTOR 3 128 #define MPI3MR_CHAINBUFDIX_FACTOR 2 129 130 /* Invalid target device handle */ 131 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 132 133 /* Controller Reset related definitions */ 134 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 135 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 136 137 /* ResponseCode definitions */ 138 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 139 #define MPI3MR_RSP_TM_COMPLETE 0x00 140 #define MPI3MR_RSP_INVALID_FRAME 0x02 141 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 142 #define MPI3MR_RSP_TM_FAILED 0x05 143 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 144 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 145 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 146 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 147 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 148 149 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 150 #define MPI3MR_DEFAULT_PGSZEXP (12) 151 /* Command retry count definitions */ 152 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 153 154 /* Default target device queue depth */ 155 #define MPI3MR_DEFAULT_SDEV_QD 32 156 157 /* Definitions for Threaded IRQ poll*/ 158 #define MPI3MR_IRQ_POLL_SLEEP 2 159 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 160 161 /* Definitions for the controller security status*/ 162 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 163 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 164 165 #define MPI3MR_INVALID_DEVICE 0x00 166 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 167 #define MPI3MR_HARD_SECURE_DEVICE 0x08 168 #define MPI3MR_TAMPERED_DEVICE 0x0C 169 170 /* SGE Flag definition */ 171 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 172 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 173 MPI3_SGE_FLAGS_END_OF_LIST) 174 175 /* MSI Index from Reply Queue Index */ 176 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 177 178 /* IOC State definitions */ 179 enum mpi3mr_iocstate { 180 MRIOC_STATE_READY = 1, 181 MRIOC_STATE_RESET, 182 MRIOC_STATE_FAULT, 183 MRIOC_STATE_BECOMING_READY, 184 MRIOC_STATE_RESET_REQUESTED, 185 MRIOC_STATE_UNRECOVERABLE, 186 }; 187 188 /* Reset reason code definitions*/ 189 enum mpi3mr_reset_reason { 190 MPI3MR_RESET_FROM_BRINGUP = 1, 191 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 192 MPI3MR_RESET_FROM_IOCTL = 3, 193 MPI3MR_RESET_FROM_EH_HOS = 4, 194 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 195 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 196 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 197 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 198 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 199 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 200 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 201 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 202 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 203 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 204 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 205 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 206 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 207 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 208 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 209 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 210 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 211 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 212 MPI3MR_RESET_FROM_SYSFS = 23, 213 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24 214 }; 215 216 /** 217 * struct mpi3mr_compimg_ver - replica of component image 218 * version defined in mpi30_image.h in host endianness 219 * 220 */ 221 struct mpi3mr_compimg_ver { 222 u16 build_num; 223 u16 cust_id; 224 u8 ph_minor; 225 u8 ph_major; 226 u8 gen_minor; 227 u8 gen_major; 228 }; 229 230 /** 231 * struct mpi3mr_ioc_facs - replica of component image version 232 * defined in mpi30_ioc.h in host endianness 233 * 234 */ 235 struct mpi3mr_ioc_facts { 236 u32 ioc_capabilities; 237 struct mpi3mr_compimg_ver fw_ver; 238 u32 mpi_version; 239 u16 max_reqs; 240 u16 product_id; 241 u16 op_req_sz; 242 u16 reply_sz; 243 u16 exceptions; 244 u16 max_perids; 245 u16 max_pds; 246 u16 max_sasexpanders; 247 u16 max_sasinitiators; 248 u16 max_enclosures; 249 u16 max_pcie_switches; 250 u16 max_nvme; 251 u16 max_vds; 252 u16 max_hpds; 253 u16 max_advhpds; 254 u16 max_raid_pds; 255 u16 min_devhandle; 256 u16 max_devhandle; 257 u16 max_op_req_q; 258 u16 max_op_reply_q; 259 u16 shutdown_timeout; 260 u8 ioc_num; 261 u8 who_init; 262 u16 max_msix_vectors; 263 u8 personality; 264 u8 dma_mask; 265 u8 protocol_flags; 266 u8 sge_mod_mask; 267 u8 sge_mod_value; 268 u8 sge_mod_shift; 269 }; 270 271 /** 272 * struct segments - memory descriptor structure to store 273 * virtual and dma addresses for operational queue segments. 274 * 275 * @segment: virtual address 276 * @segment_dma: dma address 277 */ 278 struct segments { 279 void *segment; 280 dma_addr_t segment_dma; 281 }; 282 283 /** 284 * struct op_req_qinfo - Operational Request Queue Information 285 * 286 * @ci: consumer index 287 * @pi: producer index 288 * @num_request: Maximum number of entries in the queue 289 * @qid: Queue Id starting from 1 290 * @reply_qid: Associated reply queue Id 291 * @num_segments: Number of discontiguous memory segments 292 * @segment_qd: Depth of each segments 293 * @q_lock: Concurrent queue access lock 294 * @q_segments: Segment descriptor pointer 295 * @q_segment_list: Segment list base virtual address 296 * @q_segment_list_dma: Segment list base DMA address 297 */ 298 struct op_req_qinfo { 299 u16 ci; 300 u16 pi; 301 u16 num_requests; 302 u16 qid; 303 u16 reply_qid; 304 u16 num_segments; 305 u16 segment_qd; 306 spinlock_t q_lock; 307 struct segments *q_segments; 308 void *q_segment_list; 309 dma_addr_t q_segment_list_dma; 310 }; 311 312 /** 313 * struct op_reply_qinfo - Operational Reply Queue Information 314 * 315 * @ci: consumer index 316 * @qid: Queue Id starting from 1 317 * @num_replies: Maximum number of entries in the queue 318 * @num_segments: Number of discontiguous memory segments 319 * @segment_qd: Depth of each segments 320 * @q_segments: Segment descriptor pointer 321 * @q_segment_list: Segment list base virtual address 322 * @q_segment_list_dma: Segment list base DMA address 323 * @ephase: Expected phased identifier for the reply queue 324 * @pend_ios: Number of IOs pending in HW for this queue 325 * @enable_irq_poll: Flag to indicate polling is enabled 326 * @in_use: Queue is handled by poll/ISR 327 */ 328 struct op_reply_qinfo { 329 u16 ci; 330 u16 qid; 331 u16 num_replies; 332 u16 num_segments; 333 u16 segment_qd; 334 struct segments *q_segments; 335 void *q_segment_list; 336 dma_addr_t q_segment_list_dma; 337 u8 ephase; 338 atomic_t pend_ios; 339 bool enable_irq_poll; 340 atomic_t in_use; 341 }; 342 343 /** 344 * struct mpi3mr_intr_info - Interrupt cookie information 345 * 346 * @mrioc: Adapter instance reference 347 * @msix_index: MSIx index 348 * @op_reply_q: Associated operational reply queue 349 * @name: Dev name for the irq claiming device 350 */ 351 struct mpi3mr_intr_info { 352 struct mpi3mr_ioc *mrioc; 353 u16 msix_index; 354 struct op_reply_qinfo *op_reply_q; 355 char name[MPI3MR_NAME_LENGTH]; 356 }; 357 358 /** 359 * struct tgt_dev_sas_sata - SAS/SATA device specific 360 * information cached from firmware given data 361 * 362 * @sas_address: World wide unique SAS address 363 * @dev_info: Device information bits 364 */ 365 struct tgt_dev_sas_sata { 366 u64 sas_address; 367 u16 dev_info; 368 }; 369 370 /** 371 * struct tgt_dev_pcie - PCIe device specific information cached 372 * from firmware given data 373 * 374 * @mdts: Maximum data transfer size 375 * @capb: Device capabilities 376 * @pgsz: Device page size 377 * @abort_to: Timeout for abort TM 378 * @reset_to: Timeout for Target/LUN reset TM 379 * @dev_info: Device information bits 380 */ 381 struct tgt_dev_pcie { 382 u32 mdts; 383 u16 capb; 384 u8 pgsz; 385 u8 abort_to; 386 u8 reset_to; 387 u16 dev_info; 388 }; 389 390 /** 391 * struct tgt_dev_volume - virtual device specific information 392 * cached from firmware given data 393 * 394 * @state: State of the VD 395 */ 396 struct tgt_dev_volume { 397 u8 state; 398 }; 399 400 /** 401 * union _form_spec_inf - union of device specific information 402 */ 403 union _form_spec_inf { 404 struct tgt_dev_sas_sata sas_sata_inf; 405 struct tgt_dev_pcie pcie_inf; 406 struct tgt_dev_volume vol_inf; 407 }; 408 409 410 411 /** 412 * struct mpi3mr_tgt_dev - target device data structure 413 * 414 * @list: List pointer 415 * @starget: Scsi_target pointer 416 * @dev_handle: FW device handle 417 * @parent_handle: FW parent device handle 418 * @slot: Slot number 419 * @encl_handle: FW enclosure handle 420 * @perst_id: FW assigned Persistent ID 421 * @dev_type: SAS/SATA/PCIE device type 422 * @is_hidden: Should be exposed to upper layers or not 423 * @host_exposed: Already exposed to host or not 424 * @q_depth: Device specific Queue Depth 425 * @wwid: World wide ID 426 * @dev_spec: Device type specific information 427 * @ref_count: Reference count 428 */ 429 struct mpi3mr_tgt_dev { 430 struct list_head list; 431 struct scsi_target *starget; 432 u16 dev_handle; 433 u16 parent_handle; 434 u16 slot; 435 u16 encl_handle; 436 u16 perst_id; 437 u8 dev_type; 438 u8 is_hidden; 439 u8 host_exposed; 440 u16 q_depth; 441 u64 wwid; 442 union _form_spec_inf dev_spec; 443 struct kref ref_count; 444 }; 445 446 /** 447 * mpi3mr_tgtdev_get - k reference incrementor 448 * @s: Target device reference 449 * 450 * Increment target device reference count. 451 */ 452 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 453 { 454 kref_get(&s->ref_count); 455 } 456 457 /** 458 * mpi3mr_free_tgtdev - target device memory dealloctor 459 * @r: k reference pointer of the target device 460 * 461 * Free target device memory when no reference. 462 */ 463 static inline void mpi3mr_free_tgtdev(struct kref *r) 464 { 465 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 466 } 467 468 /** 469 * mpi3mr_tgtdev_put - k reference decrementor 470 * @s: Target device reference 471 * 472 * Decrement target device reference count. 473 */ 474 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 475 { 476 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 477 } 478 479 480 /** 481 * struct mpi3mr_stgt_priv_data - SCSI target private structure 482 * 483 * @starget: Scsi_target pointer 484 * @dev_handle: FW device handle 485 * @perst_id: FW assigned Persistent ID 486 * @num_luns: Number of Logical Units 487 * @block_io: I/O blocked to the device or not 488 * @dev_removed: Device removed in the Firmware 489 * @dev_removedelay: Device is waiting to be removed in FW 490 * @dev_type: Device type 491 * @tgt_dev: Internal target device pointer 492 */ 493 struct mpi3mr_stgt_priv_data { 494 struct scsi_target *starget; 495 u16 dev_handle; 496 u16 perst_id; 497 u32 num_luns; 498 atomic_t block_io; 499 u8 dev_removed; 500 u8 dev_removedelay; 501 u8 dev_type; 502 struct mpi3mr_tgt_dev *tgt_dev; 503 }; 504 505 /** 506 * struct mpi3mr_stgt_priv_data - SCSI device private structure 507 * 508 * @tgt_priv_data: Scsi_target private data pointer 509 * @lun_id: LUN ID of the device 510 * @ncq_prio_enable: NCQ priority enable for SATA device 511 */ 512 struct mpi3mr_sdev_priv_data { 513 struct mpi3mr_stgt_priv_data *tgt_priv_data; 514 u32 lun_id; 515 u8 ncq_prio_enable; 516 }; 517 518 /** 519 * struct mpi3mr_drv_cmd - Internal command tracker 520 * 521 * @mutex: Command mutex 522 * @done: Completeor for wakeup 523 * @reply: Firmware reply for internal commands 524 * @sensebuf: Sensebuf for SCSI IO commands 525 * @iou_rc: IO Unit control reason code 526 * @state: Command State 527 * @dev_handle: Firmware handle for device specific commands 528 * @ioc_status: IOC status from the firmware 529 * @ioc_loginfo:IOC log info from the firmware 530 * @is_waiting: Is the command issued in block mode 531 * @retry_count: Retry count for retriable commands 532 * @host_tag: Host tag used by the command 533 * @callback: Callback for non blocking commands 534 */ 535 struct mpi3mr_drv_cmd { 536 struct mutex mutex; 537 struct completion done; 538 void *reply; 539 u8 *sensebuf; 540 u8 iou_rc; 541 u16 state; 542 u16 dev_handle; 543 u16 ioc_status; 544 u32 ioc_loginfo; 545 u8 is_waiting; 546 u8 retry_count; 547 u16 host_tag; 548 549 void (*callback)(struct mpi3mr_ioc *mrioc, 550 struct mpi3mr_drv_cmd *drv_cmd); 551 }; 552 553 554 /** 555 * struct chain_element - memory descriptor structure to store 556 * virtual and dma addresses for chain elements. 557 * 558 * @addr: virtual address 559 * @dma_addr: dma address 560 */ 561 struct chain_element { 562 void *addr; 563 dma_addr_t dma_addr; 564 }; 565 566 /** 567 * struct scmd_priv - SCSI command private data 568 * 569 * @host_tag: Host tag specific to operational queue 570 * @in_lld_scope: Command in LLD scope or not 571 * @meta_sg_valid: DIX command with meta data SGL or not 572 * @scmd: SCSI Command pointer 573 * @req_q_idx: Operational request queue index 574 * @chain_idx: Chain frame index 575 * @meta_chain_idx: Chain frame index of meta data SGL 576 * @mpi3mr_scsiio_req: MPI SCSI IO request 577 */ 578 struct scmd_priv { 579 u16 host_tag; 580 u8 in_lld_scope; 581 u8 meta_sg_valid; 582 struct scsi_cmnd *scmd; 583 u16 req_q_idx; 584 int chain_idx; 585 int meta_chain_idx; 586 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 587 }; 588 589 /** 590 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 591 * private data 592 * 593 * @list: List pointer 594 * @pdev: PCI device pointer 595 * @shost: Scsi_Host pointer 596 * @id: Controller ID 597 * @cpu_count: Number of online CPUs 598 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 599 * @name: Controller ASCII name 600 * @driver_name: Driver ASCII name 601 * @sysif_regs: System interface registers virtual address 602 * @sysif_regs_phys: System interface registers physical address 603 * @bars: PCI BARS 604 * @dma_mask: DMA mask 605 * @msix_count: Number of MSIX vectors used 606 * @intr_enabled: Is interrupts enabled 607 * @num_admin_req: Number of admin requests 608 * @admin_req_q_sz: Admin request queue size 609 * @admin_req_pi: Admin request queue producer index 610 * @admin_req_ci: Admin request queue consumer index 611 * @admin_req_base: Admin request queue base virtual address 612 * @admin_req_dma: Admin request queue base dma address 613 * @admin_req_lock: Admin queue access lock 614 * @num_admin_replies: Number of admin replies 615 * @admin_reply_q_sz: Admin reply queue size 616 * @admin_reply_ci: Admin reply queue consumer index 617 * @admin_reply_ephase:Admin reply queue expected phase 618 * @admin_reply_base: Admin reply queue base virtual address 619 * @admin_reply_dma: Admin reply queue base dma address 620 * @ready_timeout: Controller ready timeout 621 * @intr_info: Interrupt cookie pointer 622 * @intr_info_count: Number of interrupt cookies 623 * @is_intr_info_set: Flag to indicate intr info is setup 624 * @num_queues: Number of operational queues 625 * @num_op_req_q: Number of operational request queues 626 * @req_qinfo: Operational request queue info pointer 627 * @num_op_reply_q: Number of operational reply queues 628 * @op_reply_qinfo: Operational reply queue info pointer 629 * @init_cmds: Command tracker for initialization commands 630 * @facts: Cached IOC facts data 631 * @op_reply_desc_sz: Operational reply descriptor size 632 * @num_reply_bufs: Number of reply buffers allocated 633 * @reply_buf_pool: Reply buffer pool 634 * @reply_buf: Reply buffer base virtual address 635 * @reply_buf_dma: Reply buffer DMA address 636 * @reply_buf_dma_max_address: Reply DMA address max limit 637 * @reply_free_qsz: Reply free queue size 638 * @reply_free_q_pool: Reply free queue pool 639 * @reply_free_q: Reply free queue base virtual address 640 * @reply_free_q_dma: Reply free queue base DMA address 641 * @reply_free_queue_lock: Reply free queue lock 642 * @reply_free_queue_host_index: Reply free queue host index 643 * @num_sense_bufs: Number of sense buffers 644 * @sense_buf_pool: Sense buffer pool 645 * @sense_buf: Sense buffer base virtual address 646 * @sense_buf_dma: Sense buffer base DMA address 647 * @sense_buf_q_sz: Sense buffer queue size 648 * @sense_buf_q_pool: Sense buffer queue pool 649 * @sense_buf_q: Sense buffer queue virtual address 650 * @sense_buf_q_dma: Sense buffer queue DMA address 651 * @sbq_lock: Sense buffer queue lock 652 * @sbq_host_index: Sense buffer queuehost index 653 * @event_masks: Event mask bitmap 654 * @fwevt_worker_name: Firmware event worker thread name 655 * @fwevt_worker_thread: Firmware event worker thread 656 * @fwevt_lock: Firmware event lock 657 * @fwevt_list: Firmware event list 658 * @watchdog_work_q_name: Fault watchdog worker thread name 659 * @watchdog_work_q: Fault watchdog worker thread 660 * @watchdog_work: Fault watchdog work 661 * @watchdog_lock: Fault watchdog lock 662 * @is_driver_loading: Is driver still loading 663 * @scan_started: Async scan started 664 * @scan_failed: Asycn scan failed 665 * @stop_drv_processing: Stop all command processing 666 * @max_host_ios: Maximum host I/O count 667 * @chain_buf_count: Chain buffer count 668 * @chain_buf_pool: Chain buffer pool 669 * @chain_sgl_list: Chain SGL list 670 * @chain_bitmap_sz: Chain buffer allocator bitmap size 671 * @chain_bitmap: Chain buffer allocator bitmap 672 * @chain_buf_lock: Chain buffer list lock 673 * @host_tm_cmds: Command tracker for task management commands 674 * @dev_rmhs_cmds: Command tracker for device removal commands 675 * @devrem_bitmap_sz: Device removal bitmap size 676 * @devrem_bitmap: Device removal bitmap 677 * @dev_handle_bitmap_sz: Device handle bitmap size 678 * @removepend_bitmap: Remove pending bitmap 679 * @delayed_rmhs_list: Delayed device removal list 680 * @ts_update_counter: Timestamp update counter 681 * @fault_dbg: Fault debug flag 682 * @reset_in_progress: Reset in progress flag 683 * @unrecoverable: Controller unrecoverable flag 684 * @reset_mutex: Controller reset mutex 685 * @reset_waitq: Controller reset wait queue 686 * @diagsave_timeout: Diagnostic information save timeout 687 * @logging_level: Controller debug logging level 688 * @flush_io_count: I/O count to flush after reset 689 * @current_event: Firmware event currently in process 690 * @driver_info: Driver, Kernel, OS information to firmware 691 * @change_count: Topology change count 692 * @op_reply_q_offset: Operational reply queue offset with MSIx 693 */ 694 struct mpi3mr_ioc { 695 struct list_head list; 696 struct pci_dev *pdev; 697 struct Scsi_Host *shost; 698 u8 id; 699 int cpu_count; 700 bool enable_segqueue; 701 u32 irqpoll_sleep; 702 703 char name[MPI3MR_NAME_LENGTH]; 704 char driver_name[MPI3MR_NAME_LENGTH]; 705 706 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 707 resource_size_t sysif_regs_phys; 708 int bars; 709 u64 dma_mask; 710 711 u16 msix_count; 712 u8 intr_enabled; 713 714 u16 num_admin_req; 715 u32 admin_req_q_sz; 716 u16 admin_req_pi; 717 u16 admin_req_ci; 718 void *admin_req_base; 719 dma_addr_t admin_req_dma; 720 spinlock_t admin_req_lock; 721 722 u16 num_admin_replies; 723 u32 admin_reply_q_sz; 724 u16 admin_reply_ci; 725 u8 admin_reply_ephase; 726 void *admin_reply_base; 727 dma_addr_t admin_reply_dma; 728 729 u32 ready_timeout; 730 731 struct mpi3mr_intr_info *intr_info; 732 u16 intr_info_count; 733 bool is_intr_info_set; 734 735 u16 num_queues; 736 u16 num_op_req_q; 737 struct op_req_qinfo *req_qinfo; 738 739 u16 num_op_reply_q; 740 struct op_reply_qinfo *op_reply_qinfo; 741 742 struct mpi3mr_drv_cmd init_cmds; 743 struct mpi3mr_ioc_facts facts; 744 u16 op_reply_desc_sz; 745 746 u32 num_reply_bufs; 747 struct dma_pool *reply_buf_pool; 748 u8 *reply_buf; 749 dma_addr_t reply_buf_dma; 750 dma_addr_t reply_buf_dma_max_address; 751 752 u16 reply_free_qsz; 753 struct dma_pool *reply_free_q_pool; 754 __le64 *reply_free_q; 755 dma_addr_t reply_free_q_dma; 756 spinlock_t reply_free_queue_lock; 757 u32 reply_free_queue_host_index; 758 759 u32 num_sense_bufs; 760 struct dma_pool *sense_buf_pool; 761 u8 *sense_buf; 762 dma_addr_t sense_buf_dma; 763 764 u16 sense_buf_q_sz; 765 struct dma_pool *sense_buf_q_pool; 766 __le64 *sense_buf_q; 767 dma_addr_t sense_buf_q_dma; 768 spinlock_t sbq_lock; 769 u32 sbq_host_index; 770 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 771 772 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 773 struct workqueue_struct *fwevt_worker_thread; 774 spinlock_t fwevt_lock; 775 struct list_head fwevt_list; 776 777 char watchdog_work_q_name[20]; 778 struct workqueue_struct *watchdog_work_q; 779 struct delayed_work watchdog_work; 780 spinlock_t watchdog_lock; 781 782 u8 is_driver_loading; 783 u8 scan_started; 784 u16 scan_failed; 785 u8 stop_drv_processing; 786 787 u16 max_host_ios; 788 spinlock_t tgtdev_lock; 789 struct list_head tgtdev_list; 790 791 u32 chain_buf_count; 792 struct dma_pool *chain_buf_pool; 793 struct chain_element *chain_sgl_list; 794 u16 chain_bitmap_sz; 795 void *chain_bitmap; 796 spinlock_t chain_buf_lock; 797 798 struct mpi3mr_drv_cmd host_tm_cmds; 799 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 800 u16 devrem_bitmap_sz; 801 void *devrem_bitmap; 802 u16 dev_handle_bitmap_sz; 803 void *removepend_bitmap; 804 struct list_head delayed_rmhs_list; 805 806 u32 ts_update_counter; 807 u8 fault_dbg; 808 u8 reset_in_progress; 809 u8 unrecoverable; 810 struct mutex reset_mutex; 811 wait_queue_head_t reset_waitq; 812 813 u16 diagsave_timeout; 814 int logging_level; 815 u16 flush_io_count; 816 817 struct mpi3mr_fwevt *current_event; 818 struct mpi3_driver_info_layout driver_info; 819 u16 change_count; 820 u16 op_reply_q_offset; 821 }; 822 823 /** 824 * struct mpi3mr_fwevt - Firmware event structure. 825 * 826 * @list: list head 827 * @work: Work structure 828 * @mrioc: Adapter instance reference 829 * @event_id: MPI3 firmware event ID 830 * @send_ack: Event acknowledgment required or not 831 * @process_evt: Bottomhalf processing required or not 832 * @evt_ctx: Event context to send in Ack 833 * @ref_count: kref count 834 * @event_data: Actual MPI3 event data 835 */ 836 struct mpi3mr_fwevt { 837 struct list_head list; 838 struct work_struct work; 839 struct mpi3mr_ioc *mrioc; 840 u16 event_id; 841 bool send_ack; 842 bool process_evt; 843 u32 evt_ctx; 844 struct kref ref_count; 845 char event_data[0] __aligned(4); 846 }; 847 848 849 /** 850 * struct delayed_dev_rmhs_node - Delayed device removal node 851 * 852 * @list: list head 853 * @handle: Device handle 854 * @iou_rc: IO Unit Control Reason Code 855 */ 856 struct delayed_dev_rmhs_node { 857 struct list_head list; 858 u16 handle; 859 u8 iou_rc; 860 }; 861 862 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 863 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 864 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 865 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 866 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 867 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 868 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 869 u16 admin_req_sz, u8 ignore_reset); 870 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 871 struct op_req_qinfo *opreqq, u8 *req); 872 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 873 dma_addr_t dma_addr); 874 void mpi3mr_build_zero_len_sge(void *paddr); 875 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 876 dma_addr_t phys_addr); 877 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 878 dma_addr_t phys_addr); 879 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 880 u64 sense_buf_dma); 881 882 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 883 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 884 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 885 struct mpi3_event_notification_reply *event_reply); 886 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 887 struct mpi3_default_reply_descriptor *reply_desc, 888 u64 *reply_dma, u16 qidx); 889 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 890 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 891 892 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 893 u32 reset_reason, u8 snapdump); 894 int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc, 895 u32 reset_reason); 896 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 897 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 898 899 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 900 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 901 u32 event_ctx); 902 903 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 904 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 905 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 906 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 907 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 908 void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc); 909 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 910 911 #endif /*MPI3MR_H_INCLUDED*/ 912