1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 /* Definitions for internal SGL and Chain SGL buffers */ 70 #define MPI3MR_PAGE_SIZE_4K 4096 71 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 72 73 /* Definitions for MAX values for shost */ 74 #define MPI3MR_MAX_CMDS_LUN 7 75 #define MPI3MR_MAX_CDB_LENGTH 32 76 77 /* Admin queue management definitions */ 78 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 79 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 80 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 81 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 82 83 /* Operational queue management definitions */ 84 #define MPI3MR_OP_REQ_Q_QD 512 85 #define MPI3MR_OP_REP_Q_QD 1024 86 #define MPI3MR_OP_REP_Q_QD4K 4096 87 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 88 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 89 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 90 91 /* Reserved Host Tag definitions */ 92 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 93 #define MPI3MR_HOSTTAG_INITCMDS 1 94 #define MPI3MR_HOSTTAG_BSG_CMDS 2 95 #define MPI3MR_HOSTTAG_PEL_ABORT 3 96 #define MPI3MR_HOSTTAG_PEL_WAIT 4 97 #define MPI3MR_HOSTTAG_BLK_TMS 5 98 99 #define MPI3MR_NUM_DEVRMCMD 16 100 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 101 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 102 MPI3MR_NUM_DEVRMCMD - 1) 103 104 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 105 #define MPI3MR_NUM_EVTACKCMD 4 106 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 107 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 108 MPI3MR_NUM_EVTACKCMD - 1) 109 110 /* Reduced resource count definition for crash kernel */ 111 #define MPI3MR_HOST_IOS_KDUMP 128 112 113 /* command/controller interaction timeout definitions in seconds */ 114 #define MPI3MR_INTADMCMD_TIMEOUT 60 115 #define MPI3MR_PORTENABLE_TIMEOUT 300 116 #define MPI3MR_ABORTTM_TIMEOUT 60 117 #define MPI3MR_RESETTM_TIMEOUT 60 118 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 119 #define MPI3MR_TSUPDATE_INTERVAL 900 120 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 121 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 122 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 123 #define MPI3MR_RESET_ACK_TIMEOUT 30 124 125 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 126 127 /* Internal admin command state definitions*/ 128 #define MPI3MR_CMD_NOTUSED 0x8000 129 #define MPI3MR_CMD_COMPLETE 0x0001 130 #define MPI3MR_CMD_PENDING 0x0002 131 #define MPI3MR_CMD_REPLY_VALID 0x0004 132 #define MPI3MR_CMD_RESET 0x0008 133 134 /* Definitions for Event replies and sense buffer allocated per controller */ 135 #define MPI3MR_NUM_EVT_REPLIES 64 136 #define MPI3MR_SENSE_BUF_SZ 256 137 #define MPI3MR_SENSEBUF_FACTOR 3 138 #define MPI3MR_CHAINBUF_FACTOR 3 139 #define MPI3MR_CHAINBUFDIX_FACTOR 2 140 141 /* Invalid target device handle */ 142 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 143 144 /* Controller Reset related definitions */ 145 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 146 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 147 148 /* ResponseCode definitions */ 149 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 150 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 151 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 152 153 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 154 #define MPI3MR_DEFAULT_PGSZEXP (12) 155 156 /* Command retry count definitions */ 157 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 158 #define MPI3MR_PEL_RETRY_COUNT 3 159 160 /* Default target device queue depth */ 161 #define MPI3MR_DEFAULT_SDEV_QD 32 162 163 /* Definitions for Threaded IRQ poll*/ 164 #define MPI3MR_IRQ_POLL_SLEEP 2 165 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 166 167 /* Definitions for the controller security status*/ 168 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 169 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 170 171 #define MPI3MR_INVALID_DEVICE 0x00 172 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 173 #define MPI3MR_HARD_SECURE_DEVICE 0x08 174 #define MPI3MR_TAMPERED_DEVICE 0x0C 175 176 /* SGE Flag definition */ 177 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 178 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 179 MPI3_SGE_FLAGS_END_OF_LIST) 180 181 /* MSI Index from Reply Queue Index */ 182 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 183 184 /* 185 * Maximum data transfer size definitions for management 186 * application commands 187 */ 188 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 189 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 190 /* 191 * 2048 sectors are for data buffers and additional 512 sectors for 192 * other buffers 193 */ 194 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 195 196 /** 197 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 198 * Encapsulated commands. 199 * 200 * @base_addr: Physical address 201 * @length: SGE length 202 * @rsvd: Reserved 203 * @rsvd1: Reserved 204 * @sgl_type: sgl type 205 */ 206 struct mpi3mr_nvme_pt_sge { 207 u64 base_addr; 208 u32 length; 209 u16 rsvd; 210 u8 rsvd1; 211 u8 sgl_type; 212 }; 213 214 /** 215 * struct mpi3mr_buf_map - local structure to 216 * track kernel and user buffers associated with an BSG 217 * structure. 218 * 219 * @bsg_buf: BSG buffer virtual address 220 * @bsg_buf_len: BSG buffer length 221 * @kern_buf: Kernel buffer virtual address 222 * @kern_buf_len: Kernel buffer length 223 * @kern_buf_dma: Kernel buffer DMA address 224 * @data_dir: Data direction. 225 */ 226 struct mpi3mr_buf_map { 227 void *bsg_buf; 228 u32 bsg_buf_len; 229 void *kern_buf; 230 u32 kern_buf_len; 231 dma_addr_t kern_buf_dma; 232 u8 data_dir; 233 }; 234 235 /* IOC State definitions */ 236 enum mpi3mr_iocstate { 237 MRIOC_STATE_READY = 1, 238 MRIOC_STATE_RESET, 239 MRIOC_STATE_FAULT, 240 MRIOC_STATE_BECOMING_READY, 241 MRIOC_STATE_RESET_REQUESTED, 242 MRIOC_STATE_UNRECOVERABLE, 243 }; 244 245 /* Reset reason code definitions*/ 246 enum mpi3mr_reset_reason { 247 MPI3MR_RESET_FROM_BRINGUP = 1, 248 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 249 MPI3MR_RESET_FROM_APP = 3, 250 MPI3MR_RESET_FROM_EH_HOS = 4, 251 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 252 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 253 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 254 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 255 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 256 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 257 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 258 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 259 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 260 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 261 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 262 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 263 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 264 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 265 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 266 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 267 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 268 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 269 MPI3MR_RESET_FROM_SYSFS = 23, 270 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 271 MPI3MR_RESET_FROM_FIRMWARE = 27, 272 }; 273 274 /* Queue type definitions */ 275 enum queue_type { 276 MPI3MR_DEFAULT_QUEUE = 0, 277 MPI3MR_POLL_QUEUE, 278 }; 279 280 /** 281 * struct mpi3mr_compimg_ver - replica of component image 282 * version defined in mpi30_image.h in host endianness 283 * 284 */ 285 struct mpi3mr_compimg_ver { 286 u16 build_num; 287 u16 cust_id; 288 u8 ph_minor; 289 u8 ph_major; 290 u8 gen_minor; 291 u8 gen_major; 292 }; 293 294 /** 295 * struct mpi3mr_ioc_facs - replica of component image version 296 * defined in mpi30_ioc.h in host endianness 297 * 298 */ 299 struct mpi3mr_ioc_facts { 300 u32 ioc_capabilities; 301 struct mpi3mr_compimg_ver fw_ver; 302 u32 mpi_version; 303 u16 max_reqs; 304 u16 product_id; 305 u16 op_req_sz; 306 u16 reply_sz; 307 u16 exceptions; 308 u16 max_perids; 309 u16 max_pds; 310 u16 max_sasexpanders; 311 u16 max_sasinitiators; 312 u16 max_enclosures; 313 u16 max_pcie_switches; 314 u16 max_nvme; 315 u16 max_vds; 316 u16 max_hpds; 317 u16 max_advhpds; 318 u16 max_raid_pds; 319 u16 min_devhandle; 320 u16 max_devhandle; 321 u16 max_op_req_q; 322 u16 max_op_reply_q; 323 u16 shutdown_timeout; 324 u8 ioc_num; 325 u8 who_init; 326 u16 max_msix_vectors; 327 u8 personality; 328 u8 dma_mask; 329 u8 protocol_flags; 330 u8 sge_mod_mask; 331 u8 sge_mod_value; 332 u8 sge_mod_shift; 333 }; 334 335 /** 336 * struct segments - memory descriptor structure to store 337 * virtual and dma addresses for operational queue segments. 338 * 339 * @segment: virtual address 340 * @segment_dma: dma address 341 */ 342 struct segments { 343 void *segment; 344 dma_addr_t segment_dma; 345 }; 346 347 /** 348 * struct op_req_qinfo - Operational Request Queue Information 349 * 350 * @ci: consumer index 351 * @pi: producer index 352 * @num_request: Maximum number of entries in the queue 353 * @qid: Queue Id starting from 1 354 * @reply_qid: Associated reply queue Id 355 * @num_segments: Number of discontiguous memory segments 356 * @segment_qd: Depth of each segments 357 * @q_lock: Concurrent queue access lock 358 * @q_segments: Segment descriptor pointer 359 * @q_segment_list: Segment list base virtual address 360 * @q_segment_list_dma: Segment list base DMA address 361 */ 362 struct op_req_qinfo { 363 u16 ci; 364 u16 pi; 365 u16 num_requests; 366 u16 qid; 367 u16 reply_qid; 368 u16 num_segments; 369 u16 segment_qd; 370 spinlock_t q_lock; 371 struct segments *q_segments; 372 void *q_segment_list; 373 dma_addr_t q_segment_list_dma; 374 }; 375 376 /** 377 * struct op_reply_qinfo - Operational Reply Queue Information 378 * 379 * @ci: consumer index 380 * @qid: Queue Id starting from 1 381 * @num_replies: Maximum number of entries in the queue 382 * @num_segments: Number of discontiguous memory segments 383 * @segment_qd: Depth of each segments 384 * @q_segments: Segment descriptor pointer 385 * @q_segment_list: Segment list base virtual address 386 * @q_segment_list_dma: Segment list base DMA address 387 * @ephase: Expected phased identifier for the reply queue 388 * @pend_ios: Number of IOs pending in HW for this queue 389 * @enable_irq_poll: Flag to indicate polling is enabled 390 * @in_use: Queue is handled by poll/ISR 391 * @qtype: Type of queue (types defined in enum queue_type) 392 */ 393 struct op_reply_qinfo { 394 u16 ci; 395 u16 qid; 396 u16 num_replies; 397 u16 num_segments; 398 u16 segment_qd; 399 struct segments *q_segments; 400 void *q_segment_list; 401 dma_addr_t q_segment_list_dma; 402 u8 ephase; 403 atomic_t pend_ios; 404 bool enable_irq_poll; 405 atomic_t in_use; 406 enum queue_type qtype; 407 }; 408 409 /** 410 * struct mpi3mr_intr_info - Interrupt cookie information 411 * 412 * @mrioc: Adapter instance reference 413 * @msix_index: MSIx index 414 * @op_reply_q: Associated operational reply queue 415 * @name: Dev name for the irq claiming device 416 */ 417 struct mpi3mr_intr_info { 418 struct mpi3mr_ioc *mrioc; 419 u16 msix_index; 420 struct op_reply_qinfo *op_reply_q; 421 char name[MPI3MR_NAME_LENGTH]; 422 }; 423 424 /** 425 * struct tgt_dev_sas_sata - SAS/SATA device specific 426 * information cached from firmware given data 427 * 428 * @sas_address: World wide unique SAS address 429 * @dev_info: Device information bits 430 */ 431 struct tgt_dev_sas_sata { 432 u64 sas_address; 433 u16 dev_info; 434 }; 435 436 /** 437 * struct tgt_dev_pcie - PCIe device specific information cached 438 * from firmware given data 439 * 440 * @mdts: Maximum data transfer size 441 * @capb: Device capabilities 442 * @pgsz: Device page size 443 * @abort_to: Timeout for abort TM 444 * @reset_to: Timeout for Target/LUN reset TM 445 * @dev_info: Device information bits 446 */ 447 struct tgt_dev_pcie { 448 u32 mdts; 449 u16 capb; 450 u8 pgsz; 451 u8 abort_to; 452 u8 reset_to; 453 u16 dev_info; 454 }; 455 456 /** 457 * struct tgt_dev_volume - virtual device specific information 458 * cached from firmware given data 459 * 460 * @state: State of the VD 461 */ 462 struct tgt_dev_volume { 463 u8 state; 464 }; 465 466 /** 467 * union _form_spec_inf - union of device specific information 468 */ 469 union _form_spec_inf { 470 struct tgt_dev_sas_sata sas_sata_inf; 471 struct tgt_dev_pcie pcie_inf; 472 struct tgt_dev_volume vol_inf; 473 }; 474 475 476 477 /** 478 * struct mpi3mr_tgt_dev - target device data structure 479 * 480 * @list: List pointer 481 * @starget: Scsi_target pointer 482 * @dev_handle: FW device handle 483 * @parent_handle: FW parent device handle 484 * @slot: Slot number 485 * @encl_handle: FW enclosure handle 486 * @perst_id: FW assigned Persistent ID 487 * @dev_type: SAS/SATA/PCIE device type 488 * @is_hidden: Should be exposed to upper layers or not 489 * @host_exposed: Already exposed to host or not 490 * @q_depth: Device specific Queue Depth 491 * @wwid: World wide ID 492 * @dev_spec: Device type specific information 493 * @ref_count: Reference count 494 */ 495 struct mpi3mr_tgt_dev { 496 struct list_head list; 497 struct scsi_target *starget; 498 u16 dev_handle; 499 u16 parent_handle; 500 u16 slot; 501 u16 encl_handle; 502 u16 perst_id; 503 u8 dev_type; 504 u8 is_hidden; 505 u8 host_exposed; 506 u16 q_depth; 507 u64 wwid; 508 union _form_spec_inf dev_spec; 509 struct kref ref_count; 510 }; 511 512 /** 513 * mpi3mr_tgtdev_get - k reference incrementor 514 * @s: Target device reference 515 * 516 * Increment target device reference count. 517 */ 518 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 519 { 520 kref_get(&s->ref_count); 521 } 522 523 /** 524 * mpi3mr_free_tgtdev - target device memory dealloctor 525 * @r: k reference pointer of the target device 526 * 527 * Free target device memory when no reference. 528 */ 529 static inline void mpi3mr_free_tgtdev(struct kref *r) 530 { 531 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 532 } 533 534 /** 535 * mpi3mr_tgtdev_put - k reference decrementor 536 * @s: Target device reference 537 * 538 * Decrement target device reference count. 539 */ 540 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 541 { 542 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 543 } 544 545 546 /** 547 * struct mpi3mr_stgt_priv_data - SCSI target private structure 548 * 549 * @starget: Scsi_target pointer 550 * @dev_handle: FW device handle 551 * @perst_id: FW assigned Persistent ID 552 * @num_luns: Number of Logical Units 553 * @block_io: I/O blocked to the device or not 554 * @dev_removed: Device removed in the Firmware 555 * @dev_removedelay: Device is waiting to be removed in FW 556 * @dev_type: Device type 557 * @tgt_dev: Internal target device pointer 558 * @pend_count: Counter to track pending I/Os during error 559 * handling 560 */ 561 struct mpi3mr_stgt_priv_data { 562 struct scsi_target *starget; 563 u16 dev_handle; 564 u16 perst_id; 565 u32 num_luns; 566 atomic_t block_io; 567 u8 dev_removed; 568 u8 dev_removedelay; 569 u8 dev_type; 570 struct mpi3mr_tgt_dev *tgt_dev; 571 u32 pend_count; 572 }; 573 574 /** 575 * struct mpi3mr_stgt_priv_data - SCSI device private structure 576 * 577 * @tgt_priv_data: Scsi_target private data pointer 578 * @lun_id: LUN ID of the device 579 * @ncq_prio_enable: NCQ priority enable for SATA device 580 * @pend_count: Counter to track pending I/Os during error 581 * handling 582 */ 583 struct mpi3mr_sdev_priv_data { 584 struct mpi3mr_stgt_priv_data *tgt_priv_data; 585 u32 lun_id; 586 u8 ncq_prio_enable; 587 u32 pend_count; 588 }; 589 590 /** 591 * struct mpi3mr_drv_cmd - Internal command tracker 592 * 593 * @mutex: Command mutex 594 * @done: Completeor for wakeup 595 * @reply: Firmware reply for internal commands 596 * @sensebuf: Sensebuf for SCSI IO commands 597 * @iou_rc: IO Unit control reason code 598 * @state: Command State 599 * @dev_handle: Firmware handle for device specific commands 600 * @ioc_status: IOC status from the firmware 601 * @ioc_loginfo:IOC log info from the firmware 602 * @is_waiting: Is the command issued in block mode 603 * @is_sense: Is Sense data present 604 * @retry_count: Retry count for retriable commands 605 * @host_tag: Host tag used by the command 606 * @callback: Callback for non blocking commands 607 */ 608 struct mpi3mr_drv_cmd { 609 struct mutex mutex; 610 struct completion done; 611 void *reply; 612 u8 *sensebuf; 613 u8 iou_rc; 614 u16 state; 615 u16 dev_handle; 616 u16 ioc_status; 617 u32 ioc_loginfo; 618 u8 is_waiting; 619 u8 is_sense; 620 u8 retry_count; 621 u16 host_tag; 622 623 void (*callback)(struct mpi3mr_ioc *mrioc, 624 struct mpi3mr_drv_cmd *drv_cmd); 625 }; 626 627 628 /** 629 * struct chain_element - memory descriptor structure to store 630 * virtual and dma addresses for chain elements. 631 * 632 * @addr: virtual address 633 * @dma_addr: dma address 634 */ 635 struct chain_element { 636 void *addr; 637 dma_addr_t dma_addr; 638 }; 639 640 /** 641 * struct scmd_priv - SCSI command private data 642 * 643 * @host_tag: Host tag specific to operational queue 644 * @in_lld_scope: Command in LLD scope or not 645 * @meta_sg_valid: DIX command with meta data SGL or not 646 * @scmd: SCSI Command pointer 647 * @req_q_idx: Operational request queue index 648 * @chain_idx: Chain frame index 649 * @meta_chain_idx: Chain frame index of meta data SGL 650 * @mpi3mr_scsiio_req: MPI SCSI IO request 651 */ 652 struct scmd_priv { 653 u16 host_tag; 654 u8 in_lld_scope; 655 u8 meta_sg_valid; 656 struct scsi_cmnd *scmd; 657 u16 req_q_idx; 658 int chain_idx; 659 int meta_chain_idx; 660 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 661 }; 662 663 /** 664 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 665 * private data 666 * 667 * @list: List pointer 668 * @pdev: PCI device pointer 669 * @shost: Scsi_Host pointer 670 * @id: Controller ID 671 * @cpu_count: Number of online CPUs 672 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 673 * @name: Controller ASCII name 674 * @driver_name: Driver ASCII name 675 * @sysif_regs: System interface registers virtual address 676 * @sysif_regs_phys: System interface registers physical address 677 * @bars: PCI BARS 678 * @dma_mask: DMA mask 679 * @msix_count: Number of MSIX vectors used 680 * @intr_enabled: Is interrupts enabled 681 * @num_admin_req: Number of admin requests 682 * @admin_req_q_sz: Admin request queue size 683 * @admin_req_pi: Admin request queue producer index 684 * @admin_req_ci: Admin request queue consumer index 685 * @admin_req_base: Admin request queue base virtual address 686 * @admin_req_dma: Admin request queue base dma address 687 * @admin_req_lock: Admin queue access lock 688 * @num_admin_replies: Number of admin replies 689 * @admin_reply_q_sz: Admin reply queue size 690 * @admin_reply_ci: Admin reply queue consumer index 691 * @admin_reply_ephase:Admin reply queue expected phase 692 * @admin_reply_base: Admin reply queue base virtual address 693 * @admin_reply_dma: Admin reply queue base dma address 694 * @ready_timeout: Controller ready timeout 695 * @intr_info: Interrupt cookie pointer 696 * @intr_info_count: Number of interrupt cookies 697 * @is_intr_info_set: Flag to indicate intr info is setup 698 * @num_queues: Number of operational queues 699 * @num_op_req_q: Number of operational request queues 700 * @req_qinfo: Operational request queue info pointer 701 * @num_op_reply_q: Number of operational reply queues 702 * @op_reply_qinfo: Operational reply queue info pointer 703 * @init_cmds: Command tracker for initialization commands 704 * @facts: Cached IOC facts data 705 * @op_reply_desc_sz: Operational reply descriptor size 706 * @num_reply_bufs: Number of reply buffers allocated 707 * @reply_buf_pool: Reply buffer pool 708 * @reply_buf: Reply buffer base virtual address 709 * @reply_buf_dma: Reply buffer DMA address 710 * @reply_buf_dma_max_address: Reply DMA address max limit 711 * @reply_free_qsz: Reply free queue size 712 * @reply_free_q_pool: Reply free queue pool 713 * @reply_free_q: Reply free queue base virtual address 714 * @reply_free_q_dma: Reply free queue base DMA address 715 * @reply_free_queue_lock: Reply free queue lock 716 * @reply_free_queue_host_index: Reply free queue host index 717 * @num_sense_bufs: Number of sense buffers 718 * @sense_buf_pool: Sense buffer pool 719 * @sense_buf: Sense buffer base virtual address 720 * @sense_buf_dma: Sense buffer base DMA address 721 * @sense_buf_q_sz: Sense buffer queue size 722 * @sense_buf_q_pool: Sense buffer queue pool 723 * @sense_buf_q: Sense buffer queue virtual address 724 * @sense_buf_q_dma: Sense buffer queue DMA address 725 * @sbq_lock: Sense buffer queue lock 726 * @sbq_host_index: Sense buffer queuehost index 727 * @event_masks: Event mask bitmap 728 * @fwevt_worker_name: Firmware event worker thread name 729 * @fwevt_worker_thread: Firmware event worker thread 730 * @fwevt_lock: Firmware event lock 731 * @fwevt_list: Firmware event list 732 * @watchdog_work_q_name: Fault watchdog worker thread name 733 * @watchdog_work_q: Fault watchdog worker thread 734 * @watchdog_work: Fault watchdog work 735 * @watchdog_lock: Fault watchdog lock 736 * @is_driver_loading: Is driver still loading 737 * @scan_started: Async scan started 738 * @scan_failed: Asycn scan failed 739 * @stop_drv_processing: Stop all command processing 740 * @max_host_ios: Maximum host I/O count 741 * @chain_buf_count: Chain buffer count 742 * @chain_buf_pool: Chain buffer pool 743 * @chain_sgl_list: Chain SGL list 744 * @chain_bitmap_sz: Chain buffer allocator bitmap size 745 * @chain_bitmap: Chain buffer allocator bitmap 746 * @chain_buf_lock: Chain buffer list lock 747 * @bsg_cmds: Command tracker for BSG command 748 * @host_tm_cmds: Command tracker for task management commands 749 * @dev_rmhs_cmds: Command tracker for device removal commands 750 * @evtack_cmds: Command tracker for event ack commands 751 * @devrem_bitmap_sz: Device removal bitmap size 752 * @devrem_bitmap: Device removal bitmap 753 * @dev_handle_bitmap_sz: Device handle bitmap size 754 * @removepend_bitmap: Remove pending bitmap 755 * @delayed_rmhs_list: Delayed device removal list 756 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 757 * @evtack_cmds_bitmap: Event Ack bitmap 758 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 759 * @ts_update_counter: Timestamp update counter 760 * @reset_in_progress: Reset in progress flag 761 * @unrecoverable: Controller unrecoverable flag 762 * @prev_reset_result: Result of previous reset 763 * @reset_mutex: Controller reset mutex 764 * @reset_waitq: Controller reset wait queue 765 * @prepare_for_reset: Prepare for reset event received 766 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 767 * @prp_list_virt: NVMe encapsulated PRP list virtual base 768 * @prp_list_dma: NVMe encapsulated PRP list DMA 769 * @prp_sz: NVME encapsulated PRP list size 770 * @diagsave_timeout: Diagnostic information save timeout 771 * @logging_level: Controller debug logging level 772 * @flush_io_count: I/O count to flush after reset 773 * @current_event: Firmware event currently in process 774 * @driver_info: Driver, Kernel, OS information to firmware 775 * @change_count: Topology change count 776 * @pel_enabled: Persistent Event Log(PEL) enabled or not 777 * @pel_abort_requested: PEL abort is requested or not 778 * @pel_class: PEL Class identifier 779 * @pel_locale: PEL Locale identifier 780 * @pel_cmds: Command tracker for PEL wait command 781 * @pel_abort_cmd: Command tracker for PEL abort command 782 * @pel_newest_seqnum: Newest PEL sequenece number 783 * @pel_seqnum_virt: PEL sequence number virtual address 784 * @pel_seqnum_dma: PEL sequence number DMA address 785 * @pel_seqnum_sz: PEL sequenece number size 786 * @op_reply_q_offset: Operational reply queue offset with MSIx 787 * @default_qcount: Total Default queues 788 * @active_poll_qcount: Currently active poll queue count 789 * @requested_poll_qcount: User requested poll queue count 790 * @bsg_dev: BSG device structure 791 * @bsg_queue: Request queue for BSG device 792 * @stop_bsgs: Stop BSG request flag 793 * @logdata_buf: Circular buffer to store log data entries 794 * @logdata_buf_idx: Index of entry in buffer to store 795 * @logdata_entry_sz: log data entry size 796 */ 797 struct mpi3mr_ioc { 798 struct list_head list; 799 struct pci_dev *pdev; 800 struct Scsi_Host *shost; 801 u8 id; 802 int cpu_count; 803 bool enable_segqueue; 804 u32 irqpoll_sleep; 805 806 char name[MPI3MR_NAME_LENGTH]; 807 char driver_name[MPI3MR_NAME_LENGTH]; 808 809 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 810 resource_size_t sysif_regs_phys; 811 int bars; 812 u64 dma_mask; 813 814 u16 msix_count; 815 u8 intr_enabled; 816 817 u16 num_admin_req; 818 u32 admin_req_q_sz; 819 u16 admin_req_pi; 820 u16 admin_req_ci; 821 void *admin_req_base; 822 dma_addr_t admin_req_dma; 823 spinlock_t admin_req_lock; 824 825 u16 num_admin_replies; 826 u32 admin_reply_q_sz; 827 u16 admin_reply_ci; 828 u8 admin_reply_ephase; 829 void *admin_reply_base; 830 dma_addr_t admin_reply_dma; 831 832 u32 ready_timeout; 833 834 struct mpi3mr_intr_info *intr_info; 835 u16 intr_info_count; 836 bool is_intr_info_set; 837 838 u16 num_queues; 839 u16 num_op_req_q; 840 struct op_req_qinfo *req_qinfo; 841 842 u16 num_op_reply_q; 843 struct op_reply_qinfo *op_reply_qinfo; 844 845 struct mpi3mr_drv_cmd init_cmds; 846 struct mpi3mr_ioc_facts facts; 847 u16 op_reply_desc_sz; 848 849 u32 num_reply_bufs; 850 struct dma_pool *reply_buf_pool; 851 u8 *reply_buf; 852 dma_addr_t reply_buf_dma; 853 dma_addr_t reply_buf_dma_max_address; 854 855 u16 reply_free_qsz; 856 u16 reply_sz; 857 struct dma_pool *reply_free_q_pool; 858 __le64 *reply_free_q; 859 dma_addr_t reply_free_q_dma; 860 spinlock_t reply_free_queue_lock; 861 u32 reply_free_queue_host_index; 862 863 u32 num_sense_bufs; 864 struct dma_pool *sense_buf_pool; 865 u8 *sense_buf; 866 dma_addr_t sense_buf_dma; 867 868 u16 sense_buf_q_sz; 869 struct dma_pool *sense_buf_q_pool; 870 __le64 *sense_buf_q; 871 dma_addr_t sense_buf_q_dma; 872 spinlock_t sbq_lock; 873 u32 sbq_host_index; 874 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 875 876 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 877 struct workqueue_struct *fwevt_worker_thread; 878 spinlock_t fwevt_lock; 879 struct list_head fwevt_list; 880 881 char watchdog_work_q_name[20]; 882 struct workqueue_struct *watchdog_work_q; 883 struct delayed_work watchdog_work; 884 spinlock_t watchdog_lock; 885 886 u8 is_driver_loading; 887 u8 scan_started; 888 u16 scan_failed; 889 u8 stop_drv_processing; 890 891 u16 max_host_ios; 892 spinlock_t tgtdev_lock; 893 struct list_head tgtdev_list; 894 895 u32 chain_buf_count; 896 struct dma_pool *chain_buf_pool; 897 struct chain_element *chain_sgl_list; 898 u16 chain_bitmap_sz; 899 void *chain_bitmap; 900 spinlock_t chain_buf_lock; 901 902 struct mpi3mr_drv_cmd bsg_cmds; 903 struct mpi3mr_drv_cmd host_tm_cmds; 904 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 905 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 906 u16 devrem_bitmap_sz; 907 void *devrem_bitmap; 908 u16 dev_handle_bitmap_sz; 909 void *removepend_bitmap; 910 struct list_head delayed_rmhs_list; 911 u16 evtack_cmds_bitmap_sz; 912 void *evtack_cmds_bitmap; 913 struct list_head delayed_evtack_cmds_list; 914 915 u32 ts_update_counter; 916 u8 reset_in_progress; 917 u8 unrecoverable; 918 int prev_reset_result; 919 struct mutex reset_mutex; 920 wait_queue_head_t reset_waitq; 921 922 u8 prepare_for_reset; 923 u16 prepare_for_reset_timeout_counter; 924 925 void *prp_list_virt; 926 dma_addr_t prp_list_dma; 927 u32 prp_sz; 928 929 u16 diagsave_timeout; 930 int logging_level; 931 u16 flush_io_count; 932 933 struct mpi3mr_fwevt *current_event; 934 struct mpi3_driver_info_layout driver_info; 935 u16 change_count; 936 937 u8 pel_enabled; 938 u8 pel_abort_requested; 939 u8 pel_class; 940 u16 pel_locale; 941 struct mpi3mr_drv_cmd pel_cmds; 942 struct mpi3mr_drv_cmd pel_abort_cmd; 943 944 u32 pel_newest_seqnum; 945 void *pel_seqnum_virt; 946 dma_addr_t pel_seqnum_dma; 947 u32 pel_seqnum_sz; 948 949 u16 op_reply_q_offset; 950 u16 default_qcount; 951 u16 active_poll_qcount; 952 u16 requested_poll_qcount; 953 954 struct device *bsg_dev; 955 struct request_queue *bsg_queue; 956 u8 stop_bsgs; 957 u8 *logdata_buf; 958 u16 logdata_buf_idx; 959 u16 logdata_entry_sz; 960 }; 961 962 /** 963 * struct mpi3mr_fwevt - Firmware event structure. 964 * 965 * @list: list head 966 * @work: Work structure 967 * @mrioc: Adapter instance reference 968 * @event_id: MPI3 firmware event ID 969 * @send_ack: Event acknowledgment required or not 970 * @process_evt: Bottomhalf processing required or not 971 * @evt_ctx: Event context to send in Ack 972 * @event_data_size: size of the event data in bytes 973 * @pending_at_sml: waiting for device add/remove API to complete 974 * @discard: discard this event 975 * @ref_count: kref count 976 * @event_data: Actual MPI3 event data 977 */ 978 struct mpi3mr_fwevt { 979 struct list_head list; 980 struct work_struct work; 981 struct mpi3mr_ioc *mrioc; 982 u16 event_id; 983 bool send_ack; 984 bool process_evt; 985 u32 evt_ctx; 986 u16 event_data_size; 987 bool pending_at_sml; 988 bool discard; 989 struct kref ref_count; 990 char event_data[] __aligned(4); 991 }; 992 993 994 /** 995 * struct delayed_dev_rmhs_node - Delayed device removal node 996 * 997 * @list: list head 998 * @handle: Device handle 999 * @iou_rc: IO Unit Control Reason Code 1000 */ 1001 struct delayed_dev_rmhs_node { 1002 struct list_head list; 1003 u16 handle; 1004 u8 iou_rc; 1005 }; 1006 1007 /** 1008 * struct delayed_evt_ack_node - Delayed event ack node 1009 * @list: list head 1010 * @event: MPI3 event ID 1011 * @event_ctx: event context 1012 */ 1013 struct delayed_evt_ack_node { 1014 struct list_head list; 1015 u8 event; 1016 u32 event_ctx; 1017 }; 1018 1019 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1020 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1021 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1022 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1023 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1024 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1025 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1026 u16 admin_req_sz, u8 ignore_reset); 1027 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1028 struct op_req_qinfo *opreqq, u8 *req); 1029 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1030 dma_addr_t dma_addr); 1031 void mpi3mr_build_zero_len_sge(void *paddr); 1032 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1033 dma_addr_t phys_addr); 1034 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1035 dma_addr_t phys_addr); 1036 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1037 u64 sense_buf_dma); 1038 1039 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1040 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1041 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1042 struct mpi3_event_notification_reply *event_reply); 1043 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1044 struct mpi3_default_reply_descriptor *reply_desc, 1045 u64 *reply_dma, u16 qidx); 1046 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1047 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1048 1049 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1050 u32 reset_reason, u8 snapdump); 1051 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1052 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1053 1054 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1055 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1056 u32 event_ctx); 1057 1058 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1059 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1060 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1061 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1062 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1063 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1064 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1065 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1066 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1067 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1068 struct op_reply_qinfo *op_reply_q); 1069 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1070 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1071 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1072 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1073 u16 handle, uint lun, u16 htag, ulong timeout, 1074 struct mpi3mr_drv_cmd *drv_cmd, 1075 u8 *resp_code, struct scsi_cmnd *scmd); 1076 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1077 struct mpi3mr_ioc *mrioc, u16 handle); 1078 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1079 struct mpi3mr_drv_cmd *drv_cmd); 1080 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1081 struct mpi3mr_drv_cmd *drv_cmd); 1082 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1083 u16 event_data_size); 1084 extern const struct attribute_group *mpi3mr_host_groups[]; 1085 #endif /*MPI3MR_H_INCLUDED*/ 1086