1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_cnfg.h" 44 #include "mpi/mpi30_image.h" 45 #include "mpi/mpi30_init.h" 46 #include "mpi/mpi30_ioc.h" 47 #include "mpi/mpi30_sas.h" 48 #include "mpi/mpi30_pci.h" 49 #include "mpi3mr_debug.h" 50 51 /* Global list and lock for storing multiple adapters managed by the driver */ 52 extern spinlock_t mrioc_list_lock; 53 extern struct list_head mrioc_list; 54 extern int prot_mask; 55 56 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 57 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 58 59 #define MPI3MR_DRIVER_NAME "mpi3mr" 60 #define MPI3MR_DRIVER_LICENSE "GPL" 61 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 62 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 63 64 #define MPI3MR_NAME_LENGTH 32 65 #define IOCNAME "%s: " 66 67 /* Definitions for internal SGL and Chain SGL buffers */ 68 #define MPI3MR_PAGE_SIZE_4K 4096 69 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 70 71 /* Definitions for MAX values for shost */ 72 #define MPI3MR_MAX_CMDS_LUN 7 73 #define MPI3MR_MAX_CDB_LENGTH 32 74 75 /* Admin queue management definitions */ 76 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 77 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 78 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 79 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 80 81 /* Operational queue management definitions */ 82 #define MPI3MR_OP_REQ_Q_QD 512 83 #define MPI3MR_OP_REP_Q_QD 4096 84 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 85 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 86 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 87 88 /* Reserved Host Tag definitions */ 89 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 90 #define MPI3MR_HOSTTAG_INITCMDS 1 91 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 92 #define MPI3MR_HOSTTAG_BLK_TMS 5 93 94 #define MPI3MR_NUM_DEVRMCMD 1 95 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 96 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 97 MPI3MR_NUM_DEVRMCMD - 1) 98 99 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 100 101 /* Reduced resource count definition for crash kernel */ 102 #define MPI3MR_HOST_IOS_KDUMP 128 103 104 /* command/controller interaction timeout definitions in seconds */ 105 #define MPI3MR_INTADMCMD_TIMEOUT 10 106 #define MPI3MR_PORTENABLE_TIMEOUT 300 107 #define MPI3MR_ABORTTM_TIMEOUT 30 108 #define MPI3MR_RESETTM_TIMEOUT 30 109 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 110 #define MPI3MR_TSUPDATE_INTERVAL 900 111 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 112 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 113 114 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 115 116 /* Internal admin command state definitions*/ 117 #define MPI3MR_CMD_NOTUSED 0x8000 118 #define MPI3MR_CMD_COMPLETE 0x0001 119 #define MPI3MR_CMD_PENDING 0x0002 120 #define MPI3MR_CMD_REPLY_VALID 0x0004 121 #define MPI3MR_CMD_RESET 0x0008 122 123 /* Definitions for Event replies and sense buffer allocated per controller */ 124 #define MPI3MR_NUM_EVT_REPLIES 64 125 #define MPI3MR_SENSE_BUF_SZ 256 126 #define MPI3MR_SENSEBUF_FACTOR 3 127 #define MPI3MR_CHAINBUF_FACTOR 3 128 #define MPI3MR_CHAINBUFDIX_FACTOR 2 129 130 /* Invalid target device handle */ 131 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 132 133 /* Controller Reset related definitions */ 134 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 135 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 136 137 /* ResponseCode definitions */ 138 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 139 #define MPI3MR_RSP_TM_COMPLETE 0x00 140 #define MPI3MR_RSP_INVALID_FRAME 0x02 141 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 142 #define MPI3MR_RSP_TM_FAILED 0x05 143 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 144 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 145 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 146 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 147 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 148 149 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 150 /* Command retry count definitions */ 151 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 152 153 /* Default target device queue depth */ 154 #define MPI3MR_DEFAULT_SDEV_QD 32 155 156 /* Definitions for Threaded IRQ poll*/ 157 #define MPI3MR_IRQ_POLL_SLEEP 2 158 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 159 160 /* Definitions for the controller security status*/ 161 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 162 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 163 164 #define MPI3MR_INVALID_DEVICE 0x00 165 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 166 #define MPI3MR_HARD_SECURE_DEVICE 0x08 167 #define MPI3MR_TAMPERED_DEVICE 0x0C 168 169 /* SGE Flag definition */ 170 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 171 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 172 MPI3_SGE_FLAGS_END_OF_LIST) 173 174 /* MSI Index from Reply Queue Index */ 175 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 176 177 /* IOC State definitions */ 178 enum mpi3mr_iocstate { 179 MRIOC_STATE_READY = 1, 180 MRIOC_STATE_RESET, 181 MRIOC_STATE_FAULT, 182 MRIOC_STATE_BECOMING_READY, 183 MRIOC_STATE_RESET_REQUESTED, 184 MRIOC_STATE_UNRECOVERABLE, 185 }; 186 187 /* Init type definitions */ 188 enum mpi3mr_init_type { 189 MPI3MR_IT_INIT = 0, 190 MPI3MR_IT_RESET, 191 MPI3MR_IT_RESUME, 192 }; 193 194 /* Cleanup reason definitions */ 195 enum mpi3mr_cleanup_reason { 196 MPI3MR_COMPLETE_CLEANUP = 0, 197 MPI3MR_REINIT_FAILURE, 198 MPI3MR_SUSPEND, 199 }; 200 201 /* Reset reason code definitions*/ 202 enum mpi3mr_reset_reason { 203 MPI3MR_RESET_FROM_BRINGUP = 1, 204 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 205 MPI3MR_RESET_FROM_IOCTL = 3, 206 MPI3MR_RESET_FROM_EH_HOS = 4, 207 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 208 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 209 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 210 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 211 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 212 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 213 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 214 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 215 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 216 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 217 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 218 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 219 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 220 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 221 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 222 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 223 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 224 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 225 MPI3MR_RESET_FROM_SYSFS = 23, 226 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24 227 }; 228 229 /** 230 * struct mpi3mr_compimg_ver - replica of component image 231 * version defined in mpi30_image.h in host endianness 232 * 233 */ 234 struct mpi3mr_compimg_ver { 235 u16 build_num; 236 u16 cust_id; 237 u8 ph_minor; 238 u8 ph_major; 239 u8 gen_minor; 240 u8 gen_major; 241 }; 242 243 /** 244 * struct mpi3mr_ioc_facs - replica of component image version 245 * defined in mpi30_ioc.h in host endianness 246 * 247 */ 248 struct mpi3mr_ioc_facts { 249 u32 ioc_capabilities; 250 struct mpi3mr_compimg_ver fw_ver; 251 u32 mpi_version; 252 u16 max_reqs; 253 u16 product_id; 254 u16 op_req_sz; 255 u16 reply_sz; 256 u16 exceptions; 257 u16 max_perids; 258 u16 max_pds; 259 u16 max_sasexpanders; 260 u16 max_sasinitiators; 261 u16 max_enclosures; 262 u16 max_pcie_switches; 263 u16 max_nvme; 264 u16 max_vds; 265 u16 max_hpds; 266 u16 max_advhpds; 267 u16 max_raid_pds; 268 u16 min_devhandle; 269 u16 max_devhandle; 270 u16 max_op_req_q; 271 u16 max_op_reply_q; 272 u16 shutdown_timeout; 273 u8 ioc_num; 274 u8 who_init; 275 u16 max_msix_vectors; 276 u8 personality; 277 u8 dma_mask; 278 u8 protocol_flags; 279 u8 sge_mod_mask; 280 u8 sge_mod_value; 281 u8 sge_mod_shift; 282 }; 283 284 /** 285 * struct segments - memory descriptor structure to store 286 * virtual and dma addresses for operational queue segments. 287 * 288 * @segment: virtual address 289 * @segment_dma: dma address 290 */ 291 struct segments { 292 void *segment; 293 dma_addr_t segment_dma; 294 }; 295 296 /** 297 * struct op_req_qinfo - Operational Request Queue Information 298 * 299 * @ci: consumer index 300 * @pi: producer index 301 * @num_request: Maximum number of entries in the queue 302 * @qid: Queue Id starting from 1 303 * @reply_qid: Associated reply queue Id 304 * @num_segments: Number of discontiguous memory segments 305 * @segment_qd: Depth of each segments 306 * @q_lock: Concurrent queue access lock 307 * @q_segments: Segment descriptor pointer 308 * @q_segment_list: Segment list base virtual address 309 * @q_segment_list_dma: Segment list base DMA address 310 */ 311 struct op_req_qinfo { 312 u16 ci; 313 u16 pi; 314 u16 num_requests; 315 u16 qid; 316 u16 reply_qid; 317 u16 num_segments; 318 u16 segment_qd; 319 spinlock_t q_lock; 320 struct segments *q_segments; 321 void *q_segment_list; 322 dma_addr_t q_segment_list_dma; 323 }; 324 325 /** 326 * struct op_reply_qinfo - Operational Reply Queue Information 327 * 328 * @ci: consumer index 329 * @qid: Queue Id starting from 1 330 * @num_replies: Maximum number of entries in the queue 331 * @num_segments: Number of discontiguous memory segments 332 * @segment_qd: Depth of each segments 333 * @q_segments: Segment descriptor pointer 334 * @q_segment_list: Segment list base virtual address 335 * @q_segment_list_dma: Segment list base DMA address 336 * @ephase: Expected phased identifier for the reply queue 337 * @pend_ios: Number of IOs pending in HW for this queue 338 * @enable_irq_poll: Flag to indicate polling is enabled 339 * @in_use: Queue is handled by poll/ISR 340 */ 341 struct op_reply_qinfo { 342 u16 ci; 343 u16 qid; 344 u16 num_replies; 345 u16 num_segments; 346 u16 segment_qd; 347 struct segments *q_segments; 348 void *q_segment_list; 349 dma_addr_t q_segment_list_dma; 350 u8 ephase; 351 atomic_t pend_ios; 352 bool enable_irq_poll; 353 atomic_t in_use; 354 }; 355 356 /** 357 * struct mpi3mr_intr_info - Interrupt cookie information 358 * 359 * @mrioc: Adapter instance reference 360 * @msix_index: MSIx index 361 * @op_reply_q: Associated operational reply queue 362 * @name: Dev name for the irq claiming device 363 */ 364 struct mpi3mr_intr_info { 365 struct mpi3mr_ioc *mrioc; 366 u16 msix_index; 367 struct op_reply_qinfo *op_reply_q; 368 char name[MPI3MR_NAME_LENGTH]; 369 }; 370 371 /** 372 * struct tgt_dev_sas_sata - SAS/SATA device specific 373 * information cached from firmware given data 374 * 375 * @sas_address: World wide unique SAS address 376 * @dev_info: Device information bits 377 */ 378 struct tgt_dev_sas_sata { 379 u64 sas_address; 380 u16 dev_info; 381 }; 382 383 /** 384 * struct tgt_dev_pcie - PCIe device specific information cached 385 * from firmware given data 386 * 387 * @mdts: Maximum data transfer size 388 * @capb: Device capabilities 389 * @pgsz: Device page size 390 * @abort_to: Timeout for abort TM 391 * @reset_to: Timeout for Target/LUN reset TM 392 */ 393 struct tgt_dev_pcie { 394 u32 mdts; 395 u16 capb; 396 u8 pgsz; 397 u8 abort_to; 398 u8 reset_to; 399 }; 400 401 /** 402 * struct tgt_dev_volume - virtual device specific information 403 * cached from firmware given data 404 * 405 * @state: State of the VD 406 */ 407 struct tgt_dev_volume { 408 u8 state; 409 }; 410 411 /** 412 * union _form_spec_inf - union of device specific information 413 */ 414 union _form_spec_inf { 415 struct tgt_dev_sas_sata sas_sata_inf; 416 struct tgt_dev_pcie pcie_inf; 417 struct tgt_dev_volume vol_inf; 418 }; 419 420 421 422 /** 423 * struct mpi3mr_tgt_dev - target device data structure 424 * 425 * @list: List pointer 426 * @starget: Scsi_target pointer 427 * @dev_handle: FW device handle 428 * @parent_handle: FW parent device handle 429 * @slot: Slot number 430 * @encl_handle: FW enclosure handle 431 * @perst_id: FW assigned Persistent ID 432 * @dev_type: SAS/SATA/PCIE device type 433 * @is_hidden: Should be exposed to upper layers or not 434 * @host_exposed: Already exposed to host or not 435 * @q_depth: Device specific Queue Depth 436 * @wwid: World wide ID 437 * @dev_spec: Device type specific information 438 * @ref_count: Reference count 439 */ 440 struct mpi3mr_tgt_dev { 441 struct list_head list; 442 struct scsi_target *starget; 443 u16 dev_handle; 444 u16 parent_handle; 445 u16 slot; 446 u16 encl_handle; 447 u16 perst_id; 448 u8 dev_type; 449 u8 is_hidden; 450 u8 host_exposed; 451 u16 q_depth; 452 u64 wwid; 453 union _form_spec_inf dev_spec; 454 struct kref ref_count; 455 }; 456 457 /** 458 * mpi3mr_tgtdev_get - k reference incrementor 459 * @s: Target device reference 460 * 461 * Increment target device reference count. 462 */ 463 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 464 { 465 kref_get(&s->ref_count); 466 } 467 468 /** 469 * mpi3mr_free_tgtdev - target device memory dealloctor 470 * @r: k reference pointer of the target device 471 * 472 * Free target device memory when no reference. 473 */ 474 static inline void mpi3mr_free_tgtdev(struct kref *r) 475 { 476 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 477 } 478 479 /** 480 * mpi3mr_tgtdev_put - k reference decrementor 481 * @s: Target device reference 482 * 483 * Decrement target device reference count. 484 */ 485 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 486 { 487 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 488 } 489 490 491 /** 492 * struct mpi3mr_stgt_priv_data - SCSI target private structure 493 * 494 * @starget: Scsi_target pointer 495 * @dev_handle: FW device handle 496 * @perst_id: FW assigned Persistent ID 497 * @num_luns: Number of Logical Units 498 * @block_io: I/O blocked to the device or not 499 * @dev_removed: Device removed in the Firmware 500 * @dev_removedelay: Device is waiting to be removed in FW 501 * @dev_type: Device type 502 * @tgt_dev: Internal target device pointer 503 */ 504 struct mpi3mr_stgt_priv_data { 505 struct scsi_target *starget; 506 u16 dev_handle; 507 u16 perst_id; 508 u32 num_luns; 509 atomic_t block_io; 510 u8 dev_removed; 511 u8 dev_removedelay; 512 u8 dev_type; 513 struct mpi3mr_tgt_dev *tgt_dev; 514 }; 515 516 /** 517 * struct mpi3mr_stgt_priv_data - SCSI device private structure 518 * 519 * @tgt_priv_data: Scsi_target private data pointer 520 * @lun_id: LUN ID of the device 521 * @ncq_prio_enable: NCQ priority enable for SATA device 522 */ 523 struct mpi3mr_sdev_priv_data { 524 struct mpi3mr_stgt_priv_data *tgt_priv_data; 525 u32 lun_id; 526 u8 ncq_prio_enable; 527 }; 528 529 /** 530 * struct mpi3mr_drv_cmd - Internal command tracker 531 * 532 * @mutex: Command mutex 533 * @done: Completeor for wakeup 534 * @reply: Firmware reply for internal commands 535 * @sensebuf: Sensebuf for SCSI IO commands 536 * @iou_rc: IO Unit control reason code 537 * @state: Command State 538 * @dev_handle: Firmware handle for device specific commands 539 * @ioc_status: IOC status from the firmware 540 * @ioc_loginfo:IOC log info from the firmware 541 * @is_waiting: Is the command issued in block mode 542 * @retry_count: Retry count for retriable commands 543 * @host_tag: Host tag used by the command 544 * @callback: Callback for non blocking commands 545 */ 546 struct mpi3mr_drv_cmd { 547 struct mutex mutex; 548 struct completion done; 549 void *reply; 550 u8 *sensebuf; 551 u8 iou_rc; 552 u16 state; 553 u16 dev_handle; 554 u16 ioc_status; 555 u32 ioc_loginfo; 556 u8 is_waiting; 557 u8 retry_count; 558 u16 host_tag; 559 560 void (*callback)(struct mpi3mr_ioc *mrioc, 561 struct mpi3mr_drv_cmd *drv_cmd); 562 }; 563 564 565 /** 566 * struct chain_element - memory descriptor structure to store 567 * virtual and dma addresses for chain elements. 568 * 569 * @addr: virtual address 570 * @dma_addr: dma address 571 */ 572 struct chain_element { 573 void *addr; 574 dma_addr_t dma_addr; 575 }; 576 577 /** 578 * struct scmd_priv - SCSI command private data 579 * 580 * @host_tag: Host tag specific to operational queue 581 * @in_lld_scope: Command in LLD scope or not 582 * @meta_sg_valid: DIX command with meta data SGL or not 583 * @scmd: SCSI Command pointer 584 * @req_q_idx: Operational request queue index 585 * @chain_idx: Chain frame index 586 * @meta_chain_idx: Chain frame index of meta data SGL 587 * @mpi3mr_scsiio_req: MPI SCSI IO request 588 */ 589 struct scmd_priv { 590 u16 host_tag; 591 u8 in_lld_scope; 592 u8 meta_sg_valid; 593 struct scsi_cmnd *scmd; 594 u16 req_q_idx; 595 int chain_idx; 596 int meta_chain_idx; 597 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 598 }; 599 600 /** 601 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 602 * private data 603 * 604 * @list: List pointer 605 * @pdev: PCI device pointer 606 * @shost: Scsi_Host pointer 607 * @id: Controller ID 608 * @cpu_count: Number of online CPUs 609 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 610 * @name: Controller ASCII name 611 * @driver_name: Driver ASCII name 612 * @sysif_regs: System interface registers virtual address 613 * @sysif_regs_phys: System interface registers physical address 614 * @bars: PCI BARS 615 * @dma_mask: DMA mask 616 * @msix_count: Number of MSIX vectors used 617 * @intr_enabled: Is interrupts enabled 618 * @num_admin_req: Number of admin requests 619 * @admin_req_q_sz: Admin request queue size 620 * @admin_req_pi: Admin request queue producer index 621 * @admin_req_ci: Admin request queue consumer index 622 * @admin_req_base: Admin request queue base virtual address 623 * @admin_req_dma: Admin request queue base dma address 624 * @admin_req_lock: Admin queue access lock 625 * @num_admin_replies: Number of admin replies 626 * @admin_reply_q_sz: Admin reply queue size 627 * @admin_reply_ci: Admin reply queue consumer index 628 * @admin_reply_ephase:Admin reply queue expected phase 629 * @admin_reply_base: Admin reply queue base virtual address 630 * @admin_reply_dma: Admin reply queue base dma address 631 * @ready_timeout: Controller ready timeout 632 * @intr_info: Interrupt cookie pointer 633 * @intr_info_count: Number of interrupt cookies 634 * @num_queues: Number of operational queues 635 * @num_op_req_q: Number of operational request queues 636 * @req_qinfo: Operational request queue info pointer 637 * @num_op_reply_q: Number of operational reply queues 638 * @op_reply_qinfo: Operational reply queue info pointer 639 * @init_cmds: Command tracker for initialization commands 640 * @facts: Cached IOC facts data 641 * @op_reply_desc_sz: Operational reply descriptor size 642 * @num_reply_bufs: Number of reply buffers allocated 643 * @reply_buf_pool: Reply buffer pool 644 * @reply_buf: Reply buffer base virtual address 645 * @reply_buf_dma: Reply buffer DMA address 646 * @reply_buf_dma_max_address: Reply DMA address max limit 647 * @reply_free_qsz: Reply free queue size 648 * @reply_free_q_pool: Reply free queue pool 649 * @reply_free_q: Reply free queue base virtual address 650 * @reply_free_q_dma: Reply free queue base DMA address 651 * @reply_free_queue_lock: Reply free queue lock 652 * @reply_free_queue_host_index: Reply free queue host index 653 * @num_sense_bufs: Number of sense buffers 654 * @sense_buf_pool: Sense buffer pool 655 * @sense_buf: Sense buffer base virtual address 656 * @sense_buf_dma: Sense buffer base DMA address 657 * @sense_buf_q_sz: Sense buffer queue size 658 * @sense_buf_q_pool: Sense buffer queue pool 659 * @sense_buf_q: Sense buffer queue virtual address 660 * @sense_buf_q_dma: Sense buffer queue DMA address 661 * @sbq_lock: Sense buffer queue lock 662 * @sbq_host_index: Sense buffer queuehost index 663 * @event_masks: Event mask bitmap 664 * @fwevt_worker_name: Firmware event worker thread name 665 * @fwevt_worker_thread: Firmware event worker thread 666 * @fwevt_lock: Firmware event lock 667 * @fwevt_list: Firmware event list 668 * @watchdog_work_q_name: Fault watchdog worker thread name 669 * @watchdog_work_q: Fault watchdog worker thread 670 * @watchdog_work: Fault watchdog work 671 * @watchdog_lock: Fault watchdog lock 672 * @is_driver_loading: Is driver still loading 673 * @scan_started: Async scan started 674 * @scan_failed: Asycn scan failed 675 * @stop_drv_processing: Stop all command processing 676 * @max_host_ios: Maximum host I/O count 677 * @chain_buf_count: Chain buffer count 678 * @chain_buf_pool: Chain buffer pool 679 * @chain_sgl_list: Chain SGL list 680 * @chain_bitmap_sz: Chain buffer allocator bitmap size 681 * @chain_bitmap: Chain buffer allocator bitmap 682 * @chain_buf_lock: Chain buffer list lock 683 * @host_tm_cmds: Command tracker for task management commands 684 * @dev_rmhs_cmds: Command tracker for device removal commands 685 * @devrem_bitmap_sz: Device removal bitmap size 686 * @devrem_bitmap: Device removal bitmap 687 * @dev_handle_bitmap_sz: Device handle bitmap size 688 * @removepend_bitmap: Remove pending bitmap 689 * @delayed_rmhs_list: Delayed device removal list 690 * @ts_update_counter: Timestamp update counter 691 * @fault_dbg: Fault debug flag 692 * @reset_in_progress: Reset in progress flag 693 * @unrecoverable: Controller unrecoverable flag 694 * @reset_mutex: Controller reset mutex 695 * @reset_waitq: Controller reset wait queue 696 * @diagsave_timeout: Diagnostic information save timeout 697 * @logging_level: Controller debug logging level 698 * @flush_io_count: I/O count to flush after reset 699 * @current_event: Firmware event currently in process 700 * @driver_info: Driver, Kernel, OS information to firmware 701 * @change_count: Topology change count 702 * @op_reply_q_offset: Operational reply queue offset with MSIx 703 */ 704 struct mpi3mr_ioc { 705 struct list_head list; 706 struct pci_dev *pdev; 707 struct Scsi_Host *shost; 708 u8 id; 709 int cpu_count; 710 bool enable_segqueue; 711 u32 irqpoll_sleep; 712 713 char name[MPI3MR_NAME_LENGTH]; 714 char driver_name[MPI3MR_NAME_LENGTH]; 715 716 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 717 resource_size_t sysif_regs_phys; 718 int bars; 719 u64 dma_mask; 720 721 u16 msix_count; 722 u8 intr_enabled; 723 724 u16 num_admin_req; 725 u32 admin_req_q_sz; 726 u16 admin_req_pi; 727 u16 admin_req_ci; 728 void *admin_req_base; 729 dma_addr_t admin_req_dma; 730 spinlock_t admin_req_lock; 731 732 u16 num_admin_replies; 733 u32 admin_reply_q_sz; 734 u16 admin_reply_ci; 735 u8 admin_reply_ephase; 736 void *admin_reply_base; 737 dma_addr_t admin_reply_dma; 738 739 u32 ready_timeout; 740 741 struct mpi3mr_intr_info *intr_info; 742 u16 intr_info_count; 743 744 u16 num_queues; 745 u16 num_op_req_q; 746 struct op_req_qinfo *req_qinfo; 747 748 u16 num_op_reply_q; 749 struct op_reply_qinfo *op_reply_qinfo; 750 751 struct mpi3mr_drv_cmd init_cmds; 752 struct mpi3mr_ioc_facts facts; 753 u16 op_reply_desc_sz; 754 755 u32 num_reply_bufs; 756 struct dma_pool *reply_buf_pool; 757 u8 *reply_buf; 758 dma_addr_t reply_buf_dma; 759 dma_addr_t reply_buf_dma_max_address; 760 761 u16 reply_free_qsz; 762 struct dma_pool *reply_free_q_pool; 763 __le64 *reply_free_q; 764 dma_addr_t reply_free_q_dma; 765 spinlock_t reply_free_queue_lock; 766 u32 reply_free_queue_host_index; 767 768 u32 num_sense_bufs; 769 struct dma_pool *sense_buf_pool; 770 u8 *sense_buf; 771 dma_addr_t sense_buf_dma; 772 773 u16 sense_buf_q_sz; 774 struct dma_pool *sense_buf_q_pool; 775 __le64 *sense_buf_q; 776 dma_addr_t sense_buf_q_dma; 777 spinlock_t sbq_lock; 778 u32 sbq_host_index; 779 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 780 781 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 782 struct workqueue_struct *fwevt_worker_thread; 783 spinlock_t fwevt_lock; 784 struct list_head fwevt_list; 785 786 char watchdog_work_q_name[20]; 787 struct workqueue_struct *watchdog_work_q; 788 struct delayed_work watchdog_work; 789 spinlock_t watchdog_lock; 790 791 u8 is_driver_loading; 792 u8 scan_started; 793 u16 scan_failed; 794 u8 stop_drv_processing; 795 796 u16 max_host_ios; 797 spinlock_t tgtdev_lock; 798 struct list_head tgtdev_list; 799 800 u32 chain_buf_count; 801 struct dma_pool *chain_buf_pool; 802 struct chain_element *chain_sgl_list; 803 u16 chain_bitmap_sz; 804 void *chain_bitmap; 805 spinlock_t chain_buf_lock; 806 807 struct mpi3mr_drv_cmd host_tm_cmds; 808 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 809 u16 devrem_bitmap_sz; 810 void *devrem_bitmap; 811 u16 dev_handle_bitmap_sz; 812 void *removepend_bitmap; 813 struct list_head delayed_rmhs_list; 814 815 u32 ts_update_counter; 816 u8 fault_dbg; 817 u8 reset_in_progress; 818 u8 unrecoverable; 819 struct mutex reset_mutex; 820 wait_queue_head_t reset_waitq; 821 822 u16 diagsave_timeout; 823 int logging_level; 824 u16 flush_io_count; 825 826 struct mpi3mr_fwevt *current_event; 827 struct mpi3_driver_info_layout driver_info; 828 u16 change_count; 829 u16 op_reply_q_offset; 830 }; 831 832 /** 833 * struct mpi3mr_fwevt - Firmware event structure. 834 * 835 * @list: list head 836 * @work: Work structure 837 * @mrioc: Adapter instance reference 838 * @event_id: MPI3 firmware event ID 839 * @send_ack: Event acknowledgment required or not 840 * @process_evt: Bottomhalf processing required or not 841 * @evt_ctx: Event context to send in Ack 842 * @ref_count: kref count 843 * @event_data: Actual MPI3 event data 844 */ 845 struct mpi3mr_fwevt { 846 struct list_head list; 847 struct work_struct work; 848 struct mpi3mr_ioc *mrioc; 849 u16 event_id; 850 bool send_ack; 851 bool process_evt; 852 u32 evt_ctx; 853 struct kref ref_count; 854 char event_data[0] __aligned(4); 855 }; 856 857 858 /** 859 * struct delayed_dev_rmhs_node - Delayed device removal node 860 * 861 * @list: list head 862 * @handle: Device handle 863 * @iou_rc: IO Unit Control Reason Code 864 */ 865 struct delayed_dev_rmhs_node { 866 struct list_head list; 867 u16 handle; 868 u8 iou_rc; 869 }; 870 871 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 872 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 873 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type); 874 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason); 875 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 876 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 877 u16 admin_req_sz, u8 ignore_reset); 878 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 879 struct op_req_qinfo *opreqq, u8 *req); 880 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 881 dma_addr_t dma_addr); 882 void mpi3mr_build_zero_len_sge(void *paddr); 883 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 884 dma_addr_t phys_addr); 885 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 886 dma_addr_t phys_addr); 887 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 888 u64 sense_buf_dma); 889 890 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 891 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 892 struct mpi3_event_notification_reply *event_reply); 893 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 894 struct mpi3_default_reply_descriptor *reply_desc, 895 u64 *reply_dma, u16 qidx); 896 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 897 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 898 899 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 900 u32 reset_reason, u8 snapdump); 901 int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc, 902 u32 reset_reason); 903 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 904 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 905 906 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 907 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 908 u32 event_ctx); 909 910 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 911 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 912 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 913 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 914 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 915 void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc); 916 917 #endif /*MPI3MR_H_INCLUDED*/ 918