1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_MAX_SECTORS 2048 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 74 75 /* Definitions for MAX values for shost */ 76 #define MPI3MR_MAX_CMDS_LUN 128 77 #define MPI3MR_MAX_CDB_LENGTH 32 78 79 /* Admin queue management definitions */ 80 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 81 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 83 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 84 85 /* Operational queue management definitions */ 86 #define MPI3MR_OP_REQ_Q_QD 512 87 #define MPI3MR_OP_REP_Q_QD 1024 88 #define MPI3MR_OP_REP_Q_QD4K 4096 89 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 90 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 91 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 92 93 /* Reserved Host Tag definitions */ 94 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 95 #define MPI3MR_HOSTTAG_INITCMDS 1 96 #define MPI3MR_HOSTTAG_BSG_CMDS 2 97 #define MPI3MR_HOSTTAG_PEL_ABORT 3 98 #define MPI3MR_HOSTTAG_PEL_WAIT 4 99 #define MPI3MR_HOSTTAG_BLK_TMS 5 100 101 #define MPI3MR_NUM_DEVRMCMD 16 102 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 103 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 104 MPI3MR_NUM_DEVRMCMD - 1) 105 106 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 107 #define MPI3MR_NUM_EVTACKCMD 4 108 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 109 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 110 MPI3MR_NUM_EVTACKCMD - 1) 111 112 /* Reduced resource count definition for crash kernel */ 113 #define MPI3MR_HOST_IOS_KDUMP 128 114 115 /* command/controller interaction timeout definitions in seconds */ 116 #define MPI3MR_INTADMCMD_TIMEOUT 60 117 #define MPI3MR_PORTENABLE_TIMEOUT 300 118 #define MPI3MR_ABORTTM_TIMEOUT 60 119 #define MPI3MR_RESETTM_TIMEOUT 60 120 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 121 #define MPI3MR_TSUPDATE_INTERVAL 900 122 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 123 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 124 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 125 #define MPI3MR_RESET_ACK_TIMEOUT 30 126 127 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 128 129 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 130 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 131 132 /* Internal admin command state definitions*/ 133 #define MPI3MR_CMD_NOTUSED 0x8000 134 #define MPI3MR_CMD_COMPLETE 0x0001 135 #define MPI3MR_CMD_PENDING 0x0002 136 #define MPI3MR_CMD_REPLY_VALID 0x0004 137 #define MPI3MR_CMD_RESET 0x0008 138 139 /* Definitions for Event replies and sense buffer allocated per controller */ 140 #define MPI3MR_NUM_EVT_REPLIES 64 141 #define MPI3MR_SENSE_BUF_SZ 256 142 #define MPI3MR_SENSEBUF_FACTOR 3 143 #define MPI3MR_CHAINBUF_FACTOR 3 144 #define MPI3MR_CHAINBUFDIX_FACTOR 2 145 146 /* Invalid target device handle */ 147 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 148 149 /* Controller Reset related definitions */ 150 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 151 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 152 153 /* ResponseCode definitions */ 154 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 155 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 156 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 157 158 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 159 #define MPI3MR_DEFAULT_PGSZEXP (12) 160 161 /* Command retry count definitions */ 162 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 163 #define MPI3MR_PEL_RETRY_COUNT 3 164 165 /* Default target device queue depth */ 166 #define MPI3MR_DEFAULT_SDEV_QD 32 167 168 /* Definitions for Threaded IRQ poll*/ 169 #define MPI3MR_IRQ_POLL_SLEEP 2 170 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 171 172 /* Definitions for the controller security status*/ 173 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 174 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 175 176 #define MPI3MR_INVALID_DEVICE 0x00 177 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 178 #define MPI3MR_HARD_SECURE_DEVICE 0x08 179 #define MPI3MR_TAMPERED_DEVICE 0x0C 180 181 /* SGE Flag definition */ 182 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 183 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 184 MPI3_SGE_FLAGS_END_OF_LIST) 185 186 /* MSI Index from Reply Queue Index */ 187 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 188 189 /* 190 * Maximum data transfer size definitions for management 191 * application commands 192 */ 193 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 194 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 195 /* 196 * 2048 sectors are for data buffers and additional 512 sectors for 197 * other buffers 198 */ 199 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 200 201 /** 202 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 203 * Encapsulated commands. 204 * 205 * @base_addr: Physical address 206 * @length: SGE length 207 * @rsvd: Reserved 208 * @rsvd1: Reserved 209 * @sgl_type: sgl type 210 */ 211 struct mpi3mr_nvme_pt_sge { 212 u64 base_addr; 213 u32 length; 214 u16 rsvd; 215 u8 rsvd1; 216 u8 sgl_type; 217 }; 218 219 /** 220 * struct mpi3mr_buf_map - local structure to 221 * track kernel and user buffers associated with an BSG 222 * structure. 223 * 224 * @bsg_buf: BSG buffer virtual address 225 * @bsg_buf_len: BSG buffer length 226 * @kern_buf: Kernel buffer virtual address 227 * @kern_buf_len: Kernel buffer length 228 * @kern_buf_dma: Kernel buffer DMA address 229 * @data_dir: Data direction. 230 */ 231 struct mpi3mr_buf_map { 232 void *bsg_buf; 233 u32 bsg_buf_len; 234 void *kern_buf; 235 u32 kern_buf_len; 236 dma_addr_t kern_buf_dma; 237 u8 data_dir; 238 }; 239 240 /* IOC State definitions */ 241 enum mpi3mr_iocstate { 242 MRIOC_STATE_READY = 1, 243 MRIOC_STATE_RESET, 244 MRIOC_STATE_FAULT, 245 MRIOC_STATE_BECOMING_READY, 246 MRIOC_STATE_RESET_REQUESTED, 247 MRIOC_STATE_UNRECOVERABLE, 248 }; 249 250 /* Reset reason code definitions*/ 251 enum mpi3mr_reset_reason { 252 MPI3MR_RESET_FROM_BRINGUP = 1, 253 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 254 MPI3MR_RESET_FROM_APP = 3, 255 MPI3MR_RESET_FROM_EH_HOS = 4, 256 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 257 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 258 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 259 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 260 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 261 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 262 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 263 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 264 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 265 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 266 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 267 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 268 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 269 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 270 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 271 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 272 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 273 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 274 MPI3MR_RESET_FROM_SYSFS = 23, 275 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 276 MPI3MR_RESET_FROM_FIRMWARE = 27, 277 }; 278 279 /* Queue type definitions */ 280 enum queue_type { 281 MPI3MR_DEFAULT_QUEUE = 0, 282 MPI3MR_POLL_QUEUE, 283 }; 284 285 /** 286 * struct mpi3mr_compimg_ver - replica of component image 287 * version defined in mpi30_image.h in host endianness 288 * 289 */ 290 struct mpi3mr_compimg_ver { 291 u16 build_num; 292 u16 cust_id; 293 u8 ph_minor; 294 u8 ph_major; 295 u8 gen_minor; 296 u8 gen_major; 297 }; 298 299 /** 300 * struct mpi3mr_ioc_facs - replica of component image version 301 * defined in mpi30_ioc.h in host endianness 302 * 303 */ 304 struct mpi3mr_ioc_facts { 305 u32 ioc_capabilities; 306 struct mpi3mr_compimg_ver fw_ver; 307 u32 mpi_version; 308 u16 max_reqs; 309 u16 product_id; 310 u16 op_req_sz; 311 u16 reply_sz; 312 u16 exceptions; 313 u16 max_perids; 314 u16 max_pds; 315 u16 max_sasexpanders; 316 u16 max_sasinitiators; 317 u16 max_enclosures; 318 u16 max_pcie_switches; 319 u16 max_nvme; 320 u16 max_vds; 321 u16 max_hpds; 322 u16 max_advhpds; 323 u16 max_raid_pds; 324 u16 min_devhandle; 325 u16 max_devhandle; 326 u16 max_op_req_q; 327 u16 max_op_reply_q; 328 u16 shutdown_timeout; 329 u8 ioc_num; 330 u8 who_init; 331 u16 max_msix_vectors; 332 u8 personality; 333 u8 dma_mask; 334 u8 protocol_flags; 335 u8 sge_mod_mask; 336 u8 sge_mod_value; 337 u8 sge_mod_shift; 338 u8 max_dev_per_tg; 339 u16 max_io_throttle_group; 340 u16 io_throttle_data_length; 341 u16 io_throttle_low; 342 u16 io_throttle_high; 343 344 }; 345 346 /** 347 * struct segments - memory descriptor structure to store 348 * virtual and dma addresses for operational queue segments. 349 * 350 * @segment: virtual address 351 * @segment_dma: dma address 352 */ 353 struct segments { 354 void *segment; 355 dma_addr_t segment_dma; 356 }; 357 358 /** 359 * struct op_req_qinfo - Operational Request Queue Information 360 * 361 * @ci: consumer index 362 * @pi: producer index 363 * @num_request: Maximum number of entries in the queue 364 * @qid: Queue Id starting from 1 365 * @reply_qid: Associated reply queue Id 366 * @num_segments: Number of discontiguous memory segments 367 * @segment_qd: Depth of each segments 368 * @q_lock: Concurrent queue access lock 369 * @q_segments: Segment descriptor pointer 370 * @q_segment_list: Segment list base virtual address 371 * @q_segment_list_dma: Segment list base DMA address 372 */ 373 struct op_req_qinfo { 374 u16 ci; 375 u16 pi; 376 u16 num_requests; 377 u16 qid; 378 u16 reply_qid; 379 u16 num_segments; 380 u16 segment_qd; 381 spinlock_t q_lock; 382 struct segments *q_segments; 383 void *q_segment_list; 384 dma_addr_t q_segment_list_dma; 385 }; 386 387 /** 388 * struct op_reply_qinfo - Operational Reply Queue Information 389 * 390 * @ci: consumer index 391 * @qid: Queue Id starting from 1 392 * @num_replies: Maximum number of entries in the queue 393 * @num_segments: Number of discontiguous memory segments 394 * @segment_qd: Depth of each segments 395 * @q_segments: Segment descriptor pointer 396 * @q_segment_list: Segment list base virtual address 397 * @q_segment_list_dma: Segment list base DMA address 398 * @ephase: Expected phased identifier for the reply queue 399 * @pend_ios: Number of IOs pending in HW for this queue 400 * @enable_irq_poll: Flag to indicate polling is enabled 401 * @in_use: Queue is handled by poll/ISR 402 * @qtype: Type of queue (types defined in enum queue_type) 403 */ 404 struct op_reply_qinfo { 405 u16 ci; 406 u16 qid; 407 u16 num_replies; 408 u16 num_segments; 409 u16 segment_qd; 410 struct segments *q_segments; 411 void *q_segment_list; 412 dma_addr_t q_segment_list_dma; 413 u8 ephase; 414 atomic_t pend_ios; 415 bool enable_irq_poll; 416 atomic_t in_use; 417 enum queue_type qtype; 418 }; 419 420 /** 421 * struct mpi3mr_intr_info - Interrupt cookie information 422 * 423 * @mrioc: Adapter instance reference 424 * @msix_index: MSIx index 425 * @op_reply_q: Associated operational reply queue 426 * @name: Dev name for the irq claiming device 427 */ 428 struct mpi3mr_intr_info { 429 struct mpi3mr_ioc *mrioc; 430 u16 msix_index; 431 struct op_reply_qinfo *op_reply_q; 432 char name[MPI3MR_NAME_LENGTH]; 433 }; 434 435 /** 436 * struct mpi3mr_throttle_group_info - Throttle group info 437 * 438 * @io_divert: Flag indicates io divert is on or off for the TG 439 * @need_qd_reduction: Flag to indicate QD reduction is needed 440 * @qd_reduction: Queue Depth reduction in units of 10% 441 * @fw_qd: QueueDepth value reported by the firmware 442 * @modified_qd: Modified QueueDepth value due to throttling 443 * @id: Throttle Group ID. 444 * @high: High limit to turn on throttling in 512 byte blocks 445 * @low: Low limit to turn off throttling in 512 byte blocks 446 * @pend_large_data_sz: Counter to track pending large data 447 */ 448 struct mpi3mr_throttle_group_info { 449 u8 io_divert; 450 u8 need_qd_reduction; 451 u8 qd_reduction; 452 u16 fw_qd; 453 u16 modified_qd; 454 u16 id; 455 u32 high; 456 u32 low; 457 atomic_t pend_large_data_sz; 458 }; 459 460 /** 461 * struct tgt_dev_sas_sata - SAS/SATA device specific 462 * information cached from firmware given data 463 * 464 * @sas_address: World wide unique SAS address 465 * @dev_info: Device information bits 466 */ 467 struct tgt_dev_sas_sata { 468 u64 sas_address; 469 u16 dev_info; 470 }; 471 472 /** 473 * struct tgt_dev_pcie - PCIe device specific information cached 474 * from firmware given data 475 * 476 * @mdts: Maximum data transfer size 477 * @capb: Device capabilities 478 * @pgsz: Device page size 479 * @abort_to: Timeout for abort TM 480 * @reset_to: Timeout for Target/LUN reset TM 481 * @dev_info: Device information bits 482 */ 483 struct tgt_dev_pcie { 484 u32 mdts; 485 u16 capb; 486 u8 pgsz; 487 u8 abort_to; 488 u8 reset_to; 489 u16 dev_info; 490 }; 491 492 /** 493 * struct tgt_dev_vd - virtual device specific information 494 * cached from firmware given data 495 * 496 * @state: State of the VD 497 * @tg_qd_reduction: Queue Depth reduction in units of 10% 498 * @tg_id: VDs throttle group ID 499 * @high: High limit to turn on throttling in 512 byte blocks 500 * @low: Low limit to turn off throttling in 512 byte blocks 501 * @tg: Pointer to throttle group info 502 */ 503 struct tgt_dev_vd { 504 u8 state; 505 u8 tg_qd_reduction; 506 u16 tg_id; 507 u32 tg_high; 508 u32 tg_low; 509 struct mpi3mr_throttle_group_info *tg; 510 }; 511 512 513 /** 514 * union _form_spec_inf - union of device specific information 515 */ 516 union _form_spec_inf { 517 struct tgt_dev_sas_sata sas_sata_inf; 518 struct tgt_dev_pcie pcie_inf; 519 struct tgt_dev_vd vd_inf; 520 }; 521 522 523 524 /** 525 * struct mpi3mr_tgt_dev - target device data structure 526 * 527 * @list: List pointer 528 * @starget: Scsi_target pointer 529 * @dev_handle: FW device handle 530 * @parent_handle: FW parent device handle 531 * @slot: Slot number 532 * @encl_handle: FW enclosure handle 533 * @perst_id: FW assigned Persistent ID 534 * @dev_type: SAS/SATA/PCIE device type 535 * @is_hidden: Should be exposed to upper layers or not 536 * @host_exposed: Already exposed to host or not 537 * @io_throttle_enabled: I/O throttling needed or not 538 * @q_depth: Device specific Queue Depth 539 * @wwid: World wide ID 540 * @dev_spec: Device type specific information 541 * @ref_count: Reference count 542 */ 543 struct mpi3mr_tgt_dev { 544 struct list_head list; 545 struct scsi_target *starget; 546 u16 dev_handle; 547 u16 parent_handle; 548 u16 slot; 549 u16 encl_handle; 550 u16 perst_id; 551 u8 dev_type; 552 u8 is_hidden; 553 u8 host_exposed; 554 u8 io_throttle_enabled; 555 u16 q_depth; 556 u64 wwid; 557 union _form_spec_inf dev_spec; 558 struct kref ref_count; 559 }; 560 561 /** 562 * mpi3mr_tgtdev_get - k reference incrementor 563 * @s: Target device reference 564 * 565 * Increment target device reference count. 566 */ 567 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 568 { 569 kref_get(&s->ref_count); 570 } 571 572 /** 573 * mpi3mr_free_tgtdev - target device memory dealloctor 574 * @r: k reference pointer of the target device 575 * 576 * Free target device memory when no reference. 577 */ 578 static inline void mpi3mr_free_tgtdev(struct kref *r) 579 { 580 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 581 } 582 583 /** 584 * mpi3mr_tgtdev_put - k reference decrementor 585 * @s: Target device reference 586 * 587 * Decrement target device reference count. 588 */ 589 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 590 { 591 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 592 } 593 594 595 /** 596 * struct mpi3mr_stgt_priv_data - SCSI target private structure 597 * 598 * @starget: Scsi_target pointer 599 * @dev_handle: FW device handle 600 * @perst_id: FW assigned Persistent ID 601 * @num_luns: Number of Logical Units 602 * @block_io: I/O blocked to the device or not 603 * @dev_removed: Device removed in the Firmware 604 * @dev_removedelay: Device is waiting to be removed in FW 605 * @dev_type: Device type 606 * @io_throttle_enabled: I/O throttling needed or not 607 * @io_divert: Flag indicates io divert is on or off for the dev 608 * @throttle_group: Pointer to throttle group info 609 * @tgt_dev: Internal target device pointer 610 * @pend_count: Counter to track pending I/Os during error 611 * handling 612 */ 613 struct mpi3mr_stgt_priv_data { 614 struct scsi_target *starget; 615 u16 dev_handle; 616 u16 perst_id; 617 u32 num_luns; 618 atomic_t block_io; 619 u8 dev_removed; 620 u8 dev_removedelay; 621 u8 dev_type; 622 u8 io_throttle_enabled; 623 u8 io_divert; 624 struct mpi3mr_throttle_group_info *throttle_group; 625 struct mpi3mr_tgt_dev *tgt_dev; 626 u32 pend_count; 627 }; 628 629 /** 630 * struct mpi3mr_stgt_priv_data - SCSI device private structure 631 * 632 * @tgt_priv_data: Scsi_target private data pointer 633 * @lun_id: LUN ID of the device 634 * @ncq_prio_enable: NCQ priority enable for SATA device 635 * @pend_count: Counter to track pending I/Os during error 636 * handling 637 */ 638 struct mpi3mr_sdev_priv_data { 639 struct mpi3mr_stgt_priv_data *tgt_priv_data; 640 u32 lun_id; 641 u8 ncq_prio_enable; 642 u32 pend_count; 643 }; 644 645 /** 646 * struct mpi3mr_drv_cmd - Internal command tracker 647 * 648 * @mutex: Command mutex 649 * @done: Completeor for wakeup 650 * @reply: Firmware reply for internal commands 651 * @sensebuf: Sensebuf for SCSI IO commands 652 * @iou_rc: IO Unit control reason code 653 * @state: Command State 654 * @dev_handle: Firmware handle for device specific commands 655 * @ioc_status: IOC status from the firmware 656 * @ioc_loginfo:IOC log info from the firmware 657 * @is_waiting: Is the command issued in block mode 658 * @is_sense: Is Sense data present 659 * @retry_count: Retry count for retriable commands 660 * @host_tag: Host tag used by the command 661 * @callback: Callback for non blocking commands 662 */ 663 struct mpi3mr_drv_cmd { 664 struct mutex mutex; 665 struct completion done; 666 void *reply; 667 u8 *sensebuf; 668 u8 iou_rc; 669 u16 state; 670 u16 dev_handle; 671 u16 ioc_status; 672 u32 ioc_loginfo; 673 u8 is_waiting; 674 u8 is_sense; 675 u8 retry_count; 676 u16 host_tag; 677 678 void (*callback)(struct mpi3mr_ioc *mrioc, 679 struct mpi3mr_drv_cmd *drv_cmd); 680 }; 681 682 683 /** 684 * struct chain_element - memory descriptor structure to store 685 * virtual and dma addresses for chain elements. 686 * 687 * @addr: virtual address 688 * @dma_addr: dma address 689 */ 690 struct chain_element { 691 void *addr; 692 dma_addr_t dma_addr; 693 }; 694 695 /** 696 * struct scmd_priv - SCSI command private data 697 * 698 * @host_tag: Host tag specific to operational queue 699 * @in_lld_scope: Command in LLD scope or not 700 * @meta_sg_valid: DIX command with meta data SGL or not 701 * @scmd: SCSI Command pointer 702 * @req_q_idx: Operational request queue index 703 * @chain_idx: Chain frame index 704 * @meta_chain_idx: Chain frame index of meta data SGL 705 * @mpi3mr_scsiio_req: MPI SCSI IO request 706 */ 707 struct scmd_priv { 708 u16 host_tag; 709 u8 in_lld_scope; 710 u8 meta_sg_valid; 711 struct scsi_cmnd *scmd; 712 u16 req_q_idx; 713 int chain_idx; 714 int meta_chain_idx; 715 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 716 }; 717 718 /** 719 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 720 * private data 721 * 722 * @list: List pointer 723 * @pdev: PCI device pointer 724 * @shost: Scsi_Host pointer 725 * @id: Controller ID 726 * @cpu_count: Number of online CPUs 727 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 728 * @name: Controller ASCII name 729 * @driver_name: Driver ASCII name 730 * @sysif_regs: System interface registers virtual address 731 * @sysif_regs_phys: System interface registers physical address 732 * @bars: PCI BARS 733 * @dma_mask: DMA mask 734 * @msix_count: Number of MSIX vectors used 735 * @intr_enabled: Is interrupts enabled 736 * @num_admin_req: Number of admin requests 737 * @admin_req_q_sz: Admin request queue size 738 * @admin_req_pi: Admin request queue producer index 739 * @admin_req_ci: Admin request queue consumer index 740 * @admin_req_base: Admin request queue base virtual address 741 * @admin_req_dma: Admin request queue base dma address 742 * @admin_req_lock: Admin queue access lock 743 * @num_admin_replies: Number of admin replies 744 * @admin_reply_q_sz: Admin reply queue size 745 * @admin_reply_ci: Admin reply queue consumer index 746 * @admin_reply_ephase:Admin reply queue expected phase 747 * @admin_reply_base: Admin reply queue base virtual address 748 * @admin_reply_dma: Admin reply queue base dma address 749 * @ready_timeout: Controller ready timeout 750 * @intr_info: Interrupt cookie pointer 751 * @intr_info_count: Number of interrupt cookies 752 * @is_intr_info_set: Flag to indicate intr info is setup 753 * @num_queues: Number of operational queues 754 * @num_op_req_q: Number of operational request queues 755 * @req_qinfo: Operational request queue info pointer 756 * @num_op_reply_q: Number of operational reply queues 757 * @op_reply_qinfo: Operational reply queue info pointer 758 * @init_cmds: Command tracker for initialization commands 759 * @facts: Cached IOC facts data 760 * @op_reply_desc_sz: Operational reply descriptor size 761 * @num_reply_bufs: Number of reply buffers allocated 762 * @reply_buf_pool: Reply buffer pool 763 * @reply_buf: Reply buffer base virtual address 764 * @reply_buf_dma: Reply buffer DMA address 765 * @reply_buf_dma_max_address: Reply DMA address max limit 766 * @reply_free_qsz: Reply free queue size 767 * @reply_free_q_pool: Reply free queue pool 768 * @reply_free_q: Reply free queue base virtual address 769 * @reply_free_q_dma: Reply free queue base DMA address 770 * @reply_free_queue_lock: Reply free queue lock 771 * @reply_free_queue_host_index: Reply free queue host index 772 * @num_sense_bufs: Number of sense buffers 773 * @sense_buf_pool: Sense buffer pool 774 * @sense_buf: Sense buffer base virtual address 775 * @sense_buf_dma: Sense buffer base DMA address 776 * @sense_buf_q_sz: Sense buffer queue size 777 * @sense_buf_q_pool: Sense buffer queue pool 778 * @sense_buf_q: Sense buffer queue virtual address 779 * @sense_buf_q_dma: Sense buffer queue DMA address 780 * @sbq_lock: Sense buffer queue lock 781 * @sbq_host_index: Sense buffer queuehost index 782 * @event_masks: Event mask bitmap 783 * @fwevt_worker_name: Firmware event worker thread name 784 * @fwevt_worker_thread: Firmware event worker thread 785 * @fwevt_lock: Firmware event lock 786 * @fwevt_list: Firmware event list 787 * @watchdog_work_q_name: Fault watchdog worker thread name 788 * @watchdog_work_q: Fault watchdog worker thread 789 * @watchdog_work: Fault watchdog work 790 * @watchdog_lock: Fault watchdog lock 791 * @is_driver_loading: Is driver still loading 792 * @scan_started: Async scan started 793 * @scan_failed: Asycn scan failed 794 * @stop_drv_processing: Stop all command processing 795 * @max_host_ios: Maximum host I/O count 796 * @chain_buf_count: Chain buffer count 797 * @chain_buf_pool: Chain buffer pool 798 * @chain_sgl_list: Chain SGL list 799 * @chain_bitmap_sz: Chain buffer allocator bitmap size 800 * @chain_bitmap: Chain buffer allocator bitmap 801 * @chain_buf_lock: Chain buffer list lock 802 * @bsg_cmds: Command tracker for BSG command 803 * @host_tm_cmds: Command tracker for task management commands 804 * @dev_rmhs_cmds: Command tracker for device removal commands 805 * @evtack_cmds: Command tracker for event ack commands 806 * @devrem_bitmap_sz: Device removal bitmap size 807 * @devrem_bitmap: Device removal bitmap 808 * @dev_handle_bitmap_sz: Device handle bitmap size 809 * @removepend_bitmap: Remove pending bitmap 810 * @delayed_rmhs_list: Delayed device removal list 811 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 812 * @evtack_cmds_bitmap: Event Ack bitmap 813 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 814 * @ts_update_counter: Timestamp update counter 815 * @reset_in_progress: Reset in progress flag 816 * @unrecoverable: Controller unrecoverable flag 817 * @prev_reset_result: Result of previous reset 818 * @reset_mutex: Controller reset mutex 819 * @reset_waitq: Controller reset wait queue 820 * @prepare_for_reset: Prepare for reset event received 821 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 822 * @prp_list_virt: NVMe encapsulated PRP list virtual base 823 * @prp_list_dma: NVMe encapsulated PRP list DMA 824 * @prp_sz: NVME encapsulated PRP list size 825 * @diagsave_timeout: Diagnostic information save timeout 826 * @logging_level: Controller debug logging level 827 * @flush_io_count: I/O count to flush after reset 828 * @current_event: Firmware event currently in process 829 * @driver_info: Driver, Kernel, OS information to firmware 830 * @change_count: Topology change count 831 * @pel_enabled: Persistent Event Log(PEL) enabled or not 832 * @pel_abort_requested: PEL abort is requested or not 833 * @pel_class: PEL Class identifier 834 * @pel_locale: PEL Locale identifier 835 * @pel_cmds: Command tracker for PEL wait command 836 * @pel_abort_cmd: Command tracker for PEL abort command 837 * @pel_newest_seqnum: Newest PEL sequenece number 838 * @pel_seqnum_virt: PEL sequence number virtual address 839 * @pel_seqnum_dma: PEL sequence number DMA address 840 * @pel_seqnum_sz: PEL sequenece number size 841 * @op_reply_q_offset: Operational reply queue offset with MSIx 842 * @default_qcount: Total Default queues 843 * @active_poll_qcount: Currently active poll queue count 844 * @requested_poll_qcount: User requested poll queue count 845 * @bsg_dev: BSG device structure 846 * @bsg_queue: Request queue for BSG device 847 * @stop_bsgs: Stop BSG request flag 848 * @logdata_buf: Circular buffer to store log data entries 849 * @logdata_buf_idx: Index of entry in buffer to store 850 * @logdata_entry_sz: log data entry size 851 * @pend_large_data_sz: Counter to track pending large data 852 * @io_throttle_data_length: I/O size to track in 512b blocks 853 * @io_throttle_high: I/O size to start throttle in 512b blocks 854 * @io_throttle_low: I/O size to stop throttle in 512b blocks 855 * @num_io_throttle_group: Maximum number of throttle groups 856 * @throttle_groups: Pointer to throttle group info structures 857 */ 858 struct mpi3mr_ioc { 859 struct list_head list; 860 struct pci_dev *pdev; 861 struct Scsi_Host *shost; 862 u8 id; 863 int cpu_count; 864 bool enable_segqueue; 865 u32 irqpoll_sleep; 866 867 char name[MPI3MR_NAME_LENGTH]; 868 char driver_name[MPI3MR_NAME_LENGTH]; 869 870 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 871 resource_size_t sysif_regs_phys; 872 int bars; 873 u64 dma_mask; 874 875 u16 msix_count; 876 u8 intr_enabled; 877 878 u16 num_admin_req; 879 u32 admin_req_q_sz; 880 u16 admin_req_pi; 881 u16 admin_req_ci; 882 void *admin_req_base; 883 dma_addr_t admin_req_dma; 884 spinlock_t admin_req_lock; 885 886 u16 num_admin_replies; 887 u32 admin_reply_q_sz; 888 u16 admin_reply_ci; 889 u8 admin_reply_ephase; 890 void *admin_reply_base; 891 dma_addr_t admin_reply_dma; 892 893 u32 ready_timeout; 894 895 struct mpi3mr_intr_info *intr_info; 896 u16 intr_info_count; 897 bool is_intr_info_set; 898 899 u16 num_queues; 900 u16 num_op_req_q; 901 struct op_req_qinfo *req_qinfo; 902 903 u16 num_op_reply_q; 904 struct op_reply_qinfo *op_reply_qinfo; 905 906 struct mpi3mr_drv_cmd init_cmds; 907 struct mpi3mr_ioc_facts facts; 908 u16 op_reply_desc_sz; 909 910 u32 num_reply_bufs; 911 struct dma_pool *reply_buf_pool; 912 u8 *reply_buf; 913 dma_addr_t reply_buf_dma; 914 dma_addr_t reply_buf_dma_max_address; 915 916 u16 reply_free_qsz; 917 u16 reply_sz; 918 struct dma_pool *reply_free_q_pool; 919 __le64 *reply_free_q; 920 dma_addr_t reply_free_q_dma; 921 spinlock_t reply_free_queue_lock; 922 u32 reply_free_queue_host_index; 923 924 u32 num_sense_bufs; 925 struct dma_pool *sense_buf_pool; 926 u8 *sense_buf; 927 dma_addr_t sense_buf_dma; 928 929 u16 sense_buf_q_sz; 930 struct dma_pool *sense_buf_q_pool; 931 __le64 *sense_buf_q; 932 dma_addr_t sense_buf_q_dma; 933 spinlock_t sbq_lock; 934 u32 sbq_host_index; 935 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 936 937 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 938 struct workqueue_struct *fwevt_worker_thread; 939 spinlock_t fwevt_lock; 940 struct list_head fwevt_list; 941 942 char watchdog_work_q_name[20]; 943 struct workqueue_struct *watchdog_work_q; 944 struct delayed_work watchdog_work; 945 spinlock_t watchdog_lock; 946 947 u8 is_driver_loading; 948 u8 scan_started; 949 u16 scan_failed; 950 u8 stop_drv_processing; 951 952 u16 max_host_ios; 953 spinlock_t tgtdev_lock; 954 struct list_head tgtdev_list; 955 956 u32 chain_buf_count; 957 struct dma_pool *chain_buf_pool; 958 struct chain_element *chain_sgl_list; 959 u16 chain_bitmap_sz; 960 void *chain_bitmap; 961 spinlock_t chain_buf_lock; 962 963 struct mpi3mr_drv_cmd bsg_cmds; 964 struct mpi3mr_drv_cmd host_tm_cmds; 965 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 966 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 967 u16 devrem_bitmap_sz; 968 void *devrem_bitmap; 969 u16 dev_handle_bitmap_sz; 970 void *removepend_bitmap; 971 struct list_head delayed_rmhs_list; 972 u16 evtack_cmds_bitmap_sz; 973 void *evtack_cmds_bitmap; 974 struct list_head delayed_evtack_cmds_list; 975 976 u32 ts_update_counter; 977 u8 reset_in_progress; 978 u8 unrecoverable; 979 int prev_reset_result; 980 struct mutex reset_mutex; 981 wait_queue_head_t reset_waitq; 982 983 u8 prepare_for_reset; 984 u16 prepare_for_reset_timeout_counter; 985 986 void *prp_list_virt; 987 dma_addr_t prp_list_dma; 988 u32 prp_sz; 989 990 u16 diagsave_timeout; 991 int logging_level; 992 u16 flush_io_count; 993 994 struct mpi3mr_fwevt *current_event; 995 struct mpi3_driver_info_layout driver_info; 996 u16 change_count; 997 998 u8 pel_enabled; 999 u8 pel_abort_requested; 1000 u8 pel_class; 1001 u16 pel_locale; 1002 struct mpi3mr_drv_cmd pel_cmds; 1003 struct mpi3mr_drv_cmd pel_abort_cmd; 1004 1005 u32 pel_newest_seqnum; 1006 void *pel_seqnum_virt; 1007 dma_addr_t pel_seqnum_dma; 1008 u32 pel_seqnum_sz; 1009 1010 u16 op_reply_q_offset; 1011 u16 default_qcount; 1012 u16 active_poll_qcount; 1013 u16 requested_poll_qcount; 1014 1015 struct device bsg_dev; 1016 struct request_queue *bsg_queue; 1017 u8 stop_bsgs; 1018 u8 *logdata_buf; 1019 u16 logdata_buf_idx; 1020 u16 logdata_entry_sz; 1021 1022 atomic_t pend_large_data_sz; 1023 u32 io_throttle_data_length; 1024 u32 io_throttle_high; 1025 u32 io_throttle_low; 1026 u16 num_io_throttle_group; 1027 struct mpi3mr_throttle_group_info *throttle_groups; 1028 }; 1029 1030 /** 1031 * struct mpi3mr_fwevt - Firmware event structure. 1032 * 1033 * @list: list head 1034 * @work: Work structure 1035 * @mrioc: Adapter instance reference 1036 * @event_id: MPI3 firmware event ID 1037 * @send_ack: Event acknowledgment required or not 1038 * @process_evt: Bottomhalf processing required or not 1039 * @evt_ctx: Event context to send in Ack 1040 * @event_data_size: size of the event data in bytes 1041 * @pending_at_sml: waiting for device add/remove API to complete 1042 * @discard: discard this event 1043 * @ref_count: kref count 1044 * @event_data: Actual MPI3 event data 1045 */ 1046 struct mpi3mr_fwevt { 1047 struct list_head list; 1048 struct work_struct work; 1049 struct mpi3mr_ioc *mrioc; 1050 u16 event_id; 1051 bool send_ack; 1052 bool process_evt; 1053 u32 evt_ctx; 1054 u16 event_data_size; 1055 bool pending_at_sml; 1056 bool discard; 1057 struct kref ref_count; 1058 char event_data[] __aligned(4); 1059 }; 1060 1061 1062 /** 1063 * struct delayed_dev_rmhs_node - Delayed device removal node 1064 * 1065 * @list: list head 1066 * @handle: Device handle 1067 * @iou_rc: IO Unit Control Reason Code 1068 */ 1069 struct delayed_dev_rmhs_node { 1070 struct list_head list; 1071 u16 handle; 1072 u8 iou_rc; 1073 }; 1074 1075 /** 1076 * struct delayed_evt_ack_node - Delayed event ack node 1077 * @list: list head 1078 * @event: MPI3 event ID 1079 * @event_ctx: event context 1080 */ 1081 struct delayed_evt_ack_node { 1082 struct list_head list; 1083 u8 event; 1084 u32 event_ctx; 1085 }; 1086 1087 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1088 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1089 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1090 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1091 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1092 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1093 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1094 u16 admin_req_sz, u8 ignore_reset); 1095 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1096 struct op_req_qinfo *opreqq, u8 *req); 1097 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1098 dma_addr_t dma_addr); 1099 void mpi3mr_build_zero_len_sge(void *paddr); 1100 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1101 dma_addr_t phys_addr); 1102 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1103 dma_addr_t phys_addr); 1104 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1105 u64 sense_buf_dma); 1106 1107 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1108 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1109 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1110 struct mpi3_event_notification_reply *event_reply); 1111 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1112 struct mpi3_default_reply_descriptor *reply_desc, 1113 u64 *reply_dma, u16 qidx); 1114 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1115 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1116 1117 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1118 u32 reset_reason, u8 snapdump); 1119 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1120 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1121 1122 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1123 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1124 u32 event_ctx); 1125 1126 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1127 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1128 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1129 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1130 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1131 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1132 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1133 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1134 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1135 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1136 struct op_reply_qinfo *op_reply_q); 1137 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1138 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1139 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1140 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1141 u16 handle, uint lun, u16 htag, ulong timeout, 1142 struct mpi3mr_drv_cmd *drv_cmd, 1143 u8 *resp_code, struct scsi_cmnd *scmd); 1144 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1145 struct mpi3mr_ioc *mrioc, u16 handle); 1146 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1147 struct mpi3mr_drv_cmd *drv_cmd); 1148 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1149 struct mpi3mr_drv_cmd *drv_cmd); 1150 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1151 u16 event_data_size); 1152 extern const struct attribute_group *mpi3mr_host_groups[]; 1153 extern const struct attribute_group *mpi3mr_dev_groups[]; 1154 #endif /*MPI3MR_H_INCLUDED*/ 1155