1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/workqueue.h> 33 #include <asm/unaligned.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_dbg.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 #include <scsi/scsi_tcq.h> 40 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 41 #include <scsi/scsi_transport_sas.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.4.1.0.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2023" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_DEFAULT_SGL_ENTRIES 256 74 #define MPI3MR_MAX_SGL_ENTRIES 2048 75 76 /* Definitions for MAX values for shost */ 77 #define MPI3MR_MAX_CMDS_LUN 128 78 #define MPI3MR_MAX_CDB_LENGTH 32 79 80 /* Admin queue management definitions */ 81 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 83 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 84 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 85 86 /* Operational queue management definitions */ 87 #define MPI3MR_OP_REQ_Q_QD 512 88 #define MPI3MR_OP_REP_Q_QD 1024 89 #define MPI3MR_OP_REP_Q_QD4K 4096 90 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 91 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 92 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 93 94 /* Reserved Host Tag definitions */ 95 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 96 #define MPI3MR_HOSTTAG_INITCMDS 1 97 #define MPI3MR_HOSTTAG_BSG_CMDS 2 98 #define MPI3MR_HOSTTAG_PEL_ABORT 3 99 #define MPI3MR_HOSTTAG_PEL_WAIT 4 100 #define MPI3MR_HOSTTAG_BLK_TMS 5 101 #define MPI3MR_HOSTTAG_CFG_CMDS 6 102 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 103 104 #define MPI3MR_NUM_DEVRMCMD 16 105 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 106 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 107 MPI3MR_NUM_DEVRMCMD - 1) 108 109 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 110 #define MPI3MR_NUM_EVTACKCMD 4 111 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 112 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 113 MPI3MR_NUM_EVTACKCMD - 1) 114 115 /* Reduced resource count definition for crash kernel */ 116 #define MPI3MR_HOST_IOS_KDUMP 128 117 118 /* command/controller interaction timeout definitions in seconds */ 119 #define MPI3MR_INTADMCMD_TIMEOUT 60 120 #define MPI3MR_PORTENABLE_TIMEOUT 300 121 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5 122 #define MPI3MR_ABORTTM_TIMEOUT 60 123 #define MPI3MR_RESETTM_TIMEOUT 60 124 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 125 #define MPI3MR_TSUPDATE_INTERVAL 900 126 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 127 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 128 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 129 #define MPI3MR_RESET_ACK_TIMEOUT 30 130 #define MPI3MR_MUR_TIMEOUT 120 131 132 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 133 134 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 135 136 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 137 138 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 139 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 140 141 /* Internal admin command state definitions*/ 142 #define MPI3MR_CMD_NOTUSED 0x8000 143 #define MPI3MR_CMD_COMPLETE 0x0001 144 #define MPI3MR_CMD_PENDING 0x0002 145 #define MPI3MR_CMD_REPLY_VALID 0x0004 146 #define MPI3MR_CMD_RESET 0x0008 147 148 /* Definitions for Event replies and sense buffer allocated per controller */ 149 #define MPI3MR_NUM_EVT_REPLIES 64 150 #define MPI3MR_SENSE_BUF_SZ 256 151 #define MPI3MR_SENSEBUF_FACTOR 3 152 #define MPI3MR_CHAINBUF_FACTOR 3 153 #define MPI3MR_CHAINBUFDIX_FACTOR 2 154 155 /* Invalid target device handle */ 156 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 157 158 /* Controller Reset related definitions */ 159 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 160 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 161 162 /* ResponseCode definitions */ 163 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 164 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 165 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 166 167 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 168 #define MPI3MR_DEFAULT_PGSZEXP (12) 169 170 /* Command retry count definitions */ 171 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 172 #define MPI3MR_PEL_RETRY_COUNT 3 173 174 /* Default target device queue depth */ 175 #define MPI3MR_DEFAULT_SDEV_QD 32 176 177 /* Definitions for Threaded IRQ poll*/ 178 #define MPI3MR_IRQ_POLL_SLEEP 2 179 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 180 181 /* Definitions for the controller security status*/ 182 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 183 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 184 185 #define MPI3MR_INVALID_DEVICE 0x00 186 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 187 #define MPI3MR_HARD_SECURE_DEVICE 0x08 188 #define MPI3MR_TAMPERED_DEVICE 0x0C 189 190 /* SGE Flag definition */ 191 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 192 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 193 MPI3_SGE_FLAGS_END_OF_LIST) 194 195 /* MSI Index from Reply Queue Index */ 196 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 197 198 /* 199 * Maximum data transfer size definitions for management 200 * application commands 201 */ 202 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 203 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 204 /* 205 * 2048 sectors are for data buffers and additional 512 sectors for 206 * other buffers 207 */ 208 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 209 210 /** 211 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 212 * Encapsulated commands. 213 * 214 * @base_addr: Physical address 215 * @length: SGE length 216 * @rsvd: Reserved 217 * @rsvd1: Reserved 218 * @sgl_type: sgl type 219 */ 220 struct mpi3mr_nvme_pt_sge { 221 u64 base_addr; 222 u32 length; 223 u16 rsvd; 224 u8 rsvd1; 225 u8 sgl_type; 226 }; 227 228 /** 229 * struct mpi3mr_buf_map - local structure to 230 * track kernel and user buffers associated with an BSG 231 * structure. 232 * 233 * @bsg_buf: BSG buffer virtual address 234 * @bsg_buf_len: BSG buffer length 235 * @kern_buf: Kernel buffer virtual address 236 * @kern_buf_len: Kernel buffer length 237 * @kern_buf_dma: Kernel buffer DMA address 238 * @data_dir: Data direction. 239 */ 240 struct mpi3mr_buf_map { 241 void *bsg_buf; 242 u32 bsg_buf_len; 243 void *kern_buf; 244 u32 kern_buf_len; 245 dma_addr_t kern_buf_dma; 246 u8 data_dir; 247 }; 248 249 /* IOC State definitions */ 250 enum mpi3mr_iocstate { 251 MRIOC_STATE_READY = 1, 252 MRIOC_STATE_RESET, 253 MRIOC_STATE_FAULT, 254 MRIOC_STATE_BECOMING_READY, 255 MRIOC_STATE_RESET_REQUESTED, 256 MRIOC_STATE_UNRECOVERABLE, 257 }; 258 259 /* Reset reason code definitions*/ 260 enum mpi3mr_reset_reason { 261 MPI3MR_RESET_FROM_BRINGUP = 1, 262 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 263 MPI3MR_RESET_FROM_APP = 3, 264 MPI3MR_RESET_FROM_EH_HOS = 4, 265 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 266 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 267 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 268 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 269 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 270 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 271 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 272 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 273 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 274 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 275 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 276 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 277 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 278 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 279 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 280 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 281 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 282 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 283 MPI3MR_RESET_FROM_SYSFS = 23, 284 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 285 MPI3MR_RESET_FROM_FIRMWARE = 27, 286 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 287 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 288 }; 289 290 /* Queue type definitions */ 291 enum queue_type { 292 MPI3MR_DEFAULT_QUEUE = 0, 293 MPI3MR_POLL_QUEUE, 294 }; 295 296 /** 297 * struct mpi3mr_compimg_ver - replica of component image 298 * version defined in mpi30_image.h in host endianness 299 * 300 */ 301 struct mpi3mr_compimg_ver { 302 u16 build_num; 303 u16 cust_id; 304 u8 ph_minor; 305 u8 ph_major; 306 u8 gen_minor; 307 u8 gen_major; 308 }; 309 310 /** 311 * struct mpi3mr_ioc_facs - replica of component image version 312 * defined in mpi30_ioc.h in host endianness 313 * 314 */ 315 struct mpi3mr_ioc_facts { 316 u32 ioc_capabilities; 317 struct mpi3mr_compimg_ver fw_ver; 318 u32 mpi_version; 319 u16 max_reqs; 320 u16 product_id; 321 u16 op_req_sz; 322 u16 reply_sz; 323 u16 exceptions; 324 u16 max_perids; 325 u16 max_pds; 326 u16 max_sasexpanders; 327 u32 max_data_length; 328 u16 max_sasinitiators; 329 u16 max_enclosures; 330 u16 max_pcie_switches; 331 u16 max_nvme; 332 u16 max_vds; 333 u16 max_hpds; 334 u16 max_advhpds; 335 u16 max_raid_pds; 336 u16 min_devhandle; 337 u16 max_devhandle; 338 u16 max_op_req_q; 339 u16 max_op_reply_q; 340 u16 shutdown_timeout; 341 u8 ioc_num; 342 u8 who_init; 343 u16 max_msix_vectors; 344 u8 personality; 345 u8 dma_mask; 346 u8 protocol_flags; 347 u8 sge_mod_mask; 348 u8 sge_mod_value; 349 u8 sge_mod_shift; 350 u8 max_dev_per_tg; 351 u16 max_io_throttle_group; 352 u16 io_throttle_data_length; 353 u16 io_throttle_low; 354 u16 io_throttle_high; 355 356 }; 357 358 /** 359 * struct segments - memory descriptor structure to store 360 * virtual and dma addresses for operational queue segments. 361 * 362 * @segment: virtual address 363 * @segment_dma: dma address 364 */ 365 struct segments { 366 void *segment; 367 dma_addr_t segment_dma; 368 }; 369 370 /** 371 * struct op_req_qinfo - Operational Request Queue Information 372 * 373 * @ci: consumer index 374 * @pi: producer index 375 * @num_request: Maximum number of entries in the queue 376 * @qid: Queue Id starting from 1 377 * @reply_qid: Associated reply queue Id 378 * @num_segments: Number of discontiguous memory segments 379 * @segment_qd: Depth of each segments 380 * @q_lock: Concurrent queue access lock 381 * @q_segments: Segment descriptor pointer 382 * @q_segment_list: Segment list base virtual address 383 * @q_segment_list_dma: Segment list base DMA address 384 */ 385 struct op_req_qinfo { 386 u16 ci; 387 u16 pi; 388 u16 num_requests; 389 u16 qid; 390 u16 reply_qid; 391 u16 num_segments; 392 u16 segment_qd; 393 spinlock_t q_lock; 394 struct segments *q_segments; 395 void *q_segment_list; 396 dma_addr_t q_segment_list_dma; 397 }; 398 399 /** 400 * struct op_reply_qinfo - Operational Reply Queue Information 401 * 402 * @ci: consumer index 403 * @qid: Queue Id starting from 1 404 * @num_replies: Maximum number of entries in the queue 405 * @num_segments: Number of discontiguous memory segments 406 * @segment_qd: Depth of each segments 407 * @q_segments: Segment descriptor pointer 408 * @q_segment_list: Segment list base virtual address 409 * @q_segment_list_dma: Segment list base DMA address 410 * @ephase: Expected phased identifier for the reply queue 411 * @pend_ios: Number of IOs pending in HW for this queue 412 * @enable_irq_poll: Flag to indicate polling is enabled 413 * @in_use: Queue is handled by poll/ISR 414 * @qtype: Type of queue (types defined in enum queue_type) 415 */ 416 struct op_reply_qinfo { 417 u16 ci; 418 u16 qid; 419 u16 num_replies; 420 u16 num_segments; 421 u16 segment_qd; 422 struct segments *q_segments; 423 void *q_segment_list; 424 dma_addr_t q_segment_list_dma; 425 u8 ephase; 426 atomic_t pend_ios; 427 bool enable_irq_poll; 428 atomic_t in_use; 429 enum queue_type qtype; 430 }; 431 432 /** 433 * struct mpi3mr_intr_info - Interrupt cookie information 434 * 435 * @mrioc: Adapter instance reference 436 * @os_irq: irq number 437 * @msix_index: MSIx index 438 * @op_reply_q: Associated operational reply queue 439 * @name: Dev name for the irq claiming device 440 */ 441 struct mpi3mr_intr_info { 442 struct mpi3mr_ioc *mrioc; 443 int os_irq; 444 u16 msix_index; 445 struct op_reply_qinfo *op_reply_q; 446 char name[MPI3MR_NAME_LENGTH]; 447 }; 448 449 /** 450 * struct mpi3mr_throttle_group_info - Throttle group info 451 * 452 * @io_divert: Flag indicates io divert is on or off for the TG 453 * @need_qd_reduction: Flag to indicate QD reduction is needed 454 * @qd_reduction: Queue Depth reduction in units of 10% 455 * @fw_qd: QueueDepth value reported by the firmware 456 * @modified_qd: Modified QueueDepth value due to throttling 457 * @id: Throttle Group ID. 458 * @high: High limit to turn on throttling in 512 byte blocks 459 * @low: Low limit to turn off throttling in 512 byte blocks 460 * @pend_large_data_sz: Counter to track pending large data 461 */ 462 struct mpi3mr_throttle_group_info { 463 u8 io_divert; 464 u8 need_qd_reduction; 465 u8 qd_reduction; 466 u16 fw_qd; 467 u16 modified_qd; 468 u16 id; 469 u32 high; 470 u32 low; 471 atomic_t pend_large_data_sz; 472 }; 473 474 /* HBA port flags */ 475 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 476 477 /** 478 * struct mpi3mr_hba_port - HBA's port information 479 * @port_id: Port number 480 * @flags: HBA port flags 481 */ 482 struct mpi3mr_hba_port { 483 struct list_head list; 484 u8 port_id; 485 u8 flags; 486 }; 487 488 /** 489 * struct mpi3mr_sas_port - Internal SAS port information 490 * @port_list: List of ports belonging to a SAS node 491 * @num_phys: Number of phys associated with port 492 * @marked_responding: used while refresing the sas ports 493 * @lowest_phy: lowest phy ID of current sas port 494 * @phy_mask: phy_mask of current sas port 495 * @hba_port: HBA port entry 496 * @remote_identify: Attached device identification 497 * @rphy: SAS transport layer rphy object 498 * @port: SAS transport layer port object 499 * @phy_list: mpi3mr_sas_phy objects belonging to this port 500 */ 501 struct mpi3mr_sas_port { 502 struct list_head port_list; 503 u8 num_phys; 504 u8 marked_responding; 505 int lowest_phy; 506 u32 phy_mask; 507 struct mpi3mr_hba_port *hba_port; 508 struct sas_identify remote_identify; 509 struct sas_rphy *rphy; 510 struct sas_port *port; 511 struct list_head phy_list; 512 }; 513 514 /** 515 * struct mpi3mr_sas_phy - Internal SAS Phy information 516 * @port_siblings: List of phys belonging to a port 517 * @identify: Phy identification 518 * @remote_identify: Attached device identification 519 * @phy: SAS transport layer Phy object 520 * @phy_id: Unique phy id within a port 521 * @handle: Firmware device handle for this phy 522 * @attached_handle: Firmware device handle for attached device 523 * @phy_belongs_to_port: Flag to indicate phy belongs to port 524 @hba_port: HBA port entry 525 */ 526 struct mpi3mr_sas_phy { 527 struct list_head port_siblings; 528 struct sas_identify identify; 529 struct sas_identify remote_identify; 530 struct sas_phy *phy; 531 u8 phy_id; 532 u16 handle; 533 u16 attached_handle; 534 u8 phy_belongs_to_port; 535 struct mpi3mr_hba_port *hba_port; 536 }; 537 538 /** 539 * struct mpi3mr_sas_node - SAS host/expander information 540 * @list: List of sas nodes in a controller 541 * @parent_dev: Parent device class 542 * @num_phys: Number phys belonging to sas_node 543 * @sas_address: SAS address of sas_node 544 * @handle: Firmware device handle for this sas_host/expander 545 * @sas_address_parent: SAS address of parent expander or host 546 * @enclosure_handle: Firmware handle of enclosure of this node 547 * @device_info: Capabilities of this sas_host/expander 548 * @non_responding: used to refresh the expander devices during reset 549 * @host_node: Flag to indicate this is a host_node 550 * @hba_port: HBA port entry 551 * @phy: A list of phys that make up this sas_host/expander 552 * @sas_port_list: List of internal ports of this node 553 * @rphy: sas_rphy object of this expander node 554 */ 555 struct mpi3mr_sas_node { 556 struct list_head list; 557 struct device *parent_dev; 558 u8 num_phys; 559 u64 sas_address; 560 u16 handle; 561 u64 sas_address_parent; 562 u16 enclosure_handle; 563 u64 enclosure_logical_id; 564 u8 non_responding; 565 u8 host_node; 566 struct mpi3mr_hba_port *hba_port; 567 struct mpi3mr_sas_phy *phy; 568 struct list_head sas_port_list; 569 struct sas_rphy *rphy; 570 }; 571 572 /** 573 * struct mpi3mr_enclosure_node - enclosure information 574 * @list: List of enclosures 575 * @pg0: Enclosure page 0; 576 */ 577 struct mpi3mr_enclosure_node { 578 struct list_head list; 579 struct mpi3_enclosure_page0 pg0; 580 }; 581 582 /** 583 * struct tgt_dev_sas_sata - SAS/SATA device specific 584 * information cached from firmware given data 585 * 586 * @sas_address: World wide unique SAS address 587 * @sas_address_parent: Sas address of parent expander or host 588 * @dev_info: Device information bits 589 * @phy_id: Phy identifier provided in device page 0 590 * @attached_phy_id: Attached phy identifier provided in device page 0 591 * @sas_transport_attached: Is this device exposed to transport 592 * @pend_sas_rphy_add: Flag to check device is in process of add 593 * @hba_port: HBA port entry 594 * @rphy: SAS transport layer rphy object 595 */ 596 struct tgt_dev_sas_sata { 597 u64 sas_address; 598 u64 sas_address_parent; 599 u16 dev_info; 600 u8 phy_id; 601 u8 attached_phy_id; 602 u8 sas_transport_attached; 603 u8 pend_sas_rphy_add; 604 struct mpi3mr_hba_port *hba_port; 605 struct sas_rphy *rphy; 606 }; 607 608 /** 609 * struct tgt_dev_pcie - PCIe device specific information cached 610 * from firmware given data 611 * 612 * @mdts: Maximum data transfer size 613 * @capb: Device capabilities 614 * @pgsz: Device page size 615 * @abort_to: Timeout for abort TM 616 * @reset_to: Timeout for Target/LUN reset TM 617 * @dev_info: Device information bits 618 */ 619 struct tgt_dev_pcie { 620 u32 mdts; 621 u16 capb; 622 u8 pgsz; 623 u8 abort_to; 624 u8 reset_to; 625 u16 dev_info; 626 }; 627 628 /** 629 * struct tgt_dev_vd - virtual device specific information 630 * cached from firmware given data 631 * 632 * @state: State of the VD 633 * @tg_qd_reduction: Queue Depth reduction in units of 10% 634 * @tg_id: VDs throttle group ID 635 * @high: High limit to turn on throttling in 512 byte blocks 636 * @low: Low limit to turn off throttling in 512 byte blocks 637 * @tg: Pointer to throttle group info 638 */ 639 struct tgt_dev_vd { 640 u8 state; 641 u8 tg_qd_reduction; 642 u16 tg_id; 643 u32 tg_high; 644 u32 tg_low; 645 struct mpi3mr_throttle_group_info *tg; 646 }; 647 648 649 /** 650 * union _form_spec_inf - union of device specific information 651 */ 652 union _form_spec_inf { 653 struct tgt_dev_sas_sata sas_sata_inf; 654 struct tgt_dev_pcie pcie_inf; 655 struct tgt_dev_vd vd_inf; 656 }; 657 658 enum mpi3mr_dev_state { 659 MPI3MR_DEV_CREATED = 1, 660 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 661 MPI3MR_DEV_DELETED = 3, 662 }; 663 664 /** 665 * struct mpi3mr_tgt_dev - target device data structure 666 * 667 * @list: List pointer 668 * @starget: Scsi_target pointer 669 * @dev_handle: FW device handle 670 * @parent_handle: FW parent device handle 671 * @slot: Slot number 672 * @encl_handle: FW enclosure handle 673 * @perst_id: FW assigned Persistent ID 674 * @devpg0_flag: Device Page0 flag 675 * @dev_type: SAS/SATA/PCIE device type 676 * @is_hidden: Should be exposed to upper layers or not 677 * @host_exposed: Already exposed to host or not 678 * @io_unit_port: IO Unit port ID 679 * @non_stl: Is this device not to be attached with SAS TL 680 * @io_throttle_enabled: I/O throttling needed or not 681 * @q_depth: Device specific Queue Depth 682 * @wwid: World wide ID 683 * @enclosure_logical_id: Enclosure logical identifier 684 * @dev_spec: Device type specific information 685 * @ref_count: Reference count 686 * @state: device state 687 */ 688 struct mpi3mr_tgt_dev { 689 struct list_head list; 690 struct scsi_target *starget; 691 u16 dev_handle; 692 u16 parent_handle; 693 u16 slot; 694 u16 encl_handle; 695 u16 perst_id; 696 u16 devpg0_flag; 697 u8 dev_type; 698 u8 is_hidden; 699 u8 host_exposed; 700 u8 io_unit_port; 701 u8 non_stl; 702 u8 io_throttle_enabled; 703 u16 q_depth; 704 u64 wwid; 705 u64 enclosure_logical_id; 706 union _form_spec_inf dev_spec; 707 struct kref ref_count; 708 enum mpi3mr_dev_state state; 709 }; 710 711 /** 712 * mpi3mr_tgtdev_get - k reference incrementor 713 * @s: Target device reference 714 * 715 * Increment target device reference count. 716 */ 717 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 718 { 719 kref_get(&s->ref_count); 720 } 721 722 /** 723 * mpi3mr_free_tgtdev - target device memory dealloctor 724 * @r: k reference pointer of the target device 725 * 726 * Free target device memory when no reference. 727 */ 728 static inline void mpi3mr_free_tgtdev(struct kref *r) 729 { 730 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 731 } 732 733 /** 734 * mpi3mr_tgtdev_put - k reference decrementor 735 * @s: Target device reference 736 * 737 * Decrement target device reference count. 738 */ 739 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 740 { 741 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 742 } 743 744 745 /** 746 * struct mpi3mr_stgt_priv_data - SCSI target private structure 747 * 748 * @starget: Scsi_target pointer 749 * @dev_handle: FW device handle 750 * @perst_id: FW assigned Persistent ID 751 * @num_luns: Number of Logical Units 752 * @block_io: I/O blocked to the device or not 753 * @dev_removed: Device removed in the Firmware 754 * @dev_removedelay: Device is waiting to be removed in FW 755 * @dev_type: Device type 756 * @io_throttle_enabled: I/O throttling needed or not 757 * @io_divert: Flag indicates io divert is on or off for the dev 758 * @throttle_group: Pointer to throttle group info 759 * @tgt_dev: Internal target device pointer 760 * @pend_count: Counter to track pending I/Os during error 761 * handling 762 */ 763 struct mpi3mr_stgt_priv_data { 764 struct scsi_target *starget; 765 u16 dev_handle; 766 u16 perst_id; 767 u32 num_luns; 768 atomic_t block_io; 769 u8 dev_removed; 770 u8 dev_removedelay; 771 u8 dev_type; 772 u8 io_throttle_enabled; 773 u8 io_divert; 774 struct mpi3mr_throttle_group_info *throttle_group; 775 struct mpi3mr_tgt_dev *tgt_dev; 776 u32 pend_count; 777 }; 778 779 /** 780 * struct mpi3mr_stgt_priv_data - SCSI device private structure 781 * 782 * @tgt_priv_data: Scsi_target private data pointer 783 * @lun_id: LUN ID of the device 784 * @ncq_prio_enable: NCQ priority enable for SATA device 785 * @pend_count: Counter to track pending I/Os during error 786 * handling 787 */ 788 struct mpi3mr_sdev_priv_data { 789 struct mpi3mr_stgt_priv_data *tgt_priv_data; 790 u32 lun_id; 791 u8 ncq_prio_enable; 792 u32 pend_count; 793 }; 794 795 /** 796 * struct mpi3mr_drv_cmd - Internal command tracker 797 * 798 * @mutex: Command mutex 799 * @done: Completeor for wakeup 800 * @reply: Firmware reply for internal commands 801 * @sensebuf: Sensebuf for SCSI IO commands 802 * @iou_rc: IO Unit control reason code 803 * @state: Command State 804 * @dev_handle: Firmware handle for device specific commands 805 * @ioc_status: IOC status from the firmware 806 * @ioc_loginfo:IOC log info from the firmware 807 * @is_waiting: Is the command issued in block mode 808 * @is_sense: Is Sense data present 809 * @retry_count: Retry count for retriable commands 810 * @host_tag: Host tag used by the command 811 * @callback: Callback for non blocking commands 812 */ 813 struct mpi3mr_drv_cmd { 814 struct mutex mutex; 815 struct completion done; 816 void *reply; 817 u8 *sensebuf; 818 u8 iou_rc; 819 u16 state; 820 u16 dev_handle; 821 u16 ioc_status; 822 u32 ioc_loginfo; 823 u8 is_waiting; 824 u8 is_sense; 825 u8 retry_count; 826 u16 host_tag; 827 828 void (*callback)(struct mpi3mr_ioc *mrioc, 829 struct mpi3mr_drv_cmd *drv_cmd); 830 }; 831 832 /** 833 * struct dma_memory_desc - memory descriptor structure to store 834 * virtual address, dma address and size for any generic dma 835 * memory allocations in the driver. 836 * 837 * @size: buffer size 838 * @addr: virtual address 839 * @dma_addr: dma address 840 */ 841 struct dma_memory_desc { 842 u32 size; 843 void *addr; 844 dma_addr_t dma_addr; 845 }; 846 847 848 /** 849 * struct chain_element - memory descriptor structure to store 850 * virtual and dma addresses for chain elements. 851 * 852 * @addr: virtual address 853 * @dma_addr: dma address 854 */ 855 struct chain_element { 856 void *addr; 857 dma_addr_t dma_addr; 858 }; 859 860 /** 861 * struct scmd_priv - SCSI command private data 862 * 863 * @host_tag: Host tag specific to operational queue 864 * @in_lld_scope: Command in LLD scope or not 865 * @meta_sg_valid: DIX command with meta data SGL or not 866 * @scmd: SCSI Command pointer 867 * @req_q_idx: Operational request queue index 868 * @chain_idx: Chain frame index 869 * @meta_chain_idx: Chain frame index of meta data SGL 870 * @mpi3mr_scsiio_req: MPI SCSI IO request 871 */ 872 struct scmd_priv { 873 u16 host_tag; 874 u8 in_lld_scope; 875 u8 meta_sg_valid; 876 struct scsi_cmnd *scmd; 877 u16 req_q_idx; 878 int chain_idx; 879 int meta_chain_idx; 880 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 881 }; 882 883 /** 884 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 885 * private data 886 * 887 * @list: List pointer 888 * @pdev: PCI device pointer 889 * @shost: Scsi_Host pointer 890 * @id: Controller ID 891 * @cpu_count: Number of online CPUs 892 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 893 * @name: Controller ASCII name 894 * @driver_name: Driver ASCII name 895 * @sysif_regs: System interface registers virtual address 896 * @sysif_regs_phys: System interface registers physical address 897 * @bars: PCI BARS 898 * @dma_mask: DMA mask 899 * @msix_count: Number of MSIX vectors used 900 * @intr_enabled: Is interrupts enabled 901 * @num_admin_req: Number of admin requests 902 * @admin_req_q_sz: Admin request queue size 903 * @admin_req_pi: Admin request queue producer index 904 * @admin_req_ci: Admin request queue consumer index 905 * @admin_req_base: Admin request queue base virtual address 906 * @admin_req_dma: Admin request queue base dma address 907 * @admin_req_lock: Admin queue access lock 908 * @num_admin_replies: Number of admin replies 909 * @admin_reply_q_sz: Admin reply queue size 910 * @admin_reply_ci: Admin reply queue consumer index 911 * @admin_reply_ephase:Admin reply queue expected phase 912 * @admin_reply_base: Admin reply queue base virtual address 913 * @admin_reply_dma: Admin reply queue base dma address 914 * @admin_reply_q_in_use: Queue is handled by poll/ISR 915 * @ready_timeout: Controller ready timeout 916 * @intr_info: Interrupt cookie pointer 917 * @intr_info_count: Number of interrupt cookies 918 * @is_intr_info_set: Flag to indicate intr info is setup 919 * @num_queues: Number of operational queues 920 * @num_op_req_q: Number of operational request queues 921 * @req_qinfo: Operational request queue info pointer 922 * @num_op_reply_q: Number of operational reply queues 923 * @op_reply_qinfo: Operational reply queue info pointer 924 * @init_cmds: Command tracker for initialization commands 925 * @cfg_cmds: Command tracker for configuration requests 926 * @facts: Cached IOC facts data 927 * @op_reply_desc_sz: Operational reply descriptor size 928 * @num_reply_bufs: Number of reply buffers allocated 929 * @reply_buf_pool: Reply buffer pool 930 * @reply_buf: Reply buffer base virtual address 931 * @reply_buf_dma: Reply buffer DMA address 932 * @reply_buf_dma_max_address: Reply DMA address max limit 933 * @reply_free_qsz: Reply free queue size 934 * @reply_free_q_pool: Reply free queue pool 935 * @reply_free_q: Reply free queue base virtual address 936 * @reply_free_q_dma: Reply free queue base DMA address 937 * @reply_free_queue_lock: Reply free queue lock 938 * @reply_free_queue_host_index: Reply free queue host index 939 * @num_sense_bufs: Number of sense buffers 940 * @sense_buf_pool: Sense buffer pool 941 * @sense_buf: Sense buffer base virtual address 942 * @sense_buf_dma: Sense buffer base DMA address 943 * @sense_buf_q_sz: Sense buffer queue size 944 * @sense_buf_q_pool: Sense buffer queue pool 945 * @sense_buf_q: Sense buffer queue virtual address 946 * @sense_buf_q_dma: Sense buffer queue DMA address 947 * @sbq_lock: Sense buffer queue lock 948 * @sbq_host_index: Sense buffer queuehost index 949 * @event_masks: Event mask bitmap 950 * @fwevt_worker_name: Firmware event worker thread name 951 * @fwevt_worker_thread: Firmware event worker thread 952 * @fwevt_lock: Firmware event lock 953 * @fwevt_list: Firmware event list 954 * @watchdog_work_q_name: Fault watchdog worker thread name 955 * @watchdog_work_q: Fault watchdog worker thread 956 * @watchdog_work: Fault watchdog work 957 * @watchdog_lock: Fault watchdog lock 958 * @is_driver_loading: Is driver still loading 959 * @scan_started: Async scan started 960 * @scan_failed: Asycn scan failed 961 * @stop_drv_processing: Stop all command processing 962 * @device_refresh_on: Don't process the events until devices are refreshed 963 * @max_host_ios: Maximum host I/O count 964 * @max_sgl_entries: Max SGL entries per I/O 965 * @chain_buf_count: Chain buffer count 966 * @chain_buf_pool: Chain buffer pool 967 * @chain_sgl_list: Chain SGL list 968 * @chain_bitmap: Chain buffer allocator bitmap 969 * @chain_buf_lock: Chain buffer list lock 970 * @bsg_cmds: Command tracker for BSG command 971 * @host_tm_cmds: Command tracker for task management commands 972 * @dev_rmhs_cmds: Command tracker for device removal commands 973 * @evtack_cmds: Command tracker for event ack commands 974 * @devrem_bitmap: Device removal bitmap 975 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 976 * @removepend_bitmap: Remove pending bitmap 977 * @delayed_rmhs_list: Delayed device removal list 978 * @evtack_cmds_bitmap: Event Ack bitmap 979 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 980 * @ts_update_counter: Timestamp update counter 981 * @reset_in_progress: Reset in progress flag 982 * @unrecoverable: Controller unrecoverable flag 983 * @prev_reset_result: Result of previous reset 984 * @reset_mutex: Controller reset mutex 985 * @reset_waitq: Controller reset wait queue 986 * @prepare_for_reset: Prepare for reset event received 987 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 988 * @prp_list_virt: NVMe encapsulated PRP list virtual base 989 * @prp_list_dma: NVMe encapsulated PRP list DMA 990 * @prp_sz: NVME encapsulated PRP list size 991 * @diagsave_timeout: Diagnostic information save timeout 992 * @logging_level: Controller debug logging level 993 * @flush_io_count: I/O count to flush after reset 994 * @current_event: Firmware event currently in process 995 * @driver_info: Driver, Kernel, OS information to firmware 996 * @change_count: Topology change count 997 * @pel_enabled: Persistent Event Log(PEL) enabled or not 998 * @pel_abort_requested: PEL abort is requested or not 999 * @pel_class: PEL Class identifier 1000 * @pel_locale: PEL Locale identifier 1001 * @pel_cmds: Command tracker for PEL wait command 1002 * @pel_abort_cmd: Command tracker for PEL abort command 1003 * @pel_newest_seqnum: Newest PEL sequenece number 1004 * @pel_seqnum_virt: PEL sequence number virtual address 1005 * @pel_seqnum_dma: PEL sequence number DMA address 1006 * @pel_seqnum_sz: PEL sequenece number size 1007 * @op_reply_q_offset: Operational reply queue offset with MSIx 1008 * @default_qcount: Total Default queues 1009 * @active_poll_qcount: Currently active poll queue count 1010 * @requested_poll_qcount: User requested poll queue count 1011 * @bsg_dev: BSG device structure 1012 * @bsg_queue: Request queue for BSG device 1013 * @stop_bsgs: Stop BSG request flag 1014 * @logdata_buf: Circular buffer to store log data entries 1015 * @logdata_buf_idx: Index of entry in buffer to store 1016 * @logdata_entry_sz: log data entry size 1017 * @pend_large_data_sz: Counter to track pending large data 1018 * @io_throttle_data_length: I/O size to track in 512b blocks 1019 * @io_throttle_high: I/O size to start throttle in 512b blocks 1020 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1021 * @num_io_throttle_group: Maximum number of throttle groups 1022 * @throttle_groups: Pointer to throttle group info structures 1023 * @cfg_page: Default memory for configuration pages 1024 * @cfg_page_dma: Configuration page DMA address 1025 * @cfg_page_sz: Default configuration page memory size 1026 * @sas_transport_enabled: SAS transport enabled or not 1027 * @scsi_device_channel: Channel ID for SCSI devices 1028 * @transport_cmds: Command tracker for SAS transport commands 1029 * @sas_hba: SAS node for the controller 1030 * @sas_expander_list: SAS node list of expanders 1031 * @sas_node_lock: Lock to protect SAS node list 1032 * @hba_port_table_list: List of HBA Ports 1033 * @enclosure_list: List of Enclosure objects 1034 */ 1035 struct mpi3mr_ioc { 1036 struct list_head list; 1037 struct pci_dev *pdev; 1038 struct Scsi_Host *shost; 1039 u8 id; 1040 int cpu_count; 1041 bool enable_segqueue; 1042 u32 irqpoll_sleep; 1043 1044 char name[MPI3MR_NAME_LENGTH]; 1045 char driver_name[MPI3MR_NAME_LENGTH]; 1046 1047 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1048 resource_size_t sysif_regs_phys; 1049 int bars; 1050 u64 dma_mask; 1051 1052 u16 msix_count; 1053 u8 intr_enabled; 1054 1055 u16 num_admin_req; 1056 u32 admin_req_q_sz; 1057 u16 admin_req_pi; 1058 u16 admin_req_ci; 1059 void *admin_req_base; 1060 dma_addr_t admin_req_dma; 1061 spinlock_t admin_req_lock; 1062 1063 u16 num_admin_replies; 1064 u32 admin_reply_q_sz; 1065 u16 admin_reply_ci; 1066 u8 admin_reply_ephase; 1067 void *admin_reply_base; 1068 dma_addr_t admin_reply_dma; 1069 atomic_t admin_reply_q_in_use; 1070 1071 u32 ready_timeout; 1072 1073 struct mpi3mr_intr_info *intr_info; 1074 u16 intr_info_count; 1075 bool is_intr_info_set; 1076 1077 u16 num_queues; 1078 u16 num_op_req_q; 1079 struct op_req_qinfo *req_qinfo; 1080 1081 u16 num_op_reply_q; 1082 struct op_reply_qinfo *op_reply_qinfo; 1083 1084 struct mpi3mr_drv_cmd init_cmds; 1085 struct mpi3mr_drv_cmd cfg_cmds; 1086 struct mpi3mr_ioc_facts facts; 1087 u16 op_reply_desc_sz; 1088 1089 u32 num_reply_bufs; 1090 struct dma_pool *reply_buf_pool; 1091 u8 *reply_buf; 1092 dma_addr_t reply_buf_dma; 1093 dma_addr_t reply_buf_dma_max_address; 1094 1095 u16 reply_free_qsz; 1096 u16 reply_sz; 1097 struct dma_pool *reply_free_q_pool; 1098 __le64 *reply_free_q; 1099 dma_addr_t reply_free_q_dma; 1100 spinlock_t reply_free_queue_lock; 1101 u32 reply_free_queue_host_index; 1102 1103 u32 num_sense_bufs; 1104 struct dma_pool *sense_buf_pool; 1105 u8 *sense_buf; 1106 dma_addr_t sense_buf_dma; 1107 1108 u16 sense_buf_q_sz; 1109 struct dma_pool *sense_buf_q_pool; 1110 __le64 *sense_buf_q; 1111 dma_addr_t sense_buf_q_dma; 1112 spinlock_t sbq_lock; 1113 u32 sbq_host_index; 1114 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1115 1116 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 1117 struct workqueue_struct *fwevt_worker_thread; 1118 spinlock_t fwevt_lock; 1119 struct list_head fwevt_list; 1120 1121 char watchdog_work_q_name[20]; 1122 struct workqueue_struct *watchdog_work_q; 1123 struct delayed_work watchdog_work; 1124 spinlock_t watchdog_lock; 1125 1126 u8 is_driver_loading; 1127 u8 scan_started; 1128 u16 scan_failed; 1129 u8 stop_drv_processing; 1130 u8 device_refresh_on; 1131 1132 u16 max_host_ios; 1133 spinlock_t tgtdev_lock; 1134 struct list_head tgtdev_list; 1135 u16 max_sgl_entries; 1136 1137 u32 chain_buf_count; 1138 struct dma_pool *chain_buf_pool; 1139 struct chain_element *chain_sgl_list; 1140 unsigned long *chain_bitmap; 1141 spinlock_t chain_buf_lock; 1142 1143 struct mpi3mr_drv_cmd bsg_cmds; 1144 struct mpi3mr_drv_cmd host_tm_cmds; 1145 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1146 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1147 unsigned long *devrem_bitmap; 1148 u16 dev_handle_bitmap_bits; 1149 unsigned long *removepend_bitmap; 1150 struct list_head delayed_rmhs_list; 1151 unsigned long *evtack_cmds_bitmap; 1152 struct list_head delayed_evtack_cmds_list; 1153 1154 u32 ts_update_counter; 1155 u8 reset_in_progress; 1156 u8 unrecoverable; 1157 int prev_reset_result; 1158 struct mutex reset_mutex; 1159 wait_queue_head_t reset_waitq; 1160 1161 u8 prepare_for_reset; 1162 u16 prepare_for_reset_timeout_counter; 1163 1164 void *prp_list_virt; 1165 dma_addr_t prp_list_dma; 1166 u32 prp_sz; 1167 1168 u16 diagsave_timeout; 1169 int logging_level; 1170 u16 flush_io_count; 1171 1172 struct mpi3mr_fwevt *current_event; 1173 struct mpi3_driver_info_layout driver_info; 1174 u16 change_count; 1175 1176 u8 pel_enabled; 1177 u8 pel_abort_requested; 1178 u8 pel_class; 1179 u16 pel_locale; 1180 struct mpi3mr_drv_cmd pel_cmds; 1181 struct mpi3mr_drv_cmd pel_abort_cmd; 1182 1183 u32 pel_newest_seqnum; 1184 void *pel_seqnum_virt; 1185 dma_addr_t pel_seqnum_dma; 1186 u32 pel_seqnum_sz; 1187 1188 u16 op_reply_q_offset; 1189 u16 default_qcount; 1190 u16 active_poll_qcount; 1191 u16 requested_poll_qcount; 1192 1193 struct device bsg_dev; 1194 struct request_queue *bsg_queue; 1195 u8 stop_bsgs; 1196 u8 *logdata_buf; 1197 u16 logdata_buf_idx; 1198 u16 logdata_entry_sz; 1199 1200 atomic_t pend_large_data_sz; 1201 u32 io_throttle_data_length; 1202 u32 io_throttle_high; 1203 u32 io_throttle_low; 1204 u16 num_io_throttle_group; 1205 struct mpi3mr_throttle_group_info *throttle_groups; 1206 1207 void *cfg_page; 1208 dma_addr_t cfg_page_dma; 1209 u16 cfg_page_sz; 1210 1211 u8 sas_transport_enabled; 1212 u8 scsi_device_channel; 1213 struct mpi3mr_drv_cmd transport_cmds; 1214 struct mpi3mr_sas_node sas_hba; 1215 struct list_head sas_expander_list; 1216 spinlock_t sas_node_lock; 1217 struct list_head hba_port_table_list; 1218 struct list_head enclosure_list; 1219 }; 1220 1221 /** 1222 * struct mpi3mr_fwevt - Firmware event structure. 1223 * 1224 * @list: list head 1225 * @work: Work structure 1226 * @mrioc: Adapter instance reference 1227 * @event_id: MPI3 firmware event ID 1228 * @send_ack: Event acknowledgment required or not 1229 * @process_evt: Bottomhalf processing required or not 1230 * @evt_ctx: Event context to send in Ack 1231 * @event_data_size: size of the event data in bytes 1232 * @pending_at_sml: waiting for device add/remove API to complete 1233 * @discard: discard this event 1234 * @ref_count: kref count 1235 * @event_data: Actual MPI3 event data 1236 */ 1237 struct mpi3mr_fwevt { 1238 struct list_head list; 1239 struct work_struct work; 1240 struct mpi3mr_ioc *mrioc; 1241 u16 event_id; 1242 bool send_ack; 1243 bool process_evt; 1244 u32 evt_ctx; 1245 u16 event_data_size; 1246 bool pending_at_sml; 1247 bool discard; 1248 struct kref ref_count; 1249 char event_data[] __aligned(4); 1250 }; 1251 1252 1253 /** 1254 * struct delayed_dev_rmhs_node - Delayed device removal node 1255 * 1256 * @list: list head 1257 * @handle: Device handle 1258 * @iou_rc: IO Unit Control Reason Code 1259 */ 1260 struct delayed_dev_rmhs_node { 1261 struct list_head list; 1262 u16 handle; 1263 u8 iou_rc; 1264 }; 1265 1266 /** 1267 * struct delayed_evt_ack_node - Delayed event ack node 1268 * @list: list head 1269 * @event: MPI3 event ID 1270 * @event_ctx: event context 1271 */ 1272 struct delayed_evt_ack_node { 1273 struct list_head list; 1274 u8 event; 1275 u32 event_ctx; 1276 }; 1277 1278 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1279 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1280 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1281 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1282 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1283 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1284 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1285 u16 admin_req_sz, u8 ignore_reset); 1286 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1287 struct op_req_qinfo *opreqq, u8 *req); 1288 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1289 dma_addr_t dma_addr); 1290 void mpi3mr_build_zero_len_sge(void *paddr); 1291 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1292 dma_addr_t phys_addr); 1293 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1294 dma_addr_t phys_addr); 1295 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1296 u64 sense_buf_dma); 1297 1298 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1299 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1300 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1301 struct mpi3_event_notification_reply *event_reply); 1302 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1303 struct mpi3_default_reply_descriptor *reply_desc, 1304 u64 *reply_dma, u16 qidx); 1305 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1306 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1307 1308 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1309 u32 reset_reason, u8 snapdump); 1310 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1311 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1312 1313 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1314 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1315 u32 event_ctx); 1316 1317 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1318 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1319 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1320 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1321 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1322 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1323 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1324 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1325 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1326 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1327 struct op_reply_qinfo *op_reply_q); 1328 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1329 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1330 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1331 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1332 u16 handle, uint lun, u16 htag, ulong timeout, 1333 struct mpi3mr_drv_cmd *drv_cmd, 1334 u8 *resp_code, struct scsi_cmnd *scmd); 1335 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1336 struct mpi3mr_ioc *mrioc, u16 handle); 1337 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1338 struct mpi3mr_drv_cmd *drv_cmd); 1339 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1340 struct mpi3mr_drv_cmd *drv_cmd); 1341 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1342 u16 event_data_size); 1343 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1344 struct mpi3mr_ioc *mrioc, u16 handle); 1345 extern const struct attribute_group *mpi3mr_host_groups[]; 1346 extern const struct attribute_group *mpi3mr_dev_groups[]; 1347 1348 extern struct sas_function_template mpi3mr_transport_functions; 1349 extern struct scsi_transport_template *mpi3mr_transport_template; 1350 1351 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1352 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1353 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1354 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1355 u32 form_spec); 1356 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1357 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1358 u32 form_spec); 1359 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1360 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1361 u32 form_spec); 1362 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1363 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1364 u32 form_spec); 1365 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1366 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1367 u32 form_spec); 1368 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1369 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1370 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1371 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1372 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1373 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1374 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1375 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1376 1377 u8 mpi3mr_is_expander_device(u16 device_info); 1378 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1379 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1380 struct mpi3mr_hba_port *hba_port); 1381 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1382 *mrioc, u16 handle); 1383 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1384 u8 port_id); 1385 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1386 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1387 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1388 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1389 struct mpi3mr_hba_port *hba_port); 1390 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1391 struct mpi3mr_tgt_dev *tgtdev); 1392 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1393 struct mpi3mr_tgt_dev *tgtdev); 1394 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1395 struct mpi3mr_tgt_dev *tgtdev); 1396 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1397 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1398 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1399 bool device_add); 1400 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1401 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1402 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1403 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1404 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1405 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1406 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1407 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1408 struct mpi3mr_sas_node *sas_expander); 1409 #endif /*MPI3MR_H_INCLUDED*/ 1410