1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 /* Definitions for internal SGL and Chain SGL buffers */ 70 #define MPI3MR_PAGE_SIZE_4K 4096 71 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 72 73 /* Definitions for MAX values for shost */ 74 #define MPI3MR_MAX_CMDS_LUN 7 75 #define MPI3MR_MAX_CDB_LENGTH 32 76 77 /* Admin queue management definitions */ 78 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 79 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 80 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 81 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 82 83 /* Operational queue management definitions */ 84 #define MPI3MR_OP_REQ_Q_QD 512 85 #define MPI3MR_OP_REP_Q_QD 1024 86 #define MPI3MR_OP_REP_Q_QD4K 4096 87 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 88 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 89 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 90 91 /* Reserved Host Tag definitions */ 92 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 93 #define MPI3MR_HOSTTAG_INITCMDS 1 94 #define MPI3MR_HOSTTAG_BSG_CMDS 2 95 #define MPI3MR_HOSTTAG_PEL_ABORT 3 96 #define MPI3MR_HOSTTAG_PEL_WAIT 4 97 #define MPI3MR_HOSTTAG_BLK_TMS 5 98 99 #define MPI3MR_NUM_DEVRMCMD 16 100 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 101 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 102 MPI3MR_NUM_DEVRMCMD - 1) 103 104 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 105 #define MPI3MR_NUM_EVTACKCMD 4 106 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 107 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 108 MPI3MR_NUM_EVTACKCMD - 1) 109 110 /* Reduced resource count definition for crash kernel */ 111 #define MPI3MR_HOST_IOS_KDUMP 128 112 113 /* command/controller interaction timeout definitions in seconds */ 114 #define MPI3MR_INTADMCMD_TIMEOUT 60 115 #define MPI3MR_PORTENABLE_TIMEOUT 300 116 #define MPI3MR_ABORTTM_TIMEOUT 60 117 #define MPI3MR_RESETTM_TIMEOUT 60 118 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 119 #define MPI3MR_TSUPDATE_INTERVAL 900 120 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 121 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 122 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 123 #define MPI3MR_RESET_ACK_TIMEOUT 30 124 125 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 126 127 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 128 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 129 130 /* Internal admin command state definitions*/ 131 #define MPI3MR_CMD_NOTUSED 0x8000 132 #define MPI3MR_CMD_COMPLETE 0x0001 133 #define MPI3MR_CMD_PENDING 0x0002 134 #define MPI3MR_CMD_REPLY_VALID 0x0004 135 #define MPI3MR_CMD_RESET 0x0008 136 137 /* Definitions for Event replies and sense buffer allocated per controller */ 138 #define MPI3MR_NUM_EVT_REPLIES 64 139 #define MPI3MR_SENSE_BUF_SZ 256 140 #define MPI3MR_SENSEBUF_FACTOR 3 141 #define MPI3MR_CHAINBUF_FACTOR 3 142 #define MPI3MR_CHAINBUFDIX_FACTOR 2 143 144 /* Invalid target device handle */ 145 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 146 147 /* Controller Reset related definitions */ 148 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 149 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 150 151 /* ResponseCode definitions */ 152 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 153 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 154 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 155 156 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 157 #define MPI3MR_DEFAULT_PGSZEXP (12) 158 159 /* Command retry count definitions */ 160 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 161 #define MPI3MR_PEL_RETRY_COUNT 3 162 163 /* Default target device queue depth */ 164 #define MPI3MR_DEFAULT_SDEV_QD 32 165 166 /* Definitions for Threaded IRQ poll*/ 167 #define MPI3MR_IRQ_POLL_SLEEP 2 168 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 169 170 /* Definitions for the controller security status*/ 171 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 172 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 173 174 #define MPI3MR_INVALID_DEVICE 0x00 175 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 176 #define MPI3MR_HARD_SECURE_DEVICE 0x08 177 #define MPI3MR_TAMPERED_DEVICE 0x0C 178 179 /* SGE Flag definition */ 180 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 181 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 182 MPI3_SGE_FLAGS_END_OF_LIST) 183 184 /* MSI Index from Reply Queue Index */ 185 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 186 187 /* 188 * Maximum data transfer size definitions for management 189 * application commands 190 */ 191 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 192 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 193 /* 194 * 2048 sectors are for data buffers and additional 512 sectors for 195 * other buffers 196 */ 197 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 198 199 /** 200 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 201 * Encapsulated commands. 202 * 203 * @base_addr: Physical address 204 * @length: SGE length 205 * @rsvd: Reserved 206 * @rsvd1: Reserved 207 * @sgl_type: sgl type 208 */ 209 struct mpi3mr_nvme_pt_sge { 210 u64 base_addr; 211 u32 length; 212 u16 rsvd; 213 u8 rsvd1; 214 u8 sgl_type; 215 }; 216 217 /** 218 * struct mpi3mr_buf_map - local structure to 219 * track kernel and user buffers associated with an BSG 220 * structure. 221 * 222 * @bsg_buf: BSG buffer virtual address 223 * @bsg_buf_len: BSG buffer length 224 * @kern_buf: Kernel buffer virtual address 225 * @kern_buf_len: Kernel buffer length 226 * @kern_buf_dma: Kernel buffer DMA address 227 * @data_dir: Data direction. 228 */ 229 struct mpi3mr_buf_map { 230 void *bsg_buf; 231 u32 bsg_buf_len; 232 void *kern_buf; 233 u32 kern_buf_len; 234 dma_addr_t kern_buf_dma; 235 u8 data_dir; 236 }; 237 238 /* IOC State definitions */ 239 enum mpi3mr_iocstate { 240 MRIOC_STATE_READY = 1, 241 MRIOC_STATE_RESET, 242 MRIOC_STATE_FAULT, 243 MRIOC_STATE_BECOMING_READY, 244 MRIOC_STATE_RESET_REQUESTED, 245 MRIOC_STATE_UNRECOVERABLE, 246 }; 247 248 /* Reset reason code definitions*/ 249 enum mpi3mr_reset_reason { 250 MPI3MR_RESET_FROM_BRINGUP = 1, 251 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 252 MPI3MR_RESET_FROM_APP = 3, 253 MPI3MR_RESET_FROM_EH_HOS = 4, 254 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 255 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 256 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 257 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 258 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 259 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 260 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 261 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 262 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 263 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 264 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 265 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 266 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 267 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 268 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 269 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 270 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 271 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 272 MPI3MR_RESET_FROM_SYSFS = 23, 273 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 274 MPI3MR_RESET_FROM_FIRMWARE = 27, 275 }; 276 277 /* Queue type definitions */ 278 enum queue_type { 279 MPI3MR_DEFAULT_QUEUE = 0, 280 MPI3MR_POLL_QUEUE, 281 }; 282 283 /** 284 * struct mpi3mr_compimg_ver - replica of component image 285 * version defined in mpi30_image.h in host endianness 286 * 287 */ 288 struct mpi3mr_compimg_ver { 289 u16 build_num; 290 u16 cust_id; 291 u8 ph_minor; 292 u8 ph_major; 293 u8 gen_minor; 294 u8 gen_major; 295 }; 296 297 /** 298 * struct mpi3mr_ioc_facs - replica of component image version 299 * defined in mpi30_ioc.h in host endianness 300 * 301 */ 302 struct mpi3mr_ioc_facts { 303 u32 ioc_capabilities; 304 struct mpi3mr_compimg_ver fw_ver; 305 u32 mpi_version; 306 u16 max_reqs; 307 u16 product_id; 308 u16 op_req_sz; 309 u16 reply_sz; 310 u16 exceptions; 311 u16 max_perids; 312 u16 max_pds; 313 u16 max_sasexpanders; 314 u16 max_sasinitiators; 315 u16 max_enclosures; 316 u16 max_pcie_switches; 317 u16 max_nvme; 318 u16 max_vds; 319 u16 max_hpds; 320 u16 max_advhpds; 321 u16 max_raid_pds; 322 u16 min_devhandle; 323 u16 max_devhandle; 324 u16 max_op_req_q; 325 u16 max_op_reply_q; 326 u16 shutdown_timeout; 327 u8 ioc_num; 328 u8 who_init; 329 u16 max_msix_vectors; 330 u8 personality; 331 u8 dma_mask; 332 u8 protocol_flags; 333 u8 sge_mod_mask; 334 u8 sge_mod_value; 335 u8 sge_mod_shift; 336 }; 337 338 /** 339 * struct segments - memory descriptor structure to store 340 * virtual and dma addresses for operational queue segments. 341 * 342 * @segment: virtual address 343 * @segment_dma: dma address 344 */ 345 struct segments { 346 void *segment; 347 dma_addr_t segment_dma; 348 }; 349 350 /** 351 * struct op_req_qinfo - Operational Request Queue Information 352 * 353 * @ci: consumer index 354 * @pi: producer index 355 * @num_request: Maximum number of entries in the queue 356 * @qid: Queue Id starting from 1 357 * @reply_qid: Associated reply queue Id 358 * @num_segments: Number of discontiguous memory segments 359 * @segment_qd: Depth of each segments 360 * @q_lock: Concurrent queue access lock 361 * @q_segments: Segment descriptor pointer 362 * @q_segment_list: Segment list base virtual address 363 * @q_segment_list_dma: Segment list base DMA address 364 */ 365 struct op_req_qinfo { 366 u16 ci; 367 u16 pi; 368 u16 num_requests; 369 u16 qid; 370 u16 reply_qid; 371 u16 num_segments; 372 u16 segment_qd; 373 spinlock_t q_lock; 374 struct segments *q_segments; 375 void *q_segment_list; 376 dma_addr_t q_segment_list_dma; 377 }; 378 379 /** 380 * struct op_reply_qinfo - Operational Reply Queue Information 381 * 382 * @ci: consumer index 383 * @qid: Queue Id starting from 1 384 * @num_replies: Maximum number of entries in the queue 385 * @num_segments: Number of discontiguous memory segments 386 * @segment_qd: Depth of each segments 387 * @q_segments: Segment descriptor pointer 388 * @q_segment_list: Segment list base virtual address 389 * @q_segment_list_dma: Segment list base DMA address 390 * @ephase: Expected phased identifier for the reply queue 391 * @pend_ios: Number of IOs pending in HW for this queue 392 * @enable_irq_poll: Flag to indicate polling is enabled 393 * @in_use: Queue is handled by poll/ISR 394 * @qtype: Type of queue (types defined in enum queue_type) 395 */ 396 struct op_reply_qinfo { 397 u16 ci; 398 u16 qid; 399 u16 num_replies; 400 u16 num_segments; 401 u16 segment_qd; 402 struct segments *q_segments; 403 void *q_segment_list; 404 dma_addr_t q_segment_list_dma; 405 u8 ephase; 406 atomic_t pend_ios; 407 bool enable_irq_poll; 408 atomic_t in_use; 409 enum queue_type qtype; 410 }; 411 412 /** 413 * struct mpi3mr_intr_info - Interrupt cookie information 414 * 415 * @mrioc: Adapter instance reference 416 * @msix_index: MSIx index 417 * @op_reply_q: Associated operational reply queue 418 * @name: Dev name for the irq claiming device 419 */ 420 struct mpi3mr_intr_info { 421 struct mpi3mr_ioc *mrioc; 422 u16 msix_index; 423 struct op_reply_qinfo *op_reply_q; 424 char name[MPI3MR_NAME_LENGTH]; 425 }; 426 427 /** 428 * struct tgt_dev_sas_sata - SAS/SATA device specific 429 * information cached from firmware given data 430 * 431 * @sas_address: World wide unique SAS address 432 * @dev_info: Device information bits 433 */ 434 struct tgt_dev_sas_sata { 435 u64 sas_address; 436 u16 dev_info; 437 }; 438 439 /** 440 * struct tgt_dev_pcie - PCIe device specific information cached 441 * from firmware given data 442 * 443 * @mdts: Maximum data transfer size 444 * @capb: Device capabilities 445 * @pgsz: Device page size 446 * @abort_to: Timeout for abort TM 447 * @reset_to: Timeout for Target/LUN reset TM 448 * @dev_info: Device information bits 449 */ 450 struct tgt_dev_pcie { 451 u32 mdts; 452 u16 capb; 453 u8 pgsz; 454 u8 abort_to; 455 u8 reset_to; 456 u16 dev_info; 457 }; 458 459 /** 460 * struct tgt_dev_volume - virtual device specific information 461 * cached from firmware given data 462 * 463 * @state: State of the VD 464 */ 465 struct tgt_dev_volume { 466 u8 state; 467 }; 468 469 /** 470 * union _form_spec_inf - union of device specific information 471 */ 472 union _form_spec_inf { 473 struct tgt_dev_sas_sata sas_sata_inf; 474 struct tgt_dev_pcie pcie_inf; 475 struct tgt_dev_volume vol_inf; 476 }; 477 478 479 480 /** 481 * struct mpi3mr_tgt_dev - target device data structure 482 * 483 * @list: List pointer 484 * @starget: Scsi_target pointer 485 * @dev_handle: FW device handle 486 * @parent_handle: FW parent device handle 487 * @slot: Slot number 488 * @encl_handle: FW enclosure handle 489 * @perst_id: FW assigned Persistent ID 490 * @dev_type: SAS/SATA/PCIE device type 491 * @is_hidden: Should be exposed to upper layers or not 492 * @host_exposed: Already exposed to host or not 493 * @q_depth: Device specific Queue Depth 494 * @wwid: World wide ID 495 * @dev_spec: Device type specific information 496 * @ref_count: Reference count 497 */ 498 struct mpi3mr_tgt_dev { 499 struct list_head list; 500 struct scsi_target *starget; 501 u16 dev_handle; 502 u16 parent_handle; 503 u16 slot; 504 u16 encl_handle; 505 u16 perst_id; 506 u8 dev_type; 507 u8 is_hidden; 508 u8 host_exposed; 509 u16 q_depth; 510 u64 wwid; 511 union _form_spec_inf dev_spec; 512 struct kref ref_count; 513 }; 514 515 /** 516 * mpi3mr_tgtdev_get - k reference incrementor 517 * @s: Target device reference 518 * 519 * Increment target device reference count. 520 */ 521 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 522 { 523 kref_get(&s->ref_count); 524 } 525 526 /** 527 * mpi3mr_free_tgtdev - target device memory dealloctor 528 * @r: k reference pointer of the target device 529 * 530 * Free target device memory when no reference. 531 */ 532 static inline void mpi3mr_free_tgtdev(struct kref *r) 533 { 534 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 535 } 536 537 /** 538 * mpi3mr_tgtdev_put - k reference decrementor 539 * @s: Target device reference 540 * 541 * Decrement target device reference count. 542 */ 543 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 544 { 545 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 546 } 547 548 549 /** 550 * struct mpi3mr_stgt_priv_data - SCSI target private structure 551 * 552 * @starget: Scsi_target pointer 553 * @dev_handle: FW device handle 554 * @perst_id: FW assigned Persistent ID 555 * @num_luns: Number of Logical Units 556 * @block_io: I/O blocked to the device or not 557 * @dev_removed: Device removed in the Firmware 558 * @dev_removedelay: Device is waiting to be removed in FW 559 * @dev_type: Device type 560 * @tgt_dev: Internal target device pointer 561 * @pend_count: Counter to track pending I/Os during error 562 * handling 563 */ 564 struct mpi3mr_stgt_priv_data { 565 struct scsi_target *starget; 566 u16 dev_handle; 567 u16 perst_id; 568 u32 num_luns; 569 atomic_t block_io; 570 u8 dev_removed; 571 u8 dev_removedelay; 572 u8 dev_type; 573 struct mpi3mr_tgt_dev *tgt_dev; 574 u32 pend_count; 575 }; 576 577 /** 578 * struct mpi3mr_stgt_priv_data - SCSI device private structure 579 * 580 * @tgt_priv_data: Scsi_target private data pointer 581 * @lun_id: LUN ID of the device 582 * @ncq_prio_enable: NCQ priority enable for SATA device 583 * @pend_count: Counter to track pending I/Os during error 584 * handling 585 */ 586 struct mpi3mr_sdev_priv_data { 587 struct mpi3mr_stgt_priv_data *tgt_priv_data; 588 u32 lun_id; 589 u8 ncq_prio_enable; 590 u32 pend_count; 591 }; 592 593 /** 594 * struct mpi3mr_drv_cmd - Internal command tracker 595 * 596 * @mutex: Command mutex 597 * @done: Completeor for wakeup 598 * @reply: Firmware reply for internal commands 599 * @sensebuf: Sensebuf for SCSI IO commands 600 * @iou_rc: IO Unit control reason code 601 * @state: Command State 602 * @dev_handle: Firmware handle for device specific commands 603 * @ioc_status: IOC status from the firmware 604 * @ioc_loginfo:IOC log info from the firmware 605 * @is_waiting: Is the command issued in block mode 606 * @is_sense: Is Sense data present 607 * @retry_count: Retry count for retriable commands 608 * @host_tag: Host tag used by the command 609 * @callback: Callback for non blocking commands 610 */ 611 struct mpi3mr_drv_cmd { 612 struct mutex mutex; 613 struct completion done; 614 void *reply; 615 u8 *sensebuf; 616 u8 iou_rc; 617 u16 state; 618 u16 dev_handle; 619 u16 ioc_status; 620 u32 ioc_loginfo; 621 u8 is_waiting; 622 u8 is_sense; 623 u8 retry_count; 624 u16 host_tag; 625 626 void (*callback)(struct mpi3mr_ioc *mrioc, 627 struct mpi3mr_drv_cmd *drv_cmd); 628 }; 629 630 631 /** 632 * struct chain_element - memory descriptor structure to store 633 * virtual and dma addresses for chain elements. 634 * 635 * @addr: virtual address 636 * @dma_addr: dma address 637 */ 638 struct chain_element { 639 void *addr; 640 dma_addr_t dma_addr; 641 }; 642 643 /** 644 * struct scmd_priv - SCSI command private data 645 * 646 * @host_tag: Host tag specific to operational queue 647 * @in_lld_scope: Command in LLD scope or not 648 * @meta_sg_valid: DIX command with meta data SGL or not 649 * @scmd: SCSI Command pointer 650 * @req_q_idx: Operational request queue index 651 * @chain_idx: Chain frame index 652 * @meta_chain_idx: Chain frame index of meta data SGL 653 * @mpi3mr_scsiio_req: MPI SCSI IO request 654 */ 655 struct scmd_priv { 656 u16 host_tag; 657 u8 in_lld_scope; 658 u8 meta_sg_valid; 659 struct scsi_cmnd *scmd; 660 u16 req_q_idx; 661 int chain_idx; 662 int meta_chain_idx; 663 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 664 }; 665 666 /** 667 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 668 * private data 669 * 670 * @list: List pointer 671 * @pdev: PCI device pointer 672 * @shost: Scsi_Host pointer 673 * @id: Controller ID 674 * @cpu_count: Number of online CPUs 675 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 676 * @name: Controller ASCII name 677 * @driver_name: Driver ASCII name 678 * @sysif_regs: System interface registers virtual address 679 * @sysif_regs_phys: System interface registers physical address 680 * @bars: PCI BARS 681 * @dma_mask: DMA mask 682 * @msix_count: Number of MSIX vectors used 683 * @intr_enabled: Is interrupts enabled 684 * @num_admin_req: Number of admin requests 685 * @admin_req_q_sz: Admin request queue size 686 * @admin_req_pi: Admin request queue producer index 687 * @admin_req_ci: Admin request queue consumer index 688 * @admin_req_base: Admin request queue base virtual address 689 * @admin_req_dma: Admin request queue base dma address 690 * @admin_req_lock: Admin queue access lock 691 * @num_admin_replies: Number of admin replies 692 * @admin_reply_q_sz: Admin reply queue size 693 * @admin_reply_ci: Admin reply queue consumer index 694 * @admin_reply_ephase:Admin reply queue expected phase 695 * @admin_reply_base: Admin reply queue base virtual address 696 * @admin_reply_dma: Admin reply queue base dma address 697 * @ready_timeout: Controller ready timeout 698 * @intr_info: Interrupt cookie pointer 699 * @intr_info_count: Number of interrupt cookies 700 * @is_intr_info_set: Flag to indicate intr info is setup 701 * @num_queues: Number of operational queues 702 * @num_op_req_q: Number of operational request queues 703 * @req_qinfo: Operational request queue info pointer 704 * @num_op_reply_q: Number of operational reply queues 705 * @op_reply_qinfo: Operational reply queue info pointer 706 * @init_cmds: Command tracker for initialization commands 707 * @facts: Cached IOC facts data 708 * @op_reply_desc_sz: Operational reply descriptor size 709 * @num_reply_bufs: Number of reply buffers allocated 710 * @reply_buf_pool: Reply buffer pool 711 * @reply_buf: Reply buffer base virtual address 712 * @reply_buf_dma: Reply buffer DMA address 713 * @reply_buf_dma_max_address: Reply DMA address max limit 714 * @reply_free_qsz: Reply free queue size 715 * @reply_free_q_pool: Reply free queue pool 716 * @reply_free_q: Reply free queue base virtual address 717 * @reply_free_q_dma: Reply free queue base DMA address 718 * @reply_free_queue_lock: Reply free queue lock 719 * @reply_free_queue_host_index: Reply free queue host index 720 * @num_sense_bufs: Number of sense buffers 721 * @sense_buf_pool: Sense buffer pool 722 * @sense_buf: Sense buffer base virtual address 723 * @sense_buf_dma: Sense buffer base DMA address 724 * @sense_buf_q_sz: Sense buffer queue size 725 * @sense_buf_q_pool: Sense buffer queue pool 726 * @sense_buf_q: Sense buffer queue virtual address 727 * @sense_buf_q_dma: Sense buffer queue DMA address 728 * @sbq_lock: Sense buffer queue lock 729 * @sbq_host_index: Sense buffer queuehost index 730 * @event_masks: Event mask bitmap 731 * @fwevt_worker_name: Firmware event worker thread name 732 * @fwevt_worker_thread: Firmware event worker thread 733 * @fwevt_lock: Firmware event lock 734 * @fwevt_list: Firmware event list 735 * @watchdog_work_q_name: Fault watchdog worker thread name 736 * @watchdog_work_q: Fault watchdog worker thread 737 * @watchdog_work: Fault watchdog work 738 * @watchdog_lock: Fault watchdog lock 739 * @is_driver_loading: Is driver still loading 740 * @scan_started: Async scan started 741 * @scan_failed: Asycn scan failed 742 * @stop_drv_processing: Stop all command processing 743 * @max_host_ios: Maximum host I/O count 744 * @chain_buf_count: Chain buffer count 745 * @chain_buf_pool: Chain buffer pool 746 * @chain_sgl_list: Chain SGL list 747 * @chain_bitmap_sz: Chain buffer allocator bitmap size 748 * @chain_bitmap: Chain buffer allocator bitmap 749 * @chain_buf_lock: Chain buffer list lock 750 * @bsg_cmds: Command tracker for BSG command 751 * @host_tm_cmds: Command tracker for task management commands 752 * @dev_rmhs_cmds: Command tracker for device removal commands 753 * @evtack_cmds: Command tracker for event ack commands 754 * @devrem_bitmap_sz: Device removal bitmap size 755 * @devrem_bitmap: Device removal bitmap 756 * @dev_handle_bitmap_sz: Device handle bitmap size 757 * @removepend_bitmap: Remove pending bitmap 758 * @delayed_rmhs_list: Delayed device removal list 759 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 760 * @evtack_cmds_bitmap: Event Ack bitmap 761 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 762 * @ts_update_counter: Timestamp update counter 763 * @reset_in_progress: Reset in progress flag 764 * @unrecoverable: Controller unrecoverable flag 765 * @prev_reset_result: Result of previous reset 766 * @reset_mutex: Controller reset mutex 767 * @reset_waitq: Controller reset wait queue 768 * @prepare_for_reset: Prepare for reset event received 769 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 770 * @prp_list_virt: NVMe encapsulated PRP list virtual base 771 * @prp_list_dma: NVMe encapsulated PRP list DMA 772 * @prp_sz: NVME encapsulated PRP list size 773 * @diagsave_timeout: Diagnostic information save timeout 774 * @logging_level: Controller debug logging level 775 * @flush_io_count: I/O count to flush after reset 776 * @current_event: Firmware event currently in process 777 * @driver_info: Driver, Kernel, OS information to firmware 778 * @change_count: Topology change count 779 * @pel_enabled: Persistent Event Log(PEL) enabled or not 780 * @pel_abort_requested: PEL abort is requested or not 781 * @pel_class: PEL Class identifier 782 * @pel_locale: PEL Locale identifier 783 * @pel_cmds: Command tracker for PEL wait command 784 * @pel_abort_cmd: Command tracker for PEL abort command 785 * @pel_newest_seqnum: Newest PEL sequenece number 786 * @pel_seqnum_virt: PEL sequence number virtual address 787 * @pel_seqnum_dma: PEL sequence number DMA address 788 * @pel_seqnum_sz: PEL sequenece number size 789 * @op_reply_q_offset: Operational reply queue offset with MSIx 790 * @default_qcount: Total Default queues 791 * @active_poll_qcount: Currently active poll queue count 792 * @requested_poll_qcount: User requested poll queue count 793 * @bsg_dev: BSG device structure 794 * @bsg_queue: Request queue for BSG device 795 * @stop_bsgs: Stop BSG request flag 796 * @logdata_buf: Circular buffer to store log data entries 797 * @logdata_buf_idx: Index of entry in buffer to store 798 * @logdata_entry_sz: log data entry size 799 */ 800 struct mpi3mr_ioc { 801 struct list_head list; 802 struct pci_dev *pdev; 803 struct Scsi_Host *shost; 804 u8 id; 805 int cpu_count; 806 bool enable_segqueue; 807 u32 irqpoll_sleep; 808 809 char name[MPI3MR_NAME_LENGTH]; 810 char driver_name[MPI3MR_NAME_LENGTH]; 811 812 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 813 resource_size_t sysif_regs_phys; 814 int bars; 815 u64 dma_mask; 816 817 u16 msix_count; 818 u8 intr_enabled; 819 820 u16 num_admin_req; 821 u32 admin_req_q_sz; 822 u16 admin_req_pi; 823 u16 admin_req_ci; 824 void *admin_req_base; 825 dma_addr_t admin_req_dma; 826 spinlock_t admin_req_lock; 827 828 u16 num_admin_replies; 829 u32 admin_reply_q_sz; 830 u16 admin_reply_ci; 831 u8 admin_reply_ephase; 832 void *admin_reply_base; 833 dma_addr_t admin_reply_dma; 834 835 u32 ready_timeout; 836 837 struct mpi3mr_intr_info *intr_info; 838 u16 intr_info_count; 839 bool is_intr_info_set; 840 841 u16 num_queues; 842 u16 num_op_req_q; 843 struct op_req_qinfo *req_qinfo; 844 845 u16 num_op_reply_q; 846 struct op_reply_qinfo *op_reply_qinfo; 847 848 struct mpi3mr_drv_cmd init_cmds; 849 struct mpi3mr_ioc_facts facts; 850 u16 op_reply_desc_sz; 851 852 u32 num_reply_bufs; 853 struct dma_pool *reply_buf_pool; 854 u8 *reply_buf; 855 dma_addr_t reply_buf_dma; 856 dma_addr_t reply_buf_dma_max_address; 857 858 u16 reply_free_qsz; 859 u16 reply_sz; 860 struct dma_pool *reply_free_q_pool; 861 __le64 *reply_free_q; 862 dma_addr_t reply_free_q_dma; 863 spinlock_t reply_free_queue_lock; 864 u32 reply_free_queue_host_index; 865 866 u32 num_sense_bufs; 867 struct dma_pool *sense_buf_pool; 868 u8 *sense_buf; 869 dma_addr_t sense_buf_dma; 870 871 u16 sense_buf_q_sz; 872 struct dma_pool *sense_buf_q_pool; 873 __le64 *sense_buf_q; 874 dma_addr_t sense_buf_q_dma; 875 spinlock_t sbq_lock; 876 u32 sbq_host_index; 877 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 878 879 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 880 struct workqueue_struct *fwevt_worker_thread; 881 spinlock_t fwevt_lock; 882 struct list_head fwevt_list; 883 884 char watchdog_work_q_name[20]; 885 struct workqueue_struct *watchdog_work_q; 886 struct delayed_work watchdog_work; 887 spinlock_t watchdog_lock; 888 889 u8 is_driver_loading; 890 u8 scan_started; 891 u16 scan_failed; 892 u8 stop_drv_processing; 893 894 u16 max_host_ios; 895 spinlock_t tgtdev_lock; 896 struct list_head tgtdev_list; 897 898 u32 chain_buf_count; 899 struct dma_pool *chain_buf_pool; 900 struct chain_element *chain_sgl_list; 901 u16 chain_bitmap_sz; 902 void *chain_bitmap; 903 spinlock_t chain_buf_lock; 904 905 struct mpi3mr_drv_cmd bsg_cmds; 906 struct mpi3mr_drv_cmd host_tm_cmds; 907 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 908 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 909 u16 devrem_bitmap_sz; 910 void *devrem_bitmap; 911 u16 dev_handle_bitmap_sz; 912 void *removepend_bitmap; 913 struct list_head delayed_rmhs_list; 914 u16 evtack_cmds_bitmap_sz; 915 void *evtack_cmds_bitmap; 916 struct list_head delayed_evtack_cmds_list; 917 918 u32 ts_update_counter; 919 u8 reset_in_progress; 920 u8 unrecoverable; 921 int prev_reset_result; 922 struct mutex reset_mutex; 923 wait_queue_head_t reset_waitq; 924 925 u8 prepare_for_reset; 926 u16 prepare_for_reset_timeout_counter; 927 928 void *prp_list_virt; 929 dma_addr_t prp_list_dma; 930 u32 prp_sz; 931 932 u16 diagsave_timeout; 933 int logging_level; 934 u16 flush_io_count; 935 936 struct mpi3mr_fwevt *current_event; 937 struct mpi3_driver_info_layout driver_info; 938 u16 change_count; 939 940 u8 pel_enabled; 941 u8 pel_abort_requested; 942 u8 pel_class; 943 u16 pel_locale; 944 struct mpi3mr_drv_cmd pel_cmds; 945 struct mpi3mr_drv_cmd pel_abort_cmd; 946 947 u32 pel_newest_seqnum; 948 void *pel_seqnum_virt; 949 dma_addr_t pel_seqnum_dma; 950 u32 pel_seqnum_sz; 951 952 u16 op_reply_q_offset; 953 u16 default_qcount; 954 u16 active_poll_qcount; 955 u16 requested_poll_qcount; 956 957 struct device bsg_dev; 958 struct request_queue *bsg_queue; 959 u8 stop_bsgs; 960 u8 *logdata_buf; 961 u16 logdata_buf_idx; 962 u16 logdata_entry_sz; 963 }; 964 965 /** 966 * struct mpi3mr_fwevt - Firmware event structure. 967 * 968 * @list: list head 969 * @work: Work structure 970 * @mrioc: Adapter instance reference 971 * @event_id: MPI3 firmware event ID 972 * @send_ack: Event acknowledgment required or not 973 * @process_evt: Bottomhalf processing required or not 974 * @evt_ctx: Event context to send in Ack 975 * @event_data_size: size of the event data in bytes 976 * @pending_at_sml: waiting for device add/remove API to complete 977 * @discard: discard this event 978 * @ref_count: kref count 979 * @event_data: Actual MPI3 event data 980 */ 981 struct mpi3mr_fwevt { 982 struct list_head list; 983 struct work_struct work; 984 struct mpi3mr_ioc *mrioc; 985 u16 event_id; 986 bool send_ack; 987 bool process_evt; 988 u32 evt_ctx; 989 u16 event_data_size; 990 bool pending_at_sml; 991 bool discard; 992 struct kref ref_count; 993 char event_data[] __aligned(4); 994 }; 995 996 997 /** 998 * struct delayed_dev_rmhs_node - Delayed device removal node 999 * 1000 * @list: list head 1001 * @handle: Device handle 1002 * @iou_rc: IO Unit Control Reason Code 1003 */ 1004 struct delayed_dev_rmhs_node { 1005 struct list_head list; 1006 u16 handle; 1007 u8 iou_rc; 1008 }; 1009 1010 /** 1011 * struct delayed_evt_ack_node - Delayed event ack node 1012 * @list: list head 1013 * @event: MPI3 event ID 1014 * @event_ctx: event context 1015 */ 1016 struct delayed_evt_ack_node { 1017 struct list_head list; 1018 u8 event; 1019 u32 event_ctx; 1020 }; 1021 1022 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1023 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1024 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1025 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1026 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1027 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1028 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1029 u16 admin_req_sz, u8 ignore_reset); 1030 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1031 struct op_req_qinfo *opreqq, u8 *req); 1032 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1033 dma_addr_t dma_addr); 1034 void mpi3mr_build_zero_len_sge(void *paddr); 1035 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1036 dma_addr_t phys_addr); 1037 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1038 dma_addr_t phys_addr); 1039 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1040 u64 sense_buf_dma); 1041 1042 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1043 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1044 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1045 struct mpi3_event_notification_reply *event_reply); 1046 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1047 struct mpi3_default_reply_descriptor *reply_desc, 1048 u64 *reply_dma, u16 qidx); 1049 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1050 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1051 1052 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1053 u32 reset_reason, u8 snapdump); 1054 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1055 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1056 1057 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1058 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1059 u32 event_ctx); 1060 1061 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1062 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1063 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1064 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1065 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1066 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1067 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1068 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1069 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1070 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1071 struct op_reply_qinfo *op_reply_q); 1072 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1073 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1074 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1075 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1076 u16 handle, uint lun, u16 htag, ulong timeout, 1077 struct mpi3mr_drv_cmd *drv_cmd, 1078 u8 *resp_code, struct scsi_cmnd *scmd); 1079 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1080 struct mpi3mr_ioc *mrioc, u16 handle); 1081 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1082 struct mpi3mr_drv_cmd *drv_cmd); 1083 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1084 struct mpi3mr_drv_cmd *drv_cmd); 1085 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1086 u16 event_data_size); 1087 extern const struct attribute_group *mpi3mr_host_groups[]; 1088 extern const struct attribute_group *mpi3mr_dev_groups[]; 1089 #endif /*MPI3MR_H_INCLUDED*/ 1090