1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_image.h" 44 #include "mpi/mpi30_init.h" 45 #include "mpi/mpi30_ioc.h" 46 #include "mpi3mr_debug.h" 47 48 /* Global list and lock for storing multiple adapters managed by the driver */ 49 extern spinlock_t mrioc_list_lock; 50 extern struct list_head mrioc_list; 51 52 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 53 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 54 55 #define MPI3MR_DRIVER_NAME "mpi3mr" 56 #define MPI3MR_DRIVER_LICENSE "GPL" 57 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 58 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 59 60 #define MPI3MR_NAME_LENGTH 32 61 #define IOCNAME "%s: " 62 63 /* Definitions for internal SGL and Chain SGL buffers */ 64 #define MPI3MR_PAGE_SIZE_4K 4096 65 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 66 67 /* Definitions for MAX values for shost */ 68 #define MPI3MR_MAX_CMDS_LUN 7 69 #define MPI3MR_MAX_CDB_LENGTH 32 70 71 /* Admin queue management definitions */ 72 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 73 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 74 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 75 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 76 77 /* Operational queue management definitions */ 78 #define MPI3MR_OP_REQ_Q_QD 512 79 #define MPI3MR_OP_REP_Q_QD 4096 80 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 81 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 82 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 83 84 /* Reserved Host Tag definitions */ 85 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 86 #define MPI3MR_HOSTTAG_INITCMDS 1 87 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 88 #define MPI3MR_HOSTTAG_BLK_TMS 5 89 90 #define MPI3MR_NUM_DEVRMCMD 1 91 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 92 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 93 MPI3MR_NUM_DEVRMCMD - 1) 94 95 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 96 97 /* Reduced resource count definition for crash kernel */ 98 #define MPI3MR_HOST_IOS_KDUMP 128 99 100 /* command/controller interaction timeout definitions in seconds */ 101 #define MPI3MR_INTADMCMD_TIMEOUT 10 102 #define MPI3MR_RESETTM_TIMEOUT 30 103 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 104 105 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 106 107 /* Internal admin command state definitions*/ 108 #define MPI3MR_CMD_NOTUSED 0x8000 109 #define MPI3MR_CMD_COMPLETE 0x0001 110 #define MPI3MR_CMD_PENDING 0x0002 111 #define MPI3MR_CMD_REPLY_VALID 0x0004 112 #define MPI3MR_CMD_RESET 0x0008 113 114 /* Definitions for Event replies and sense buffer allocated per controller */ 115 #define MPI3MR_NUM_EVT_REPLIES 64 116 #define MPI3MR_SENSEBUF_SZ 256 117 #define MPI3MR_SENSEBUF_FACTOR 3 118 #define MPI3MR_CHAINBUF_FACTOR 3 119 120 /* Invalid target device handle */ 121 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 122 123 /* Controller Reset related definitions */ 124 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 125 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 126 127 /* ResponseCode definitions */ 128 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 129 #define MPI3MR_RSP_TM_COMPLETE 0x00 130 #define MPI3MR_RSP_INVALID_FRAME 0x02 131 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 132 #define MPI3MR_RSP_TM_FAILED 0x05 133 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 134 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 135 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 136 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 137 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 138 139 /* SGE Flag definition */ 140 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 141 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 142 MPI3_SGE_FLAGS_END_OF_LIST) 143 144 /* MSI Index from Reply Queue Index */ 145 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 146 147 /* IOC State definitions */ 148 enum mpi3mr_iocstate { 149 MRIOC_STATE_READY = 1, 150 MRIOC_STATE_RESET, 151 MRIOC_STATE_FAULT, 152 MRIOC_STATE_BECOMING_READY, 153 MRIOC_STATE_RESET_REQUESTED, 154 MRIOC_STATE_UNRECOVERABLE, 155 }; 156 157 /* Reset reason code definitions*/ 158 enum mpi3mr_reset_reason { 159 MPI3MR_RESET_FROM_BRINGUP = 1, 160 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 161 MPI3MR_RESET_FROM_IOCTL = 3, 162 MPI3MR_RESET_FROM_EH_HOS = 4, 163 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 164 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 165 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 166 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 167 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 168 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 169 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 170 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 171 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 172 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 173 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 174 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 175 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 176 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 177 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 178 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 179 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 180 }; 181 182 /** 183 * struct mpi3mr_compimg_ver - replica of component image 184 * version defined in mpi30_image.h in host endianness 185 * 186 */ 187 struct mpi3mr_compimg_ver { 188 u16 build_num; 189 u16 cust_id; 190 u8 ph_minor; 191 u8 ph_major; 192 u8 gen_minor; 193 u8 gen_major; 194 }; 195 196 /** 197 * struct mpi3mr_ioc_facs - replica of component image version 198 * defined in mpi30_ioc.h in host endianness 199 * 200 */ 201 struct mpi3mr_ioc_facts { 202 u32 ioc_capabilities; 203 struct mpi3mr_compimg_ver fw_ver; 204 u32 mpi_version; 205 u16 max_reqs; 206 u16 product_id; 207 u16 op_req_sz; 208 u16 reply_sz; 209 u16 exceptions; 210 u16 max_perids; 211 u16 max_pds; 212 u16 max_sasexpanders; 213 u16 max_sasinitiators; 214 u16 max_enclosures; 215 u16 max_pcie_switches; 216 u16 max_nvme; 217 u16 max_vds; 218 u16 max_hpds; 219 u16 max_advhpds; 220 u16 max_raidpds; 221 u16 min_devhandle; 222 u16 max_devhandle; 223 u16 max_op_req_q; 224 u16 max_op_reply_q; 225 u16 shutdown_timeout; 226 u8 ioc_num; 227 u8 who_init; 228 u16 max_msix_vectors; 229 u8 personality; 230 u8 dma_mask; 231 u8 protocol_flags; 232 u8 sge_mod_mask; 233 u8 sge_mod_value; 234 u8 sge_mod_shift; 235 }; 236 237 /** 238 * struct segments - memory descriptor structure to store 239 * virtual and dma addresses for operational queue segments. 240 * 241 * @segment: virtual address 242 * @segment_dma: dma address 243 */ 244 struct segments { 245 void *segment; 246 dma_addr_t segment_dma; 247 }; 248 249 /** 250 * struct op_req_qinfo - Operational Request Queue Information 251 * 252 * @ci: consumer index 253 * @pi: producer index 254 * @num_request: Maximum number of entries in the queue 255 * @qid: Queue Id starting from 1 256 * @reply_qid: Associated reply queue Id 257 * @num_segments: Number of discontiguous memory segments 258 * @segment_qd: Depth of each segments 259 * @q_lock: Concurrent queue access lock 260 * @q_segments: Segment descriptor pointer 261 * @q_segment_list: Segment list base virtual address 262 * @q_segment_list_dma: Segment list base DMA address 263 */ 264 struct op_req_qinfo { 265 u16 ci; 266 u16 pi; 267 u16 num_requests; 268 u16 qid; 269 u16 reply_qid; 270 u16 num_segments; 271 u16 segment_qd; 272 spinlock_t q_lock; 273 struct segments *q_segments; 274 void *q_segment_list; 275 dma_addr_t q_segment_list_dma; 276 }; 277 278 /** 279 * struct op_reply_qinfo - Operational Reply Queue Information 280 * 281 * @ci: consumer index 282 * @qid: Queue Id starting from 1 283 * @num_replies: Maximum number of entries in the queue 284 * @num_segments: Number of discontiguous memory segments 285 * @segment_qd: Depth of each segments 286 * @q_segments: Segment descriptor pointer 287 * @q_segment_list: Segment list base virtual address 288 * @q_segment_list_dma: Segment list base DMA address 289 * @ephase: Expected phased identifier for the reply queue 290 */ 291 struct op_reply_qinfo { 292 u16 ci; 293 u16 qid; 294 u16 num_replies; 295 u16 num_segments; 296 u16 segment_qd; 297 struct segments *q_segments; 298 void *q_segment_list; 299 dma_addr_t q_segment_list_dma; 300 u8 ephase; 301 }; 302 303 /** 304 * struct mpi3mr_intr_info - Interrupt cookie information 305 * 306 * @mrioc: Adapter instance reference 307 * @msix_index: MSIx index 308 * @op_reply_q: Associated operational reply queue 309 * @name: Dev name for the irq claiming device 310 */ 311 struct mpi3mr_intr_info { 312 struct mpi3mr_ioc *mrioc; 313 u16 msix_index; 314 struct op_reply_qinfo *op_reply_q; 315 char name[MPI3MR_NAME_LENGTH]; 316 }; 317 318 319 320 /** 321 * struct mpi3mr_drv_cmd - Internal command tracker 322 * 323 * @mutex: Command mutex 324 * @done: Completeor for wakeup 325 * @reply: Firmware reply for internal commands 326 * @sensebuf: Sensebuf for SCSI IO commands 327 * @state: Command State 328 * @dev_handle: Firmware handle for device specific commands 329 * @ioc_status: IOC status from the firmware 330 * @ioc_loginfo:IOC log info from the firmware 331 * @is_waiting: Is the command issued in block mode 332 * @retry_count: Retry count for retriable commands 333 * @host_tag: Host tag used by the command 334 * @callback: Callback for non blocking commands 335 */ 336 struct mpi3mr_drv_cmd { 337 struct mutex mutex; 338 struct completion done; 339 void *reply; 340 u8 *sensebuf; 341 u16 state; 342 u16 dev_handle; 343 u16 ioc_status; 344 u32 ioc_loginfo; 345 u8 is_waiting; 346 u8 retry_count; 347 u16 host_tag; 348 349 void (*callback)(struct mpi3mr_ioc *mrioc, 350 struct mpi3mr_drv_cmd *drv_cmd); 351 }; 352 353 354 /** 355 * struct chain_element - memory descriptor structure to store 356 * virtual and dma addresses for chain elements. 357 * 358 * @addr: virtual address 359 * @dma_addr: dma address 360 */ 361 struct chain_element { 362 void *addr; 363 dma_addr_t dma_addr; 364 }; 365 366 /** 367 * struct scmd_priv - SCSI command private data 368 * 369 * @host_tag: Host tag specific to operational queue 370 * @in_lld_scope: Command in LLD scope or not 371 * @scmd: SCSI Command pointer 372 * @req_q_idx: Operational request queue index 373 * @chain_idx: Chain frame index 374 * @mpi3mr_scsiio_req: MPI SCSI IO request 375 */ 376 struct scmd_priv { 377 u16 host_tag; 378 u8 in_lld_scope; 379 struct scsi_cmnd *scmd; 380 u16 req_q_idx; 381 int chain_idx; 382 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 383 }; 384 385 /** 386 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 387 * private data 388 * 389 * @list: List pointer 390 * @pdev: PCI device pointer 391 * @shost: Scsi_Host pointer 392 * @id: Controller ID 393 * @cpu_count: Number of online CPUs 394 * @name: Controller ASCII name 395 * @driver_name: Driver ASCII name 396 * @sysif_regs: System interface registers virtual address 397 * @sysif_regs_phys: System interface registers physical address 398 * @bars: PCI BARS 399 * @dma_mask: DMA mask 400 * @msix_count: Number of MSIX vectors used 401 * @intr_enabled: Is interrupts enabled 402 * @num_admin_req: Number of admin requests 403 * @admin_req_q_sz: Admin request queue size 404 * @admin_req_pi: Admin request queue producer index 405 * @admin_req_ci: Admin request queue consumer index 406 * @admin_req_base: Admin request queue base virtual address 407 * @admin_req_dma: Admin request queue base dma address 408 * @admin_req_lock: Admin queue access lock 409 * @num_admin_replies: Number of admin replies 410 * @admin_reply_q_sz: Admin reply queue size 411 * @admin_reply_ci: Admin reply queue consumer index 412 * @admin_reply_ephase:Admin reply queue expected phase 413 * @admin_reply_base: Admin reply queue base virtual address 414 * @admin_reply_dma: Admin reply queue base dma address 415 * @ready_timeout: Controller ready timeout 416 * @intr_info: Interrupt cookie pointer 417 * @intr_info_count: Number of interrupt cookies 418 * @num_queues: Number of operational queues 419 * @num_op_req_q: Number of operational request queues 420 * @req_qinfo: Operational request queue info pointer 421 * @num_op_reply_q: Number of operational reply queues 422 * @op_reply_qinfo: Operational reply queue info pointer 423 * @init_cmds: Command tracker for initialization commands 424 * @facts: Cached IOC facts data 425 * @op_reply_desc_sz: Operational reply descriptor size 426 * @num_reply_bufs: Number of reply buffers allocated 427 * @reply_buf_pool: Reply buffer pool 428 * @reply_buf: Reply buffer base virtual address 429 * @reply_buf_dma: Reply buffer DMA address 430 * @reply_buf_dma_max_address: Reply DMA address max limit 431 * @reply_free_qsz: Reply free queue size 432 * @reply_free_q_pool: Reply free queue pool 433 * @reply_free_q: Reply free queue base virtual address 434 * @reply_free_q_dma: Reply free queue base DMA address 435 * @reply_free_queue_lock: Reply free queue lock 436 * @reply_free_queue_host_index: Reply free queue host index 437 * @num_sense_bufs: Number of sense buffers 438 * @sense_buf_pool: Sense buffer pool 439 * @sense_buf: Sense buffer base virtual address 440 * @sense_buf_dma: Sense buffer base DMA address 441 * @sense_buf_q_sz: Sense buffer queue size 442 * @sense_buf_q_pool: Sense buffer queue pool 443 * @sense_buf_q: Sense buffer queue virtual address 444 * @sense_buf_q_dma: Sense buffer queue DMA address 445 * @sbq_lock: Sense buffer queue lock 446 * @sbq_host_index: Sense buffer queuehost index 447 * @is_driver_loading: Is driver still loading 448 * @max_host_ios: Maximum host I/O count 449 * @chain_buf_count: Chain buffer count 450 * @chain_buf_pool: Chain buffer pool 451 * @chain_sgl_list: Chain SGL list 452 * @chain_bitmap_sz: Chain buffer allocator bitmap size 453 * @chain_bitmap: Chain buffer allocator bitmap 454 * @reset_in_progress: Reset in progress flag 455 * @unrecoverable: Controller unrecoverable flag 456 * @logging_level: Controller debug logging level 457 * @current_event: Firmware event currently in process 458 * @driver_info: Driver, Kernel, OS information to firmware 459 * @change_count: Topology change count 460 * @op_reply_q_offset: Operational reply queue offset with MSIx 461 */ 462 struct mpi3mr_ioc { 463 struct list_head list; 464 struct pci_dev *pdev; 465 struct Scsi_Host *shost; 466 u8 id; 467 int cpu_count; 468 bool enable_segqueue; 469 470 char name[MPI3MR_NAME_LENGTH]; 471 char driver_name[MPI3MR_NAME_LENGTH]; 472 473 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 474 resource_size_t sysif_regs_phys; 475 int bars; 476 u64 dma_mask; 477 478 u16 msix_count; 479 u8 intr_enabled; 480 481 u16 num_admin_req; 482 u32 admin_req_q_sz; 483 u16 admin_req_pi; 484 u16 admin_req_ci; 485 void *admin_req_base; 486 dma_addr_t admin_req_dma; 487 spinlock_t admin_req_lock; 488 489 u16 num_admin_replies; 490 u32 admin_reply_q_sz; 491 u16 admin_reply_ci; 492 u8 admin_reply_ephase; 493 void *admin_reply_base; 494 dma_addr_t admin_reply_dma; 495 496 u32 ready_timeout; 497 498 struct mpi3mr_intr_info *intr_info; 499 u16 intr_info_count; 500 501 u16 num_queues; 502 u16 num_op_req_q; 503 struct op_req_qinfo *req_qinfo; 504 505 u16 num_op_reply_q; 506 struct op_reply_qinfo *op_reply_qinfo; 507 508 struct mpi3mr_drv_cmd init_cmds; 509 struct mpi3mr_ioc_facts facts; 510 u16 op_reply_desc_sz; 511 512 u32 num_reply_bufs; 513 struct dma_pool *reply_buf_pool; 514 u8 *reply_buf; 515 dma_addr_t reply_buf_dma; 516 dma_addr_t reply_buf_dma_max_address; 517 518 u16 reply_free_qsz; 519 struct dma_pool *reply_free_q_pool; 520 __le64 *reply_free_q; 521 dma_addr_t reply_free_q_dma; 522 spinlock_t reply_free_queue_lock; 523 u32 reply_free_queue_host_index; 524 525 u32 num_sense_bufs; 526 struct dma_pool *sense_buf_pool; 527 u8 *sense_buf; 528 dma_addr_t sense_buf_dma; 529 530 u16 sense_buf_q_sz; 531 struct dma_pool *sense_buf_q_pool; 532 __le64 *sense_buf_q; 533 dma_addr_t sense_buf_q_dma; 534 spinlock_t sbq_lock; 535 u32 sbq_host_index; 536 537 u8 is_driver_loading; 538 539 u16 max_host_ios; 540 541 u32 chain_buf_count; 542 struct dma_pool *chain_buf_pool; 543 struct chain_element *chain_sgl_list; 544 u16 chain_bitmap_sz; 545 void *chain_bitmap; 546 547 u8 reset_in_progress; 548 u8 unrecoverable; 549 550 int logging_level; 551 552 struct mpi3mr_fwevt *current_event; 553 struct mpi3_driver_info_layout driver_info; 554 u16 change_count; 555 u16 op_reply_q_offset; 556 }; 557 558 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 559 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 560 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 561 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 562 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 563 u16 admin_req_sz, u8 ignore_reset); 564 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 565 dma_addr_t dma_addr); 566 void mpi3mr_build_zero_len_sge(void *paddr); 567 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 568 dma_addr_t phys_addr); 569 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 570 dma_addr_t phys_addr); 571 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 572 u64 sense_buf_dma); 573 574 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 575 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 576 577 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 578 u32 reset_reason, u8 snapdump); 579 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 580 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 581 582 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 583 584 #endif /*MPI3MR_H_INCLUDED*/ 585