1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_cnfg.h" 44 #include "mpi/mpi30_image.h" 45 #include "mpi/mpi30_init.h" 46 #include "mpi/mpi30_ioc.h" 47 #include "mpi/mpi30_sas.h" 48 #include "mpi/mpi30_pci.h" 49 #include "mpi3mr_debug.h" 50 51 /* Global list and lock for storing multiple adapters managed by the driver */ 52 extern spinlock_t mrioc_list_lock; 53 extern struct list_head mrioc_list; 54 extern int prot_mask; 55 56 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 57 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 58 59 #define MPI3MR_DRIVER_NAME "mpi3mr" 60 #define MPI3MR_DRIVER_LICENSE "GPL" 61 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 62 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 63 64 #define MPI3MR_NAME_LENGTH 32 65 #define IOCNAME "%s: " 66 67 /* Definitions for internal SGL and Chain SGL buffers */ 68 #define MPI3MR_PAGE_SIZE_4K 4096 69 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 70 71 /* Definitions for MAX values for shost */ 72 #define MPI3MR_MAX_CMDS_LUN 7 73 #define MPI3MR_MAX_CDB_LENGTH 32 74 75 /* Admin queue management definitions */ 76 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 77 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 78 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 79 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 80 81 /* Operational queue management definitions */ 82 #define MPI3MR_OP_REQ_Q_QD 512 83 #define MPI3MR_OP_REP_Q_QD 4096 84 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 85 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 86 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 87 88 /* Reserved Host Tag definitions */ 89 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 90 #define MPI3MR_HOSTTAG_INITCMDS 1 91 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 92 #define MPI3MR_HOSTTAG_BLK_TMS 5 93 94 #define MPI3MR_NUM_DEVRMCMD 16 95 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 96 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 97 MPI3MR_NUM_DEVRMCMD - 1) 98 99 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 100 101 /* Reduced resource count definition for crash kernel */ 102 #define MPI3MR_HOST_IOS_KDUMP 128 103 104 /* command/controller interaction timeout definitions in seconds */ 105 #define MPI3MR_INTADMCMD_TIMEOUT 60 106 #define MPI3MR_PORTENABLE_TIMEOUT 300 107 #define MPI3MR_ABORTTM_TIMEOUT 60 108 #define MPI3MR_RESETTM_TIMEOUT 60 109 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 110 #define MPI3MR_TSUPDATE_INTERVAL 900 111 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 112 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 113 #define MPI3MR_RESET_ACK_TIMEOUT 30 114 115 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 116 117 /* Internal admin command state definitions*/ 118 #define MPI3MR_CMD_NOTUSED 0x8000 119 #define MPI3MR_CMD_COMPLETE 0x0001 120 #define MPI3MR_CMD_PENDING 0x0002 121 #define MPI3MR_CMD_REPLY_VALID 0x0004 122 #define MPI3MR_CMD_RESET 0x0008 123 124 /* Definitions for Event replies and sense buffer allocated per controller */ 125 #define MPI3MR_NUM_EVT_REPLIES 64 126 #define MPI3MR_SENSE_BUF_SZ 256 127 #define MPI3MR_SENSEBUF_FACTOR 3 128 #define MPI3MR_CHAINBUF_FACTOR 3 129 #define MPI3MR_CHAINBUFDIX_FACTOR 2 130 131 /* Invalid target device handle */ 132 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 133 134 /* Controller Reset related definitions */ 135 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 136 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 137 138 /* ResponseCode definitions */ 139 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 140 #define MPI3MR_RSP_TM_COMPLETE 0x00 141 #define MPI3MR_RSP_INVALID_FRAME 0x02 142 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 143 #define MPI3MR_RSP_TM_FAILED 0x05 144 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 145 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 146 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 147 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 148 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 149 150 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 151 #define MPI3MR_DEFAULT_PGSZEXP (12) 152 /* Command retry count definitions */ 153 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 154 155 /* Default target device queue depth */ 156 #define MPI3MR_DEFAULT_SDEV_QD 32 157 158 /* Definitions for Threaded IRQ poll*/ 159 #define MPI3MR_IRQ_POLL_SLEEP 2 160 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 161 162 /* Definitions for the controller security status*/ 163 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 164 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 165 166 #define MPI3MR_INVALID_DEVICE 0x00 167 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 168 #define MPI3MR_HARD_SECURE_DEVICE 0x08 169 #define MPI3MR_TAMPERED_DEVICE 0x0C 170 171 /* SGE Flag definition */ 172 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 173 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 174 MPI3_SGE_FLAGS_END_OF_LIST) 175 176 /* MSI Index from Reply Queue Index */ 177 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 178 179 /* IOC State definitions */ 180 enum mpi3mr_iocstate { 181 MRIOC_STATE_READY = 1, 182 MRIOC_STATE_RESET, 183 MRIOC_STATE_FAULT, 184 MRIOC_STATE_BECOMING_READY, 185 MRIOC_STATE_RESET_REQUESTED, 186 MRIOC_STATE_UNRECOVERABLE, 187 }; 188 189 /* Reset reason code definitions*/ 190 enum mpi3mr_reset_reason { 191 MPI3MR_RESET_FROM_BRINGUP = 1, 192 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 193 MPI3MR_RESET_FROM_IOCTL = 3, 194 MPI3MR_RESET_FROM_EH_HOS = 4, 195 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 196 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 197 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 198 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 199 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 200 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 201 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 202 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 203 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 204 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 205 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 206 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 207 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 208 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 209 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 210 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 211 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 212 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 213 MPI3MR_RESET_FROM_SYSFS = 23, 214 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 215 MPI3MR_RESET_FROM_FIRMWARE = 27, 216 }; 217 218 /** 219 * struct mpi3mr_compimg_ver - replica of component image 220 * version defined in mpi30_image.h in host endianness 221 * 222 */ 223 struct mpi3mr_compimg_ver { 224 u16 build_num; 225 u16 cust_id; 226 u8 ph_minor; 227 u8 ph_major; 228 u8 gen_minor; 229 u8 gen_major; 230 }; 231 232 /** 233 * struct mpi3mr_ioc_facs - replica of component image version 234 * defined in mpi30_ioc.h in host endianness 235 * 236 */ 237 struct mpi3mr_ioc_facts { 238 u32 ioc_capabilities; 239 struct mpi3mr_compimg_ver fw_ver; 240 u32 mpi_version; 241 u16 max_reqs; 242 u16 product_id; 243 u16 op_req_sz; 244 u16 reply_sz; 245 u16 exceptions; 246 u16 max_perids; 247 u16 max_pds; 248 u16 max_sasexpanders; 249 u16 max_sasinitiators; 250 u16 max_enclosures; 251 u16 max_pcie_switches; 252 u16 max_nvme; 253 u16 max_vds; 254 u16 max_hpds; 255 u16 max_advhpds; 256 u16 max_raid_pds; 257 u16 min_devhandle; 258 u16 max_devhandle; 259 u16 max_op_req_q; 260 u16 max_op_reply_q; 261 u16 shutdown_timeout; 262 u8 ioc_num; 263 u8 who_init; 264 u16 max_msix_vectors; 265 u8 personality; 266 u8 dma_mask; 267 u8 protocol_flags; 268 u8 sge_mod_mask; 269 u8 sge_mod_value; 270 u8 sge_mod_shift; 271 }; 272 273 /** 274 * struct segments - memory descriptor structure to store 275 * virtual and dma addresses for operational queue segments. 276 * 277 * @segment: virtual address 278 * @segment_dma: dma address 279 */ 280 struct segments { 281 void *segment; 282 dma_addr_t segment_dma; 283 }; 284 285 /** 286 * struct op_req_qinfo - Operational Request Queue Information 287 * 288 * @ci: consumer index 289 * @pi: producer index 290 * @num_request: Maximum number of entries in the queue 291 * @qid: Queue Id starting from 1 292 * @reply_qid: Associated reply queue Id 293 * @num_segments: Number of discontiguous memory segments 294 * @segment_qd: Depth of each segments 295 * @q_lock: Concurrent queue access lock 296 * @q_segments: Segment descriptor pointer 297 * @q_segment_list: Segment list base virtual address 298 * @q_segment_list_dma: Segment list base DMA address 299 */ 300 struct op_req_qinfo { 301 u16 ci; 302 u16 pi; 303 u16 num_requests; 304 u16 qid; 305 u16 reply_qid; 306 u16 num_segments; 307 u16 segment_qd; 308 spinlock_t q_lock; 309 struct segments *q_segments; 310 void *q_segment_list; 311 dma_addr_t q_segment_list_dma; 312 }; 313 314 /** 315 * struct op_reply_qinfo - Operational Reply Queue Information 316 * 317 * @ci: consumer index 318 * @qid: Queue Id starting from 1 319 * @num_replies: Maximum number of entries in the queue 320 * @num_segments: Number of discontiguous memory segments 321 * @segment_qd: Depth of each segments 322 * @q_segments: Segment descriptor pointer 323 * @q_segment_list: Segment list base virtual address 324 * @q_segment_list_dma: Segment list base DMA address 325 * @ephase: Expected phased identifier for the reply queue 326 * @pend_ios: Number of IOs pending in HW for this queue 327 * @enable_irq_poll: Flag to indicate polling is enabled 328 * @in_use: Queue is handled by poll/ISR 329 */ 330 struct op_reply_qinfo { 331 u16 ci; 332 u16 qid; 333 u16 num_replies; 334 u16 num_segments; 335 u16 segment_qd; 336 struct segments *q_segments; 337 void *q_segment_list; 338 dma_addr_t q_segment_list_dma; 339 u8 ephase; 340 atomic_t pend_ios; 341 bool enable_irq_poll; 342 atomic_t in_use; 343 }; 344 345 /** 346 * struct mpi3mr_intr_info - Interrupt cookie information 347 * 348 * @mrioc: Adapter instance reference 349 * @msix_index: MSIx index 350 * @op_reply_q: Associated operational reply queue 351 * @name: Dev name for the irq claiming device 352 */ 353 struct mpi3mr_intr_info { 354 struct mpi3mr_ioc *mrioc; 355 u16 msix_index; 356 struct op_reply_qinfo *op_reply_q; 357 char name[MPI3MR_NAME_LENGTH]; 358 }; 359 360 /** 361 * struct tgt_dev_sas_sata - SAS/SATA device specific 362 * information cached from firmware given data 363 * 364 * @sas_address: World wide unique SAS address 365 * @dev_info: Device information bits 366 */ 367 struct tgt_dev_sas_sata { 368 u64 sas_address; 369 u16 dev_info; 370 }; 371 372 /** 373 * struct tgt_dev_pcie - PCIe device specific information cached 374 * from firmware given data 375 * 376 * @mdts: Maximum data transfer size 377 * @capb: Device capabilities 378 * @pgsz: Device page size 379 * @abort_to: Timeout for abort TM 380 * @reset_to: Timeout for Target/LUN reset TM 381 * @dev_info: Device information bits 382 */ 383 struct tgt_dev_pcie { 384 u32 mdts; 385 u16 capb; 386 u8 pgsz; 387 u8 abort_to; 388 u8 reset_to; 389 u16 dev_info; 390 }; 391 392 /** 393 * struct tgt_dev_volume - virtual device specific information 394 * cached from firmware given data 395 * 396 * @state: State of the VD 397 */ 398 struct tgt_dev_volume { 399 u8 state; 400 }; 401 402 /** 403 * union _form_spec_inf - union of device specific information 404 */ 405 union _form_spec_inf { 406 struct tgt_dev_sas_sata sas_sata_inf; 407 struct tgt_dev_pcie pcie_inf; 408 struct tgt_dev_volume vol_inf; 409 }; 410 411 412 413 /** 414 * struct mpi3mr_tgt_dev - target device data structure 415 * 416 * @list: List pointer 417 * @starget: Scsi_target pointer 418 * @dev_handle: FW device handle 419 * @parent_handle: FW parent device handle 420 * @slot: Slot number 421 * @encl_handle: FW enclosure handle 422 * @perst_id: FW assigned Persistent ID 423 * @dev_type: SAS/SATA/PCIE device type 424 * @is_hidden: Should be exposed to upper layers or not 425 * @host_exposed: Already exposed to host or not 426 * @q_depth: Device specific Queue Depth 427 * @wwid: World wide ID 428 * @dev_spec: Device type specific information 429 * @ref_count: Reference count 430 */ 431 struct mpi3mr_tgt_dev { 432 struct list_head list; 433 struct scsi_target *starget; 434 u16 dev_handle; 435 u16 parent_handle; 436 u16 slot; 437 u16 encl_handle; 438 u16 perst_id; 439 u8 dev_type; 440 u8 is_hidden; 441 u8 host_exposed; 442 u16 q_depth; 443 u64 wwid; 444 union _form_spec_inf dev_spec; 445 struct kref ref_count; 446 }; 447 448 /** 449 * mpi3mr_tgtdev_get - k reference incrementor 450 * @s: Target device reference 451 * 452 * Increment target device reference count. 453 */ 454 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 455 { 456 kref_get(&s->ref_count); 457 } 458 459 /** 460 * mpi3mr_free_tgtdev - target device memory dealloctor 461 * @r: k reference pointer of the target device 462 * 463 * Free target device memory when no reference. 464 */ 465 static inline void mpi3mr_free_tgtdev(struct kref *r) 466 { 467 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 468 } 469 470 /** 471 * mpi3mr_tgtdev_put - k reference decrementor 472 * @s: Target device reference 473 * 474 * Decrement target device reference count. 475 */ 476 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 477 { 478 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 479 } 480 481 482 /** 483 * struct mpi3mr_stgt_priv_data - SCSI target private structure 484 * 485 * @starget: Scsi_target pointer 486 * @dev_handle: FW device handle 487 * @perst_id: FW assigned Persistent ID 488 * @num_luns: Number of Logical Units 489 * @block_io: I/O blocked to the device or not 490 * @dev_removed: Device removed in the Firmware 491 * @dev_removedelay: Device is waiting to be removed in FW 492 * @dev_type: Device type 493 * @tgt_dev: Internal target device pointer 494 */ 495 struct mpi3mr_stgt_priv_data { 496 struct scsi_target *starget; 497 u16 dev_handle; 498 u16 perst_id; 499 u32 num_luns; 500 atomic_t block_io; 501 u8 dev_removed; 502 u8 dev_removedelay; 503 u8 dev_type; 504 struct mpi3mr_tgt_dev *tgt_dev; 505 }; 506 507 /** 508 * struct mpi3mr_stgt_priv_data - SCSI device private structure 509 * 510 * @tgt_priv_data: Scsi_target private data pointer 511 * @lun_id: LUN ID of the device 512 * @ncq_prio_enable: NCQ priority enable for SATA device 513 */ 514 struct mpi3mr_sdev_priv_data { 515 struct mpi3mr_stgt_priv_data *tgt_priv_data; 516 u32 lun_id; 517 u8 ncq_prio_enable; 518 }; 519 520 /** 521 * struct mpi3mr_drv_cmd - Internal command tracker 522 * 523 * @mutex: Command mutex 524 * @done: Completeor for wakeup 525 * @reply: Firmware reply for internal commands 526 * @sensebuf: Sensebuf for SCSI IO commands 527 * @iou_rc: IO Unit control reason code 528 * @state: Command State 529 * @dev_handle: Firmware handle for device specific commands 530 * @ioc_status: IOC status from the firmware 531 * @ioc_loginfo:IOC log info from the firmware 532 * @is_waiting: Is the command issued in block mode 533 * @retry_count: Retry count for retriable commands 534 * @host_tag: Host tag used by the command 535 * @callback: Callback for non blocking commands 536 */ 537 struct mpi3mr_drv_cmd { 538 struct mutex mutex; 539 struct completion done; 540 void *reply; 541 u8 *sensebuf; 542 u8 iou_rc; 543 u16 state; 544 u16 dev_handle; 545 u16 ioc_status; 546 u32 ioc_loginfo; 547 u8 is_waiting; 548 u8 retry_count; 549 u16 host_tag; 550 551 void (*callback)(struct mpi3mr_ioc *mrioc, 552 struct mpi3mr_drv_cmd *drv_cmd); 553 }; 554 555 556 /** 557 * struct chain_element - memory descriptor structure to store 558 * virtual and dma addresses for chain elements. 559 * 560 * @addr: virtual address 561 * @dma_addr: dma address 562 */ 563 struct chain_element { 564 void *addr; 565 dma_addr_t dma_addr; 566 }; 567 568 /** 569 * struct scmd_priv - SCSI command private data 570 * 571 * @host_tag: Host tag specific to operational queue 572 * @in_lld_scope: Command in LLD scope or not 573 * @meta_sg_valid: DIX command with meta data SGL or not 574 * @scmd: SCSI Command pointer 575 * @req_q_idx: Operational request queue index 576 * @chain_idx: Chain frame index 577 * @meta_chain_idx: Chain frame index of meta data SGL 578 * @mpi3mr_scsiio_req: MPI SCSI IO request 579 */ 580 struct scmd_priv { 581 u16 host_tag; 582 u8 in_lld_scope; 583 u8 meta_sg_valid; 584 struct scsi_cmnd *scmd; 585 u16 req_q_idx; 586 int chain_idx; 587 int meta_chain_idx; 588 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 589 }; 590 591 /** 592 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 593 * private data 594 * 595 * @list: List pointer 596 * @pdev: PCI device pointer 597 * @shost: Scsi_Host pointer 598 * @id: Controller ID 599 * @cpu_count: Number of online CPUs 600 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 601 * @name: Controller ASCII name 602 * @driver_name: Driver ASCII name 603 * @sysif_regs: System interface registers virtual address 604 * @sysif_regs_phys: System interface registers physical address 605 * @bars: PCI BARS 606 * @dma_mask: DMA mask 607 * @msix_count: Number of MSIX vectors used 608 * @intr_enabled: Is interrupts enabled 609 * @num_admin_req: Number of admin requests 610 * @admin_req_q_sz: Admin request queue size 611 * @admin_req_pi: Admin request queue producer index 612 * @admin_req_ci: Admin request queue consumer index 613 * @admin_req_base: Admin request queue base virtual address 614 * @admin_req_dma: Admin request queue base dma address 615 * @admin_req_lock: Admin queue access lock 616 * @num_admin_replies: Number of admin replies 617 * @admin_reply_q_sz: Admin reply queue size 618 * @admin_reply_ci: Admin reply queue consumer index 619 * @admin_reply_ephase:Admin reply queue expected phase 620 * @admin_reply_base: Admin reply queue base virtual address 621 * @admin_reply_dma: Admin reply queue base dma address 622 * @ready_timeout: Controller ready timeout 623 * @intr_info: Interrupt cookie pointer 624 * @intr_info_count: Number of interrupt cookies 625 * @is_intr_info_set: Flag to indicate intr info is setup 626 * @num_queues: Number of operational queues 627 * @num_op_req_q: Number of operational request queues 628 * @req_qinfo: Operational request queue info pointer 629 * @num_op_reply_q: Number of operational reply queues 630 * @op_reply_qinfo: Operational reply queue info pointer 631 * @init_cmds: Command tracker for initialization commands 632 * @facts: Cached IOC facts data 633 * @op_reply_desc_sz: Operational reply descriptor size 634 * @num_reply_bufs: Number of reply buffers allocated 635 * @reply_buf_pool: Reply buffer pool 636 * @reply_buf: Reply buffer base virtual address 637 * @reply_buf_dma: Reply buffer DMA address 638 * @reply_buf_dma_max_address: Reply DMA address max limit 639 * @reply_free_qsz: Reply free queue size 640 * @reply_free_q_pool: Reply free queue pool 641 * @reply_free_q: Reply free queue base virtual address 642 * @reply_free_q_dma: Reply free queue base DMA address 643 * @reply_free_queue_lock: Reply free queue lock 644 * @reply_free_queue_host_index: Reply free queue host index 645 * @num_sense_bufs: Number of sense buffers 646 * @sense_buf_pool: Sense buffer pool 647 * @sense_buf: Sense buffer base virtual address 648 * @sense_buf_dma: Sense buffer base DMA address 649 * @sense_buf_q_sz: Sense buffer queue size 650 * @sense_buf_q_pool: Sense buffer queue pool 651 * @sense_buf_q: Sense buffer queue virtual address 652 * @sense_buf_q_dma: Sense buffer queue DMA address 653 * @sbq_lock: Sense buffer queue lock 654 * @sbq_host_index: Sense buffer queuehost index 655 * @event_masks: Event mask bitmap 656 * @fwevt_worker_name: Firmware event worker thread name 657 * @fwevt_worker_thread: Firmware event worker thread 658 * @fwevt_lock: Firmware event lock 659 * @fwevt_list: Firmware event list 660 * @watchdog_work_q_name: Fault watchdog worker thread name 661 * @watchdog_work_q: Fault watchdog worker thread 662 * @watchdog_work: Fault watchdog work 663 * @watchdog_lock: Fault watchdog lock 664 * @is_driver_loading: Is driver still loading 665 * @scan_started: Async scan started 666 * @scan_failed: Asycn scan failed 667 * @stop_drv_processing: Stop all command processing 668 * @max_host_ios: Maximum host I/O count 669 * @chain_buf_count: Chain buffer count 670 * @chain_buf_pool: Chain buffer pool 671 * @chain_sgl_list: Chain SGL list 672 * @chain_bitmap_sz: Chain buffer allocator bitmap size 673 * @chain_bitmap: Chain buffer allocator bitmap 674 * @chain_buf_lock: Chain buffer list lock 675 * @host_tm_cmds: Command tracker for task management commands 676 * @dev_rmhs_cmds: Command tracker for device removal commands 677 * @devrem_bitmap_sz: Device removal bitmap size 678 * @devrem_bitmap: Device removal bitmap 679 * @dev_handle_bitmap_sz: Device handle bitmap size 680 * @removepend_bitmap: Remove pending bitmap 681 * @delayed_rmhs_list: Delayed device removal list 682 * @ts_update_counter: Timestamp update counter 683 * @reset_in_progress: Reset in progress flag 684 * @unrecoverable: Controller unrecoverable flag 685 * @prev_reset_result: Result of previous reset 686 * @reset_mutex: Controller reset mutex 687 * @reset_waitq: Controller reset wait queue 688 * @diagsave_timeout: Diagnostic information save timeout 689 * @logging_level: Controller debug logging level 690 * @flush_io_count: I/O count to flush after reset 691 * @current_event: Firmware event currently in process 692 * @driver_info: Driver, Kernel, OS information to firmware 693 * @change_count: Topology change count 694 * @op_reply_q_offset: Operational reply queue offset with MSIx 695 */ 696 struct mpi3mr_ioc { 697 struct list_head list; 698 struct pci_dev *pdev; 699 struct Scsi_Host *shost; 700 u8 id; 701 int cpu_count; 702 bool enable_segqueue; 703 u32 irqpoll_sleep; 704 705 char name[MPI3MR_NAME_LENGTH]; 706 char driver_name[MPI3MR_NAME_LENGTH]; 707 708 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 709 resource_size_t sysif_regs_phys; 710 int bars; 711 u64 dma_mask; 712 713 u16 msix_count; 714 u8 intr_enabled; 715 716 u16 num_admin_req; 717 u32 admin_req_q_sz; 718 u16 admin_req_pi; 719 u16 admin_req_ci; 720 void *admin_req_base; 721 dma_addr_t admin_req_dma; 722 spinlock_t admin_req_lock; 723 724 u16 num_admin_replies; 725 u32 admin_reply_q_sz; 726 u16 admin_reply_ci; 727 u8 admin_reply_ephase; 728 void *admin_reply_base; 729 dma_addr_t admin_reply_dma; 730 731 u32 ready_timeout; 732 733 struct mpi3mr_intr_info *intr_info; 734 u16 intr_info_count; 735 bool is_intr_info_set; 736 737 u16 num_queues; 738 u16 num_op_req_q; 739 struct op_req_qinfo *req_qinfo; 740 741 u16 num_op_reply_q; 742 struct op_reply_qinfo *op_reply_qinfo; 743 744 struct mpi3mr_drv_cmd init_cmds; 745 struct mpi3mr_ioc_facts facts; 746 u16 op_reply_desc_sz; 747 748 u32 num_reply_bufs; 749 struct dma_pool *reply_buf_pool; 750 u8 *reply_buf; 751 dma_addr_t reply_buf_dma; 752 dma_addr_t reply_buf_dma_max_address; 753 754 u16 reply_free_qsz; 755 struct dma_pool *reply_free_q_pool; 756 __le64 *reply_free_q; 757 dma_addr_t reply_free_q_dma; 758 spinlock_t reply_free_queue_lock; 759 u32 reply_free_queue_host_index; 760 761 u32 num_sense_bufs; 762 struct dma_pool *sense_buf_pool; 763 u8 *sense_buf; 764 dma_addr_t sense_buf_dma; 765 766 u16 sense_buf_q_sz; 767 struct dma_pool *sense_buf_q_pool; 768 __le64 *sense_buf_q; 769 dma_addr_t sense_buf_q_dma; 770 spinlock_t sbq_lock; 771 u32 sbq_host_index; 772 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 773 774 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 775 struct workqueue_struct *fwevt_worker_thread; 776 spinlock_t fwevt_lock; 777 struct list_head fwevt_list; 778 779 char watchdog_work_q_name[20]; 780 struct workqueue_struct *watchdog_work_q; 781 struct delayed_work watchdog_work; 782 spinlock_t watchdog_lock; 783 784 u8 is_driver_loading; 785 u8 scan_started; 786 u16 scan_failed; 787 u8 stop_drv_processing; 788 789 u16 max_host_ios; 790 spinlock_t tgtdev_lock; 791 struct list_head tgtdev_list; 792 793 u32 chain_buf_count; 794 struct dma_pool *chain_buf_pool; 795 struct chain_element *chain_sgl_list; 796 u16 chain_bitmap_sz; 797 void *chain_bitmap; 798 spinlock_t chain_buf_lock; 799 800 struct mpi3mr_drv_cmd host_tm_cmds; 801 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 802 u16 devrem_bitmap_sz; 803 void *devrem_bitmap; 804 u16 dev_handle_bitmap_sz; 805 void *removepend_bitmap; 806 struct list_head delayed_rmhs_list; 807 808 u32 ts_update_counter; 809 u8 reset_in_progress; 810 u8 unrecoverable; 811 int prev_reset_result; 812 struct mutex reset_mutex; 813 wait_queue_head_t reset_waitq; 814 815 u16 diagsave_timeout; 816 int logging_level; 817 u16 flush_io_count; 818 819 struct mpi3mr_fwevt *current_event; 820 struct mpi3_driver_info_layout driver_info; 821 u16 change_count; 822 u16 op_reply_q_offset; 823 }; 824 825 /** 826 * struct mpi3mr_fwevt - Firmware event structure. 827 * 828 * @list: list head 829 * @work: Work structure 830 * @mrioc: Adapter instance reference 831 * @event_id: MPI3 firmware event ID 832 * @send_ack: Event acknowledgment required or not 833 * @process_evt: Bottomhalf processing required or not 834 * @evt_ctx: Event context to send in Ack 835 * @ref_count: kref count 836 * @event_data: Actual MPI3 event data 837 */ 838 struct mpi3mr_fwevt { 839 struct list_head list; 840 struct work_struct work; 841 struct mpi3mr_ioc *mrioc; 842 u16 event_id; 843 bool send_ack; 844 bool process_evt; 845 u32 evt_ctx; 846 struct kref ref_count; 847 char event_data[0] __aligned(4); 848 }; 849 850 851 /** 852 * struct delayed_dev_rmhs_node - Delayed device removal node 853 * 854 * @list: list head 855 * @handle: Device handle 856 * @iou_rc: IO Unit Control Reason Code 857 */ 858 struct delayed_dev_rmhs_node { 859 struct list_head list; 860 u16 handle; 861 u8 iou_rc; 862 }; 863 864 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 865 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 866 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 867 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 868 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 869 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 870 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 871 u16 admin_req_sz, u8 ignore_reset); 872 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 873 struct op_req_qinfo *opreqq, u8 *req); 874 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 875 dma_addr_t dma_addr); 876 void mpi3mr_build_zero_len_sge(void *paddr); 877 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 878 dma_addr_t phys_addr); 879 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 880 dma_addr_t phys_addr); 881 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 882 u64 sense_buf_dma); 883 884 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 885 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 886 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 887 struct mpi3_event_notification_reply *event_reply); 888 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 889 struct mpi3_default_reply_descriptor *reply_desc, 890 u64 *reply_dma, u16 qidx); 891 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 892 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 893 894 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 895 u32 reset_reason, u8 snapdump); 896 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 897 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 898 899 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 900 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 901 u32 event_ctx); 902 903 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 904 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 905 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 906 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 907 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 908 void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc); 909 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 910 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 911 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 912 913 #endif /*MPI3MR_H_INCLUDED*/ 914