1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_cnfg.h" 44 #include "mpi/mpi30_image.h" 45 #include "mpi/mpi30_init.h" 46 #include "mpi/mpi30_ioc.h" 47 #include "mpi/mpi30_sas.h" 48 #include "mpi/mpi30_pci.h" 49 #include "mpi3mr_debug.h" 50 51 /* Global list and lock for storing multiple adapters managed by the driver */ 52 extern spinlock_t mrioc_list_lock; 53 extern struct list_head mrioc_list; 54 extern int prot_mask; 55 56 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 57 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 58 59 #define MPI3MR_DRIVER_NAME "mpi3mr" 60 #define MPI3MR_DRIVER_LICENSE "GPL" 61 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 62 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 63 64 #define MPI3MR_NAME_LENGTH 32 65 #define IOCNAME "%s: " 66 67 /* Definitions for internal SGL and Chain SGL buffers */ 68 #define MPI3MR_PAGE_SIZE_4K 4096 69 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 70 71 /* Definitions for MAX values for shost */ 72 #define MPI3MR_MAX_CMDS_LUN 7 73 #define MPI3MR_MAX_CDB_LENGTH 32 74 75 /* Admin queue management definitions */ 76 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 77 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 78 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 79 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 80 81 /* Operational queue management definitions */ 82 #define MPI3MR_OP_REQ_Q_QD 512 83 #define MPI3MR_OP_REP_Q_QD 4096 84 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 85 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 86 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 87 88 /* Reserved Host Tag definitions */ 89 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 90 #define MPI3MR_HOSTTAG_INITCMDS 1 91 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 92 #define MPI3MR_HOSTTAG_BLK_TMS 5 93 94 #define MPI3MR_NUM_DEVRMCMD 16 95 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 96 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 97 MPI3MR_NUM_DEVRMCMD - 1) 98 99 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 100 101 /* Reduced resource count definition for crash kernel */ 102 #define MPI3MR_HOST_IOS_KDUMP 128 103 104 /* command/controller interaction timeout definitions in seconds */ 105 #define MPI3MR_INTADMCMD_TIMEOUT 60 106 #define MPI3MR_PORTENABLE_TIMEOUT 300 107 #define MPI3MR_ABORTTM_TIMEOUT 60 108 #define MPI3MR_RESETTM_TIMEOUT 60 109 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 110 #define MPI3MR_TSUPDATE_INTERVAL 900 111 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 112 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 113 114 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 115 116 /* Internal admin command state definitions*/ 117 #define MPI3MR_CMD_NOTUSED 0x8000 118 #define MPI3MR_CMD_COMPLETE 0x0001 119 #define MPI3MR_CMD_PENDING 0x0002 120 #define MPI3MR_CMD_REPLY_VALID 0x0004 121 #define MPI3MR_CMD_RESET 0x0008 122 123 /* Definitions for Event replies and sense buffer allocated per controller */ 124 #define MPI3MR_NUM_EVT_REPLIES 64 125 #define MPI3MR_SENSE_BUF_SZ 256 126 #define MPI3MR_SENSEBUF_FACTOR 3 127 #define MPI3MR_CHAINBUF_FACTOR 3 128 #define MPI3MR_CHAINBUFDIX_FACTOR 2 129 130 /* Invalid target device handle */ 131 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 132 133 /* Controller Reset related definitions */ 134 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 135 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 136 137 /* ResponseCode definitions */ 138 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 139 #define MPI3MR_RSP_TM_COMPLETE 0x00 140 #define MPI3MR_RSP_INVALID_FRAME 0x02 141 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 142 #define MPI3MR_RSP_TM_FAILED 0x05 143 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 144 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 145 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 146 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 147 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 148 149 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 150 #define MPI3MR_DEFAULT_PGSZEXP (12) 151 /* Command retry count definitions */ 152 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 153 154 /* Default target device queue depth */ 155 #define MPI3MR_DEFAULT_SDEV_QD 32 156 157 /* Definitions for Threaded IRQ poll*/ 158 #define MPI3MR_IRQ_POLL_SLEEP 2 159 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 160 161 /* Definitions for the controller security status*/ 162 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 163 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 164 165 #define MPI3MR_INVALID_DEVICE 0x00 166 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 167 #define MPI3MR_HARD_SECURE_DEVICE 0x08 168 #define MPI3MR_TAMPERED_DEVICE 0x0C 169 170 /* SGE Flag definition */ 171 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 172 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 173 MPI3_SGE_FLAGS_END_OF_LIST) 174 175 /* MSI Index from Reply Queue Index */ 176 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 177 178 /* IOC State definitions */ 179 enum mpi3mr_iocstate { 180 MRIOC_STATE_READY = 1, 181 MRIOC_STATE_RESET, 182 MRIOC_STATE_FAULT, 183 MRIOC_STATE_BECOMING_READY, 184 MRIOC_STATE_RESET_REQUESTED, 185 MRIOC_STATE_UNRECOVERABLE, 186 }; 187 188 /* Init type definitions */ 189 enum mpi3mr_init_type { 190 MPI3MR_IT_INIT = 0, 191 MPI3MR_IT_RESET, 192 MPI3MR_IT_RESUME, 193 }; 194 195 /* Cleanup reason definitions */ 196 enum mpi3mr_cleanup_reason { 197 MPI3MR_COMPLETE_CLEANUP = 0, 198 MPI3MR_REINIT_FAILURE, 199 MPI3MR_SUSPEND, 200 }; 201 202 /* Reset reason code definitions*/ 203 enum mpi3mr_reset_reason { 204 MPI3MR_RESET_FROM_BRINGUP = 1, 205 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 206 MPI3MR_RESET_FROM_IOCTL = 3, 207 MPI3MR_RESET_FROM_EH_HOS = 4, 208 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 209 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 210 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 211 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 212 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 213 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 214 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 215 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 216 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 217 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 218 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 219 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 220 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 221 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 222 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 223 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 224 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 225 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 226 MPI3MR_RESET_FROM_SYSFS = 23, 227 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24 228 }; 229 230 /** 231 * struct mpi3mr_compimg_ver - replica of component image 232 * version defined in mpi30_image.h in host endianness 233 * 234 */ 235 struct mpi3mr_compimg_ver { 236 u16 build_num; 237 u16 cust_id; 238 u8 ph_minor; 239 u8 ph_major; 240 u8 gen_minor; 241 u8 gen_major; 242 }; 243 244 /** 245 * struct mpi3mr_ioc_facs - replica of component image version 246 * defined in mpi30_ioc.h in host endianness 247 * 248 */ 249 struct mpi3mr_ioc_facts { 250 u32 ioc_capabilities; 251 struct mpi3mr_compimg_ver fw_ver; 252 u32 mpi_version; 253 u16 max_reqs; 254 u16 product_id; 255 u16 op_req_sz; 256 u16 reply_sz; 257 u16 exceptions; 258 u16 max_perids; 259 u16 max_pds; 260 u16 max_sasexpanders; 261 u16 max_sasinitiators; 262 u16 max_enclosures; 263 u16 max_pcie_switches; 264 u16 max_nvme; 265 u16 max_vds; 266 u16 max_hpds; 267 u16 max_advhpds; 268 u16 max_raid_pds; 269 u16 min_devhandle; 270 u16 max_devhandle; 271 u16 max_op_req_q; 272 u16 max_op_reply_q; 273 u16 shutdown_timeout; 274 u8 ioc_num; 275 u8 who_init; 276 u16 max_msix_vectors; 277 u8 personality; 278 u8 dma_mask; 279 u8 protocol_flags; 280 u8 sge_mod_mask; 281 u8 sge_mod_value; 282 u8 sge_mod_shift; 283 }; 284 285 /** 286 * struct segments - memory descriptor structure to store 287 * virtual and dma addresses for operational queue segments. 288 * 289 * @segment: virtual address 290 * @segment_dma: dma address 291 */ 292 struct segments { 293 void *segment; 294 dma_addr_t segment_dma; 295 }; 296 297 /** 298 * struct op_req_qinfo - Operational Request Queue Information 299 * 300 * @ci: consumer index 301 * @pi: producer index 302 * @num_request: Maximum number of entries in the queue 303 * @qid: Queue Id starting from 1 304 * @reply_qid: Associated reply queue Id 305 * @num_segments: Number of discontiguous memory segments 306 * @segment_qd: Depth of each segments 307 * @q_lock: Concurrent queue access lock 308 * @q_segments: Segment descriptor pointer 309 * @q_segment_list: Segment list base virtual address 310 * @q_segment_list_dma: Segment list base DMA address 311 */ 312 struct op_req_qinfo { 313 u16 ci; 314 u16 pi; 315 u16 num_requests; 316 u16 qid; 317 u16 reply_qid; 318 u16 num_segments; 319 u16 segment_qd; 320 spinlock_t q_lock; 321 struct segments *q_segments; 322 void *q_segment_list; 323 dma_addr_t q_segment_list_dma; 324 }; 325 326 /** 327 * struct op_reply_qinfo - Operational Reply Queue Information 328 * 329 * @ci: consumer index 330 * @qid: Queue Id starting from 1 331 * @num_replies: Maximum number of entries in the queue 332 * @num_segments: Number of discontiguous memory segments 333 * @segment_qd: Depth of each segments 334 * @q_segments: Segment descriptor pointer 335 * @q_segment_list: Segment list base virtual address 336 * @q_segment_list_dma: Segment list base DMA address 337 * @ephase: Expected phased identifier for the reply queue 338 * @pend_ios: Number of IOs pending in HW for this queue 339 * @enable_irq_poll: Flag to indicate polling is enabled 340 * @in_use: Queue is handled by poll/ISR 341 */ 342 struct op_reply_qinfo { 343 u16 ci; 344 u16 qid; 345 u16 num_replies; 346 u16 num_segments; 347 u16 segment_qd; 348 struct segments *q_segments; 349 void *q_segment_list; 350 dma_addr_t q_segment_list_dma; 351 u8 ephase; 352 atomic_t pend_ios; 353 bool enable_irq_poll; 354 atomic_t in_use; 355 }; 356 357 /** 358 * struct mpi3mr_intr_info - Interrupt cookie information 359 * 360 * @mrioc: Adapter instance reference 361 * @msix_index: MSIx index 362 * @op_reply_q: Associated operational reply queue 363 * @name: Dev name for the irq claiming device 364 */ 365 struct mpi3mr_intr_info { 366 struct mpi3mr_ioc *mrioc; 367 u16 msix_index; 368 struct op_reply_qinfo *op_reply_q; 369 char name[MPI3MR_NAME_LENGTH]; 370 }; 371 372 /** 373 * struct tgt_dev_sas_sata - SAS/SATA device specific 374 * information cached from firmware given data 375 * 376 * @sas_address: World wide unique SAS address 377 * @dev_info: Device information bits 378 */ 379 struct tgt_dev_sas_sata { 380 u64 sas_address; 381 u16 dev_info; 382 }; 383 384 /** 385 * struct tgt_dev_pcie - PCIe device specific information cached 386 * from firmware given data 387 * 388 * @mdts: Maximum data transfer size 389 * @capb: Device capabilities 390 * @pgsz: Device page size 391 * @abort_to: Timeout for abort TM 392 * @reset_to: Timeout for Target/LUN reset TM 393 * @dev_info: Device information bits 394 */ 395 struct tgt_dev_pcie { 396 u32 mdts; 397 u16 capb; 398 u8 pgsz; 399 u8 abort_to; 400 u8 reset_to; 401 u16 dev_info; 402 }; 403 404 /** 405 * struct tgt_dev_volume - virtual device specific information 406 * cached from firmware given data 407 * 408 * @state: State of the VD 409 */ 410 struct tgt_dev_volume { 411 u8 state; 412 }; 413 414 /** 415 * union _form_spec_inf - union of device specific information 416 */ 417 union _form_spec_inf { 418 struct tgt_dev_sas_sata sas_sata_inf; 419 struct tgt_dev_pcie pcie_inf; 420 struct tgt_dev_volume vol_inf; 421 }; 422 423 424 425 /** 426 * struct mpi3mr_tgt_dev - target device data structure 427 * 428 * @list: List pointer 429 * @starget: Scsi_target pointer 430 * @dev_handle: FW device handle 431 * @parent_handle: FW parent device handle 432 * @slot: Slot number 433 * @encl_handle: FW enclosure handle 434 * @perst_id: FW assigned Persistent ID 435 * @dev_type: SAS/SATA/PCIE device type 436 * @is_hidden: Should be exposed to upper layers or not 437 * @host_exposed: Already exposed to host or not 438 * @q_depth: Device specific Queue Depth 439 * @wwid: World wide ID 440 * @dev_spec: Device type specific information 441 * @ref_count: Reference count 442 */ 443 struct mpi3mr_tgt_dev { 444 struct list_head list; 445 struct scsi_target *starget; 446 u16 dev_handle; 447 u16 parent_handle; 448 u16 slot; 449 u16 encl_handle; 450 u16 perst_id; 451 u8 dev_type; 452 u8 is_hidden; 453 u8 host_exposed; 454 u16 q_depth; 455 u64 wwid; 456 union _form_spec_inf dev_spec; 457 struct kref ref_count; 458 }; 459 460 /** 461 * mpi3mr_tgtdev_get - k reference incrementor 462 * @s: Target device reference 463 * 464 * Increment target device reference count. 465 */ 466 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 467 { 468 kref_get(&s->ref_count); 469 } 470 471 /** 472 * mpi3mr_free_tgtdev - target device memory dealloctor 473 * @r: k reference pointer of the target device 474 * 475 * Free target device memory when no reference. 476 */ 477 static inline void mpi3mr_free_tgtdev(struct kref *r) 478 { 479 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 480 } 481 482 /** 483 * mpi3mr_tgtdev_put - k reference decrementor 484 * @s: Target device reference 485 * 486 * Decrement target device reference count. 487 */ 488 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 489 { 490 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 491 } 492 493 494 /** 495 * struct mpi3mr_stgt_priv_data - SCSI target private structure 496 * 497 * @starget: Scsi_target pointer 498 * @dev_handle: FW device handle 499 * @perst_id: FW assigned Persistent ID 500 * @num_luns: Number of Logical Units 501 * @block_io: I/O blocked to the device or not 502 * @dev_removed: Device removed in the Firmware 503 * @dev_removedelay: Device is waiting to be removed in FW 504 * @dev_type: Device type 505 * @tgt_dev: Internal target device pointer 506 */ 507 struct mpi3mr_stgt_priv_data { 508 struct scsi_target *starget; 509 u16 dev_handle; 510 u16 perst_id; 511 u32 num_luns; 512 atomic_t block_io; 513 u8 dev_removed; 514 u8 dev_removedelay; 515 u8 dev_type; 516 struct mpi3mr_tgt_dev *tgt_dev; 517 }; 518 519 /** 520 * struct mpi3mr_stgt_priv_data - SCSI device private structure 521 * 522 * @tgt_priv_data: Scsi_target private data pointer 523 * @lun_id: LUN ID of the device 524 * @ncq_prio_enable: NCQ priority enable for SATA device 525 */ 526 struct mpi3mr_sdev_priv_data { 527 struct mpi3mr_stgt_priv_data *tgt_priv_data; 528 u32 lun_id; 529 u8 ncq_prio_enable; 530 }; 531 532 /** 533 * struct mpi3mr_drv_cmd - Internal command tracker 534 * 535 * @mutex: Command mutex 536 * @done: Completeor for wakeup 537 * @reply: Firmware reply for internal commands 538 * @sensebuf: Sensebuf for SCSI IO commands 539 * @iou_rc: IO Unit control reason code 540 * @state: Command State 541 * @dev_handle: Firmware handle for device specific commands 542 * @ioc_status: IOC status from the firmware 543 * @ioc_loginfo:IOC log info from the firmware 544 * @is_waiting: Is the command issued in block mode 545 * @retry_count: Retry count for retriable commands 546 * @host_tag: Host tag used by the command 547 * @callback: Callback for non blocking commands 548 */ 549 struct mpi3mr_drv_cmd { 550 struct mutex mutex; 551 struct completion done; 552 void *reply; 553 u8 *sensebuf; 554 u8 iou_rc; 555 u16 state; 556 u16 dev_handle; 557 u16 ioc_status; 558 u32 ioc_loginfo; 559 u8 is_waiting; 560 u8 retry_count; 561 u16 host_tag; 562 563 void (*callback)(struct mpi3mr_ioc *mrioc, 564 struct mpi3mr_drv_cmd *drv_cmd); 565 }; 566 567 568 /** 569 * struct chain_element - memory descriptor structure to store 570 * virtual and dma addresses for chain elements. 571 * 572 * @addr: virtual address 573 * @dma_addr: dma address 574 */ 575 struct chain_element { 576 void *addr; 577 dma_addr_t dma_addr; 578 }; 579 580 /** 581 * struct scmd_priv - SCSI command private data 582 * 583 * @host_tag: Host tag specific to operational queue 584 * @in_lld_scope: Command in LLD scope or not 585 * @meta_sg_valid: DIX command with meta data SGL or not 586 * @scmd: SCSI Command pointer 587 * @req_q_idx: Operational request queue index 588 * @chain_idx: Chain frame index 589 * @meta_chain_idx: Chain frame index of meta data SGL 590 * @mpi3mr_scsiio_req: MPI SCSI IO request 591 */ 592 struct scmd_priv { 593 u16 host_tag; 594 u8 in_lld_scope; 595 u8 meta_sg_valid; 596 struct scsi_cmnd *scmd; 597 u16 req_q_idx; 598 int chain_idx; 599 int meta_chain_idx; 600 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 601 }; 602 603 /** 604 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 605 * private data 606 * 607 * @list: List pointer 608 * @pdev: PCI device pointer 609 * @shost: Scsi_Host pointer 610 * @id: Controller ID 611 * @cpu_count: Number of online CPUs 612 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 613 * @name: Controller ASCII name 614 * @driver_name: Driver ASCII name 615 * @sysif_regs: System interface registers virtual address 616 * @sysif_regs_phys: System interface registers physical address 617 * @bars: PCI BARS 618 * @dma_mask: DMA mask 619 * @msix_count: Number of MSIX vectors used 620 * @intr_enabled: Is interrupts enabled 621 * @num_admin_req: Number of admin requests 622 * @admin_req_q_sz: Admin request queue size 623 * @admin_req_pi: Admin request queue producer index 624 * @admin_req_ci: Admin request queue consumer index 625 * @admin_req_base: Admin request queue base virtual address 626 * @admin_req_dma: Admin request queue base dma address 627 * @admin_req_lock: Admin queue access lock 628 * @num_admin_replies: Number of admin replies 629 * @admin_reply_q_sz: Admin reply queue size 630 * @admin_reply_ci: Admin reply queue consumer index 631 * @admin_reply_ephase:Admin reply queue expected phase 632 * @admin_reply_base: Admin reply queue base virtual address 633 * @admin_reply_dma: Admin reply queue base dma address 634 * @ready_timeout: Controller ready timeout 635 * @intr_info: Interrupt cookie pointer 636 * @intr_info_count: Number of interrupt cookies 637 * @num_queues: Number of operational queues 638 * @num_op_req_q: Number of operational request queues 639 * @req_qinfo: Operational request queue info pointer 640 * @num_op_reply_q: Number of operational reply queues 641 * @op_reply_qinfo: Operational reply queue info pointer 642 * @init_cmds: Command tracker for initialization commands 643 * @facts: Cached IOC facts data 644 * @op_reply_desc_sz: Operational reply descriptor size 645 * @num_reply_bufs: Number of reply buffers allocated 646 * @reply_buf_pool: Reply buffer pool 647 * @reply_buf: Reply buffer base virtual address 648 * @reply_buf_dma: Reply buffer DMA address 649 * @reply_buf_dma_max_address: Reply DMA address max limit 650 * @reply_free_qsz: Reply free queue size 651 * @reply_free_q_pool: Reply free queue pool 652 * @reply_free_q: Reply free queue base virtual address 653 * @reply_free_q_dma: Reply free queue base DMA address 654 * @reply_free_queue_lock: Reply free queue lock 655 * @reply_free_queue_host_index: Reply free queue host index 656 * @num_sense_bufs: Number of sense buffers 657 * @sense_buf_pool: Sense buffer pool 658 * @sense_buf: Sense buffer base virtual address 659 * @sense_buf_dma: Sense buffer base DMA address 660 * @sense_buf_q_sz: Sense buffer queue size 661 * @sense_buf_q_pool: Sense buffer queue pool 662 * @sense_buf_q: Sense buffer queue virtual address 663 * @sense_buf_q_dma: Sense buffer queue DMA address 664 * @sbq_lock: Sense buffer queue lock 665 * @sbq_host_index: Sense buffer queuehost index 666 * @event_masks: Event mask bitmap 667 * @fwevt_worker_name: Firmware event worker thread name 668 * @fwevt_worker_thread: Firmware event worker thread 669 * @fwevt_lock: Firmware event lock 670 * @fwevt_list: Firmware event list 671 * @watchdog_work_q_name: Fault watchdog worker thread name 672 * @watchdog_work_q: Fault watchdog worker thread 673 * @watchdog_work: Fault watchdog work 674 * @watchdog_lock: Fault watchdog lock 675 * @is_driver_loading: Is driver still loading 676 * @scan_started: Async scan started 677 * @scan_failed: Asycn scan failed 678 * @stop_drv_processing: Stop all command processing 679 * @max_host_ios: Maximum host I/O count 680 * @chain_buf_count: Chain buffer count 681 * @chain_buf_pool: Chain buffer pool 682 * @chain_sgl_list: Chain SGL list 683 * @chain_bitmap_sz: Chain buffer allocator bitmap size 684 * @chain_bitmap: Chain buffer allocator bitmap 685 * @chain_buf_lock: Chain buffer list lock 686 * @host_tm_cmds: Command tracker for task management commands 687 * @dev_rmhs_cmds: Command tracker for device removal commands 688 * @devrem_bitmap_sz: Device removal bitmap size 689 * @devrem_bitmap: Device removal bitmap 690 * @dev_handle_bitmap_sz: Device handle bitmap size 691 * @removepend_bitmap: Remove pending bitmap 692 * @delayed_rmhs_list: Delayed device removal list 693 * @ts_update_counter: Timestamp update counter 694 * @fault_dbg: Fault debug flag 695 * @reset_in_progress: Reset in progress flag 696 * @unrecoverable: Controller unrecoverable flag 697 * @reset_mutex: Controller reset mutex 698 * @reset_waitq: Controller reset wait queue 699 * @diagsave_timeout: Diagnostic information save timeout 700 * @logging_level: Controller debug logging level 701 * @flush_io_count: I/O count to flush after reset 702 * @current_event: Firmware event currently in process 703 * @driver_info: Driver, Kernel, OS information to firmware 704 * @change_count: Topology change count 705 * @op_reply_q_offset: Operational reply queue offset with MSIx 706 */ 707 struct mpi3mr_ioc { 708 struct list_head list; 709 struct pci_dev *pdev; 710 struct Scsi_Host *shost; 711 u8 id; 712 int cpu_count; 713 bool enable_segqueue; 714 u32 irqpoll_sleep; 715 716 char name[MPI3MR_NAME_LENGTH]; 717 char driver_name[MPI3MR_NAME_LENGTH]; 718 719 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 720 resource_size_t sysif_regs_phys; 721 int bars; 722 u64 dma_mask; 723 724 u16 msix_count; 725 u8 intr_enabled; 726 727 u16 num_admin_req; 728 u32 admin_req_q_sz; 729 u16 admin_req_pi; 730 u16 admin_req_ci; 731 void *admin_req_base; 732 dma_addr_t admin_req_dma; 733 spinlock_t admin_req_lock; 734 735 u16 num_admin_replies; 736 u32 admin_reply_q_sz; 737 u16 admin_reply_ci; 738 u8 admin_reply_ephase; 739 void *admin_reply_base; 740 dma_addr_t admin_reply_dma; 741 742 u32 ready_timeout; 743 744 struct mpi3mr_intr_info *intr_info; 745 u16 intr_info_count; 746 747 u16 num_queues; 748 u16 num_op_req_q; 749 struct op_req_qinfo *req_qinfo; 750 751 u16 num_op_reply_q; 752 struct op_reply_qinfo *op_reply_qinfo; 753 754 struct mpi3mr_drv_cmd init_cmds; 755 struct mpi3mr_ioc_facts facts; 756 u16 op_reply_desc_sz; 757 758 u32 num_reply_bufs; 759 struct dma_pool *reply_buf_pool; 760 u8 *reply_buf; 761 dma_addr_t reply_buf_dma; 762 dma_addr_t reply_buf_dma_max_address; 763 764 u16 reply_free_qsz; 765 struct dma_pool *reply_free_q_pool; 766 __le64 *reply_free_q; 767 dma_addr_t reply_free_q_dma; 768 spinlock_t reply_free_queue_lock; 769 u32 reply_free_queue_host_index; 770 771 u32 num_sense_bufs; 772 struct dma_pool *sense_buf_pool; 773 u8 *sense_buf; 774 dma_addr_t sense_buf_dma; 775 776 u16 sense_buf_q_sz; 777 struct dma_pool *sense_buf_q_pool; 778 __le64 *sense_buf_q; 779 dma_addr_t sense_buf_q_dma; 780 spinlock_t sbq_lock; 781 u32 sbq_host_index; 782 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 783 784 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 785 struct workqueue_struct *fwevt_worker_thread; 786 spinlock_t fwevt_lock; 787 struct list_head fwevt_list; 788 789 char watchdog_work_q_name[20]; 790 struct workqueue_struct *watchdog_work_q; 791 struct delayed_work watchdog_work; 792 spinlock_t watchdog_lock; 793 794 u8 is_driver_loading; 795 u8 scan_started; 796 u16 scan_failed; 797 u8 stop_drv_processing; 798 799 u16 max_host_ios; 800 spinlock_t tgtdev_lock; 801 struct list_head tgtdev_list; 802 803 u32 chain_buf_count; 804 struct dma_pool *chain_buf_pool; 805 struct chain_element *chain_sgl_list; 806 u16 chain_bitmap_sz; 807 void *chain_bitmap; 808 spinlock_t chain_buf_lock; 809 810 struct mpi3mr_drv_cmd host_tm_cmds; 811 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 812 u16 devrem_bitmap_sz; 813 void *devrem_bitmap; 814 u16 dev_handle_bitmap_sz; 815 void *removepend_bitmap; 816 struct list_head delayed_rmhs_list; 817 818 u32 ts_update_counter; 819 u8 fault_dbg; 820 u8 reset_in_progress; 821 u8 unrecoverable; 822 struct mutex reset_mutex; 823 wait_queue_head_t reset_waitq; 824 825 u16 diagsave_timeout; 826 int logging_level; 827 u16 flush_io_count; 828 829 struct mpi3mr_fwevt *current_event; 830 struct mpi3_driver_info_layout driver_info; 831 u16 change_count; 832 u16 op_reply_q_offset; 833 }; 834 835 /** 836 * struct mpi3mr_fwevt - Firmware event structure. 837 * 838 * @list: list head 839 * @work: Work structure 840 * @mrioc: Adapter instance reference 841 * @event_id: MPI3 firmware event ID 842 * @send_ack: Event acknowledgment required or not 843 * @process_evt: Bottomhalf processing required or not 844 * @evt_ctx: Event context to send in Ack 845 * @ref_count: kref count 846 * @event_data: Actual MPI3 event data 847 */ 848 struct mpi3mr_fwevt { 849 struct list_head list; 850 struct work_struct work; 851 struct mpi3mr_ioc *mrioc; 852 u16 event_id; 853 bool send_ack; 854 bool process_evt; 855 u32 evt_ctx; 856 struct kref ref_count; 857 char event_data[0] __aligned(4); 858 }; 859 860 861 /** 862 * struct delayed_dev_rmhs_node - Delayed device removal node 863 * 864 * @list: list head 865 * @handle: Device handle 866 * @iou_rc: IO Unit Control Reason Code 867 */ 868 struct delayed_dev_rmhs_node { 869 struct list_head list; 870 u16 handle; 871 u8 iou_rc; 872 }; 873 874 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 875 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 876 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 init_type); 877 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 reason); 878 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 879 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 880 u16 admin_req_sz, u8 ignore_reset); 881 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 882 struct op_req_qinfo *opreqq, u8 *req); 883 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 884 dma_addr_t dma_addr); 885 void mpi3mr_build_zero_len_sge(void *paddr); 886 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 887 dma_addr_t phys_addr); 888 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 889 dma_addr_t phys_addr); 890 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 891 u64 sense_buf_dma); 892 893 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 894 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 895 struct mpi3_event_notification_reply *event_reply); 896 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 897 struct mpi3_default_reply_descriptor *reply_desc, 898 u64 *reply_dma, u16 qidx); 899 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 900 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 901 902 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 903 u32 reset_reason, u8 snapdump); 904 int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc, 905 u32 reset_reason); 906 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 907 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 908 909 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 910 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 911 u32 event_ctx); 912 913 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 914 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 915 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 916 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 917 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 918 void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc); 919 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 920 921 #endif /*MPI3MR_H_INCLUDED*/ 922