1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_image.h" 44 #include "mpi/mpi30_init.h" 45 #include "mpi/mpi30_ioc.h" 46 #include "mpi3mr_debug.h" 47 48 /* Global list and lock for storing multiple adapters managed by the driver */ 49 extern spinlock_t mrioc_list_lock; 50 extern struct list_head mrioc_list; 51 52 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 53 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 54 55 #define MPI3MR_DRIVER_NAME "mpi3mr" 56 #define MPI3MR_DRIVER_LICENSE "GPL" 57 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 58 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 59 60 #define MPI3MR_NAME_LENGTH 32 61 #define IOCNAME "%s: " 62 63 /* Definitions for internal SGL and Chain SGL buffers */ 64 #define MPI3MR_PAGE_SIZE_4K 4096 65 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 66 67 /* Definitions for MAX values for shost */ 68 #define MPI3MR_MAX_CMDS_LUN 7 69 #define MPI3MR_MAX_CDB_LENGTH 32 70 71 /* Admin queue management definitions */ 72 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 73 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 74 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 75 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 76 77 78 /* Reserved Host Tag definitions */ 79 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 80 #define MPI3MR_HOSTTAG_INITCMDS 1 81 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 82 #define MPI3MR_HOSTTAG_BLK_TMS 5 83 84 #define MPI3MR_NUM_DEVRMCMD 1 85 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 86 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 87 MPI3MR_NUM_DEVRMCMD - 1) 88 89 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 90 91 /* Reduced resource count definition for crash kernel */ 92 #define MPI3MR_HOST_IOS_KDUMP 128 93 94 /* command/controller interaction timeout definitions in seconds */ 95 #define MPI3MR_INTADMCMD_TIMEOUT 10 96 #define MPI3MR_RESETTM_TIMEOUT 30 97 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 98 99 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 100 101 /* Internal admin command state definitions*/ 102 #define MPI3MR_CMD_NOTUSED 0x8000 103 #define MPI3MR_CMD_COMPLETE 0x0001 104 #define MPI3MR_CMD_PENDING 0x0002 105 #define MPI3MR_CMD_REPLY_VALID 0x0004 106 #define MPI3MR_CMD_RESET 0x0008 107 108 /* Definitions for Event replies and sense buffer allocated per controller */ 109 #define MPI3MR_NUM_EVT_REPLIES 64 110 #define MPI3MR_SENSEBUF_SZ 256 111 #define MPI3MR_SENSEBUF_FACTOR 3 112 #define MPI3MR_CHAINBUF_FACTOR 3 113 114 /* Invalid target device handle */ 115 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 116 117 /* Controller Reset related definitions */ 118 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 119 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 120 121 /* ResponseCode definitions */ 122 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 123 #define MPI3MR_RSP_TM_COMPLETE 0x00 124 #define MPI3MR_RSP_INVALID_FRAME 0x02 125 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 126 #define MPI3MR_RSP_TM_FAILED 0x05 127 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 128 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 129 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 130 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 131 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 132 133 /* SGE Flag definition */ 134 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 135 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 136 MPI3_SGE_FLAGS_END_OF_LIST) 137 138 /* IOC State definitions */ 139 enum mpi3mr_iocstate { 140 MRIOC_STATE_READY = 1, 141 MRIOC_STATE_RESET, 142 MRIOC_STATE_FAULT, 143 MRIOC_STATE_BECOMING_READY, 144 MRIOC_STATE_RESET_REQUESTED, 145 MRIOC_STATE_UNRECOVERABLE, 146 }; 147 148 /* Reset reason code definitions*/ 149 enum mpi3mr_reset_reason { 150 MPI3MR_RESET_FROM_BRINGUP = 1, 151 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 152 MPI3MR_RESET_FROM_IOCTL = 3, 153 MPI3MR_RESET_FROM_EH_HOS = 4, 154 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 155 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 156 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 157 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 158 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 159 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 160 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 161 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 162 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 163 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 164 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 165 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 166 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 167 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 168 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 169 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 170 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 171 }; 172 173 /** 174 * struct mpi3mr_compimg_ver - replica of component image 175 * version defined in mpi30_image.h in host endianness 176 * 177 */ 178 struct mpi3mr_compimg_ver { 179 u16 build_num; 180 u16 cust_id; 181 u8 ph_minor; 182 u8 ph_major; 183 u8 gen_minor; 184 u8 gen_major; 185 }; 186 187 /** 188 * struct mpi3mr_ioc_facs - replica of component image version 189 * defined in mpi30_ioc.h in host endianness 190 * 191 */ 192 struct mpi3mr_ioc_facts { 193 u32 ioc_capabilities; 194 struct mpi3mr_compimg_ver fw_ver; 195 u32 mpi_version; 196 u16 max_reqs; 197 u16 product_id; 198 u16 op_req_sz; 199 u16 reply_sz; 200 u16 exceptions; 201 u16 max_perids; 202 u16 max_pds; 203 u16 max_sasexpanders; 204 u16 max_sasinitiators; 205 u16 max_enclosures; 206 u16 max_pcie_switches; 207 u16 max_nvme; 208 u16 max_vds; 209 u16 max_hpds; 210 u16 max_advhpds; 211 u16 max_raidpds; 212 u16 min_devhandle; 213 u16 max_devhandle; 214 u16 max_op_req_q; 215 u16 max_op_reply_q; 216 u16 shutdown_timeout; 217 u8 ioc_num; 218 u8 who_init; 219 u16 max_msix_vectors; 220 u8 personality; 221 u8 dma_mask; 222 u8 protocol_flags; 223 u8 sge_mod_mask; 224 u8 sge_mod_value; 225 u8 sge_mod_shift; 226 }; 227 228 /** 229 * struct op_req_qinfo - Operational Request Queue Information 230 * 231 * @ci: consumer index 232 * @pi: producer index 233 */ 234 struct op_req_qinfo { 235 u16 ci; 236 u16 pi; 237 }; 238 239 /** 240 * struct op_reply_qinfo - Operational Reply Queue Information 241 * 242 * @ci: consumer index 243 * @qid: Queue Id starting from 1 244 */ 245 struct op_reply_qinfo { 246 u16 ci; 247 u16 qid; 248 }; 249 250 /** 251 * struct mpi3mr_intr_info - Interrupt cookie information 252 * 253 * @mrioc: Adapter instance reference 254 * @msix_index: MSIx index 255 * @op_reply_q: Associated operational reply queue 256 * @name: Dev name for the irq claiming device 257 */ 258 struct mpi3mr_intr_info { 259 struct mpi3mr_ioc *mrioc; 260 u16 msix_index; 261 struct op_reply_qinfo *op_reply_q; 262 char name[MPI3MR_NAME_LENGTH]; 263 }; 264 265 266 267 /** 268 * struct mpi3mr_drv_cmd - Internal command tracker 269 * 270 * @mutex: Command mutex 271 * @done: Completeor for wakeup 272 * @reply: Firmware reply for internal commands 273 * @sensebuf: Sensebuf for SCSI IO commands 274 * @state: Command State 275 * @dev_handle: Firmware handle for device specific commands 276 * @ioc_status: IOC status from the firmware 277 * @ioc_loginfo:IOC log info from the firmware 278 * @is_waiting: Is the command issued in block mode 279 * @retry_count: Retry count for retriable commands 280 * @host_tag: Host tag used by the command 281 * @callback: Callback for non blocking commands 282 */ 283 struct mpi3mr_drv_cmd { 284 struct mutex mutex; 285 struct completion done; 286 void *reply; 287 u8 *sensebuf; 288 u16 state; 289 u16 dev_handle; 290 u16 ioc_status; 291 u32 ioc_loginfo; 292 u8 is_waiting; 293 u8 retry_count; 294 u16 host_tag; 295 296 void (*callback)(struct mpi3mr_ioc *mrioc, 297 struct mpi3mr_drv_cmd *drv_cmd); 298 }; 299 300 301 /** 302 * struct chain_element - memory descriptor structure to store 303 * virtual and dma addresses for chain elements. 304 * 305 * @addr: virtual address 306 * @dma_addr: dma address 307 */ 308 struct chain_element { 309 void *addr; 310 dma_addr_t dma_addr; 311 }; 312 313 /** 314 * struct scmd_priv - SCSI command private data 315 * 316 * @host_tag: Host tag specific to operational queue 317 * @in_lld_scope: Command in LLD scope or not 318 * @scmd: SCSI Command pointer 319 * @req_q_idx: Operational request queue index 320 * @chain_idx: Chain frame index 321 * @mpi3mr_scsiio_req: MPI SCSI IO request 322 */ 323 struct scmd_priv { 324 u16 host_tag; 325 u8 in_lld_scope; 326 struct scsi_cmnd *scmd; 327 u16 req_q_idx; 328 int chain_idx; 329 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 330 }; 331 332 /** 333 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 334 * private data 335 * 336 * @list: List pointer 337 * @pdev: PCI device pointer 338 * @shost: Scsi_Host pointer 339 * @id: Controller ID 340 * @cpu_count: Number of online CPUs 341 * @name: Controller ASCII name 342 * @driver_name: Driver ASCII name 343 * @sysif_regs: System interface registers virtual address 344 * @sysif_regs_phys: System interface registers physical address 345 * @bars: PCI BARS 346 * @dma_mask: DMA mask 347 * @msix_count: Number of MSIX vectors used 348 * @intr_enabled: Is interrupts enabled 349 * @num_admin_req: Number of admin requests 350 * @admin_req_q_sz: Admin request queue size 351 * @admin_req_pi: Admin request queue producer index 352 * @admin_req_ci: Admin request queue consumer index 353 * @admin_req_base: Admin request queue base virtual address 354 * @admin_req_dma: Admin request queue base dma address 355 * @admin_req_lock: Admin queue access lock 356 * @num_admin_replies: Number of admin replies 357 * @admin_reply_q_sz: Admin reply queue size 358 * @admin_reply_ci: Admin reply queue consumer index 359 * @admin_reply_ephase:Admin reply queue expected phase 360 * @admin_reply_base: Admin reply queue base virtual address 361 * @admin_reply_dma: Admin reply queue base dma address 362 * @ready_timeout: Controller ready timeout 363 * @intr_info: Interrupt cookie pointer 364 * @intr_info_count: Number of interrupt cookies 365 * @num_queues: Number of operational queues 366 * @num_op_req_q: Number of operational request queues 367 * @req_qinfo: Operational request queue info pointer 368 * @num_op_reply_q: Number of operational reply queues 369 * @op_reply_qinfo: Operational reply queue info pointer 370 * @init_cmds: Command tracker for initialization commands 371 * @facts: Cached IOC facts data 372 * @op_reply_desc_sz: Operational reply descriptor size 373 * @num_reply_bufs: Number of reply buffers allocated 374 * @reply_buf_pool: Reply buffer pool 375 * @reply_buf: Reply buffer base virtual address 376 * @reply_buf_dma: Reply buffer DMA address 377 * @reply_buf_dma_max_address: Reply DMA address max limit 378 * @reply_free_qsz: Reply free queue size 379 * @reply_free_q_pool: Reply free queue pool 380 * @reply_free_q: Reply free queue base virtual address 381 * @reply_free_q_dma: Reply free queue base DMA address 382 * @reply_free_queue_lock: Reply free queue lock 383 * @reply_free_queue_host_index: Reply free queue host index 384 * @num_sense_bufs: Number of sense buffers 385 * @sense_buf_pool: Sense buffer pool 386 * @sense_buf: Sense buffer base virtual address 387 * @sense_buf_dma: Sense buffer base DMA address 388 * @sense_buf_q_sz: Sense buffer queue size 389 * @sense_buf_q_pool: Sense buffer queue pool 390 * @sense_buf_q: Sense buffer queue virtual address 391 * @sense_buf_q_dma: Sense buffer queue DMA address 392 * @sbq_lock: Sense buffer queue lock 393 * @sbq_host_index: Sense buffer queuehost index 394 * @is_driver_loading: Is driver still loading 395 * @max_host_ios: Maximum host I/O count 396 * @chain_buf_count: Chain buffer count 397 * @chain_buf_pool: Chain buffer pool 398 * @chain_sgl_list: Chain SGL list 399 * @chain_bitmap_sz: Chain buffer allocator bitmap size 400 * @chain_bitmap: Chain buffer allocator bitmap 401 * @reset_in_progress: Reset in progress flag 402 * @unrecoverable: Controller unrecoverable flag 403 * @logging_level: Controller debug logging level 404 * @current_event: Firmware event currently in process 405 * @driver_info: Driver, Kernel, OS information to firmware 406 * @change_count: Topology change count 407 */ 408 struct mpi3mr_ioc { 409 struct list_head list; 410 struct pci_dev *pdev; 411 struct Scsi_Host *shost; 412 u8 id; 413 int cpu_count; 414 415 char name[MPI3MR_NAME_LENGTH]; 416 char driver_name[MPI3MR_NAME_LENGTH]; 417 418 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 419 resource_size_t sysif_regs_phys; 420 int bars; 421 u64 dma_mask; 422 423 u16 msix_count; 424 u8 intr_enabled; 425 426 u16 num_admin_req; 427 u32 admin_req_q_sz; 428 u16 admin_req_pi; 429 u16 admin_req_ci; 430 void *admin_req_base; 431 dma_addr_t admin_req_dma; 432 spinlock_t admin_req_lock; 433 434 u16 num_admin_replies; 435 u32 admin_reply_q_sz; 436 u16 admin_reply_ci; 437 u8 admin_reply_ephase; 438 void *admin_reply_base; 439 dma_addr_t admin_reply_dma; 440 441 u32 ready_timeout; 442 443 struct mpi3mr_intr_info *intr_info; 444 u16 intr_info_count; 445 446 u16 num_queues; 447 u16 num_op_req_q; 448 struct op_req_qinfo *req_qinfo; 449 450 u16 num_op_reply_q; 451 struct op_reply_qinfo *op_reply_qinfo; 452 453 struct mpi3mr_drv_cmd init_cmds; 454 struct mpi3mr_ioc_facts facts; 455 u16 op_reply_desc_sz; 456 457 u32 num_reply_bufs; 458 struct dma_pool *reply_buf_pool; 459 u8 *reply_buf; 460 dma_addr_t reply_buf_dma; 461 dma_addr_t reply_buf_dma_max_address; 462 463 u16 reply_free_qsz; 464 struct dma_pool *reply_free_q_pool; 465 __le64 *reply_free_q; 466 dma_addr_t reply_free_q_dma; 467 spinlock_t reply_free_queue_lock; 468 u32 reply_free_queue_host_index; 469 470 u32 num_sense_bufs; 471 struct dma_pool *sense_buf_pool; 472 u8 *sense_buf; 473 dma_addr_t sense_buf_dma; 474 475 u16 sense_buf_q_sz; 476 struct dma_pool *sense_buf_q_pool; 477 __le64 *sense_buf_q; 478 dma_addr_t sense_buf_q_dma; 479 spinlock_t sbq_lock; 480 u32 sbq_host_index; 481 482 u8 is_driver_loading; 483 484 u16 max_host_ios; 485 486 u32 chain_buf_count; 487 struct dma_pool *chain_buf_pool; 488 struct chain_element *chain_sgl_list; 489 u16 chain_bitmap_sz; 490 void *chain_bitmap; 491 492 u8 reset_in_progress; 493 u8 unrecoverable; 494 495 int logging_level; 496 497 struct mpi3mr_fwevt *current_event; 498 struct mpi3_driver_info_layout driver_info; 499 u16 change_count; 500 }; 501 502 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 503 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 504 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 505 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 506 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 507 u16 admin_req_sz, u8 ignore_reset); 508 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 509 dma_addr_t dma_addr); 510 void mpi3mr_build_zero_len_sge(void *paddr); 511 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 512 dma_addr_t phys_addr); 513 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 514 dma_addr_t phys_addr); 515 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 516 u64 sense_buf_dma); 517 518 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 519 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 520 521 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 522 u32 reset_reason, u8 snapdump); 523 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 524 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 525 526 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 527 528 #endif /*MPI3MR_H_INCLUDED*/ 529