1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_MAX_SECTORS 2048 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 74 75 /* Definitions for MAX values for shost */ 76 #define MPI3MR_MAX_CMDS_LUN 128 77 #define MPI3MR_MAX_CDB_LENGTH 32 78 79 /* Admin queue management definitions */ 80 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 81 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 83 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 84 85 /* Operational queue management definitions */ 86 #define MPI3MR_OP_REQ_Q_QD 512 87 #define MPI3MR_OP_REP_Q_QD 1024 88 #define MPI3MR_OP_REP_Q_QD4K 4096 89 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 90 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 91 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 92 93 /* Reserved Host Tag definitions */ 94 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 95 #define MPI3MR_HOSTTAG_INITCMDS 1 96 #define MPI3MR_HOSTTAG_BSG_CMDS 2 97 #define MPI3MR_HOSTTAG_PEL_ABORT 3 98 #define MPI3MR_HOSTTAG_PEL_WAIT 4 99 #define MPI3MR_HOSTTAG_BLK_TMS 5 100 #define MPI3MR_HOSTTAG_CFG_CMDS 6 101 102 #define MPI3MR_NUM_DEVRMCMD 16 103 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 104 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 105 MPI3MR_NUM_DEVRMCMD - 1) 106 107 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 108 #define MPI3MR_NUM_EVTACKCMD 4 109 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 110 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 111 MPI3MR_NUM_EVTACKCMD - 1) 112 113 /* Reduced resource count definition for crash kernel */ 114 #define MPI3MR_HOST_IOS_KDUMP 128 115 116 /* command/controller interaction timeout definitions in seconds */ 117 #define MPI3MR_INTADMCMD_TIMEOUT 60 118 #define MPI3MR_PORTENABLE_TIMEOUT 300 119 #define MPI3MR_ABORTTM_TIMEOUT 60 120 #define MPI3MR_RESETTM_TIMEOUT 60 121 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 122 #define MPI3MR_TSUPDATE_INTERVAL 900 123 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 124 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 125 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 126 #define MPI3MR_RESET_ACK_TIMEOUT 30 127 128 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 129 130 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 131 132 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 133 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 134 135 /* Internal admin command state definitions*/ 136 #define MPI3MR_CMD_NOTUSED 0x8000 137 #define MPI3MR_CMD_COMPLETE 0x0001 138 #define MPI3MR_CMD_PENDING 0x0002 139 #define MPI3MR_CMD_REPLY_VALID 0x0004 140 #define MPI3MR_CMD_RESET 0x0008 141 142 /* Definitions for Event replies and sense buffer allocated per controller */ 143 #define MPI3MR_NUM_EVT_REPLIES 64 144 #define MPI3MR_SENSE_BUF_SZ 256 145 #define MPI3MR_SENSEBUF_FACTOR 3 146 #define MPI3MR_CHAINBUF_FACTOR 3 147 #define MPI3MR_CHAINBUFDIX_FACTOR 2 148 149 /* Invalid target device handle */ 150 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 151 152 /* Controller Reset related definitions */ 153 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 154 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 155 156 /* ResponseCode definitions */ 157 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 158 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 159 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 160 161 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 162 #define MPI3MR_DEFAULT_PGSZEXP (12) 163 164 /* Command retry count definitions */ 165 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 166 #define MPI3MR_PEL_RETRY_COUNT 3 167 168 /* Default target device queue depth */ 169 #define MPI3MR_DEFAULT_SDEV_QD 32 170 171 /* Definitions for Threaded IRQ poll*/ 172 #define MPI3MR_IRQ_POLL_SLEEP 2 173 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 174 175 /* Definitions for the controller security status*/ 176 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 177 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 178 179 #define MPI3MR_INVALID_DEVICE 0x00 180 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 181 #define MPI3MR_HARD_SECURE_DEVICE 0x08 182 #define MPI3MR_TAMPERED_DEVICE 0x0C 183 184 /* SGE Flag definition */ 185 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 186 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 187 MPI3_SGE_FLAGS_END_OF_LIST) 188 189 /* MSI Index from Reply Queue Index */ 190 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 191 192 /* 193 * Maximum data transfer size definitions for management 194 * application commands 195 */ 196 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 197 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 198 /* 199 * 2048 sectors are for data buffers and additional 512 sectors for 200 * other buffers 201 */ 202 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 203 204 /** 205 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 206 * Encapsulated commands. 207 * 208 * @base_addr: Physical address 209 * @length: SGE length 210 * @rsvd: Reserved 211 * @rsvd1: Reserved 212 * @sgl_type: sgl type 213 */ 214 struct mpi3mr_nvme_pt_sge { 215 u64 base_addr; 216 u32 length; 217 u16 rsvd; 218 u8 rsvd1; 219 u8 sgl_type; 220 }; 221 222 /** 223 * struct mpi3mr_buf_map - local structure to 224 * track kernel and user buffers associated with an BSG 225 * structure. 226 * 227 * @bsg_buf: BSG buffer virtual address 228 * @bsg_buf_len: BSG buffer length 229 * @kern_buf: Kernel buffer virtual address 230 * @kern_buf_len: Kernel buffer length 231 * @kern_buf_dma: Kernel buffer DMA address 232 * @data_dir: Data direction. 233 */ 234 struct mpi3mr_buf_map { 235 void *bsg_buf; 236 u32 bsg_buf_len; 237 void *kern_buf; 238 u32 kern_buf_len; 239 dma_addr_t kern_buf_dma; 240 u8 data_dir; 241 }; 242 243 /* IOC State definitions */ 244 enum mpi3mr_iocstate { 245 MRIOC_STATE_READY = 1, 246 MRIOC_STATE_RESET, 247 MRIOC_STATE_FAULT, 248 MRIOC_STATE_BECOMING_READY, 249 MRIOC_STATE_RESET_REQUESTED, 250 MRIOC_STATE_UNRECOVERABLE, 251 }; 252 253 /* Reset reason code definitions*/ 254 enum mpi3mr_reset_reason { 255 MPI3MR_RESET_FROM_BRINGUP = 1, 256 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 257 MPI3MR_RESET_FROM_APP = 3, 258 MPI3MR_RESET_FROM_EH_HOS = 4, 259 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 260 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 261 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 262 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 263 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 264 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 265 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 266 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 267 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 268 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 269 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 270 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 271 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 272 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 273 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 274 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 275 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 276 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 277 MPI3MR_RESET_FROM_SYSFS = 23, 278 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 279 MPI3MR_RESET_FROM_FIRMWARE = 27, 280 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 281 }; 282 283 /* Queue type definitions */ 284 enum queue_type { 285 MPI3MR_DEFAULT_QUEUE = 0, 286 MPI3MR_POLL_QUEUE, 287 }; 288 289 /** 290 * struct mpi3mr_compimg_ver - replica of component image 291 * version defined in mpi30_image.h in host endianness 292 * 293 */ 294 struct mpi3mr_compimg_ver { 295 u16 build_num; 296 u16 cust_id; 297 u8 ph_minor; 298 u8 ph_major; 299 u8 gen_minor; 300 u8 gen_major; 301 }; 302 303 /** 304 * struct mpi3mr_ioc_facs - replica of component image version 305 * defined in mpi30_ioc.h in host endianness 306 * 307 */ 308 struct mpi3mr_ioc_facts { 309 u32 ioc_capabilities; 310 struct mpi3mr_compimg_ver fw_ver; 311 u32 mpi_version; 312 u16 max_reqs; 313 u16 product_id; 314 u16 op_req_sz; 315 u16 reply_sz; 316 u16 exceptions; 317 u16 max_perids; 318 u16 max_pds; 319 u16 max_sasexpanders; 320 u16 max_sasinitiators; 321 u16 max_enclosures; 322 u16 max_pcie_switches; 323 u16 max_nvme; 324 u16 max_vds; 325 u16 max_hpds; 326 u16 max_advhpds; 327 u16 max_raid_pds; 328 u16 min_devhandle; 329 u16 max_devhandle; 330 u16 max_op_req_q; 331 u16 max_op_reply_q; 332 u16 shutdown_timeout; 333 u8 ioc_num; 334 u8 who_init; 335 u16 max_msix_vectors; 336 u8 personality; 337 u8 dma_mask; 338 u8 protocol_flags; 339 u8 sge_mod_mask; 340 u8 sge_mod_value; 341 u8 sge_mod_shift; 342 u8 max_dev_per_tg; 343 u16 max_io_throttle_group; 344 u16 io_throttle_data_length; 345 u16 io_throttle_low; 346 u16 io_throttle_high; 347 348 }; 349 350 /** 351 * struct segments - memory descriptor structure to store 352 * virtual and dma addresses for operational queue segments. 353 * 354 * @segment: virtual address 355 * @segment_dma: dma address 356 */ 357 struct segments { 358 void *segment; 359 dma_addr_t segment_dma; 360 }; 361 362 /** 363 * struct op_req_qinfo - Operational Request Queue Information 364 * 365 * @ci: consumer index 366 * @pi: producer index 367 * @num_request: Maximum number of entries in the queue 368 * @qid: Queue Id starting from 1 369 * @reply_qid: Associated reply queue Id 370 * @num_segments: Number of discontiguous memory segments 371 * @segment_qd: Depth of each segments 372 * @q_lock: Concurrent queue access lock 373 * @q_segments: Segment descriptor pointer 374 * @q_segment_list: Segment list base virtual address 375 * @q_segment_list_dma: Segment list base DMA address 376 */ 377 struct op_req_qinfo { 378 u16 ci; 379 u16 pi; 380 u16 num_requests; 381 u16 qid; 382 u16 reply_qid; 383 u16 num_segments; 384 u16 segment_qd; 385 spinlock_t q_lock; 386 struct segments *q_segments; 387 void *q_segment_list; 388 dma_addr_t q_segment_list_dma; 389 }; 390 391 /** 392 * struct op_reply_qinfo - Operational Reply Queue Information 393 * 394 * @ci: consumer index 395 * @qid: Queue Id starting from 1 396 * @num_replies: Maximum number of entries in the queue 397 * @num_segments: Number of discontiguous memory segments 398 * @segment_qd: Depth of each segments 399 * @q_segments: Segment descriptor pointer 400 * @q_segment_list: Segment list base virtual address 401 * @q_segment_list_dma: Segment list base DMA address 402 * @ephase: Expected phased identifier for the reply queue 403 * @pend_ios: Number of IOs pending in HW for this queue 404 * @enable_irq_poll: Flag to indicate polling is enabled 405 * @in_use: Queue is handled by poll/ISR 406 * @qtype: Type of queue (types defined in enum queue_type) 407 */ 408 struct op_reply_qinfo { 409 u16 ci; 410 u16 qid; 411 u16 num_replies; 412 u16 num_segments; 413 u16 segment_qd; 414 struct segments *q_segments; 415 void *q_segment_list; 416 dma_addr_t q_segment_list_dma; 417 u8 ephase; 418 atomic_t pend_ios; 419 bool enable_irq_poll; 420 atomic_t in_use; 421 enum queue_type qtype; 422 }; 423 424 /** 425 * struct mpi3mr_intr_info - Interrupt cookie information 426 * 427 * @mrioc: Adapter instance reference 428 * @msix_index: MSIx index 429 * @op_reply_q: Associated operational reply queue 430 * @name: Dev name for the irq claiming device 431 */ 432 struct mpi3mr_intr_info { 433 struct mpi3mr_ioc *mrioc; 434 u16 msix_index; 435 struct op_reply_qinfo *op_reply_q; 436 char name[MPI3MR_NAME_LENGTH]; 437 }; 438 439 /** 440 * struct mpi3mr_throttle_group_info - Throttle group info 441 * 442 * @io_divert: Flag indicates io divert is on or off for the TG 443 * @need_qd_reduction: Flag to indicate QD reduction is needed 444 * @qd_reduction: Queue Depth reduction in units of 10% 445 * @fw_qd: QueueDepth value reported by the firmware 446 * @modified_qd: Modified QueueDepth value due to throttling 447 * @id: Throttle Group ID. 448 * @high: High limit to turn on throttling in 512 byte blocks 449 * @low: Low limit to turn off throttling in 512 byte blocks 450 * @pend_large_data_sz: Counter to track pending large data 451 */ 452 struct mpi3mr_throttle_group_info { 453 u8 io_divert; 454 u8 need_qd_reduction; 455 u8 qd_reduction; 456 u16 fw_qd; 457 u16 modified_qd; 458 u16 id; 459 u32 high; 460 u32 low; 461 atomic_t pend_large_data_sz; 462 }; 463 464 /** 465 * struct mpi3mr_enclosure_node - enclosure information 466 * @list: List of enclosures 467 * @pg0: Enclosure page 0; 468 */ 469 struct mpi3mr_enclosure_node { 470 struct list_head list; 471 struct mpi3_enclosure_page0 pg0; 472 }; 473 474 /** 475 * struct tgt_dev_sas_sata - SAS/SATA device specific 476 * information cached from firmware given data 477 * 478 * @sas_address: World wide unique SAS address 479 * @dev_info: Device information bits 480 */ 481 struct tgt_dev_sas_sata { 482 u64 sas_address; 483 u16 dev_info; 484 }; 485 486 /** 487 * struct tgt_dev_pcie - PCIe device specific information cached 488 * from firmware given data 489 * 490 * @mdts: Maximum data transfer size 491 * @capb: Device capabilities 492 * @pgsz: Device page size 493 * @abort_to: Timeout for abort TM 494 * @reset_to: Timeout for Target/LUN reset TM 495 * @dev_info: Device information bits 496 */ 497 struct tgt_dev_pcie { 498 u32 mdts; 499 u16 capb; 500 u8 pgsz; 501 u8 abort_to; 502 u8 reset_to; 503 u16 dev_info; 504 }; 505 506 /** 507 * struct tgt_dev_vd - virtual device specific information 508 * cached from firmware given data 509 * 510 * @state: State of the VD 511 * @tg_qd_reduction: Queue Depth reduction in units of 10% 512 * @tg_id: VDs throttle group ID 513 * @high: High limit to turn on throttling in 512 byte blocks 514 * @low: Low limit to turn off throttling in 512 byte blocks 515 * @tg: Pointer to throttle group info 516 */ 517 struct tgt_dev_vd { 518 u8 state; 519 u8 tg_qd_reduction; 520 u16 tg_id; 521 u32 tg_high; 522 u32 tg_low; 523 struct mpi3mr_throttle_group_info *tg; 524 }; 525 526 527 /** 528 * union _form_spec_inf - union of device specific information 529 */ 530 union _form_spec_inf { 531 struct tgt_dev_sas_sata sas_sata_inf; 532 struct tgt_dev_pcie pcie_inf; 533 struct tgt_dev_vd vd_inf; 534 }; 535 536 537 538 /** 539 * struct mpi3mr_tgt_dev - target device data structure 540 * 541 * @list: List pointer 542 * @starget: Scsi_target pointer 543 * @dev_handle: FW device handle 544 * @parent_handle: FW parent device handle 545 * @slot: Slot number 546 * @encl_handle: FW enclosure handle 547 * @perst_id: FW assigned Persistent ID 548 * @devpg0_flag: Device Page0 flag 549 * @dev_type: SAS/SATA/PCIE device type 550 * @is_hidden: Should be exposed to upper layers or not 551 * @host_exposed: Already exposed to host or not 552 * @io_throttle_enabled: I/O throttling needed or not 553 * @q_depth: Device specific Queue Depth 554 * @wwid: World wide ID 555 * @enclosure_logical_id: Enclosure logical identifier 556 * @dev_spec: Device type specific information 557 * @ref_count: Reference count 558 */ 559 struct mpi3mr_tgt_dev { 560 struct list_head list; 561 struct scsi_target *starget; 562 u16 dev_handle; 563 u16 parent_handle; 564 u16 slot; 565 u16 encl_handle; 566 u16 perst_id; 567 u16 devpg0_flag; 568 u8 dev_type; 569 u8 is_hidden; 570 u8 host_exposed; 571 u8 io_throttle_enabled; 572 u16 q_depth; 573 u64 wwid; 574 u64 enclosure_logical_id; 575 union _form_spec_inf dev_spec; 576 struct kref ref_count; 577 }; 578 579 /** 580 * mpi3mr_tgtdev_get - k reference incrementor 581 * @s: Target device reference 582 * 583 * Increment target device reference count. 584 */ 585 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 586 { 587 kref_get(&s->ref_count); 588 } 589 590 /** 591 * mpi3mr_free_tgtdev - target device memory dealloctor 592 * @r: k reference pointer of the target device 593 * 594 * Free target device memory when no reference. 595 */ 596 static inline void mpi3mr_free_tgtdev(struct kref *r) 597 { 598 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 599 } 600 601 /** 602 * mpi3mr_tgtdev_put - k reference decrementor 603 * @s: Target device reference 604 * 605 * Decrement target device reference count. 606 */ 607 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 608 { 609 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 610 } 611 612 613 /** 614 * struct mpi3mr_stgt_priv_data - SCSI target private structure 615 * 616 * @starget: Scsi_target pointer 617 * @dev_handle: FW device handle 618 * @perst_id: FW assigned Persistent ID 619 * @num_luns: Number of Logical Units 620 * @block_io: I/O blocked to the device or not 621 * @dev_removed: Device removed in the Firmware 622 * @dev_removedelay: Device is waiting to be removed in FW 623 * @dev_type: Device type 624 * @io_throttle_enabled: I/O throttling needed or not 625 * @io_divert: Flag indicates io divert is on or off for the dev 626 * @throttle_group: Pointer to throttle group info 627 * @tgt_dev: Internal target device pointer 628 * @pend_count: Counter to track pending I/Os during error 629 * handling 630 */ 631 struct mpi3mr_stgt_priv_data { 632 struct scsi_target *starget; 633 u16 dev_handle; 634 u16 perst_id; 635 u32 num_luns; 636 atomic_t block_io; 637 u8 dev_removed; 638 u8 dev_removedelay; 639 u8 dev_type; 640 u8 io_throttle_enabled; 641 u8 io_divert; 642 struct mpi3mr_throttle_group_info *throttle_group; 643 struct mpi3mr_tgt_dev *tgt_dev; 644 u32 pend_count; 645 }; 646 647 /** 648 * struct mpi3mr_stgt_priv_data - SCSI device private structure 649 * 650 * @tgt_priv_data: Scsi_target private data pointer 651 * @lun_id: LUN ID of the device 652 * @ncq_prio_enable: NCQ priority enable for SATA device 653 * @pend_count: Counter to track pending I/Os during error 654 * handling 655 */ 656 struct mpi3mr_sdev_priv_data { 657 struct mpi3mr_stgt_priv_data *tgt_priv_data; 658 u32 lun_id; 659 u8 ncq_prio_enable; 660 u32 pend_count; 661 }; 662 663 /** 664 * struct mpi3mr_drv_cmd - Internal command tracker 665 * 666 * @mutex: Command mutex 667 * @done: Completeor for wakeup 668 * @reply: Firmware reply for internal commands 669 * @sensebuf: Sensebuf for SCSI IO commands 670 * @iou_rc: IO Unit control reason code 671 * @state: Command State 672 * @dev_handle: Firmware handle for device specific commands 673 * @ioc_status: IOC status from the firmware 674 * @ioc_loginfo:IOC log info from the firmware 675 * @is_waiting: Is the command issued in block mode 676 * @is_sense: Is Sense data present 677 * @retry_count: Retry count for retriable commands 678 * @host_tag: Host tag used by the command 679 * @callback: Callback for non blocking commands 680 */ 681 struct mpi3mr_drv_cmd { 682 struct mutex mutex; 683 struct completion done; 684 void *reply; 685 u8 *sensebuf; 686 u8 iou_rc; 687 u16 state; 688 u16 dev_handle; 689 u16 ioc_status; 690 u32 ioc_loginfo; 691 u8 is_waiting; 692 u8 is_sense; 693 u8 retry_count; 694 u16 host_tag; 695 696 void (*callback)(struct mpi3mr_ioc *mrioc, 697 struct mpi3mr_drv_cmd *drv_cmd); 698 }; 699 700 /** 701 * struct dma_memory_desc - memory descriptor structure to store 702 * virtual address, dma address and size for any generic dma 703 * memory allocations in the driver. 704 * 705 * @size: buffer size 706 * @addr: virtual address 707 * @dma_addr: dma address 708 */ 709 struct dma_memory_desc { 710 u32 size; 711 void *addr; 712 dma_addr_t dma_addr; 713 }; 714 715 716 /** 717 * struct chain_element - memory descriptor structure to store 718 * virtual and dma addresses for chain elements. 719 * 720 * @addr: virtual address 721 * @dma_addr: dma address 722 */ 723 struct chain_element { 724 void *addr; 725 dma_addr_t dma_addr; 726 }; 727 728 /** 729 * struct scmd_priv - SCSI command private data 730 * 731 * @host_tag: Host tag specific to operational queue 732 * @in_lld_scope: Command in LLD scope or not 733 * @meta_sg_valid: DIX command with meta data SGL or not 734 * @scmd: SCSI Command pointer 735 * @req_q_idx: Operational request queue index 736 * @chain_idx: Chain frame index 737 * @meta_chain_idx: Chain frame index of meta data SGL 738 * @mpi3mr_scsiio_req: MPI SCSI IO request 739 */ 740 struct scmd_priv { 741 u16 host_tag; 742 u8 in_lld_scope; 743 u8 meta_sg_valid; 744 struct scsi_cmnd *scmd; 745 u16 req_q_idx; 746 int chain_idx; 747 int meta_chain_idx; 748 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 749 }; 750 751 /** 752 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 753 * private data 754 * 755 * @list: List pointer 756 * @pdev: PCI device pointer 757 * @shost: Scsi_Host pointer 758 * @id: Controller ID 759 * @cpu_count: Number of online CPUs 760 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 761 * @name: Controller ASCII name 762 * @driver_name: Driver ASCII name 763 * @sysif_regs: System interface registers virtual address 764 * @sysif_regs_phys: System interface registers physical address 765 * @bars: PCI BARS 766 * @dma_mask: DMA mask 767 * @msix_count: Number of MSIX vectors used 768 * @intr_enabled: Is interrupts enabled 769 * @num_admin_req: Number of admin requests 770 * @admin_req_q_sz: Admin request queue size 771 * @admin_req_pi: Admin request queue producer index 772 * @admin_req_ci: Admin request queue consumer index 773 * @admin_req_base: Admin request queue base virtual address 774 * @admin_req_dma: Admin request queue base dma address 775 * @admin_req_lock: Admin queue access lock 776 * @num_admin_replies: Number of admin replies 777 * @admin_reply_q_sz: Admin reply queue size 778 * @admin_reply_ci: Admin reply queue consumer index 779 * @admin_reply_ephase:Admin reply queue expected phase 780 * @admin_reply_base: Admin reply queue base virtual address 781 * @admin_reply_dma: Admin reply queue base dma address 782 * @ready_timeout: Controller ready timeout 783 * @intr_info: Interrupt cookie pointer 784 * @intr_info_count: Number of interrupt cookies 785 * @is_intr_info_set: Flag to indicate intr info is setup 786 * @num_queues: Number of operational queues 787 * @num_op_req_q: Number of operational request queues 788 * @req_qinfo: Operational request queue info pointer 789 * @num_op_reply_q: Number of operational reply queues 790 * @op_reply_qinfo: Operational reply queue info pointer 791 * @init_cmds: Command tracker for initialization commands 792 * @cfg_cmds: Command tracker for configuration requests 793 * @facts: Cached IOC facts data 794 * @op_reply_desc_sz: Operational reply descriptor size 795 * @num_reply_bufs: Number of reply buffers allocated 796 * @reply_buf_pool: Reply buffer pool 797 * @reply_buf: Reply buffer base virtual address 798 * @reply_buf_dma: Reply buffer DMA address 799 * @reply_buf_dma_max_address: Reply DMA address max limit 800 * @reply_free_qsz: Reply free queue size 801 * @reply_free_q_pool: Reply free queue pool 802 * @reply_free_q: Reply free queue base virtual address 803 * @reply_free_q_dma: Reply free queue base DMA address 804 * @reply_free_queue_lock: Reply free queue lock 805 * @reply_free_queue_host_index: Reply free queue host index 806 * @num_sense_bufs: Number of sense buffers 807 * @sense_buf_pool: Sense buffer pool 808 * @sense_buf: Sense buffer base virtual address 809 * @sense_buf_dma: Sense buffer base DMA address 810 * @sense_buf_q_sz: Sense buffer queue size 811 * @sense_buf_q_pool: Sense buffer queue pool 812 * @sense_buf_q: Sense buffer queue virtual address 813 * @sense_buf_q_dma: Sense buffer queue DMA address 814 * @sbq_lock: Sense buffer queue lock 815 * @sbq_host_index: Sense buffer queuehost index 816 * @event_masks: Event mask bitmap 817 * @fwevt_worker_name: Firmware event worker thread name 818 * @fwevt_worker_thread: Firmware event worker thread 819 * @fwevt_lock: Firmware event lock 820 * @fwevt_list: Firmware event list 821 * @watchdog_work_q_name: Fault watchdog worker thread name 822 * @watchdog_work_q: Fault watchdog worker thread 823 * @watchdog_work: Fault watchdog work 824 * @watchdog_lock: Fault watchdog lock 825 * @is_driver_loading: Is driver still loading 826 * @scan_started: Async scan started 827 * @scan_failed: Asycn scan failed 828 * @stop_drv_processing: Stop all command processing 829 * @max_host_ios: Maximum host I/O count 830 * @chain_buf_count: Chain buffer count 831 * @chain_buf_pool: Chain buffer pool 832 * @chain_sgl_list: Chain SGL list 833 * @chain_bitmap_sz: Chain buffer allocator bitmap size 834 * @chain_bitmap: Chain buffer allocator bitmap 835 * @chain_buf_lock: Chain buffer list lock 836 * @bsg_cmds: Command tracker for BSG command 837 * @host_tm_cmds: Command tracker for task management commands 838 * @dev_rmhs_cmds: Command tracker for device removal commands 839 * @evtack_cmds: Command tracker for event ack commands 840 * @devrem_bitmap_sz: Device removal bitmap size 841 * @devrem_bitmap: Device removal bitmap 842 * @dev_handle_bitmap_sz: Device handle bitmap size 843 * @removepend_bitmap: Remove pending bitmap 844 * @delayed_rmhs_list: Delayed device removal list 845 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 846 * @evtack_cmds_bitmap: Event Ack bitmap 847 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 848 * @ts_update_counter: Timestamp update counter 849 * @reset_in_progress: Reset in progress flag 850 * @unrecoverable: Controller unrecoverable flag 851 * @prev_reset_result: Result of previous reset 852 * @reset_mutex: Controller reset mutex 853 * @reset_waitq: Controller reset wait queue 854 * @prepare_for_reset: Prepare for reset event received 855 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 856 * @prp_list_virt: NVMe encapsulated PRP list virtual base 857 * @prp_list_dma: NVMe encapsulated PRP list DMA 858 * @prp_sz: NVME encapsulated PRP list size 859 * @diagsave_timeout: Diagnostic information save timeout 860 * @logging_level: Controller debug logging level 861 * @flush_io_count: I/O count to flush after reset 862 * @current_event: Firmware event currently in process 863 * @driver_info: Driver, Kernel, OS information to firmware 864 * @change_count: Topology change count 865 * @pel_enabled: Persistent Event Log(PEL) enabled or not 866 * @pel_abort_requested: PEL abort is requested or not 867 * @pel_class: PEL Class identifier 868 * @pel_locale: PEL Locale identifier 869 * @pel_cmds: Command tracker for PEL wait command 870 * @pel_abort_cmd: Command tracker for PEL abort command 871 * @pel_newest_seqnum: Newest PEL sequenece number 872 * @pel_seqnum_virt: PEL sequence number virtual address 873 * @pel_seqnum_dma: PEL sequence number DMA address 874 * @pel_seqnum_sz: PEL sequenece number size 875 * @op_reply_q_offset: Operational reply queue offset with MSIx 876 * @default_qcount: Total Default queues 877 * @active_poll_qcount: Currently active poll queue count 878 * @requested_poll_qcount: User requested poll queue count 879 * @bsg_dev: BSG device structure 880 * @bsg_queue: Request queue for BSG device 881 * @stop_bsgs: Stop BSG request flag 882 * @logdata_buf: Circular buffer to store log data entries 883 * @logdata_buf_idx: Index of entry in buffer to store 884 * @logdata_entry_sz: log data entry size 885 * @pend_large_data_sz: Counter to track pending large data 886 * @io_throttle_data_length: I/O size to track in 512b blocks 887 * @io_throttle_high: I/O size to start throttle in 512b blocks 888 * @io_throttle_low: I/O size to stop throttle in 512b blocks 889 * @num_io_throttle_group: Maximum number of throttle groups 890 * @throttle_groups: Pointer to throttle group info structures 891 * @cfg_page: Default memory for configuration pages 892 * @cfg_page_dma: Configuration page DMA address 893 * @cfg_page_sz: Default configuration page memory size 894 * @enclosure_list: List of Enclosure objects 895 */ 896 struct mpi3mr_ioc { 897 struct list_head list; 898 struct pci_dev *pdev; 899 struct Scsi_Host *shost; 900 u8 id; 901 int cpu_count; 902 bool enable_segqueue; 903 u32 irqpoll_sleep; 904 905 char name[MPI3MR_NAME_LENGTH]; 906 char driver_name[MPI3MR_NAME_LENGTH]; 907 908 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 909 resource_size_t sysif_regs_phys; 910 int bars; 911 u64 dma_mask; 912 913 u16 msix_count; 914 u8 intr_enabled; 915 916 u16 num_admin_req; 917 u32 admin_req_q_sz; 918 u16 admin_req_pi; 919 u16 admin_req_ci; 920 void *admin_req_base; 921 dma_addr_t admin_req_dma; 922 spinlock_t admin_req_lock; 923 924 u16 num_admin_replies; 925 u32 admin_reply_q_sz; 926 u16 admin_reply_ci; 927 u8 admin_reply_ephase; 928 void *admin_reply_base; 929 dma_addr_t admin_reply_dma; 930 931 u32 ready_timeout; 932 933 struct mpi3mr_intr_info *intr_info; 934 u16 intr_info_count; 935 bool is_intr_info_set; 936 937 u16 num_queues; 938 u16 num_op_req_q; 939 struct op_req_qinfo *req_qinfo; 940 941 u16 num_op_reply_q; 942 struct op_reply_qinfo *op_reply_qinfo; 943 944 struct mpi3mr_drv_cmd init_cmds; 945 struct mpi3mr_drv_cmd cfg_cmds; 946 struct mpi3mr_ioc_facts facts; 947 u16 op_reply_desc_sz; 948 949 u32 num_reply_bufs; 950 struct dma_pool *reply_buf_pool; 951 u8 *reply_buf; 952 dma_addr_t reply_buf_dma; 953 dma_addr_t reply_buf_dma_max_address; 954 955 u16 reply_free_qsz; 956 u16 reply_sz; 957 struct dma_pool *reply_free_q_pool; 958 __le64 *reply_free_q; 959 dma_addr_t reply_free_q_dma; 960 spinlock_t reply_free_queue_lock; 961 u32 reply_free_queue_host_index; 962 963 u32 num_sense_bufs; 964 struct dma_pool *sense_buf_pool; 965 u8 *sense_buf; 966 dma_addr_t sense_buf_dma; 967 968 u16 sense_buf_q_sz; 969 struct dma_pool *sense_buf_q_pool; 970 __le64 *sense_buf_q; 971 dma_addr_t sense_buf_q_dma; 972 spinlock_t sbq_lock; 973 u32 sbq_host_index; 974 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 975 976 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 977 struct workqueue_struct *fwevt_worker_thread; 978 spinlock_t fwevt_lock; 979 struct list_head fwevt_list; 980 981 char watchdog_work_q_name[20]; 982 struct workqueue_struct *watchdog_work_q; 983 struct delayed_work watchdog_work; 984 spinlock_t watchdog_lock; 985 986 u8 is_driver_loading; 987 u8 scan_started; 988 u16 scan_failed; 989 u8 stop_drv_processing; 990 991 u16 max_host_ios; 992 spinlock_t tgtdev_lock; 993 struct list_head tgtdev_list; 994 995 u32 chain_buf_count; 996 struct dma_pool *chain_buf_pool; 997 struct chain_element *chain_sgl_list; 998 u16 chain_bitmap_sz; 999 void *chain_bitmap; 1000 spinlock_t chain_buf_lock; 1001 1002 struct mpi3mr_drv_cmd bsg_cmds; 1003 struct mpi3mr_drv_cmd host_tm_cmds; 1004 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1005 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1006 u16 devrem_bitmap_sz; 1007 void *devrem_bitmap; 1008 u16 dev_handle_bitmap_sz; 1009 void *removepend_bitmap; 1010 struct list_head delayed_rmhs_list; 1011 u16 evtack_cmds_bitmap_sz; 1012 void *evtack_cmds_bitmap; 1013 struct list_head delayed_evtack_cmds_list; 1014 1015 u32 ts_update_counter; 1016 u8 reset_in_progress; 1017 u8 unrecoverable; 1018 int prev_reset_result; 1019 struct mutex reset_mutex; 1020 wait_queue_head_t reset_waitq; 1021 1022 u8 prepare_for_reset; 1023 u16 prepare_for_reset_timeout_counter; 1024 1025 void *prp_list_virt; 1026 dma_addr_t prp_list_dma; 1027 u32 prp_sz; 1028 1029 u16 diagsave_timeout; 1030 int logging_level; 1031 u16 flush_io_count; 1032 1033 struct mpi3mr_fwevt *current_event; 1034 struct mpi3_driver_info_layout driver_info; 1035 u16 change_count; 1036 1037 u8 pel_enabled; 1038 u8 pel_abort_requested; 1039 u8 pel_class; 1040 u16 pel_locale; 1041 struct mpi3mr_drv_cmd pel_cmds; 1042 struct mpi3mr_drv_cmd pel_abort_cmd; 1043 1044 u32 pel_newest_seqnum; 1045 void *pel_seqnum_virt; 1046 dma_addr_t pel_seqnum_dma; 1047 u32 pel_seqnum_sz; 1048 1049 u16 op_reply_q_offset; 1050 u16 default_qcount; 1051 u16 active_poll_qcount; 1052 u16 requested_poll_qcount; 1053 1054 struct device bsg_dev; 1055 struct request_queue *bsg_queue; 1056 u8 stop_bsgs; 1057 u8 *logdata_buf; 1058 u16 logdata_buf_idx; 1059 u16 logdata_entry_sz; 1060 1061 atomic_t pend_large_data_sz; 1062 u32 io_throttle_data_length; 1063 u32 io_throttle_high; 1064 u32 io_throttle_low; 1065 u16 num_io_throttle_group; 1066 struct mpi3mr_throttle_group_info *throttle_groups; 1067 1068 void *cfg_page; 1069 dma_addr_t cfg_page_dma; 1070 u16 cfg_page_sz; 1071 1072 struct list_head enclosure_list; 1073 }; 1074 1075 /** 1076 * struct mpi3mr_fwevt - Firmware event structure. 1077 * 1078 * @list: list head 1079 * @work: Work structure 1080 * @mrioc: Adapter instance reference 1081 * @event_id: MPI3 firmware event ID 1082 * @send_ack: Event acknowledgment required or not 1083 * @process_evt: Bottomhalf processing required or not 1084 * @evt_ctx: Event context to send in Ack 1085 * @event_data_size: size of the event data in bytes 1086 * @pending_at_sml: waiting for device add/remove API to complete 1087 * @discard: discard this event 1088 * @ref_count: kref count 1089 * @event_data: Actual MPI3 event data 1090 */ 1091 struct mpi3mr_fwevt { 1092 struct list_head list; 1093 struct work_struct work; 1094 struct mpi3mr_ioc *mrioc; 1095 u16 event_id; 1096 bool send_ack; 1097 bool process_evt; 1098 u32 evt_ctx; 1099 u16 event_data_size; 1100 bool pending_at_sml; 1101 bool discard; 1102 struct kref ref_count; 1103 char event_data[] __aligned(4); 1104 }; 1105 1106 1107 /** 1108 * struct delayed_dev_rmhs_node - Delayed device removal node 1109 * 1110 * @list: list head 1111 * @handle: Device handle 1112 * @iou_rc: IO Unit Control Reason Code 1113 */ 1114 struct delayed_dev_rmhs_node { 1115 struct list_head list; 1116 u16 handle; 1117 u8 iou_rc; 1118 }; 1119 1120 /** 1121 * struct delayed_evt_ack_node - Delayed event ack node 1122 * @list: list head 1123 * @event: MPI3 event ID 1124 * @event_ctx: event context 1125 */ 1126 struct delayed_evt_ack_node { 1127 struct list_head list; 1128 u8 event; 1129 u32 event_ctx; 1130 }; 1131 1132 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1133 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1134 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1135 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1136 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1137 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1138 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1139 u16 admin_req_sz, u8 ignore_reset); 1140 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1141 struct op_req_qinfo *opreqq, u8 *req); 1142 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1143 dma_addr_t dma_addr); 1144 void mpi3mr_build_zero_len_sge(void *paddr); 1145 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1146 dma_addr_t phys_addr); 1147 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1148 dma_addr_t phys_addr); 1149 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1150 u64 sense_buf_dma); 1151 1152 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1153 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1154 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1155 struct mpi3_event_notification_reply *event_reply); 1156 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1157 struct mpi3_default_reply_descriptor *reply_desc, 1158 u64 *reply_dma, u16 qidx); 1159 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1160 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1161 1162 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1163 u32 reset_reason, u8 snapdump); 1164 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1165 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1166 1167 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1168 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1169 u32 event_ctx); 1170 1171 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1172 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1173 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1174 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1175 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1176 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1177 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1178 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1179 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1180 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1181 struct op_reply_qinfo *op_reply_q); 1182 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1183 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1184 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1185 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1186 u16 handle, uint lun, u16 htag, ulong timeout, 1187 struct mpi3mr_drv_cmd *drv_cmd, 1188 u8 *resp_code, struct scsi_cmnd *scmd); 1189 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1190 struct mpi3mr_ioc *mrioc, u16 handle); 1191 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1192 struct mpi3mr_drv_cmd *drv_cmd); 1193 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1194 struct mpi3mr_drv_cmd *drv_cmd); 1195 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1196 u16 event_data_size); 1197 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1198 struct mpi3mr_ioc *mrioc, u16 handle); 1199 extern const struct attribute_group *mpi3mr_host_groups[]; 1200 extern const struct attribute_group *mpi3mr_dev_groups[]; 1201 1202 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1203 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1204 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1205 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1206 u32 form_spec); 1207 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1208 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1209 u32 form_spec); 1210 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1211 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1212 u32 form_spec); 1213 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1214 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1215 u32 form_spec); 1216 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1217 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1218 u32 form_spec); 1219 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1220 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1221 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1222 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1223 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1224 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1225 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1226 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1227 #endif /*MPI3MR_H_INCLUDED*/ 1228