1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.68.0" 59 #define MPI3MR_DRIVER_RELDATE "10-February-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 /* Definitions for internal SGL and Chain SGL buffers */ 70 #define MPI3MR_PAGE_SIZE_4K 4096 71 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 72 73 /* Definitions for MAX values for shost */ 74 #define MPI3MR_MAX_CMDS_LUN 7 75 #define MPI3MR_MAX_CDB_LENGTH 32 76 77 /* Admin queue management definitions */ 78 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 79 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 80 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 81 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 82 83 /* Operational queue management definitions */ 84 #define MPI3MR_OP_REQ_Q_QD 512 85 #define MPI3MR_OP_REP_Q_QD 1024 86 #define MPI3MR_OP_REP_Q_QD4K 4096 87 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 88 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 89 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 90 91 /* Reserved Host Tag definitions */ 92 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 93 #define MPI3MR_HOSTTAG_INITCMDS 1 94 #define MPI3MR_HOSTTAG_BSG_CMDS 2 95 #define MPI3MR_HOSTTAG_PEL_ABORT 3 96 #define MPI3MR_HOSTTAG_PEL_WAIT 4 97 #define MPI3MR_HOSTTAG_BLK_TMS 5 98 99 #define MPI3MR_NUM_DEVRMCMD 16 100 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 101 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 102 MPI3MR_NUM_DEVRMCMD - 1) 103 104 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 105 #define MPI3MR_NUM_EVTACKCMD 4 106 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 107 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 108 MPI3MR_NUM_EVTACKCMD - 1) 109 110 /* Reduced resource count definition for crash kernel */ 111 #define MPI3MR_HOST_IOS_KDUMP 128 112 113 /* command/controller interaction timeout definitions in seconds */ 114 #define MPI3MR_INTADMCMD_TIMEOUT 60 115 #define MPI3MR_PORTENABLE_TIMEOUT 300 116 #define MPI3MR_ABORTTM_TIMEOUT 60 117 #define MPI3MR_RESETTM_TIMEOUT 60 118 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 119 #define MPI3MR_TSUPDATE_INTERVAL 900 120 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 121 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 122 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 123 #define MPI3MR_RESET_ACK_TIMEOUT 30 124 125 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 126 127 /* Internal admin command state definitions*/ 128 #define MPI3MR_CMD_NOTUSED 0x8000 129 #define MPI3MR_CMD_COMPLETE 0x0001 130 #define MPI3MR_CMD_PENDING 0x0002 131 #define MPI3MR_CMD_REPLY_VALID 0x0004 132 #define MPI3MR_CMD_RESET 0x0008 133 134 /* Definitions for Event replies and sense buffer allocated per controller */ 135 #define MPI3MR_NUM_EVT_REPLIES 64 136 #define MPI3MR_SENSE_BUF_SZ 256 137 #define MPI3MR_SENSEBUF_FACTOR 3 138 #define MPI3MR_CHAINBUF_FACTOR 3 139 #define MPI3MR_CHAINBUFDIX_FACTOR 2 140 141 /* Invalid target device handle */ 142 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 143 144 /* Controller Reset related definitions */ 145 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 146 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 147 148 /* ResponseCode definitions */ 149 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 150 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 151 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 152 153 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 154 #define MPI3MR_DEFAULT_PGSZEXP (12) 155 156 /* Command retry count definitions */ 157 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 158 #define MPI3MR_PEL_RETRY_COUNT 3 159 160 /* Default target device queue depth */ 161 #define MPI3MR_DEFAULT_SDEV_QD 32 162 163 /* Definitions for Threaded IRQ poll*/ 164 #define MPI3MR_IRQ_POLL_SLEEP 2 165 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 166 167 /* Definitions for the controller security status*/ 168 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 169 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 170 171 #define MPI3MR_INVALID_DEVICE 0x00 172 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 173 #define MPI3MR_HARD_SECURE_DEVICE 0x08 174 #define MPI3MR_TAMPERED_DEVICE 0x0C 175 176 /* SGE Flag definition */ 177 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 178 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 179 MPI3_SGE_FLAGS_END_OF_LIST) 180 181 /* MSI Index from Reply Queue Index */ 182 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 183 184 /* 185 * Maximum data transfer size definitions for management 186 * application commands 187 */ 188 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 189 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 190 /* 191 * 2048 sectors are for data buffers and additional 512 sectors for 192 * other buffers 193 */ 194 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 195 196 /** 197 * struct mpi3mr_buf_map - local structure to 198 * track kernel and user buffers associated with an BSG 199 * structure. 200 * 201 * @bsg_buf: BSG buffer virtual address 202 * @bsg_buf_len: BSG buffer length 203 * @kern_buf: Kernel buffer virtual address 204 * @kern_buf_len: Kernel buffer length 205 * @kern_buf_dma: Kernel buffer DMA address 206 * @data_dir: Data direction. 207 */ 208 struct mpi3mr_buf_map { 209 void *bsg_buf; 210 u32 bsg_buf_len; 211 void *kern_buf; 212 u32 kern_buf_len; 213 dma_addr_t kern_buf_dma; 214 u8 data_dir; 215 }; 216 217 /* IOC State definitions */ 218 enum mpi3mr_iocstate { 219 MRIOC_STATE_READY = 1, 220 MRIOC_STATE_RESET, 221 MRIOC_STATE_FAULT, 222 MRIOC_STATE_BECOMING_READY, 223 MRIOC_STATE_RESET_REQUESTED, 224 MRIOC_STATE_UNRECOVERABLE, 225 }; 226 227 /* Reset reason code definitions*/ 228 enum mpi3mr_reset_reason { 229 MPI3MR_RESET_FROM_BRINGUP = 1, 230 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 231 MPI3MR_RESET_FROM_APP = 3, 232 MPI3MR_RESET_FROM_EH_HOS = 4, 233 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 234 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 235 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 236 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 237 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 238 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 239 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 240 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 241 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 242 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 243 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 244 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 245 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 246 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 247 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 248 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 249 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 250 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 251 MPI3MR_RESET_FROM_SYSFS = 23, 252 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 253 MPI3MR_RESET_FROM_FIRMWARE = 27, 254 }; 255 256 /* Queue type definitions */ 257 enum queue_type { 258 MPI3MR_DEFAULT_QUEUE = 0, 259 MPI3MR_POLL_QUEUE, 260 }; 261 262 /** 263 * struct mpi3mr_compimg_ver - replica of component image 264 * version defined in mpi30_image.h in host endianness 265 * 266 */ 267 struct mpi3mr_compimg_ver { 268 u16 build_num; 269 u16 cust_id; 270 u8 ph_minor; 271 u8 ph_major; 272 u8 gen_minor; 273 u8 gen_major; 274 }; 275 276 /** 277 * struct mpi3mr_ioc_facs - replica of component image version 278 * defined in mpi30_ioc.h in host endianness 279 * 280 */ 281 struct mpi3mr_ioc_facts { 282 u32 ioc_capabilities; 283 struct mpi3mr_compimg_ver fw_ver; 284 u32 mpi_version; 285 u16 max_reqs; 286 u16 product_id; 287 u16 op_req_sz; 288 u16 reply_sz; 289 u16 exceptions; 290 u16 max_perids; 291 u16 max_pds; 292 u16 max_sasexpanders; 293 u16 max_sasinitiators; 294 u16 max_enclosures; 295 u16 max_pcie_switches; 296 u16 max_nvme; 297 u16 max_vds; 298 u16 max_hpds; 299 u16 max_advhpds; 300 u16 max_raid_pds; 301 u16 min_devhandle; 302 u16 max_devhandle; 303 u16 max_op_req_q; 304 u16 max_op_reply_q; 305 u16 shutdown_timeout; 306 u8 ioc_num; 307 u8 who_init; 308 u16 max_msix_vectors; 309 u8 personality; 310 u8 dma_mask; 311 u8 protocol_flags; 312 u8 sge_mod_mask; 313 u8 sge_mod_value; 314 u8 sge_mod_shift; 315 }; 316 317 /** 318 * struct segments - memory descriptor structure to store 319 * virtual and dma addresses for operational queue segments. 320 * 321 * @segment: virtual address 322 * @segment_dma: dma address 323 */ 324 struct segments { 325 void *segment; 326 dma_addr_t segment_dma; 327 }; 328 329 /** 330 * struct op_req_qinfo - Operational Request Queue Information 331 * 332 * @ci: consumer index 333 * @pi: producer index 334 * @num_request: Maximum number of entries in the queue 335 * @qid: Queue Id starting from 1 336 * @reply_qid: Associated reply queue Id 337 * @num_segments: Number of discontiguous memory segments 338 * @segment_qd: Depth of each segments 339 * @q_lock: Concurrent queue access lock 340 * @q_segments: Segment descriptor pointer 341 * @q_segment_list: Segment list base virtual address 342 * @q_segment_list_dma: Segment list base DMA address 343 */ 344 struct op_req_qinfo { 345 u16 ci; 346 u16 pi; 347 u16 num_requests; 348 u16 qid; 349 u16 reply_qid; 350 u16 num_segments; 351 u16 segment_qd; 352 spinlock_t q_lock; 353 struct segments *q_segments; 354 void *q_segment_list; 355 dma_addr_t q_segment_list_dma; 356 }; 357 358 /** 359 * struct op_reply_qinfo - Operational Reply Queue Information 360 * 361 * @ci: consumer index 362 * @qid: Queue Id starting from 1 363 * @num_replies: Maximum number of entries in the queue 364 * @num_segments: Number of discontiguous memory segments 365 * @segment_qd: Depth of each segments 366 * @q_segments: Segment descriptor pointer 367 * @q_segment_list: Segment list base virtual address 368 * @q_segment_list_dma: Segment list base DMA address 369 * @ephase: Expected phased identifier for the reply queue 370 * @pend_ios: Number of IOs pending in HW for this queue 371 * @enable_irq_poll: Flag to indicate polling is enabled 372 * @in_use: Queue is handled by poll/ISR 373 * @qtype: Type of queue (types defined in enum queue_type) 374 */ 375 struct op_reply_qinfo { 376 u16 ci; 377 u16 qid; 378 u16 num_replies; 379 u16 num_segments; 380 u16 segment_qd; 381 struct segments *q_segments; 382 void *q_segment_list; 383 dma_addr_t q_segment_list_dma; 384 u8 ephase; 385 atomic_t pend_ios; 386 bool enable_irq_poll; 387 atomic_t in_use; 388 enum queue_type qtype; 389 }; 390 391 /** 392 * struct mpi3mr_intr_info - Interrupt cookie information 393 * 394 * @mrioc: Adapter instance reference 395 * @msix_index: MSIx index 396 * @op_reply_q: Associated operational reply queue 397 * @name: Dev name for the irq claiming device 398 */ 399 struct mpi3mr_intr_info { 400 struct mpi3mr_ioc *mrioc; 401 u16 msix_index; 402 struct op_reply_qinfo *op_reply_q; 403 char name[MPI3MR_NAME_LENGTH]; 404 }; 405 406 /** 407 * struct tgt_dev_sas_sata - SAS/SATA device specific 408 * information cached from firmware given data 409 * 410 * @sas_address: World wide unique SAS address 411 * @dev_info: Device information bits 412 */ 413 struct tgt_dev_sas_sata { 414 u64 sas_address; 415 u16 dev_info; 416 }; 417 418 /** 419 * struct tgt_dev_pcie - PCIe device specific information cached 420 * from firmware given data 421 * 422 * @mdts: Maximum data transfer size 423 * @capb: Device capabilities 424 * @pgsz: Device page size 425 * @abort_to: Timeout for abort TM 426 * @reset_to: Timeout for Target/LUN reset TM 427 * @dev_info: Device information bits 428 */ 429 struct tgt_dev_pcie { 430 u32 mdts; 431 u16 capb; 432 u8 pgsz; 433 u8 abort_to; 434 u8 reset_to; 435 u16 dev_info; 436 }; 437 438 /** 439 * struct tgt_dev_volume - virtual device specific information 440 * cached from firmware given data 441 * 442 * @state: State of the VD 443 */ 444 struct tgt_dev_volume { 445 u8 state; 446 }; 447 448 /** 449 * union _form_spec_inf - union of device specific information 450 */ 451 union _form_spec_inf { 452 struct tgt_dev_sas_sata sas_sata_inf; 453 struct tgt_dev_pcie pcie_inf; 454 struct tgt_dev_volume vol_inf; 455 }; 456 457 458 459 /** 460 * struct mpi3mr_tgt_dev - target device data structure 461 * 462 * @list: List pointer 463 * @starget: Scsi_target pointer 464 * @dev_handle: FW device handle 465 * @parent_handle: FW parent device handle 466 * @slot: Slot number 467 * @encl_handle: FW enclosure handle 468 * @perst_id: FW assigned Persistent ID 469 * @dev_type: SAS/SATA/PCIE device type 470 * @is_hidden: Should be exposed to upper layers or not 471 * @host_exposed: Already exposed to host or not 472 * @q_depth: Device specific Queue Depth 473 * @wwid: World wide ID 474 * @dev_spec: Device type specific information 475 * @ref_count: Reference count 476 */ 477 struct mpi3mr_tgt_dev { 478 struct list_head list; 479 struct scsi_target *starget; 480 u16 dev_handle; 481 u16 parent_handle; 482 u16 slot; 483 u16 encl_handle; 484 u16 perst_id; 485 u8 dev_type; 486 u8 is_hidden; 487 u8 host_exposed; 488 u16 q_depth; 489 u64 wwid; 490 union _form_spec_inf dev_spec; 491 struct kref ref_count; 492 }; 493 494 /** 495 * mpi3mr_tgtdev_get - k reference incrementor 496 * @s: Target device reference 497 * 498 * Increment target device reference count. 499 */ 500 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 501 { 502 kref_get(&s->ref_count); 503 } 504 505 /** 506 * mpi3mr_free_tgtdev - target device memory dealloctor 507 * @r: k reference pointer of the target device 508 * 509 * Free target device memory when no reference. 510 */ 511 static inline void mpi3mr_free_tgtdev(struct kref *r) 512 { 513 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 514 } 515 516 /** 517 * mpi3mr_tgtdev_put - k reference decrementor 518 * @s: Target device reference 519 * 520 * Decrement target device reference count. 521 */ 522 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 523 { 524 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 525 } 526 527 528 /** 529 * struct mpi3mr_stgt_priv_data - SCSI target private structure 530 * 531 * @starget: Scsi_target pointer 532 * @dev_handle: FW device handle 533 * @perst_id: FW assigned Persistent ID 534 * @num_luns: Number of Logical Units 535 * @block_io: I/O blocked to the device or not 536 * @dev_removed: Device removed in the Firmware 537 * @dev_removedelay: Device is waiting to be removed in FW 538 * @dev_type: Device type 539 * @tgt_dev: Internal target device pointer 540 * @pend_count: Counter to track pending I/Os during error 541 * handling 542 */ 543 struct mpi3mr_stgt_priv_data { 544 struct scsi_target *starget; 545 u16 dev_handle; 546 u16 perst_id; 547 u32 num_luns; 548 atomic_t block_io; 549 u8 dev_removed; 550 u8 dev_removedelay; 551 u8 dev_type; 552 struct mpi3mr_tgt_dev *tgt_dev; 553 u32 pend_count; 554 }; 555 556 /** 557 * struct mpi3mr_stgt_priv_data - SCSI device private structure 558 * 559 * @tgt_priv_data: Scsi_target private data pointer 560 * @lun_id: LUN ID of the device 561 * @ncq_prio_enable: NCQ priority enable for SATA device 562 * @pend_count: Counter to track pending I/Os during error 563 * handling 564 */ 565 struct mpi3mr_sdev_priv_data { 566 struct mpi3mr_stgt_priv_data *tgt_priv_data; 567 u32 lun_id; 568 u8 ncq_prio_enable; 569 u32 pend_count; 570 }; 571 572 /** 573 * struct mpi3mr_drv_cmd - Internal command tracker 574 * 575 * @mutex: Command mutex 576 * @done: Completeor for wakeup 577 * @reply: Firmware reply for internal commands 578 * @sensebuf: Sensebuf for SCSI IO commands 579 * @iou_rc: IO Unit control reason code 580 * @state: Command State 581 * @dev_handle: Firmware handle for device specific commands 582 * @ioc_status: IOC status from the firmware 583 * @ioc_loginfo:IOC log info from the firmware 584 * @is_waiting: Is the command issued in block mode 585 * @is_sense: Is Sense data present 586 * @retry_count: Retry count for retriable commands 587 * @host_tag: Host tag used by the command 588 * @callback: Callback for non blocking commands 589 */ 590 struct mpi3mr_drv_cmd { 591 struct mutex mutex; 592 struct completion done; 593 void *reply; 594 u8 *sensebuf; 595 u8 iou_rc; 596 u16 state; 597 u16 dev_handle; 598 u16 ioc_status; 599 u32 ioc_loginfo; 600 u8 is_waiting; 601 u8 is_sense; 602 u8 retry_count; 603 u16 host_tag; 604 605 void (*callback)(struct mpi3mr_ioc *mrioc, 606 struct mpi3mr_drv_cmd *drv_cmd); 607 }; 608 609 610 /** 611 * struct chain_element - memory descriptor structure to store 612 * virtual and dma addresses for chain elements. 613 * 614 * @addr: virtual address 615 * @dma_addr: dma address 616 */ 617 struct chain_element { 618 void *addr; 619 dma_addr_t dma_addr; 620 }; 621 622 /** 623 * struct scmd_priv - SCSI command private data 624 * 625 * @host_tag: Host tag specific to operational queue 626 * @in_lld_scope: Command in LLD scope or not 627 * @meta_sg_valid: DIX command with meta data SGL or not 628 * @scmd: SCSI Command pointer 629 * @req_q_idx: Operational request queue index 630 * @chain_idx: Chain frame index 631 * @meta_chain_idx: Chain frame index of meta data SGL 632 * @mpi3mr_scsiio_req: MPI SCSI IO request 633 */ 634 struct scmd_priv { 635 u16 host_tag; 636 u8 in_lld_scope; 637 u8 meta_sg_valid; 638 struct scsi_cmnd *scmd; 639 u16 req_q_idx; 640 int chain_idx; 641 int meta_chain_idx; 642 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 643 }; 644 645 /** 646 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 647 * private data 648 * 649 * @list: List pointer 650 * @pdev: PCI device pointer 651 * @shost: Scsi_Host pointer 652 * @id: Controller ID 653 * @cpu_count: Number of online CPUs 654 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 655 * @name: Controller ASCII name 656 * @driver_name: Driver ASCII name 657 * @sysif_regs: System interface registers virtual address 658 * @sysif_regs_phys: System interface registers physical address 659 * @bars: PCI BARS 660 * @dma_mask: DMA mask 661 * @msix_count: Number of MSIX vectors used 662 * @intr_enabled: Is interrupts enabled 663 * @num_admin_req: Number of admin requests 664 * @admin_req_q_sz: Admin request queue size 665 * @admin_req_pi: Admin request queue producer index 666 * @admin_req_ci: Admin request queue consumer index 667 * @admin_req_base: Admin request queue base virtual address 668 * @admin_req_dma: Admin request queue base dma address 669 * @admin_req_lock: Admin queue access lock 670 * @num_admin_replies: Number of admin replies 671 * @admin_reply_q_sz: Admin reply queue size 672 * @admin_reply_ci: Admin reply queue consumer index 673 * @admin_reply_ephase:Admin reply queue expected phase 674 * @admin_reply_base: Admin reply queue base virtual address 675 * @admin_reply_dma: Admin reply queue base dma address 676 * @ready_timeout: Controller ready timeout 677 * @intr_info: Interrupt cookie pointer 678 * @intr_info_count: Number of interrupt cookies 679 * @is_intr_info_set: Flag to indicate intr info is setup 680 * @num_queues: Number of operational queues 681 * @num_op_req_q: Number of operational request queues 682 * @req_qinfo: Operational request queue info pointer 683 * @num_op_reply_q: Number of operational reply queues 684 * @op_reply_qinfo: Operational reply queue info pointer 685 * @init_cmds: Command tracker for initialization commands 686 * @facts: Cached IOC facts data 687 * @op_reply_desc_sz: Operational reply descriptor size 688 * @num_reply_bufs: Number of reply buffers allocated 689 * @reply_buf_pool: Reply buffer pool 690 * @reply_buf: Reply buffer base virtual address 691 * @reply_buf_dma: Reply buffer DMA address 692 * @reply_buf_dma_max_address: Reply DMA address max limit 693 * @reply_free_qsz: Reply free queue size 694 * @reply_free_q_pool: Reply free queue pool 695 * @reply_free_q: Reply free queue base virtual address 696 * @reply_free_q_dma: Reply free queue base DMA address 697 * @reply_free_queue_lock: Reply free queue lock 698 * @reply_free_queue_host_index: Reply free queue host index 699 * @num_sense_bufs: Number of sense buffers 700 * @sense_buf_pool: Sense buffer pool 701 * @sense_buf: Sense buffer base virtual address 702 * @sense_buf_dma: Sense buffer base DMA address 703 * @sense_buf_q_sz: Sense buffer queue size 704 * @sense_buf_q_pool: Sense buffer queue pool 705 * @sense_buf_q: Sense buffer queue virtual address 706 * @sense_buf_q_dma: Sense buffer queue DMA address 707 * @sbq_lock: Sense buffer queue lock 708 * @sbq_host_index: Sense buffer queuehost index 709 * @event_masks: Event mask bitmap 710 * @fwevt_worker_name: Firmware event worker thread name 711 * @fwevt_worker_thread: Firmware event worker thread 712 * @fwevt_lock: Firmware event lock 713 * @fwevt_list: Firmware event list 714 * @watchdog_work_q_name: Fault watchdog worker thread name 715 * @watchdog_work_q: Fault watchdog worker thread 716 * @watchdog_work: Fault watchdog work 717 * @watchdog_lock: Fault watchdog lock 718 * @is_driver_loading: Is driver still loading 719 * @scan_started: Async scan started 720 * @scan_failed: Asycn scan failed 721 * @stop_drv_processing: Stop all command processing 722 * @max_host_ios: Maximum host I/O count 723 * @chain_buf_count: Chain buffer count 724 * @chain_buf_pool: Chain buffer pool 725 * @chain_sgl_list: Chain SGL list 726 * @chain_bitmap_sz: Chain buffer allocator bitmap size 727 * @chain_bitmap: Chain buffer allocator bitmap 728 * @chain_buf_lock: Chain buffer list lock 729 * @bsg_cmds: Command tracker for BSG command 730 * @host_tm_cmds: Command tracker for task management commands 731 * @dev_rmhs_cmds: Command tracker for device removal commands 732 * @evtack_cmds: Command tracker for event ack commands 733 * @devrem_bitmap_sz: Device removal bitmap size 734 * @devrem_bitmap: Device removal bitmap 735 * @dev_handle_bitmap_sz: Device handle bitmap size 736 * @removepend_bitmap: Remove pending bitmap 737 * @delayed_rmhs_list: Delayed device removal list 738 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 739 * @evtack_cmds_bitmap: Event Ack bitmap 740 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 741 * @ts_update_counter: Timestamp update counter 742 * @reset_in_progress: Reset in progress flag 743 * @unrecoverable: Controller unrecoverable flag 744 * @prev_reset_result: Result of previous reset 745 * @reset_mutex: Controller reset mutex 746 * @reset_waitq: Controller reset wait queue 747 * @prepare_for_reset: Prepare for reset event received 748 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 749 * @diagsave_timeout: Diagnostic information save timeout 750 * @logging_level: Controller debug logging level 751 * @flush_io_count: I/O count to flush after reset 752 * @current_event: Firmware event currently in process 753 * @driver_info: Driver, Kernel, OS information to firmware 754 * @change_count: Topology change count 755 * @pel_enabled: Persistent Event Log(PEL) enabled or not 756 * @pel_abort_requested: PEL abort is requested or not 757 * @pel_class: PEL Class identifier 758 * @pel_locale: PEL Locale identifier 759 * @pel_cmds: Command tracker for PEL wait command 760 * @pel_abort_cmd: Command tracker for PEL abort command 761 * @pel_newest_seqnum: Newest PEL sequenece number 762 * @pel_seqnum_virt: PEL sequence number virtual address 763 * @pel_seqnum_dma: PEL sequence number DMA address 764 * @pel_seqnum_sz: PEL sequenece number size 765 * @op_reply_q_offset: Operational reply queue offset with MSIx 766 * @default_qcount: Total Default queues 767 * @active_poll_qcount: Currently active poll queue count 768 * @requested_poll_qcount: User requested poll queue count 769 * @bsg_dev: BSG device structure 770 * @bsg_queue: Request queue for BSG device 771 * @stop_bsgs: Stop BSG request flag 772 * @logdata_buf: Circular buffer to store log data entries 773 * @logdata_buf_idx: Index of entry in buffer to store 774 * @logdata_entry_sz: log data entry size 775 */ 776 struct mpi3mr_ioc { 777 struct list_head list; 778 struct pci_dev *pdev; 779 struct Scsi_Host *shost; 780 u8 id; 781 int cpu_count; 782 bool enable_segqueue; 783 u32 irqpoll_sleep; 784 785 char name[MPI3MR_NAME_LENGTH]; 786 char driver_name[MPI3MR_NAME_LENGTH]; 787 788 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 789 resource_size_t sysif_regs_phys; 790 int bars; 791 u64 dma_mask; 792 793 u16 msix_count; 794 u8 intr_enabled; 795 796 u16 num_admin_req; 797 u32 admin_req_q_sz; 798 u16 admin_req_pi; 799 u16 admin_req_ci; 800 void *admin_req_base; 801 dma_addr_t admin_req_dma; 802 spinlock_t admin_req_lock; 803 804 u16 num_admin_replies; 805 u32 admin_reply_q_sz; 806 u16 admin_reply_ci; 807 u8 admin_reply_ephase; 808 void *admin_reply_base; 809 dma_addr_t admin_reply_dma; 810 811 u32 ready_timeout; 812 813 struct mpi3mr_intr_info *intr_info; 814 u16 intr_info_count; 815 bool is_intr_info_set; 816 817 u16 num_queues; 818 u16 num_op_req_q; 819 struct op_req_qinfo *req_qinfo; 820 821 u16 num_op_reply_q; 822 struct op_reply_qinfo *op_reply_qinfo; 823 824 struct mpi3mr_drv_cmd init_cmds; 825 struct mpi3mr_ioc_facts facts; 826 u16 op_reply_desc_sz; 827 828 u32 num_reply_bufs; 829 struct dma_pool *reply_buf_pool; 830 u8 *reply_buf; 831 dma_addr_t reply_buf_dma; 832 dma_addr_t reply_buf_dma_max_address; 833 834 u16 reply_free_qsz; 835 u16 reply_sz; 836 struct dma_pool *reply_free_q_pool; 837 __le64 *reply_free_q; 838 dma_addr_t reply_free_q_dma; 839 spinlock_t reply_free_queue_lock; 840 u32 reply_free_queue_host_index; 841 842 u32 num_sense_bufs; 843 struct dma_pool *sense_buf_pool; 844 u8 *sense_buf; 845 dma_addr_t sense_buf_dma; 846 847 u16 sense_buf_q_sz; 848 struct dma_pool *sense_buf_q_pool; 849 __le64 *sense_buf_q; 850 dma_addr_t sense_buf_q_dma; 851 spinlock_t sbq_lock; 852 u32 sbq_host_index; 853 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 854 855 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 856 struct workqueue_struct *fwevt_worker_thread; 857 spinlock_t fwevt_lock; 858 struct list_head fwevt_list; 859 860 char watchdog_work_q_name[20]; 861 struct workqueue_struct *watchdog_work_q; 862 struct delayed_work watchdog_work; 863 spinlock_t watchdog_lock; 864 865 u8 is_driver_loading; 866 u8 scan_started; 867 u16 scan_failed; 868 u8 stop_drv_processing; 869 870 u16 max_host_ios; 871 spinlock_t tgtdev_lock; 872 struct list_head tgtdev_list; 873 874 u32 chain_buf_count; 875 struct dma_pool *chain_buf_pool; 876 struct chain_element *chain_sgl_list; 877 u16 chain_bitmap_sz; 878 void *chain_bitmap; 879 spinlock_t chain_buf_lock; 880 881 struct mpi3mr_drv_cmd bsg_cmds; 882 struct mpi3mr_drv_cmd host_tm_cmds; 883 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 884 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 885 u16 devrem_bitmap_sz; 886 void *devrem_bitmap; 887 u16 dev_handle_bitmap_sz; 888 void *removepend_bitmap; 889 struct list_head delayed_rmhs_list; 890 u16 evtack_cmds_bitmap_sz; 891 void *evtack_cmds_bitmap; 892 struct list_head delayed_evtack_cmds_list; 893 894 u32 ts_update_counter; 895 u8 reset_in_progress; 896 u8 unrecoverable; 897 int prev_reset_result; 898 struct mutex reset_mutex; 899 wait_queue_head_t reset_waitq; 900 901 u8 prepare_for_reset; 902 u16 prepare_for_reset_timeout_counter; 903 904 u16 diagsave_timeout; 905 int logging_level; 906 u16 flush_io_count; 907 908 struct mpi3mr_fwevt *current_event; 909 struct mpi3_driver_info_layout driver_info; 910 u16 change_count; 911 912 u8 pel_enabled; 913 u8 pel_abort_requested; 914 u8 pel_class; 915 u16 pel_locale; 916 struct mpi3mr_drv_cmd pel_cmds; 917 struct mpi3mr_drv_cmd pel_abort_cmd; 918 919 u32 pel_newest_seqnum; 920 void *pel_seqnum_virt; 921 dma_addr_t pel_seqnum_dma; 922 u32 pel_seqnum_sz; 923 924 u16 op_reply_q_offset; 925 u16 default_qcount; 926 u16 active_poll_qcount; 927 u16 requested_poll_qcount; 928 929 struct device *bsg_dev; 930 struct request_queue *bsg_queue; 931 u8 stop_bsgs; 932 u8 *logdata_buf; 933 u16 logdata_buf_idx; 934 u16 logdata_entry_sz; 935 }; 936 937 /** 938 * struct mpi3mr_fwevt - Firmware event structure. 939 * 940 * @list: list head 941 * @work: Work structure 942 * @mrioc: Adapter instance reference 943 * @event_id: MPI3 firmware event ID 944 * @send_ack: Event acknowledgment required or not 945 * @process_evt: Bottomhalf processing required or not 946 * @evt_ctx: Event context to send in Ack 947 * @event_data_size: size of the event data in bytes 948 * @pending_at_sml: waiting for device add/remove API to complete 949 * @discard: discard this event 950 * @ref_count: kref count 951 * @event_data: Actual MPI3 event data 952 */ 953 struct mpi3mr_fwevt { 954 struct list_head list; 955 struct work_struct work; 956 struct mpi3mr_ioc *mrioc; 957 u16 event_id; 958 bool send_ack; 959 bool process_evt; 960 u32 evt_ctx; 961 u16 event_data_size; 962 bool pending_at_sml; 963 bool discard; 964 struct kref ref_count; 965 char event_data[] __aligned(4); 966 }; 967 968 969 /** 970 * struct delayed_dev_rmhs_node - Delayed device removal node 971 * 972 * @list: list head 973 * @handle: Device handle 974 * @iou_rc: IO Unit Control Reason Code 975 */ 976 struct delayed_dev_rmhs_node { 977 struct list_head list; 978 u16 handle; 979 u8 iou_rc; 980 }; 981 982 /** 983 * struct delayed_evt_ack_node - Delayed event ack node 984 * @list: list head 985 * @event: MPI3 event ID 986 * @event_ctx: event context 987 */ 988 struct delayed_evt_ack_node { 989 struct list_head list; 990 u8 event; 991 u32 event_ctx; 992 }; 993 994 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 995 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 996 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 997 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 998 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 999 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1000 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1001 u16 admin_req_sz, u8 ignore_reset); 1002 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1003 struct op_req_qinfo *opreqq, u8 *req); 1004 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1005 dma_addr_t dma_addr); 1006 void mpi3mr_build_zero_len_sge(void *paddr); 1007 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1008 dma_addr_t phys_addr); 1009 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1010 dma_addr_t phys_addr); 1011 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1012 u64 sense_buf_dma); 1013 1014 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1015 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1016 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1017 struct mpi3_event_notification_reply *event_reply); 1018 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1019 struct mpi3_default_reply_descriptor *reply_desc, 1020 u64 *reply_dma, u16 qidx); 1021 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1022 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1023 1024 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1025 u32 reset_reason, u8 snapdump); 1026 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1027 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1028 1029 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1030 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1031 u32 event_ctx); 1032 1033 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1034 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1035 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1036 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1037 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1038 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1039 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1040 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1041 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1042 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1043 struct op_reply_qinfo *op_reply_q); 1044 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1045 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1046 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1047 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1048 u16 handle, uint lun, u16 htag, ulong timeout, 1049 struct mpi3mr_drv_cmd *drv_cmd, 1050 u8 *resp_code, struct scsi_cmnd *scmd); 1051 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1052 struct mpi3mr_ioc *mrioc, u16 handle); 1053 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1054 struct mpi3mr_drv_cmd *drv_cmd); 1055 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1056 struct mpi3mr_drv_cmd *drv_cmd); 1057 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1058 u16 event_data_size); 1059 1060 #endif /*MPI3MR_H_INCLUDED*/ 1061