1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2022 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 43 #include "mpi/mpi30_transport.h" 44 #include "mpi/mpi30_cnfg.h" 45 #include "mpi/mpi30_image.h" 46 #include "mpi/mpi30_init.h" 47 #include "mpi/mpi30_ioc.h" 48 #include "mpi/mpi30_sas.h" 49 #include "mpi/mpi30_pci.h" 50 #include "mpi3mr_debug.h" 51 52 /* Global list and lock for storing multiple adapters managed by the driver */ 53 extern spinlock_t mrioc_list_lock; 54 extern struct list_head mrioc_list; 55 extern int prot_mask; 56 extern atomic64_t event_counter; 57 58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0" 59 #define MPI3MR_DRIVER_RELDATE "16-March-2022" 60 61 #define MPI3MR_DRIVER_NAME "mpi3mr" 62 #define MPI3MR_DRIVER_LICENSE "GPL" 63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66 #define MPI3MR_NAME_LENGTH 32 67 #define IOCNAME "%s: " 68 69 #define MPI3MR_MAX_SECTORS 2048 70 71 /* Definitions for internal SGL and Chain SGL buffers */ 72 #define MPI3MR_PAGE_SIZE_4K 4096 73 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 74 75 /* Definitions for MAX values for shost */ 76 #define MPI3MR_MAX_CMDS_LUN 128 77 #define MPI3MR_MAX_CDB_LENGTH 32 78 79 /* Admin queue management definitions */ 80 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 81 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 82 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 83 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 84 85 /* Operational queue management definitions */ 86 #define MPI3MR_OP_REQ_Q_QD 512 87 #define MPI3MR_OP_REP_Q_QD 1024 88 #define MPI3MR_OP_REP_Q_QD4K 4096 89 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 90 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 91 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 92 93 /* Reserved Host Tag definitions */ 94 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 95 #define MPI3MR_HOSTTAG_INITCMDS 1 96 #define MPI3MR_HOSTTAG_BSG_CMDS 2 97 #define MPI3MR_HOSTTAG_PEL_ABORT 3 98 #define MPI3MR_HOSTTAG_PEL_WAIT 4 99 #define MPI3MR_HOSTTAG_BLK_TMS 5 100 #define MPI3MR_HOSTTAG_CFG_CMDS 6 101 102 #define MPI3MR_NUM_DEVRMCMD 16 103 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 104 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 105 MPI3MR_NUM_DEVRMCMD - 1) 106 107 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 108 #define MPI3MR_NUM_EVTACKCMD 4 109 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 110 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 111 MPI3MR_NUM_EVTACKCMD - 1) 112 113 /* Reduced resource count definition for crash kernel */ 114 #define MPI3MR_HOST_IOS_KDUMP 128 115 116 /* command/controller interaction timeout definitions in seconds */ 117 #define MPI3MR_INTADMCMD_TIMEOUT 60 118 #define MPI3MR_PORTENABLE_TIMEOUT 300 119 #define MPI3MR_ABORTTM_TIMEOUT 60 120 #define MPI3MR_RESETTM_TIMEOUT 60 121 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 122 #define MPI3MR_TSUPDATE_INTERVAL 900 123 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 124 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 125 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 126 #define MPI3MR_RESET_ACK_TIMEOUT 30 127 128 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 129 130 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 131 132 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 133 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 134 135 /* Internal admin command state definitions*/ 136 #define MPI3MR_CMD_NOTUSED 0x8000 137 #define MPI3MR_CMD_COMPLETE 0x0001 138 #define MPI3MR_CMD_PENDING 0x0002 139 #define MPI3MR_CMD_REPLY_VALID 0x0004 140 #define MPI3MR_CMD_RESET 0x0008 141 142 /* Definitions for Event replies and sense buffer allocated per controller */ 143 #define MPI3MR_NUM_EVT_REPLIES 64 144 #define MPI3MR_SENSE_BUF_SZ 256 145 #define MPI3MR_SENSEBUF_FACTOR 3 146 #define MPI3MR_CHAINBUF_FACTOR 3 147 #define MPI3MR_CHAINBUFDIX_FACTOR 2 148 149 /* Invalid target device handle */ 150 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 151 152 /* Controller Reset related definitions */ 153 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 154 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 155 156 /* ResponseCode definitions */ 157 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 158 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 159 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 160 161 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 162 #define MPI3MR_DEFAULT_PGSZEXP (12) 163 164 /* Command retry count definitions */ 165 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 166 #define MPI3MR_PEL_RETRY_COUNT 3 167 168 /* Default target device queue depth */ 169 #define MPI3MR_DEFAULT_SDEV_QD 32 170 171 /* Definitions for Threaded IRQ poll*/ 172 #define MPI3MR_IRQ_POLL_SLEEP 2 173 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 174 175 /* Definitions for the controller security status*/ 176 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 177 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 178 179 #define MPI3MR_INVALID_DEVICE 0x00 180 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 181 #define MPI3MR_HARD_SECURE_DEVICE 0x08 182 #define MPI3MR_TAMPERED_DEVICE 0x0C 183 184 /* SGE Flag definition */ 185 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 186 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 187 MPI3_SGE_FLAGS_END_OF_LIST) 188 189 /* MSI Index from Reply Queue Index */ 190 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 191 192 /* 193 * Maximum data transfer size definitions for management 194 * application commands 195 */ 196 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 197 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 198 /* 199 * 2048 sectors are for data buffers and additional 512 sectors for 200 * other buffers 201 */ 202 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 203 204 /** 205 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 206 * Encapsulated commands. 207 * 208 * @base_addr: Physical address 209 * @length: SGE length 210 * @rsvd: Reserved 211 * @rsvd1: Reserved 212 * @sgl_type: sgl type 213 */ 214 struct mpi3mr_nvme_pt_sge { 215 u64 base_addr; 216 u32 length; 217 u16 rsvd; 218 u8 rsvd1; 219 u8 sgl_type; 220 }; 221 222 /** 223 * struct mpi3mr_buf_map - local structure to 224 * track kernel and user buffers associated with an BSG 225 * structure. 226 * 227 * @bsg_buf: BSG buffer virtual address 228 * @bsg_buf_len: BSG buffer length 229 * @kern_buf: Kernel buffer virtual address 230 * @kern_buf_len: Kernel buffer length 231 * @kern_buf_dma: Kernel buffer DMA address 232 * @data_dir: Data direction. 233 */ 234 struct mpi3mr_buf_map { 235 void *bsg_buf; 236 u32 bsg_buf_len; 237 void *kern_buf; 238 u32 kern_buf_len; 239 dma_addr_t kern_buf_dma; 240 u8 data_dir; 241 }; 242 243 /* IOC State definitions */ 244 enum mpi3mr_iocstate { 245 MRIOC_STATE_READY = 1, 246 MRIOC_STATE_RESET, 247 MRIOC_STATE_FAULT, 248 MRIOC_STATE_BECOMING_READY, 249 MRIOC_STATE_RESET_REQUESTED, 250 MRIOC_STATE_UNRECOVERABLE, 251 }; 252 253 /* Reset reason code definitions*/ 254 enum mpi3mr_reset_reason { 255 MPI3MR_RESET_FROM_BRINGUP = 1, 256 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 257 MPI3MR_RESET_FROM_APP = 3, 258 MPI3MR_RESET_FROM_EH_HOS = 4, 259 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 260 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 261 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 262 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 263 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 264 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 265 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 266 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 267 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 268 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 269 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 270 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 271 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 272 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 273 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 274 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 275 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 276 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 277 MPI3MR_RESET_FROM_SYSFS = 23, 278 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 279 MPI3MR_RESET_FROM_FIRMWARE = 27, 280 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 281 }; 282 283 /* Queue type definitions */ 284 enum queue_type { 285 MPI3MR_DEFAULT_QUEUE = 0, 286 MPI3MR_POLL_QUEUE, 287 }; 288 289 /** 290 * struct mpi3mr_compimg_ver - replica of component image 291 * version defined in mpi30_image.h in host endianness 292 * 293 */ 294 struct mpi3mr_compimg_ver { 295 u16 build_num; 296 u16 cust_id; 297 u8 ph_minor; 298 u8 ph_major; 299 u8 gen_minor; 300 u8 gen_major; 301 }; 302 303 /** 304 * struct mpi3mr_ioc_facs - replica of component image version 305 * defined in mpi30_ioc.h in host endianness 306 * 307 */ 308 struct mpi3mr_ioc_facts { 309 u32 ioc_capabilities; 310 struct mpi3mr_compimg_ver fw_ver; 311 u32 mpi_version; 312 u16 max_reqs; 313 u16 product_id; 314 u16 op_req_sz; 315 u16 reply_sz; 316 u16 exceptions; 317 u16 max_perids; 318 u16 max_pds; 319 u16 max_sasexpanders; 320 u16 max_sasinitiators; 321 u16 max_enclosures; 322 u16 max_pcie_switches; 323 u16 max_nvme; 324 u16 max_vds; 325 u16 max_hpds; 326 u16 max_advhpds; 327 u16 max_raid_pds; 328 u16 min_devhandle; 329 u16 max_devhandle; 330 u16 max_op_req_q; 331 u16 max_op_reply_q; 332 u16 shutdown_timeout; 333 u8 ioc_num; 334 u8 who_init; 335 u16 max_msix_vectors; 336 u8 personality; 337 u8 dma_mask; 338 u8 protocol_flags; 339 u8 sge_mod_mask; 340 u8 sge_mod_value; 341 u8 sge_mod_shift; 342 u8 max_dev_per_tg; 343 u16 max_io_throttle_group; 344 u16 io_throttle_data_length; 345 u16 io_throttle_low; 346 u16 io_throttle_high; 347 348 }; 349 350 /** 351 * struct segments - memory descriptor structure to store 352 * virtual and dma addresses for operational queue segments. 353 * 354 * @segment: virtual address 355 * @segment_dma: dma address 356 */ 357 struct segments { 358 void *segment; 359 dma_addr_t segment_dma; 360 }; 361 362 /** 363 * struct op_req_qinfo - Operational Request Queue Information 364 * 365 * @ci: consumer index 366 * @pi: producer index 367 * @num_request: Maximum number of entries in the queue 368 * @qid: Queue Id starting from 1 369 * @reply_qid: Associated reply queue Id 370 * @num_segments: Number of discontiguous memory segments 371 * @segment_qd: Depth of each segments 372 * @q_lock: Concurrent queue access lock 373 * @q_segments: Segment descriptor pointer 374 * @q_segment_list: Segment list base virtual address 375 * @q_segment_list_dma: Segment list base DMA address 376 */ 377 struct op_req_qinfo { 378 u16 ci; 379 u16 pi; 380 u16 num_requests; 381 u16 qid; 382 u16 reply_qid; 383 u16 num_segments; 384 u16 segment_qd; 385 spinlock_t q_lock; 386 struct segments *q_segments; 387 void *q_segment_list; 388 dma_addr_t q_segment_list_dma; 389 }; 390 391 /** 392 * struct op_reply_qinfo - Operational Reply Queue Information 393 * 394 * @ci: consumer index 395 * @qid: Queue Id starting from 1 396 * @num_replies: Maximum number of entries in the queue 397 * @num_segments: Number of discontiguous memory segments 398 * @segment_qd: Depth of each segments 399 * @q_segments: Segment descriptor pointer 400 * @q_segment_list: Segment list base virtual address 401 * @q_segment_list_dma: Segment list base DMA address 402 * @ephase: Expected phased identifier for the reply queue 403 * @pend_ios: Number of IOs pending in HW for this queue 404 * @enable_irq_poll: Flag to indicate polling is enabled 405 * @in_use: Queue is handled by poll/ISR 406 * @qtype: Type of queue (types defined in enum queue_type) 407 */ 408 struct op_reply_qinfo { 409 u16 ci; 410 u16 qid; 411 u16 num_replies; 412 u16 num_segments; 413 u16 segment_qd; 414 struct segments *q_segments; 415 void *q_segment_list; 416 dma_addr_t q_segment_list_dma; 417 u8 ephase; 418 atomic_t pend_ios; 419 bool enable_irq_poll; 420 atomic_t in_use; 421 enum queue_type qtype; 422 }; 423 424 /** 425 * struct mpi3mr_intr_info - Interrupt cookie information 426 * 427 * @mrioc: Adapter instance reference 428 * @msix_index: MSIx index 429 * @op_reply_q: Associated operational reply queue 430 * @name: Dev name for the irq claiming device 431 */ 432 struct mpi3mr_intr_info { 433 struct mpi3mr_ioc *mrioc; 434 u16 msix_index; 435 struct op_reply_qinfo *op_reply_q; 436 char name[MPI3MR_NAME_LENGTH]; 437 }; 438 439 /** 440 * struct mpi3mr_throttle_group_info - Throttle group info 441 * 442 * @io_divert: Flag indicates io divert is on or off for the TG 443 * @need_qd_reduction: Flag to indicate QD reduction is needed 444 * @qd_reduction: Queue Depth reduction in units of 10% 445 * @fw_qd: QueueDepth value reported by the firmware 446 * @modified_qd: Modified QueueDepth value due to throttling 447 * @id: Throttle Group ID. 448 * @high: High limit to turn on throttling in 512 byte blocks 449 * @low: Low limit to turn off throttling in 512 byte blocks 450 * @pend_large_data_sz: Counter to track pending large data 451 */ 452 struct mpi3mr_throttle_group_info { 453 u8 io_divert; 454 u8 need_qd_reduction; 455 u8 qd_reduction; 456 u16 fw_qd; 457 u16 modified_qd; 458 u16 id; 459 u32 high; 460 u32 low; 461 atomic_t pend_large_data_sz; 462 }; 463 464 /** 465 * struct tgt_dev_sas_sata - SAS/SATA device specific 466 * information cached from firmware given data 467 * 468 * @sas_address: World wide unique SAS address 469 * @dev_info: Device information bits 470 */ 471 struct tgt_dev_sas_sata { 472 u64 sas_address; 473 u16 dev_info; 474 }; 475 476 /** 477 * struct tgt_dev_pcie - PCIe device specific information cached 478 * from firmware given data 479 * 480 * @mdts: Maximum data transfer size 481 * @capb: Device capabilities 482 * @pgsz: Device page size 483 * @abort_to: Timeout for abort TM 484 * @reset_to: Timeout for Target/LUN reset TM 485 * @dev_info: Device information bits 486 */ 487 struct tgt_dev_pcie { 488 u32 mdts; 489 u16 capb; 490 u8 pgsz; 491 u8 abort_to; 492 u8 reset_to; 493 u16 dev_info; 494 }; 495 496 /** 497 * struct tgt_dev_vd - virtual device specific information 498 * cached from firmware given data 499 * 500 * @state: State of the VD 501 * @tg_qd_reduction: Queue Depth reduction in units of 10% 502 * @tg_id: VDs throttle group ID 503 * @high: High limit to turn on throttling in 512 byte blocks 504 * @low: Low limit to turn off throttling in 512 byte blocks 505 * @tg: Pointer to throttle group info 506 */ 507 struct tgt_dev_vd { 508 u8 state; 509 u8 tg_qd_reduction; 510 u16 tg_id; 511 u32 tg_high; 512 u32 tg_low; 513 struct mpi3mr_throttle_group_info *tg; 514 }; 515 516 517 /** 518 * union _form_spec_inf - union of device specific information 519 */ 520 union _form_spec_inf { 521 struct tgt_dev_sas_sata sas_sata_inf; 522 struct tgt_dev_pcie pcie_inf; 523 struct tgt_dev_vd vd_inf; 524 }; 525 526 527 528 /** 529 * struct mpi3mr_tgt_dev - target device data structure 530 * 531 * @list: List pointer 532 * @starget: Scsi_target pointer 533 * @dev_handle: FW device handle 534 * @parent_handle: FW parent device handle 535 * @slot: Slot number 536 * @encl_handle: FW enclosure handle 537 * @perst_id: FW assigned Persistent ID 538 * @dev_type: SAS/SATA/PCIE device type 539 * @is_hidden: Should be exposed to upper layers or not 540 * @host_exposed: Already exposed to host or not 541 * @io_throttle_enabled: I/O throttling needed or not 542 * @q_depth: Device specific Queue Depth 543 * @wwid: World wide ID 544 * @dev_spec: Device type specific information 545 * @ref_count: Reference count 546 */ 547 struct mpi3mr_tgt_dev { 548 struct list_head list; 549 struct scsi_target *starget; 550 u16 dev_handle; 551 u16 parent_handle; 552 u16 slot; 553 u16 encl_handle; 554 u16 perst_id; 555 u8 dev_type; 556 u8 is_hidden; 557 u8 host_exposed; 558 u8 io_throttle_enabled; 559 u16 q_depth; 560 u64 wwid; 561 union _form_spec_inf dev_spec; 562 struct kref ref_count; 563 }; 564 565 /** 566 * mpi3mr_tgtdev_get - k reference incrementor 567 * @s: Target device reference 568 * 569 * Increment target device reference count. 570 */ 571 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 572 { 573 kref_get(&s->ref_count); 574 } 575 576 /** 577 * mpi3mr_free_tgtdev - target device memory dealloctor 578 * @r: k reference pointer of the target device 579 * 580 * Free target device memory when no reference. 581 */ 582 static inline void mpi3mr_free_tgtdev(struct kref *r) 583 { 584 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 585 } 586 587 /** 588 * mpi3mr_tgtdev_put - k reference decrementor 589 * @s: Target device reference 590 * 591 * Decrement target device reference count. 592 */ 593 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 594 { 595 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 596 } 597 598 599 /** 600 * struct mpi3mr_stgt_priv_data - SCSI target private structure 601 * 602 * @starget: Scsi_target pointer 603 * @dev_handle: FW device handle 604 * @perst_id: FW assigned Persistent ID 605 * @num_luns: Number of Logical Units 606 * @block_io: I/O blocked to the device or not 607 * @dev_removed: Device removed in the Firmware 608 * @dev_removedelay: Device is waiting to be removed in FW 609 * @dev_type: Device type 610 * @io_throttle_enabled: I/O throttling needed or not 611 * @io_divert: Flag indicates io divert is on or off for the dev 612 * @throttle_group: Pointer to throttle group info 613 * @tgt_dev: Internal target device pointer 614 * @pend_count: Counter to track pending I/Os during error 615 * handling 616 */ 617 struct mpi3mr_stgt_priv_data { 618 struct scsi_target *starget; 619 u16 dev_handle; 620 u16 perst_id; 621 u32 num_luns; 622 atomic_t block_io; 623 u8 dev_removed; 624 u8 dev_removedelay; 625 u8 dev_type; 626 u8 io_throttle_enabled; 627 u8 io_divert; 628 struct mpi3mr_throttle_group_info *throttle_group; 629 struct mpi3mr_tgt_dev *tgt_dev; 630 u32 pend_count; 631 }; 632 633 /** 634 * struct mpi3mr_stgt_priv_data - SCSI device private structure 635 * 636 * @tgt_priv_data: Scsi_target private data pointer 637 * @lun_id: LUN ID of the device 638 * @ncq_prio_enable: NCQ priority enable for SATA device 639 * @pend_count: Counter to track pending I/Os during error 640 * handling 641 */ 642 struct mpi3mr_sdev_priv_data { 643 struct mpi3mr_stgt_priv_data *tgt_priv_data; 644 u32 lun_id; 645 u8 ncq_prio_enable; 646 u32 pend_count; 647 }; 648 649 /** 650 * struct mpi3mr_drv_cmd - Internal command tracker 651 * 652 * @mutex: Command mutex 653 * @done: Completeor for wakeup 654 * @reply: Firmware reply for internal commands 655 * @sensebuf: Sensebuf for SCSI IO commands 656 * @iou_rc: IO Unit control reason code 657 * @state: Command State 658 * @dev_handle: Firmware handle for device specific commands 659 * @ioc_status: IOC status from the firmware 660 * @ioc_loginfo:IOC log info from the firmware 661 * @is_waiting: Is the command issued in block mode 662 * @is_sense: Is Sense data present 663 * @retry_count: Retry count for retriable commands 664 * @host_tag: Host tag used by the command 665 * @callback: Callback for non blocking commands 666 */ 667 struct mpi3mr_drv_cmd { 668 struct mutex mutex; 669 struct completion done; 670 void *reply; 671 u8 *sensebuf; 672 u8 iou_rc; 673 u16 state; 674 u16 dev_handle; 675 u16 ioc_status; 676 u32 ioc_loginfo; 677 u8 is_waiting; 678 u8 is_sense; 679 u8 retry_count; 680 u16 host_tag; 681 682 void (*callback)(struct mpi3mr_ioc *mrioc, 683 struct mpi3mr_drv_cmd *drv_cmd); 684 }; 685 686 /** 687 * struct dma_memory_desc - memory descriptor structure to store 688 * virtual address, dma address and size for any generic dma 689 * memory allocations in the driver. 690 * 691 * @size: buffer size 692 * @addr: virtual address 693 * @dma_addr: dma address 694 */ 695 struct dma_memory_desc { 696 u32 size; 697 void *addr; 698 dma_addr_t dma_addr; 699 }; 700 701 702 /** 703 * struct chain_element - memory descriptor structure to store 704 * virtual and dma addresses for chain elements. 705 * 706 * @addr: virtual address 707 * @dma_addr: dma address 708 */ 709 struct chain_element { 710 void *addr; 711 dma_addr_t dma_addr; 712 }; 713 714 /** 715 * struct scmd_priv - SCSI command private data 716 * 717 * @host_tag: Host tag specific to operational queue 718 * @in_lld_scope: Command in LLD scope or not 719 * @meta_sg_valid: DIX command with meta data SGL or not 720 * @scmd: SCSI Command pointer 721 * @req_q_idx: Operational request queue index 722 * @chain_idx: Chain frame index 723 * @meta_chain_idx: Chain frame index of meta data SGL 724 * @mpi3mr_scsiio_req: MPI SCSI IO request 725 */ 726 struct scmd_priv { 727 u16 host_tag; 728 u8 in_lld_scope; 729 u8 meta_sg_valid; 730 struct scsi_cmnd *scmd; 731 u16 req_q_idx; 732 int chain_idx; 733 int meta_chain_idx; 734 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 735 }; 736 737 /** 738 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 739 * private data 740 * 741 * @list: List pointer 742 * @pdev: PCI device pointer 743 * @shost: Scsi_Host pointer 744 * @id: Controller ID 745 * @cpu_count: Number of online CPUs 746 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 747 * @name: Controller ASCII name 748 * @driver_name: Driver ASCII name 749 * @sysif_regs: System interface registers virtual address 750 * @sysif_regs_phys: System interface registers physical address 751 * @bars: PCI BARS 752 * @dma_mask: DMA mask 753 * @msix_count: Number of MSIX vectors used 754 * @intr_enabled: Is interrupts enabled 755 * @num_admin_req: Number of admin requests 756 * @admin_req_q_sz: Admin request queue size 757 * @admin_req_pi: Admin request queue producer index 758 * @admin_req_ci: Admin request queue consumer index 759 * @admin_req_base: Admin request queue base virtual address 760 * @admin_req_dma: Admin request queue base dma address 761 * @admin_req_lock: Admin queue access lock 762 * @num_admin_replies: Number of admin replies 763 * @admin_reply_q_sz: Admin reply queue size 764 * @admin_reply_ci: Admin reply queue consumer index 765 * @admin_reply_ephase:Admin reply queue expected phase 766 * @admin_reply_base: Admin reply queue base virtual address 767 * @admin_reply_dma: Admin reply queue base dma address 768 * @ready_timeout: Controller ready timeout 769 * @intr_info: Interrupt cookie pointer 770 * @intr_info_count: Number of interrupt cookies 771 * @is_intr_info_set: Flag to indicate intr info is setup 772 * @num_queues: Number of operational queues 773 * @num_op_req_q: Number of operational request queues 774 * @req_qinfo: Operational request queue info pointer 775 * @num_op_reply_q: Number of operational reply queues 776 * @op_reply_qinfo: Operational reply queue info pointer 777 * @init_cmds: Command tracker for initialization commands 778 * @cfg_cmds: Command tracker for configuration requests 779 * @facts: Cached IOC facts data 780 * @op_reply_desc_sz: Operational reply descriptor size 781 * @num_reply_bufs: Number of reply buffers allocated 782 * @reply_buf_pool: Reply buffer pool 783 * @reply_buf: Reply buffer base virtual address 784 * @reply_buf_dma: Reply buffer DMA address 785 * @reply_buf_dma_max_address: Reply DMA address max limit 786 * @reply_free_qsz: Reply free queue size 787 * @reply_free_q_pool: Reply free queue pool 788 * @reply_free_q: Reply free queue base virtual address 789 * @reply_free_q_dma: Reply free queue base DMA address 790 * @reply_free_queue_lock: Reply free queue lock 791 * @reply_free_queue_host_index: Reply free queue host index 792 * @num_sense_bufs: Number of sense buffers 793 * @sense_buf_pool: Sense buffer pool 794 * @sense_buf: Sense buffer base virtual address 795 * @sense_buf_dma: Sense buffer base DMA address 796 * @sense_buf_q_sz: Sense buffer queue size 797 * @sense_buf_q_pool: Sense buffer queue pool 798 * @sense_buf_q: Sense buffer queue virtual address 799 * @sense_buf_q_dma: Sense buffer queue DMA address 800 * @sbq_lock: Sense buffer queue lock 801 * @sbq_host_index: Sense buffer queuehost index 802 * @event_masks: Event mask bitmap 803 * @fwevt_worker_name: Firmware event worker thread name 804 * @fwevt_worker_thread: Firmware event worker thread 805 * @fwevt_lock: Firmware event lock 806 * @fwevt_list: Firmware event list 807 * @watchdog_work_q_name: Fault watchdog worker thread name 808 * @watchdog_work_q: Fault watchdog worker thread 809 * @watchdog_work: Fault watchdog work 810 * @watchdog_lock: Fault watchdog lock 811 * @is_driver_loading: Is driver still loading 812 * @scan_started: Async scan started 813 * @scan_failed: Asycn scan failed 814 * @stop_drv_processing: Stop all command processing 815 * @max_host_ios: Maximum host I/O count 816 * @chain_buf_count: Chain buffer count 817 * @chain_buf_pool: Chain buffer pool 818 * @chain_sgl_list: Chain SGL list 819 * @chain_bitmap_sz: Chain buffer allocator bitmap size 820 * @chain_bitmap: Chain buffer allocator bitmap 821 * @chain_buf_lock: Chain buffer list lock 822 * @bsg_cmds: Command tracker for BSG command 823 * @host_tm_cmds: Command tracker for task management commands 824 * @dev_rmhs_cmds: Command tracker for device removal commands 825 * @evtack_cmds: Command tracker for event ack commands 826 * @devrem_bitmap_sz: Device removal bitmap size 827 * @devrem_bitmap: Device removal bitmap 828 * @dev_handle_bitmap_sz: Device handle bitmap size 829 * @removepend_bitmap: Remove pending bitmap 830 * @delayed_rmhs_list: Delayed device removal list 831 * @evtack_cmds_bitmap_sz: Event Ack bitmap size 832 * @evtack_cmds_bitmap: Event Ack bitmap 833 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 834 * @ts_update_counter: Timestamp update counter 835 * @reset_in_progress: Reset in progress flag 836 * @unrecoverable: Controller unrecoverable flag 837 * @prev_reset_result: Result of previous reset 838 * @reset_mutex: Controller reset mutex 839 * @reset_waitq: Controller reset wait queue 840 * @prepare_for_reset: Prepare for reset event received 841 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 842 * @prp_list_virt: NVMe encapsulated PRP list virtual base 843 * @prp_list_dma: NVMe encapsulated PRP list DMA 844 * @prp_sz: NVME encapsulated PRP list size 845 * @diagsave_timeout: Diagnostic information save timeout 846 * @logging_level: Controller debug logging level 847 * @flush_io_count: I/O count to flush after reset 848 * @current_event: Firmware event currently in process 849 * @driver_info: Driver, Kernel, OS information to firmware 850 * @change_count: Topology change count 851 * @pel_enabled: Persistent Event Log(PEL) enabled or not 852 * @pel_abort_requested: PEL abort is requested or not 853 * @pel_class: PEL Class identifier 854 * @pel_locale: PEL Locale identifier 855 * @pel_cmds: Command tracker for PEL wait command 856 * @pel_abort_cmd: Command tracker for PEL abort command 857 * @pel_newest_seqnum: Newest PEL sequenece number 858 * @pel_seqnum_virt: PEL sequence number virtual address 859 * @pel_seqnum_dma: PEL sequence number DMA address 860 * @pel_seqnum_sz: PEL sequenece number size 861 * @op_reply_q_offset: Operational reply queue offset with MSIx 862 * @default_qcount: Total Default queues 863 * @active_poll_qcount: Currently active poll queue count 864 * @requested_poll_qcount: User requested poll queue count 865 * @bsg_dev: BSG device structure 866 * @bsg_queue: Request queue for BSG device 867 * @stop_bsgs: Stop BSG request flag 868 * @logdata_buf: Circular buffer to store log data entries 869 * @logdata_buf_idx: Index of entry in buffer to store 870 * @logdata_entry_sz: log data entry size 871 * @pend_large_data_sz: Counter to track pending large data 872 * @io_throttle_data_length: I/O size to track in 512b blocks 873 * @io_throttle_high: I/O size to start throttle in 512b blocks 874 * @io_throttle_low: I/O size to stop throttle in 512b blocks 875 * @num_io_throttle_group: Maximum number of throttle groups 876 * @throttle_groups: Pointer to throttle group info structures 877 * @cfg_page: Default memory for configuration pages 878 * @cfg_page_dma: Configuration page DMA address 879 * @cfg_page_sz: Default configuration page memory size 880 */ 881 struct mpi3mr_ioc { 882 struct list_head list; 883 struct pci_dev *pdev; 884 struct Scsi_Host *shost; 885 u8 id; 886 int cpu_count; 887 bool enable_segqueue; 888 u32 irqpoll_sleep; 889 890 char name[MPI3MR_NAME_LENGTH]; 891 char driver_name[MPI3MR_NAME_LENGTH]; 892 893 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 894 resource_size_t sysif_regs_phys; 895 int bars; 896 u64 dma_mask; 897 898 u16 msix_count; 899 u8 intr_enabled; 900 901 u16 num_admin_req; 902 u32 admin_req_q_sz; 903 u16 admin_req_pi; 904 u16 admin_req_ci; 905 void *admin_req_base; 906 dma_addr_t admin_req_dma; 907 spinlock_t admin_req_lock; 908 909 u16 num_admin_replies; 910 u32 admin_reply_q_sz; 911 u16 admin_reply_ci; 912 u8 admin_reply_ephase; 913 void *admin_reply_base; 914 dma_addr_t admin_reply_dma; 915 916 u32 ready_timeout; 917 918 struct mpi3mr_intr_info *intr_info; 919 u16 intr_info_count; 920 bool is_intr_info_set; 921 922 u16 num_queues; 923 u16 num_op_req_q; 924 struct op_req_qinfo *req_qinfo; 925 926 u16 num_op_reply_q; 927 struct op_reply_qinfo *op_reply_qinfo; 928 929 struct mpi3mr_drv_cmd init_cmds; 930 struct mpi3mr_drv_cmd cfg_cmds; 931 struct mpi3mr_ioc_facts facts; 932 u16 op_reply_desc_sz; 933 934 u32 num_reply_bufs; 935 struct dma_pool *reply_buf_pool; 936 u8 *reply_buf; 937 dma_addr_t reply_buf_dma; 938 dma_addr_t reply_buf_dma_max_address; 939 940 u16 reply_free_qsz; 941 u16 reply_sz; 942 struct dma_pool *reply_free_q_pool; 943 __le64 *reply_free_q; 944 dma_addr_t reply_free_q_dma; 945 spinlock_t reply_free_queue_lock; 946 u32 reply_free_queue_host_index; 947 948 u32 num_sense_bufs; 949 struct dma_pool *sense_buf_pool; 950 u8 *sense_buf; 951 dma_addr_t sense_buf_dma; 952 953 u16 sense_buf_q_sz; 954 struct dma_pool *sense_buf_q_pool; 955 __le64 *sense_buf_q; 956 dma_addr_t sense_buf_q_dma; 957 spinlock_t sbq_lock; 958 u32 sbq_host_index; 959 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 960 961 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 962 struct workqueue_struct *fwevt_worker_thread; 963 spinlock_t fwevt_lock; 964 struct list_head fwevt_list; 965 966 char watchdog_work_q_name[20]; 967 struct workqueue_struct *watchdog_work_q; 968 struct delayed_work watchdog_work; 969 spinlock_t watchdog_lock; 970 971 u8 is_driver_loading; 972 u8 scan_started; 973 u16 scan_failed; 974 u8 stop_drv_processing; 975 976 u16 max_host_ios; 977 spinlock_t tgtdev_lock; 978 struct list_head tgtdev_list; 979 980 u32 chain_buf_count; 981 struct dma_pool *chain_buf_pool; 982 struct chain_element *chain_sgl_list; 983 u16 chain_bitmap_sz; 984 void *chain_bitmap; 985 spinlock_t chain_buf_lock; 986 987 struct mpi3mr_drv_cmd bsg_cmds; 988 struct mpi3mr_drv_cmd host_tm_cmds; 989 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 990 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 991 u16 devrem_bitmap_sz; 992 void *devrem_bitmap; 993 u16 dev_handle_bitmap_sz; 994 void *removepend_bitmap; 995 struct list_head delayed_rmhs_list; 996 u16 evtack_cmds_bitmap_sz; 997 void *evtack_cmds_bitmap; 998 struct list_head delayed_evtack_cmds_list; 999 1000 u32 ts_update_counter; 1001 u8 reset_in_progress; 1002 u8 unrecoverable; 1003 int prev_reset_result; 1004 struct mutex reset_mutex; 1005 wait_queue_head_t reset_waitq; 1006 1007 u8 prepare_for_reset; 1008 u16 prepare_for_reset_timeout_counter; 1009 1010 void *prp_list_virt; 1011 dma_addr_t prp_list_dma; 1012 u32 prp_sz; 1013 1014 u16 diagsave_timeout; 1015 int logging_level; 1016 u16 flush_io_count; 1017 1018 struct mpi3mr_fwevt *current_event; 1019 struct mpi3_driver_info_layout driver_info; 1020 u16 change_count; 1021 1022 u8 pel_enabled; 1023 u8 pel_abort_requested; 1024 u8 pel_class; 1025 u16 pel_locale; 1026 struct mpi3mr_drv_cmd pel_cmds; 1027 struct mpi3mr_drv_cmd pel_abort_cmd; 1028 1029 u32 pel_newest_seqnum; 1030 void *pel_seqnum_virt; 1031 dma_addr_t pel_seqnum_dma; 1032 u32 pel_seqnum_sz; 1033 1034 u16 op_reply_q_offset; 1035 u16 default_qcount; 1036 u16 active_poll_qcount; 1037 u16 requested_poll_qcount; 1038 1039 struct device bsg_dev; 1040 struct request_queue *bsg_queue; 1041 u8 stop_bsgs; 1042 u8 *logdata_buf; 1043 u16 logdata_buf_idx; 1044 u16 logdata_entry_sz; 1045 1046 atomic_t pend_large_data_sz; 1047 u32 io_throttle_data_length; 1048 u32 io_throttle_high; 1049 u32 io_throttle_low; 1050 u16 num_io_throttle_group; 1051 struct mpi3mr_throttle_group_info *throttle_groups; 1052 1053 void *cfg_page; 1054 dma_addr_t cfg_page_dma; 1055 u16 cfg_page_sz; 1056 }; 1057 1058 /** 1059 * struct mpi3mr_fwevt - Firmware event structure. 1060 * 1061 * @list: list head 1062 * @work: Work structure 1063 * @mrioc: Adapter instance reference 1064 * @event_id: MPI3 firmware event ID 1065 * @send_ack: Event acknowledgment required or not 1066 * @process_evt: Bottomhalf processing required or not 1067 * @evt_ctx: Event context to send in Ack 1068 * @event_data_size: size of the event data in bytes 1069 * @pending_at_sml: waiting for device add/remove API to complete 1070 * @discard: discard this event 1071 * @ref_count: kref count 1072 * @event_data: Actual MPI3 event data 1073 */ 1074 struct mpi3mr_fwevt { 1075 struct list_head list; 1076 struct work_struct work; 1077 struct mpi3mr_ioc *mrioc; 1078 u16 event_id; 1079 bool send_ack; 1080 bool process_evt; 1081 u32 evt_ctx; 1082 u16 event_data_size; 1083 bool pending_at_sml; 1084 bool discard; 1085 struct kref ref_count; 1086 char event_data[] __aligned(4); 1087 }; 1088 1089 1090 /** 1091 * struct delayed_dev_rmhs_node - Delayed device removal node 1092 * 1093 * @list: list head 1094 * @handle: Device handle 1095 * @iou_rc: IO Unit Control Reason Code 1096 */ 1097 struct delayed_dev_rmhs_node { 1098 struct list_head list; 1099 u16 handle; 1100 u8 iou_rc; 1101 }; 1102 1103 /** 1104 * struct delayed_evt_ack_node - Delayed event ack node 1105 * @list: list head 1106 * @event: MPI3 event ID 1107 * @event_ctx: event context 1108 */ 1109 struct delayed_evt_ack_node { 1110 struct list_head list; 1111 u8 event; 1112 u32 event_ctx; 1113 }; 1114 1115 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1116 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1117 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1118 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1119 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1120 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1121 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1122 u16 admin_req_sz, u8 ignore_reset); 1123 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1124 struct op_req_qinfo *opreqq, u8 *req); 1125 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1126 dma_addr_t dma_addr); 1127 void mpi3mr_build_zero_len_sge(void *paddr); 1128 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1129 dma_addr_t phys_addr); 1130 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1131 dma_addr_t phys_addr); 1132 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1133 u64 sense_buf_dma); 1134 1135 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1136 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1137 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1138 struct mpi3_event_notification_reply *event_reply); 1139 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1140 struct mpi3_default_reply_descriptor *reply_desc, 1141 u64 *reply_dma, u16 qidx); 1142 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1143 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1144 1145 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1146 u32 reset_reason, u8 snapdump); 1147 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1148 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1149 1150 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1151 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1152 u32 event_ctx); 1153 1154 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1155 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1156 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1157 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1158 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1159 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1160 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1161 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1162 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1163 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1164 struct op_reply_qinfo *op_reply_q); 1165 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1166 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1167 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1168 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1169 u16 handle, uint lun, u16 htag, ulong timeout, 1170 struct mpi3mr_drv_cmd *drv_cmd, 1171 u8 *resp_code, struct scsi_cmnd *scmd); 1172 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1173 struct mpi3mr_ioc *mrioc, u16 handle); 1174 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1175 struct mpi3mr_drv_cmd *drv_cmd); 1176 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1177 struct mpi3mr_drv_cmd *drv_cmd); 1178 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1179 u16 event_data_size); 1180 extern const struct attribute_group *mpi3mr_host_groups[]; 1181 extern const struct attribute_group *mpi3mr_dev_groups[]; 1182 #endif /*MPI3MR_H_INCLUDED*/ 1183