1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_cnfg.h" 44 #include "mpi/mpi30_image.h" 45 #include "mpi/mpi30_init.h" 46 #include "mpi/mpi30_ioc.h" 47 #include "mpi/mpi30_sas.h" 48 #include "mpi3mr_debug.h" 49 50 /* Global list and lock for storing multiple adapters managed by the driver */ 51 extern spinlock_t mrioc_list_lock; 52 extern struct list_head mrioc_list; 53 54 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 55 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 56 57 #define MPI3MR_DRIVER_NAME "mpi3mr" 58 #define MPI3MR_DRIVER_LICENSE "GPL" 59 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 60 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 61 62 #define MPI3MR_NAME_LENGTH 32 63 #define IOCNAME "%s: " 64 65 /* Definitions for internal SGL and Chain SGL buffers */ 66 #define MPI3MR_PAGE_SIZE_4K 4096 67 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 68 69 /* Definitions for MAX values for shost */ 70 #define MPI3MR_MAX_CMDS_LUN 7 71 #define MPI3MR_MAX_CDB_LENGTH 32 72 73 /* Admin queue management definitions */ 74 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 75 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 76 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 77 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 78 79 /* Operational queue management definitions */ 80 #define MPI3MR_OP_REQ_Q_QD 512 81 #define MPI3MR_OP_REP_Q_QD 4096 82 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 83 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 84 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 85 86 /* Reserved Host Tag definitions */ 87 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 88 #define MPI3MR_HOSTTAG_INITCMDS 1 89 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 90 #define MPI3MR_HOSTTAG_BLK_TMS 5 91 92 #define MPI3MR_NUM_DEVRMCMD 1 93 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 94 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 95 MPI3MR_NUM_DEVRMCMD - 1) 96 97 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 98 99 /* Reduced resource count definition for crash kernel */ 100 #define MPI3MR_HOST_IOS_KDUMP 128 101 102 /* command/controller interaction timeout definitions in seconds */ 103 #define MPI3MR_INTADMCMD_TIMEOUT 10 104 #define MPI3MR_PORTENABLE_TIMEOUT 300 105 #define MPI3MR_RESETTM_TIMEOUT 30 106 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 107 108 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 109 110 /* Internal admin command state definitions*/ 111 #define MPI3MR_CMD_NOTUSED 0x8000 112 #define MPI3MR_CMD_COMPLETE 0x0001 113 #define MPI3MR_CMD_PENDING 0x0002 114 #define MPI3MR_CMD_REPLY_VALID 0x0004 115 #define MPI3MR_CMD_RESET 0x0008 116 117 /* Definitions for Event replies and sense buffer allocated per controller */ 118 #define MPI3MR_NUM_EVT_REPLIES 64 119 #define MPI3MR_SENSEBUF_SZ 256 120 #define MPI3MR_SENSEBUF_FACTOR 3 121 #define MPI3MR_CHAINBUF_FACTOR 3 122 123 /* Invalid target device handle */ 124 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 125 126 /* Controller Reset related definitions */ 127 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 128 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 129 130 /* ResponseCode definitions */ 131 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 132 #define MPI3MR_RSP_TM_COMPLETE 0x00 133 #define MPI3MR_RSP_INVALID_FRAME 0x02 134 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 135 #define MPI3MR_RSP_TM_FAILED 0x05 136 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 137 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 138 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 139 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 140 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 141 142 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 143 /* Command retry count definitions */ 144 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 145 146 /* SGE Flag definition */ 147 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 148 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 149 MPI3_SGE_FLAGS_END_OF_LIST) 150 151 /* MSI Index from Reply Queue Index */ 152 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 153 154 /* IOC State definitions */ 155 enum mpi3mr_iocstate { 156 MRIOC_STATE_READY = 1, 157 MRIOC_STATE_RESET, 158 MRIOC_STATE_FAULT, 159 MRIOC_STATE_BECOMING_READY, 160 MRIOC_STATE_RESET_REQUESTED, 161 MRIOC_STATE_UNRECOVERABLE, 162 }; 163 164 /* Reset reason code definitions*/ 165 enum mpi3mr_reset_reason { 166 MPI3MR_RESET_FROM_BRINGUP = 1, 167 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 168 MPI3MR_RESET_FROM_IOCTL = 3, 169 MPI3MR_RESET_FROM_EH_HOS = 4, 170 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 171 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 172 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 173 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 174 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 175 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 176 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 177 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 178 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 179 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 180 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 181 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 182 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 183 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 184 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 185 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 186 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 187 }; 188 189 /** 190 * struct mpi3mr_compimg_ver - replica of component image 191 * version defined in mpi30_image.h in host endianness 192 * 193 */ 194 struct mpi3mr_compimg_ver { 195 u16 build_num; 196 u16 cust_id; 197 u8 ph_minor; 198 u8 ph_major; 199 u8 gen_minor; 200 u8 gen_major; 201 }; 202 203 /** 204 * struct mpi3mr_ioc_facs - replica of component image version 205 * defined in mpi30_ioc.h in host endianness 206 * 207 */ 208 struct mpi3mr_ioc_facts { 209 u32 ioc_capabilities; 210 struct mpi3mr_compimg_ver fw_ver; 211 u32 mpi_version; 212 u16 max_reqs; 213 u16 product_id; 214 u16 op_req_sz; 215 u16 reply_sz; 216 u16 exceptions; 217 u16 max_perids; 218 u16 max_pds; 219 u16 max_sasexpanders; 220 u16 max_sasinitiators; 221 u16 max_enclosures; 222 u16 max_pcie_switches; 223 u16 max_nvme; 224 u16 max_vds; 225 u16 max_hpds; 226 u16 max_advhpds; 227 u16 max_raidpds; 228 u16 min_devhandle; 229 u16 max_devhandle; 230 u16 max_op_req_q; 231 u16 max_op_reply_q; 232 u16 shutdown_timeout; 233 u8 ioc_num; 234 u8 who_init; 235 u16 max_msix_vectors; 236 u8 personality; 237 u8 dma_mask; 238 u8 protocol_flags; 239 u8 sge_mod_mask; 240 u8 sge_mod_value; 241 u8 sge_mod_shift; 242 }; 243 244 /** 245 * struct segments - memory descriptor structure to store 246 * virtual and dma addresses for operational queue segments. 247 * 248 * @segment: virtual address 249 * @segment_dma: dma address 250 */ 251 struct segments { 252 void *segment; 253 dma_addr_t segment_dma; 254 }; 255 256 /** 257 * struct op_req_qinfo - Operational Request Queue Information 258 * 259 * @ci: consumer index 260 * @pi: producer index 261 * @num_request: Maximum number of entries in the queue 262 * @qid: Queue Id starting from 1 263 * @reply_qid: Associated reply queue Id 264 * @num_segments: Number of discontiguous memory segments 265 * @segment_qd: Depth of each segments 266 * @q_lock: Concurrent queue access lock 267 * @q_segments: Segment descriptor pointer 268 * @q_segment_list: Segment list base virtual address 269 * @q_segment_list_dma: Segment list base DMA address 270 */ 271 struct op_req_qinfo { 272 u16 ci; 273 u16 pi; 274 u16 num_requests; 275 u16 qid; 276 u16 reply_qid; 277 u16 num_segments; 278 u16 segment_qd; 279 spinlock_t q_lock; 280 struct segments *q_segments; 281 void *q_segment_list; 282 dma_addr_t q_segment_list_dma; 283 }; 284 285 /** 286 * struct op_reply_qinfo - Operational Reply Queue Information 287 * 288 * @ci: consumer index 289 * @qid: Queue Id starting from 1 290 * @num_replies: Maximum number of entries in the queue 291 * @num_segments: Number of discontiguous memory segments 292 * @segment_qd: Depth of each segments 293 * @q_segments: Segment descriptor pointer 294 * @q_segment_list: Segment list base virtual address 295 * @q_segment_list_dma: Segment list base DMA address 296 * @ephase: Expected phased identifier for the reply queue 297 */ 298 struct op_reply_qinfo { 299 u16 ci; 300 u16 qid; 301 u16 num_replies; 302 u16 num_segments; 303 u16 segment_qd; 304 struct segments *q_segments; 305 void *q_segment_list; 306 dma_addr_t q_segment_list_dma; 307 u8 ephase; 308 }; 309 310 /** 311 * struct mpi3mr_intr_info - Interrupt cookie information 312 * 313 * @mrioc: Adapter instance reference 314 * @msix_index: MSIx index 315 * @op_reply_q: Associated operational reply queue 316 * @name: Dev name for the irq claiming device 317 */ 318 struct mpi3mr_intr_info { 319 struct mpi3mr_ioc *mrioc; 320 u16 msix_index; 321 struct op_reply_qinfo *op_reply_q; 322 char name[MPI3MR_NAME_LENGTH]; 323 }; 324 325 /** 326 * struct tgt_dev_sas_sata - SAS/SATA device specific 327 * information cached from firmware given data 328 * 329 * @sas_address: World wide unique SAS address 330 * @dev_info: Device information bits 331 */ 332 struct tgt_dev_sas_sata { 333 u64 sas_address; 334 u16 dev_info; 335 }; 336 337 /** 338 * struct tgt_dev_pcie - PCIe device specific information cached 339 * from firmware given data 340 * 341 * @mdts: Maximum data transfer size 342 * @capb: Device capabilities 343 * @pgsz: Device page size 344 * @abort_to: Timeout for abort TM 345 * @reset_to: Timeout for Target/LUN reset TM 346 */ 347 struct tgt_dev_pcie { 348 u32 mdts; 349 u16 capb; 350 u8 pgsz; 351 u8 abort_to; 352 u8 reset_to; 353 }; 354 355 /** 356 * struct tgt_dev_volume - virtual device specific information 357 * cached from firmware given data 358 * 359 * @state: State of the VD 360 */ 361 struct tgt_dev_volume { 362 u8 state; 363 }; 364 365 /** 366 * union _form_spec_inf - union of device specific information 367 */ 368 union _form_spec_inf { 369 struct tgt_dev_sas_sata sas_sata_inf; 370 struct tgt_dev_pcie pcie_inf; 371 struct tgt_dev_volume vol_inf; 372 }; 373 374 375 376 /** 377 * struct mpi3mr_tgt_dev - target device data structure 378 * 379 * @list: List pointer 380 * @starget: Scsi_target pointer 381 * @dev_handle: FW device handle 382 * @parent_handle: FW parent device handle 383 * @slot: Slot number 384 * @encl_handle: FW enclosure handle 385 * @perst_id: FW assigned Persistent ID 386 * @dev_type: SAS/SATA/PCIE device type 387 * @is_hidden: Should be exposed to upper layers or not 388 * @host_exposed: Already exposed to host or not 389 * @q_depth: Device specific Queue Depth 390 * @wwid: World wide ID 391 * @dev_spec: Device type specific information 392 * @ref_count: Reference count 393 */ 394 struct mpi3mr_tgt_dev { 395 struct list_head list; 396 struct scsi_target *starget; 397 u16 dev_handle; 398 u16 parent_handle; 399 u16 slot; 400 u16 encl_handle; 401 u16 perst_id; 402 u8 dev_type; 403 u8 is_hidden; 404 u8 host_exposed; 405 u16 q_depth; 406 u64 wwid; 407 union _form_spec_inf dev_spec; 408 struct kref ref_count; 409 }; 410 411 /** 412 * mpi3mr_tgtdev_get - k reference incrementor 413 * @s: Target device reference 414 * 415 * Increment target device reference count. 416 */ 417 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 418 { 419 kref_get(&s->ref_count); 420 } 421 422 /** 423 * mpi3mr_free_tgtdev - target device memory dealloctor 424 * @r: k reference pointer of the target device 425 * 426 * Free target device memory when no reference. 427 */ 428 static inline void mpi3mr_free_tgtdev(struct kref *r) 429 { 430 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 431 } 432 433 /** 434 * mpi3mr_tgtdev_put - k reference decrementor 435 * @s: Target device reference 436 * 437 * Decrement target device reference count. 438 */ 439 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 440 { 441 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 442 } 443 444 445 /** 446 * struct mpi3mr_stgt_priv_data - SCSI target private structure 447 * 448 * @starget: Scsi_target pointer 449 * @dev_handle: FW device handle 450 * @perst_id: FW assigned Persistent ID 451 * @num_luns: Number of Logical Units 452 * @block_io: I/O blocked to the device or not 453 * @dev_removed: Device removed in the Firmware 454 * @dev_removedelay: Device is waiting to be removed in FW 455 * @dev_type: Device type 456 * @tgt_dev: Internal target device pointer 457 */ 458 struct mpi3mr_stgt_priv_data { 459 struct scsi_target *starget; 460 u16 dev_handle; 461 u16 perst_id; 462 u32 num_luns; 463 atomic_t block_io; 464 u8 dev_removed; 465 u8 dev_removedelay; 466 u8 dev_type; 467 struct mpi3mr_tgt_dev *tgt_dev; 468 }; 469 470 /** 471 * struct mpi3mr_stgt_priv_data - SCSI device private structure 472 * 473 * @tgt_priv_data: Scsi_target private data pointer 474 * @lun_id: LUN ID of the device 475 * @ncq_prio_enable: NCQ priority enable for SATA device 476 */ 477 struct mpi3mr_sdev_priv_data { 478 struct mpi3mr_stgt_priv_data *tgt_priv_data; 479 u32 lun_id; 480 u8 ncq_prio_enable; 481 }; 482 483 /** 484 * struct mpi3mr_drv_cmd - Internal command tracker 485 * 486 * @mutex: Command mutex 487 * @done: Completeor for wakeup 488 * @reply: Firmware reply for internal commands 489 * @sensebuf: Sensebuf for SCSI IO commands 490 * @iou_rc: IO Unit control reason code 491 * @state: Command State 492 * @dev_handle: Firmware handle for device specific commands 493 * @ioc_status: IOC status from the firmware 494 * @ioc_loginfo:IOC log info from the firmware 495 * @is_waiting: Is the command issued in block mode 496 * @retry_count: Retry count for retriable commands 497 * @host_tag: Host tag used by the command 498 * @callback: Callback for non blocking commands 499 */ 500 struct mpi3mr_drv_cmd { 501 struct mutex mutex; 502 struct completion done; 503 void *reply; 504 u8 *sensebuf; 505 u8 iou_rc; 506 u16 state; 507 u16 dev_handle; 508 u16 ioc_status; 509 u32 ioc_loginfo; 510 u8 is_waiting; 511 u8 retry_count; 512 u16 host_tag; 513 514 void (*callback)(struct mpi3mr_ioc *mrioc, 515 struct mpi3mr_drv_cmd *drv_cmd); 516 }; 517 518 519 /** 520 * struct chain_element - memory descriptor structure to store 521 * virtual and dma addresses for chain elements. 522 * 523 * @addr: virtual address 524 * @dma_addr: dma address 525 */ 526 struct chain_element { 527 void *addr; 528 dma_addr_t dma_addr; 529 }; 530 531 /** 532 * struct scmd_priv - SCSI command private data 533 * 534 * @host_tag: Host tag specific to operational queue 535 * @in_lld_scope: Command in LLD scope or not 536 * @scmd: SCSI Command pointer 537 * @req_q_idx: Operational request queue index 538 * @chain_idx: Chain frame index 539 * @mpi3mr_scsiio_req: MPI SCSI IO request 540 */ 541 struct scmd_priv { 542 u16 host_tag; 543 u8 in_lld_scope; 544 struct scsi_cmnd *scmd; 545 u16 req_q_idx; 546 int chain_idx; 547 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 548 }; 549 550 /** 551 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 552 * private data 553 * 554 * @list: List pointer 555 * @pdev: PCI device pointer 556 * @shost: Scsi_Host pointer 557 * @id: Controller ID 558 * @cpu_count: Number of online CPUs 559 * @name: Controller ASCII name 560 * @driver_name: Driver ASCII name 561 * @sysif_regs: System interface registers virtual address 562 * @sysif_regs_phys: System interface registers physical address 563 * @bars: PCI BARS 564 * @dma_mask: DMA mask 565 * @msix_count: Number of MSIX vectors used 566 * @intr_enabled: Is interrupts enabled 567 * @num_admin_req: Number of admin requests 568 * @admin_req_q_sz: Admin request queue size 569 * @admin_req_pi: Admin request queue producer index 570 * @admin_req_ci: Admin request queue consumer index 571 * @admin_req_base: Admin request queue base virtual address 572 * @admin_req_dma: Admin request queue base dma address 573 * @admin_req_lock: Admin queue access lock 574 * @num_admin_replies: Number of admin replies 575 * @admin_reply_q_sz: Admin reply queue size 576 * @admin_reply_ci: Admin reply queue consumer index 577 * @admin_reply_ephase:Admin reply queue expected phase 578 * @admin_reply_base: Admin reply queue base virtual address 579 * @admin_reply_dma: Admin reply queue base dma address 580 * @ready_timeout: Controller ready timeout 581 * @intr_info: Interrupt cookie pointer 582 * @intr_info_count: Number of interrupt cookies 583 * @num_queues: Number of operational queues 584 * @num_op_req_q: Number of operational request queues 585 * @req_qinfo: Operational request queue info pointer 586 * @num_op_reply_q: Number of operational reply queues 587 * @op_reply_qinfo: Operational reply queue info pointer 588 * @init_cmds: Command tracker for initialization commands 589 * @facts: Cached IOC facts data 590 * @op_reply_desc_sz: Operational reply descriptor size 591 * @num_reply_bufs: Number of reply buffers allocated 592 * @reply_buf_pool: Reply buffer pool 593 * @reply_buf: Reply buffer base virtual address 594 * @reply_buf_dma: Reply buffer DMA address 595 * @reply_buf_dma_max_address: Reply DMA address max limit 596 * @reply_free_qsz: Reply free queue size 597 * @reply_free_q_pool: Reply free queue pool 598 * @reply_free_q: Reply free queue base virtual address 599 * @reply_free_q_dma: Reply free queue base DMA address 600 * @reply_free_queue_lock: Reply free queue lock 601 * @reply_free_queue_host_index: Reply free queue host index 602 * @num_sense_bufs: Number of sense buffers 603 * @sense_buf_pool: Sense buffer pool 604 * @sense_buf: Sense buffer base virtual address 605 * @sense_buf_dma: Sense buffer base DMA address 606 * @sense_buf_q_sz: Sense buffer queue size 607 * @sense_buf_q_pool: Sense buffer queue pool 608 * @sense_buf_q: Sense buffer queue virtual address 609 * @sense_buf_q_dma: Sense buffer queue DMA address 610 * @sbq_lock: Sense buffer queue lock 611 * @sbq_host_index: Sense buffer queuehost index 612 * @event_masks: Event mask bitmap 613 * @fwevt_worker_name: Firmware event worker thread name 614 * @fwevt_worker_thread: Firmware event worker thread 615 * @fwevt_lock: Firmware event lock 616 * @fwevt_list: Firmware event list 617 * @watchdog_work_q_name: Fault watchdog worker thread name 618 * @watchdog_work_q: Fault watchdog worker thread 619 * @watchdog_work: Fault watchdog work 620 * @watchdog_lock: Fault watchdog lock 621 * @is_driver_loading: Is driver still loading 622 * @scan_started: Async scan started 623 * @scan_failed: Asycn scan failed 624 * @stop_drv_processing: Stop all command processing 625 * @max_host_ios: Maximum host I/O count 626 * @chain_buf_count: Chain buffer count 627 * @chain_buf_pool: Chain buffer pool 628 * @chain_sgl_list: Chain SGL list 629 * @chain_bitmap_sz: Chain buffer allocator bitmap size 630 * @chain_bitmap: Chain buffer allocator bitmap 631 * @chain_buf_lock: Chain buffer list lock 632 * @dev_rmhs_cmds: Command tracker for device removal commands 633 * @devrem_bitmap_sz: Device removal bitmap size 634 * @devrem_bitmap: Device removal bitmap 635 * @dev_handle_bitmap_sz: Device handle bitmap size 636 * @removepend_bitmap: Remove pending bitmap 637 * @delayed_rmhs_list: Delayed device removal list 638 * @reset_in_progress: Reset in progress flag 639 * @unrecoverable: Controller unrecoverable flag 640 * @diagsave_timeout: Diagnostic information save timeout 641 * @logging_level: Controller debug logging level 642 * @current_event: Firmware event currently in process 643 * @driver_info: Driver, Kernel, OS information to firmware 644 * @change_count: Topology change count 645 * @op_reply_q_offset: Operational reply queue offset with MSIx 646 */ 647 struct mpi3mr_ioc { 648 struct list_head list; 649 struct pci_dev *pdev; 650 struct Scsi_Host *shost; 651 u8 id; 652 int cpu_count; 653 bool enable_segqueue; 654 655 char name[MPI3MR_NAME_LENGTH]; 656 char driver_name[MPI3MR_NAME_LENGTH]; 657 658 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 659 resource_size_t sysif_regs_phys; 660 int bars; 661 u64 dma_mask; 662 663 u16 msix_count; 664 u8 intr_enabled; 665 666 u16 num_admin_req; 667 u32 admin_req_q_sz; 668 u16 admin_req_pi; 669 u16 admin_req_ci; 670 void *admin_req_base; 671 dma_addr_t admin_req_dma; 672 spinlock_t admin_req_lock; 673 674 u16 num_admin_replies; 675 u32 admin_reply_q_sz; 676 u16 admin_reply_ci; 677 u8 admin_reply_ephase; 678 void *admin_reply_base; 679 dma_addr_t admin_reply_dma; 680 681 u32 ready_timeout; 682 683 struct mpi3mr_intr_info *intr_info; 684 u16 intr_info_count; 685 686 u16 num_queues; 687 u16 num_op_req_q; 688 struct op_req_qinfo *req_qinfo; 689 690 u16 num_op_reply_q; 691 struct op_reply_qinfo *op_reply_qinfo; 692 693 struct mpi3mr_drv_cmd init_cmds; 694 struct mpi3mr_ioc_facts facts; 695 u16 op_reply_desc_sz; 696 697 u32 num_reply_bufs; 698 struct dma_pool *reply_buf_pool; 699 u8 *reply_buf; 700 dma_addr_t reply_buf_dma; 701 dma_addr_t reply_buf_dma_max_address; 702 703 u16 reply_free_qsz; 704 struct dma_pool *reply_free_q_pool; 705 __le64 *reply_free_q; 706 dma_addr_t reply_free_q_dma; 707 spinlock_t reply_free_queue_lock; 708 u32 reply_free_queue_host_index; 709 710 u32 num_sense_bufs; 711 struct dma_pool *sense_buf_pool; 712 u8 *sense_buf; 713 dma_addr_t sense_buf_dma; 714 715 u16 sense_buf_q_sz; 716 struct dma_pool *sense_buf_q_pool; 717 __le64 *sense_buf_q; 718 dma_addr_t sense_buf_q_dma; 719 spinlock_t sbq_lock; 720 u32 sbq_host_index; 721 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 722 723 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 724 struct workqueue_struct *fwevt_worker_thread; 725 spinlock_t fwevt_lock; 726 struct list_head fwevt_list; 727 728 char watchdog_work_q_name[20]; 729 struct workqueue_struct *watchdog_work_q; 730 struct delayed_work watchdog_work; 731 spinlock_t watchdog_lock; 732 733 u8 is_driver_loading; 734 u8 scan_started; 735 u16 scan_failed; 736 u8 stop_drv_processing; 737 738 u16 max_host_ios; 739 spinlock_t tgtdev_lock; 740 struct list_head tgtdev_list; 741 742 u32 chain_buf_count; 743 struct dma_pool *chain_buf_pool; 744 struct chain_element *chain_sgl_list; 745 u16 chain_bitmap_sz; 746 void *chain_bitmap; 747 spinlock_t chain_buf_lock; 748 749 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 750 u16 devrem_bitmap_sz; 751 void *devrem_bitmap; 752 u16 dev_handle_bitmap_sz; 753 void *removepend_bitmap; 754 struct list_head delayed_rmhs_list; 755 756 u8 reset_in_progress; 757 u8 unrecoverable; 758 759 u16 diagsave_timeout; 760 int logging_level; 761 762 struct mpi3mr_fwevt *current_event; 763 struct mpi3_driver_info_layout driver_info; 764 u16 change_count; 765 u16 op_reply_q_offset; 766 }; 767 768 /** 769 * struct mpi3mr_fwevt - Firmware event structure. 770 * 771 * @list: list head 772 * @work: Work structure 773 * @mrioc: Adapter instance reference 774 * @event_id: MPI3 firmware event ID 775 * @send_ack: Event acknowledgment required or not 776 * @process_evt: Bottomhalf processing required or not 777 * @evt_ctx: Event context to send in Ack 778 * @ref_count: kref count 779 * @event_data: Actual MPI3 event data 780 */ 781 struct mpi3mr_fwevt { 782 struct list_head list; 783 struct work_struct work; 784 struct mpi3mr_ioc *mrioc; 785 u16 event_id; 786 bool send_ack; 787 bool process_evt; 788 u32 evt_ctx; 789 struct kref ref_count; 790 char event_data[0] __aligned(4); 791 }; 792 793 794 /** 795 * struct delayed_dev_rmhs_node - Delayed device removal node 796 * 797 * @list: list head 798 * @handle: Device handle 799 * @iou_rc: IO Unit Control Reason Code 800 */ 801 struct delayed_dev_rmhs_node { 802 struct list_head list; 803 u16 handle; 804 u8 iou_rc; 805 }; 806 807 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 808 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 809 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 810 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 811 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 812 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 813 u16 admin_req_sz, u8 ignore_reset); 814 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 815 struct op_req_qinfo *opreqq, u8 *req); 816 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 817 dma_addr_t dma_addr); 818 void mpi3mr_build_zero_len_sge(void *paddr); 819 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 820 dma_addr_t phys_addr); 821 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 822 dma_addr_t phys_addr); 823 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 824 u64 sense_buf_dma); 825 826 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 827 struct mpi3_event_notification_reply *event_reply); 828 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 829 struct mpi3_default_reply_descriptor *reply_desc, 830 u64 *reply_dma, u16 qidx); 831 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 832 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 833 834 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 835 u32 reset_reason, u8 snapdump); 836 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 837 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 838 839 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 840 int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 841 u32 event_ctx); 842 843 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 844 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 845 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 846 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 847 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 848 void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc); 849 850 #endif /*MPI3MR_H_INCLUDED*/ 851