1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2021 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 #include <linux/uaccess.h> 31 #include <linux/utsname.h> 32 #include <linux/version.h> 33 #include <linux/workqueue.h> 34 #include <asm/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 42 #include "mpi/mpi30_transport.h" 43 #include "mpi/mpi30_image.h" 44 #include "mpi/mpi30_init.h" 45 #include "mpi/mpi30_ioc.h" 46 #include "mpi3mr_debug.h" 47 48 /* Global list and lock for storing multiple adapters managed by the driver */ 49 extern spinlock_t mrioc_list_lock; 50 extern struct list_head mrioc_list; 51 52 #define MPI3MR_DRIVER_VERSION "00.255.45.01" 53 #define MPI3MR_DRIVER_RELDATE "12-December-2020" 54 55 #define MPI3MR_DRIVER_NAME "mpi3mr" 56 #define MPI3MR_DRIVER_LICENSE "GPL" 57 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 58 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 59 60 #define MPI3MR_NAME_LENGTH 32 61 #define IOCNAME "%s: " 62 63 /* Definitions for internal SGL and Chain SGL buffers */ 64 #define MPI3MR_PAGE_SIZE_4K 4096 65 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common)) 66 67 /* Definitions for MAX values for shost */ 68 #define MPI3MR_MAX_CMDS_LUN 7 69 #define MPI3MR_MAX_CDB_LENGTH 32 70 71 /* Admin queue management definitions */ 72 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 73 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 74 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 75 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 76 77 /* Operational queue management definitions */ 78 #define MPI3MR_OP_REQ_Q_QD 512 79 #define MPI3MR_OP_REP_Q_QD 4096 80 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 81 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 82 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 83 84 /* Reserved Host Tag definitions */ 85 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 86 #define MPI3MR_HOSTTAG_INITCMDS 1 87 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 88 #define MPI3MR_HOSTTAG_BLK_TMS 5 89 90 #define MPI3MR_NUM_DEVRMCMD 1 91 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1) 92 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 93 MPI3MR_NUM_DEVRMCMD - 1) 94 95 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 96 97 /* Reduced resource count definition for crash kernel */ 98 #define MPI3MR_HOST_IOS_KDUMP 128 99 100 /* command/controller interaction timeout definitions in seconds */ 101 #define MPI3MR_INTADMCMD_TIMEOUT 10 102 #define MPI3MR_PORTENABLE_TIMEOUT 300 103 #define MPI3MR_RESETTM_TIMEOUT 30 104 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 105 106 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 107 108 /* Internal admin command state definitions*/ 109 #define MPI3MR_CMD_NOTUSED 0x8000 110 #define MPI3MR_CMD_COMPLETE 0x0001 111 #define MPI3MR_CMD_PENDING 0x0002 112 #define MPI3MR_CMD_REPLY_VALID 0x0004 113 #define MPI3MR_CMD_RESET 0x0008 114 115 /* Definitions for Event replies and sense buffer allocated per controller */ 116 #define MPI3MR_NUM_EVT_REPLIES 64 117 #define MPI3MR_SENSEBUF_SZ 256 118 #define MPI3MR_SENSEBUF_FACTOR 3 119 #define MPI3MR_CHAINBUF_FACTOR 3 120 121 /* Invalid target device handle */ 122 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 123 124 /* Controller Reset related definitions */ 125 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 126 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 127 128 /* ResponseCode definitions */ 129 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 130 #define MPI3MR_RSP_TM_COMPLETE 0x00 131 #define MPI3MR_RSP_INVALID_FRAME 0x02 132 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 133 #define MPI3MR_RSP_TM_FAILED 0x05 134 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 135 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 136 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 137 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 138 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 139 140 /* SGE Flag definition */ 141 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 142 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 143 MPI3_SGE_FLAGS_END_OF_LIST) 144 145 /* MSI Index from Reply Queue Index */ 146 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 147 148 /* IOC State definitions */ 149 enum mpi3mr_iocstate { 150 MRIOC_STATE_READY = 1, 151 MRIOC_STATE_RESET, 152 MRIOC_STATE_FAULT, 153 MRIOC_STATE_BECOMING_READY, 154 MRIOC_STATE_RESET_REQUESTED, 155 MRIOC_STATE_UNRECOVERABLE, 156 }; 157 158 /* Reset reason code definitions*/ 159 enum mpi3mr_reset_reason { 160 MPI3MR_RESET_FROM_BRINGUP = 1, 161 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 162 MPI3MR_RESET_FROM_IOCTL = 3, 163 MPI3MR_RESET_FROM_EH_HOS = 4, 164 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 165 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 166 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 167 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 168 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 169 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 170 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 171 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 172 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 173 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 174 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 175 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 176 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 177 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 178 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 179 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 180 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 181 }; 182 183 /** 184 * struct mpi3mr_compimg_ver - replica of component image 185 * version defined in mpi30_image.h in host endianness 186 * 187 */ 188 struct mpi3mr_compimg_ver { 189 u16 build_num; 190 u16 cust_id; 191 u8 ph_minor; 192 u8 ph_major; 193 u8 gen_minor; 194 u8 gen_major; 195 }; 196 197 /** 198 * struct mpi3mr_ioc_facs - replica of component image version 199 * defined in mpi30_ioc.h in host endianness 200 * 201 */ 202 struct mpi3mr_ioc_facts { 203 u32 ioc_capabilities; 204 struct mpi3mr_compimg_ver fw_ver; 205 u32 mpi_version; 206 u16 max_reqs; 207 u16 product_id; 208 u16 op_req_sz; 209 u16 reply_sz; 210 u16 exceptions; 211 u16 max_perids; 212 u16 max_pds; 213 u16 max_sasexpanders; 214 u16 max_sasinitiators; 215 u16 max_enclosures; 216 u16 max_pcie_switches; 217 u16 max_nvme; 218 u16 max_vds; 219 u16 max_hpds; 220 u16 max_advhpds; 221 u16 max_raidpds; 222 u16 min_devhandle; 223 u16 max_devhandle; 224 u16 max_op_req_q; 225 u16 max_op_reply_q; 226 u16 shutdown_timeout; 227 u8 ioc_num; 228 u8 who_init; 229 u16 max_msix_vectors; 230 u8 personality; 231 u8 dma_mask; 232 u8 protocol_flags; 233 u8 sge_mod_mask; 234 u8 sge_mod_value; 235 u8 sge_mod_shift; 236 }; 237 238 /** 239 * struct segments - memory descriptor structure to store 240 * virtual and dma addresses for operational queue segments. 241 * 242 * @segment: virtual address 243 * @segment_dma: dma address 244 */ 245 struct segments { 246 void *segment; 247 dma_addr_t segment_dma; 248 }; 249 250 /** 251 * struct op_req_qinfo - Operational Request Queue Information 252 * 253 * @ci: consumer index 254 * @pi: producer index 255 * @num_request: Maximum number of entries in the queue 256 * @qid: Queue Id starting from 1 257 * @reply_qid: Associated reply queue Id 258 * @num_segments: Number of discontiguous memory segments 259 * @segment_qd: Depth of each segments 260 * @q_lock: Concurrent queue access lock 261 * @q_segments: Segment descriptor pointer 262 * @q_segment_list: Segment list base virtual address 263 * @q_segment_list_dma: Segment list base DMA address 264 */ 265 struct op_req_qinfo { 266 u16 ci; 267 u16 pi; 268 u16 num_requests; 269 u16 qid; 270 u16 reply_qid; 271 u16 num_segments; 272 u16 segment_qd; 273 spinlock_t q_lock; 274 struct segments *q_segments; 275 void *q_segment_list; 276 dma_addr_t q_segment_list_dma; 277 }; 278 279 /** 280 * struct op_reply_qinfo - Operational Reply Queue Information 281 * 282 * @ci: consumer index 283 * @qid: Queue Id starting from 1 284 * @num_replies: Maximum number of entries in the queue 285 * @num_segments: Number of discontiguous memory segments 286 * @segment_qd: Depth of each segments 287 * @q_segments: Segment descriptor pointer 288 * @q_segment_list: Segment list base virtual address 289 * @q_segment_list_dma: Segment list base DMA address 290 * @ephase: Expected phased identifier for the reply queue 291 */ 292 struct op_reply_qinfo { 293 u16 ci; 294 u16 qid; 295 u16 num_replies; 296 u16 num_segments; 297 u16 segment_qd; 298 struct segments *q_segments; 299 void *q_segment_list; 300 dma_addr_t q_segment_list_dma; 301 u8 ephase; 302 }; 303 304 /** 305 * struct mpi3mr_intr_info - Interrupt cookie information 306 * 307 * @mrioc: Adapter instance reference 308 * @msix_index: MSIx index 309 * @op_reply_q: Associated operational reply queue 310 * @name: Dev name for the irq claiming device 311 */ 312 struct mpi3mr_intr_info { 313 struct mpi3mr_ioc *mrioc; 314 u16 msix_index; 315 struct op_reply_qinfo *op_reply_q; 316 char name[MPI3MR_NAME_LENGTH]; 317 }; 318 319 /** 320 * struct mpi3mr_stgt_priv_data - SCSI target private structure 321 * 322 * @starget: Scsi_target pointer 323 * @dev_handle: FW device handle 324 * @perst_id: FW assigned Persistent ID 325 * @num_luns: Number of Logical Units 326 * @block_io: I/O blocked to the device or not 327 * @dev_removed: Device removed in the Firmware 328 * @dev_removedelay: Device is waiting to be removed in FW 329 * @dev_type: Device type 330 * @tgt_dev: Internal target device pointer 331 */ 332 struct mpi3mr_stgt_priv_data { 333 struct scsi_target *starget; 334 u16 dev_handle; 335 u16 perst_id; 336 u32 num_luns; 337 atomic_t block_io; 338 u8 dev_removed; 339 u8 dev_removedelay; 340 u8 dev_type; 341 struct mpi3mr_tgt_dev *tgt_dev; 342 }; 343 344 /** 345 * struct mpi3mr_stgt_priv_data - SCSI device private structure 346 * 347 * @tgt_priv_data: Scsi_target private data pointer 348 * @lun_id: LUN ID of the device 349 * @ncq_prio_enable: NCQ priority enable for SATA device 350 */ 351 struct mpi3mr_sdev_priv_data { 352 struct mpi3mr_stgt_priv_data *tgt_priv_data; 353 u32 lun_id; 354 u8 ncq_prio_enable; 355 }; 356 357 /** 358 * struct mpi3mr_drv_cmd - Internal command tracker 359 * 360 * @mutex: Command mutex 361 * @done: Completeor for wakeup 362 * @reply: Firmware reply for internal commands 363 * @sensebuf: Sensebuf for SCSI IO commands 364 * @state: Command State 365 * @dev_handle: Firmware handle for device specific commands 366 * @ioc_status: IOC status from the firmware 367 * @ioc_loginfo:IOC log info from the firmware 368 * @is_waiting: Is the command issued in block mode 369 * @retry_count: Retry count for retriable commands 370 * @host_tag: Host tag used by the command 371 * @callback: Callback for non blocking commands 372 */ 373 struct mpi3mr_drv_cmd { 374 struct mutex mutex; 375 struct completion done; 376 void *reply; 377 u8 *sensebuf; 378 u16 state; 379 u16 dev_handle; 380 u16 ioc_status; 381 u32 ioc_loginfo; 382 u8 is_waiting; 383 u8 retry_count; 384 u16 host_tag; 385 386 void (*callback)(struct mpi3mr_ioc *mrioc, 387 struct mpi3mr_drv_cmd *drv_cmd); 388 }; 389 390 391 /** 392 * struct chain_element - memory descriptor structure to store 393 * virtual and dma addresses for chain elements. 394 * 395 * @addr: virtual address 396 * @dma_addr: dma address 397 */ 398 struct chain_element { 399 void *addr; 400 dma_addr_t dma_addr; 401 }; 402 403 /** 404 * struct scmd_priv - SCSI command private data 405 * 406 * @host_tag: Host tag specific to operational queue 407 * @in_lld_scope: Command in LLD scope or not 408 * @scmd: SCSI Command pointer 409 * @req_q_idx: Operational request queue index 410 * @chain_idx: Chain frame index 411 * @mpi3mr_scsiio_req: MPI SCSI IO request 412 */ 413 struct scmd_priv { 414 u16 host_tag; 415 u8 in_lld_scope; 416 struct scsi_cmnd *scmd; 417 u16 req_q_idx; 418 int chain_idx; 419 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 420 }; 421 422 /** 423 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 424 * private data 425 * 426 * @list: List pointer 427 * @pdev: PCI device pointer 428 * @shost: Scsi_Host pointer 429 * @id: Controller ID 430 * @cpu_count: Number of online CPUs 431 * @name: Controller ASCII name 432 * @driver_name: Driver ASCII name 433 * @sysif_regs: System interface registers virtual address 434 * @sysif_regs_phys: System interface registers physical address 435 * @bars: PCI BARS 436 * @dma_mask: DMA mask 437 * @msix_count: Number of MSIX vectors used 438 * @intr_enabled: Is interrupts enabled 439 * @num_admin_req: Number of admin requests 440 * @admin_req_q_sz: Admin request queue size 441 * @admin_req_pi: Admin request queue producer index 442 * @admin_req_ci: Admin request queue consumer index 443 * @admin_req_base: Admin request queue base virtual address 444 * @admin_req_dma: Admin request queue base dma address 445 * @admin_req_lock: Admin queue access lock 446 * @num_admin_replies: Number of admin replies 447 * @admin_reply_q_sz: Admin reply queue size 448 * @admin_reply_ci: Admin reply queue consumer index 449 * @admin_reply_ephase:Admin reply queue expected phase 450 * @admin_reply_base: Admin reply queue base virtual address 451 * @admin_reply_dma: Admin reply queue base dma address 452 * @ready_timeout: Controller ready timeout 453 * @intr_info: Interrupt cookie pointer 454 * @intr_info_count: Number of interrupt cookies 455 * @num_queues: Number of operational queues 456 * @num_op_req_q: Number of operational request queues 457 * @req_qinfo: Operational request queue info pointer 458 * @num_op_reply_q: Number of operational reply queues 459 * @op_reply_qinfo: Operational reply queue info pointer 460 * @init_cmds: Command tracker for initialization commands 461 * @facts: Cached IOC facts data 462 * @op_reply_desc_sz: Operational reply descriptor size 463 * @num_reply_bufs: Number of reply buffers allocated 464 * @reply_buf_pool: Reply buffer pool 465 * @reply_buf: Reply buffer base virtual address 466 * @reply_buf_dma: Reply buffer DMA address 467 * @reply_buf_dma_max_address: Reply DMA address max limit 468 * @reply_free_qsz: Reply free queue size 469 * @reply_free_q_pool: Reply free queue pool 470 * @reply_free_q: Reply free queue base virtual address 471 * @reply_free_q_dma: Reply free queue base DMA address 472 * @reply_free_queue_lock: Reply free queue lock 473 * @reply_free_queue_host_index: Reply free queue host index 474 * @num_sense_bufs: Number of sense buffers 475 * @sense_buf_pool: Sense buffer pool 476 * @sense_buf: Sense buffer base virtual address 477 * @sense_buf_dma: Sense buffer base DMA address 478 * @sense_buf_q_sz: Sense buffer queue size 479 * @sense_buf_q_pool: Sense buffer queue pool 480 * @sense_buf_q: Sense buffer queue virtual address 481 * @sense_buf_q_dma: Sense buffer queue DMA address 482 * @sbq_lock: Sense buffer queue lock 483 * @sbq_host_index: Sense buffer queuehost index 484 * @is_driver_loading: Is driver still loading 485 * @scan_started: Async scan started 486 * @scan_failed: Asycn scan failed 487 * @stop_drv_processing: Stop all command processing 488 * @max_host_ios: Maximum host I/O count 489 * @chain_buf_count: Chain buffer count 490 * @chain_buf_pool: Chain buffer pool 491 * @chain_sgl_list: Chain SGL list 492 * @chain_bitmap_sz: Chain buffer allocator bitmap size 493 * @chain_bitmap: Chain buffer allocator bitmap 494 * @chain_buf_lock: Chain buffer list lock 495 * @reset_in_progress: Reset in progress flag 496 * @unrecoverable: Controller unrecoverable flag 497 * @logging_level: Controller debug logging level 498 * @current_event: Firmware event currently in process 499 * @driver_info: Driver, Kernel, OS information to firmware 500 * @change_count: Topology change count 501 * @op_reply_q_offset: Operational reply queue offset with MSIx 502 */ 503 struct mpi3mr_ioc { 504 struct list_head list; 505 struct pci_dev *pdev; 506 struct Scsi_Host *shost; 507 u8 id; 508 int cpu_count; 509 bool enable_segqueue; 510 511 char name[MPI3MR_NAME_LENGTH]; 512 char driver_name[MPI3MR_NAME_LENGTH]; 513 514 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 515 resource_size_t sysif_regs_phys; 516 int bars; 517 u64 dma_mask; 518 519 u16 msix_count; 520 u8 intr_enabled; 521 522 u16 num_admin_req; 523 u32 admin_req_q_sz; 524 u16 admin_req_pi; 525 u16 admin_req_ci; 526 void *admin_req_base; 527 dma_addr_t admin_req_dma; 528 spinlock_t admin_req_lock; 529 530 u16 num_admin_replies; 531 u32 admin_reply_q_sz; 532 u16 admin_reply_ci; 533 u8 admin_reply_ephase; 534 void *admin_reply_base; 535 dma_addr_t admin_reply_dma; 536 537 u32 ready_timeout; 538 539 struct mpi3mr_intr_info *intr_info; 540 u16 intr_info_count; 541 542 u16 num_queues; 543 u16 num_op_req_q; 544 struct op_req_qinfo *req_qinfo; 545 546 u16 num_op_reply_q; 547 struct op_reply_qinfo *op_reply_qinfo; 548 549 struct mpi3mr_drv_cmd init_cmds; 550 struct mpi3mr_ioc_facts facts; 551 u16 op_reply_desc_sz; 552 553 u32 num_reply_bufs; 554 struct dma_pool *reply_buf_pool; 555 u8 *reply_buf; 556 dma_addr_t reply_buf_dma; 557 dma_addr_t reply_buf_dma_max_address; 558 559 u16 reply_free_qsz; 560 struct dma_pool *reply_free_q_pool; 561 __le64 *reply_free_q; 562 dma_addr_t reply_free_q_dma; 563 spinlock_t reply_free_queue_lock; 564 u32 reply_free_queue_host_index; 565 566 u32 num_sense_bufs; 567 struct dma_pool *sense_buf_pool; 568 u8 *sense_buf; 569 dma_addr_t sense_buf_dma; 570 571 u16 sense_buf_q_sz; 572 struct dma_pool *sense_buf_q_pool; 573 __le64 *sense_buf_q; 574 dma_addr_t sense_buf_q_dma; 575 spinlock_t sbq_lock; 576 u32 sbq_host_index; 577 578 u8 is_driver_loading; 579 u8 scan_started; 580 u16 scan_failed; 581 u8 stop_drv_processing; 582 583 u16 max_host_ios; 584 585 u32 chain_buf_count; 586 struct dma_pool *chain_buf_pool; 587 struct chain_element *chain_sgl_list; 588 u16 chain_bitmap_sz; 589 void *chain_bitmap; 590 spinlock_t chain_buf_lock; 591 592 u8 reset_in_progress; 593 u8 unrecoverable; 594 595 int logging_level; 596 597 struct mpi3mr_fwevt *current_event; 598 struct mpi3_driver_info_layout driver_info; 599 u16 change_count; 600 u16 op_reply_q_offset; 601 }; 602 603 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 604 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 605 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 606 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 607 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 608 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 609 u16 admin_req_sz, u8 ignore_reset); 610 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 611 struct op_req_qinfo *opreqq, u8 *req); 612 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 613 dma_addr_t dma_addr); 614 void mpi3mr_build_zero_len_sge(void *paddr); 615 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 616 dma_addr_t phys_addr); 617 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 618 dma_addr_t phys_addr); 619 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 620 u64 sense_buf_dma); 621 622 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 623 struct mpi3_default_reply_descriptor *reply_desc, 624 u64 *reply_dma, u16 qidx); 625 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 626 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 627 628 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 629 u32 reset_reason, u8 snapdump); 630 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 631 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 632 633 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 634 635 #endif /*MPI3MR_H_INCLUDED*/ 636