1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2021 Broadcom Inc. All rights reserved. 4 * 5 */ 6 #ifndef MPI30_TRANSPORT_H 7 #define MPI30_TRANSPORT_H 1 8 struct mpi3_version_struct { 9 u8 dev; 10 u8 unit; 11 u8 minor; 12 u8 major; 13 }; 14 15 union mpi3_version_union { 16 struct mpi3_version_struct mpi3_version; 17 __le32 word; 18 }; 19 20 #define MPI3_VERSION_MAJOR (3) 21 #define MPI3_VERSION_MINOR (0) 22 #define MPI3_VERSION_UNIT (0) 23 #define MPI3_VERSION_DEV (18) 24 struct mpi3_sysif_oper_queue_indexes { 25 __le16 producer_index; 26 __le16 reserved02; 27 __le16 consumer_index; 28 __le16 reserved06; 29 }; 30 31 struct mpi3_sysif_registers { 32 __le64 ioc_information; 33 union mpi3_version_union version; 34 __le32 reserved0c[2]; 35 __le32 ioc_configuration; 36 __le32 reserved18; 37 __le32 ioc_status; 38 __le32 reserved20; 39 __le32 admin_queue_num_entries; 40 __le64 admin_request_queue_address; 41 __le64 admin_reply_queue_address; 42 __le32 reserved38[2]; 43 __le32 coalesce_control; 44 __le32 reserved44[1007]; 45 __le16 admin_request_queue_pi; 46 __le16 reserved1002; 47 __le16 admin_reply_queue_ci; 48 __le16 reserved1006; 49 struct mpi3_sysif_oper_queue_indexes oper_queue_indexes[383]; 50 __le32 reserved1c00; 51 __le32 write_sequence; 52 __le32 host_diagnostic; 53 __le32 reserved1c0c; 54 __le32 fault; 55 __le32 fault_info[3]; 56 __le32 reserved1c20[4]; 57 __le64 hcb_address; 58 __le32 hcb_size; 59 __le32 reserved1c3c; 60 __le32 reply_free_host_index; 61 __le32 sense_buffer_free_host_index; 62 __le32 reserved1c48[2]; 63 __le64 diag_rw_data; 64 __le64 diag_rw_address; 65 __le16 diag_rw_control; 66 __le16 diag_rw_status; 67 __le32 reserved1c64[35]; 68 __le32 scratchpad[4]; 69 __le32 reserved1d00[192]; 70 __le32 device_assigned_registers[2048]; 71 }; 72 73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) 74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) 75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000) 76 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) 77 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) 78 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000) 79 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) 80 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000) 81 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) 82 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000) 83 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) 84 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) 85 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN (0x00002000) 86 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) 87 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) 88 #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c) 89 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) 90 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c) 91 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) 92 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) 93 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) 94 #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) 95 #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) 96 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) 97 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0fff) 98 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) 99 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0fff0000) 100 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) 101 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) 102 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002c) 103 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) 104 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) 105 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) 106 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xc0000000) 107 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) 108 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) 109 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000) 110 #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x30000000) 111 #define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_MASK (0x00ff0000) 112 #define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_SHIFT (16) 113 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00) 114 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) 115 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff) 116 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) 117 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) 118 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) 119 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) 120 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(n) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((n) - 1) * 8)) 121 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c) 122 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(n) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((n) - 1) * 8)) 123 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04) 124 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f) 125 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) 126 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xf) 127 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) 128 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xb) 129 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) 130 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) 131 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xd) 132 #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001c08) 133 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) 134 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) 135 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) 136 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_FLASH_RCVRY_RESET (0x00000200) 137 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) 138 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) 139 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) 140 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) 141 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) 142 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) 143 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) 144 #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) 145 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) 146 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) 147 #define MPI3_SYSIF_FAULT_OFFSET (0x00001c10) 148 #define MPI3_SYSIF_FAULT_FUNC_AREA_MASK (0xff000000) 149 #define MPI3_SYSIF_FAULT_FUNC_AREA_SHIFT (24) 150 #define MPI3_SYSIF_FAULT_FUNC_AREA_MPI_DEFINED (0x00000000) 151 #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000ffff) 152 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000f000) 153 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001) 154 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002) 155 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003) 156 #define MPI3_SYSIF_FAULT_CODE_SAFE_MODE_EXIT (0x0000f004) 157 #define MPI3_SYSIF_FAULT_CODE_FACTORY_RESET (0x0000f005) 158 #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14) 159 #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18) 160 #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c) 161 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001c30) 162 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001c34) 163 #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001c38) 164 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xfffff000) 165 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) 166 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) 167 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001c40) 168 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001c44) 169 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001c50) 170 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001c54) 171 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001c58) 172 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001c5c) 173 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001c60) 174 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) 175 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) 176 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) 177 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) 178 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) 179 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) 180 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) 181 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) 182 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) 183 #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) 184 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001c62) 185 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000e) 186 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) 187 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) 188 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) 189 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) 190 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) 191 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001cf0) 192 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001cf4) 193 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001cf8) 194 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001cfc) 195 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) 196 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) 197 struct mpi3_default_reply_descriptor { 198 __le32 descriptor_type_dependent1[2]; 199 __le16 request_queue_ci; 200 __le16 request_queue_id; 201 __le16 descriptor_type_dependent2; 202 __le16 reply_flags; 203 }; 204 205 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) 206 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xf000) 207 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) 208 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) 209 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) 210 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) 211 struct mpi3_address_reply_descriptor { 212 __le64 reply_frame_address; 213 __le16 request_queue_ci; 214 __le16 request_queue_id; 215 __le16 reserved0c; 216 __le16 reply_flags; 217 }; 218 219 struct mpi3_success_reply_descriptor { 220 __le32 reserved00[2]; 221 __le16 request_queue_ci; 222 __le16 request_queue_id; 223 __le16 host_tag; 224 __le16 reply_flags; 225 }; 226 227 struct mpi3_target_command_buffer_reply_descriptor { 228 __le32 reserved00; 229 __le16 initiator_dev_handle; 230 u8 phy_num; 231 u8 reserved07; 232 __le16 request_queue_ci; 233 __le16 request_queue_id; 234 __le16 io_index; 235 __le16 reply_flags; 236 }; 237 238 struct mpi3_status_reply_descriptor { 239 __le16 ioc_status; 240 __le16 reserved02; 241 __le32 ioc_log_info; 242 __le16 request_queue_ci; 243 __le16 request_queue_id; 244 __le16 host_tag; 245 __le16 reply_flags; 246 }; 247 248 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000) 249 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7fff) 250 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xf0000000) 251 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000) 252 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000) 253 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0fffffff) 254 union mpi3_reply_descriptors_union { 255 struct mpi3_default_reply_descriptor default_reply; 256 struct mpi3_address_reply_descriptor address_reply; 257 struct mpi3_success_reply_descriptor success; 258 struct mpi3_target_command_buffer_reply_descriptor target_command_buffer; 259 struct mpi3_status_reply_descriptor status; 260 __le32 words[4]; 261 }; 262 263 struct mpi3_sge_common { 264 __le64 address; 265 __le32 length; 266 u8 reserved0c[3]; 267 u8 flags; 268 }; 269 270 struct mpi3_sge_bit_bucket { 271 __le64 reserved00; 272 __le32 length; 273 u8 reserved0c[3]; 274 u8 flags; 275 }; 276 277 struct mpi3_sge_extended_eedp { 278 u8 user_data_size; 279 u8 reserved01; 280 __le16 eedp_flags; 281 __le32 secondary_reference_tag; 282 __le16 secondary_application_tag; 283 __le16 application_tag_translation_mask; 284 __le16 reserved0c; 285 u8 extended_operation; 286 u8 flags; 287 }; 288 289 union mpi3_sge_union { 290 struct mpi3_sge_common simple; 291 struct mpi3_sge_common chain; 292 struct mpi3_sge_common last_chain; 293 struct mpi3_sge_bit_bucket bit_bucket; 294 struct mpi3_sge_extended_eedp eedp; 295 __le32 words[4]; 296 }; 297 298 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xf0) 299 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) 300 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) 301 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) 302 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) 303 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xf0) 304 #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) 305 #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) 306 #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) 307 #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) 308 #define MPI3_SGE_FLAGS_DLAS_IOC_DDR (0x01) 309 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) 310 #define MPI3_SGE_EXT_OPER_EEDP (0x00) 311 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) 312 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) 313 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) 314 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) 315 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) 316 #define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) 317 #define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) 318 #define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) 319 #define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00c0) 320 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) 321 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) 322 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00c0) 323 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) 324 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) 325 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) 326 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) 327 #define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) 328 #define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) 329 #define MPI3_EEDPFLAGS_EEDP_OP_NOOP (0x0000) 330 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) 331 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) 332 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) 333 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) 334 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) 335 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) 336 #define MPI3_EEDP_UDS_512 (0x01) 337 #define MPI3_EEDP_UDS_520 (0x02) 338 #define MPI3_EEDP_UDS_4080 (0x03) 339 #define MPI3_EEDP_UDS_4088 (0x04) 340 #define MPI3_EEDP_UDS_4096 (0x05) 341 #define MPI3_EEDP_UDS_4104 (0x06) 342 #define MPI3_EEDP_UDS_4160 (0x07) 343 struct mpi3_request_header { 344 __le16 host_tag; 345 u8 ioc_use_only02; 346 u8 function; 347 __le16 ioc_use_only04; 348 u8 ioc_use_only06; 349 u8 msg_flags; 350 __le16 change_count; 351 __le16 function_dependent; 352 }; 353 354 struct mpi3_default_reply { 355 __le16 host_tag; 356 u8 ioc_use_only02; 357 u8 function; 358 __le16 ioc_use_only04; 359 u8 ioc_use_only06; 360 u8 msg_flags; 361 __le16 ioc_use_only08; 362 __le16 ioc_status; 363 __le32 ioc_log_info; 364 }; 365 366 #define MPI3_HOST_TAG_INVALID (0xffff) 367 #define MPI3_FUNCTION_IOC_FACTS (0x01) 368 #define MPI3_FUNCTION_IOC_INIT (0x02) 369 #define MPI3_FUNCTION_PORT_ENABLE (0x03) 370 #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) 371 #define MPI3_FUNCTION_EVENT_ACK (0x05) 372 #define MPI3_FUNCTION_CI_DOWNLOAD (0x06) 373 #define MPI3_FUNCTION_CI_UPLOAD (0x07) 374 #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) 375 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) 376 #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0a) 377 #define MPI3_FUNCTION_CONFIG (0x10) 378 #define MPI3_FUNCTION_SCSI_IO (0x20) 379 #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) 380 #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) 381 #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) 382 #define MPI3_FUNCTION_TARGET_ASSIST (0x30) 383 #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) 384 #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) 385 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) 386 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) 387 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) 388 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) 389 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) 390 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) 391 #define MPI3_FUNCTION_TOOLBOX (0x80) 392 #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) 393 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) 394 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) 395 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xc0) 396 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xef) 397 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xf0) 398 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xff) 399 #define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000) 400 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) 401 #define MPI3_IOCSTATUS_STATUS_MASK (0x7fff) 402 #define MPI3_IOCSTATUS_SUCCESS (0x0000) 403 #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) 404 #define MPI3_IOCSTATUS_BUSY (0x0002) 405 #define MPI3_IOCSTATUS_INVALID_SGL (0x0003) 406 #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) 407 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 408 #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) 409 #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) 410 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a) 411 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b) 412 #define MPI3_IOCSTATUS_FAILURE (0x001f) 413 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 414 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 415 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 416 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 417 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 418 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 419 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 420 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) 421 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 422 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 423 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 424 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 425 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 426 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 427 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 428 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 429 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 430 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 431 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 432 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 433 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 434 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 435 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 436 #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) 437 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 438 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 439 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 440 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 441 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 442 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 443 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 444 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 445 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 446 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 447 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 448 #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0) 449 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1) 450 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2) 451 #define MPI3_IOCSTATUS_CI_UPDATE_PENDING (0x00b3) 452 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0) 453 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00) 454 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01) 455 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02) 456 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0f03) 457 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0f04) 458 #define MPI3_IOCLOGINFO_TYPE_MASK (0xf0000000) 459 #define MPI3_IOCLOGINFO_TYPE_SHIFT (28) 460 #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) 461 #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) 462 #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0fffffff) 463 #endif 464