1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2021 Broadcom Inc. All rights reserved. 4 * 5 */ 6 #ifndef MPI30_IOC_H 7 #define MPI30_IOC_H 1 8 struct mpi3_ioc_init_request { 9 __le16 host_tag; 10 u8 ioc_use_only02; 11 u8 function; 12 __le16 ioc_use_only04; 13 u8 ioc_use_only06; 14 u8 msg_flags; 15 __le16 change_count; 16 __le16 reserved0a; 17 union mpi3_version_union mpi_version; 18 __le64 time_stamp; 19 u8 reserved18; 20 u8 who_init; 21 __le16 reserved1a; 22 __le16 reply_free_queue_depth; 23 __le16 reserved1e; 24 __le64 reply_free_queue_address; 25 __le32 reserved28; 26 __le16 sense_buffer_free_queue_depth; 27 __le16 sense_buffer_length; 28 __le64 sense_buffer_free_queue_address; 29 __le64 driver_information_address; 30 }; 31 32 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 33 #define MPI3_WHOINIT_ROM_BIOS (0x02) 34 #define MPI3_WHOINIT_HOST_DRIVER (0x03) 35 #define MPI3_WHOINIT_MANUFACTURER (0x04) 36 struct mpi3_driver_info_layout { 37 __le32 information_length; 38 u8 driver_signature[12]; 39 u8 os_name[16]; 40 u8 os_version[12]; 41 u8 driver_name[20]; 42 u8 driver_version[32]; 43 u8 driver_release_date[20]; 44 __le32 driver_capabilities; 45 }; 46 47 struct mpi3_ioc_facts_request { 48 __le16 host_tag; 49 u8 ioc_use_only02; 50 u8 function; 51 __le16 ioc_use_only04; 52 u8 ioc_use_only06; 53 u8 msg_flags; 54 __le16 change_count; 55 __le16 reserved0a; 56 __le32 reserved0c; 57 union mpi3_sge_union sgl; 58 }; 59 60 struct mpi3_ioc_facts_data { 61 __le16 ioc_facts_data_length; 62 __le16 reserved02; 63 union mpi3_version_union mpi_version; 64 struct mpi3_comp_image_version fw_version; 65 __le32 ioc_capabilities; 66 u8 ioc_number; 67 u8 who_init; 68 __le16 max_msix_vectors; 69 __le16 max_outstanding_request; 70 __le16 product_id; 71 __le16 ioc_request_frame_size; 72 __le16 reply_frame_size; 73 __le16 ioc_exceptions; 74 __le16 max_persistent_id; 75 u8 sge_modifier_mask; 76 u8 sge_modifier_value; 77 u8 sge_modifier_shift; 78 u8 protocol_flags; 79 __le16 max_sas_initiators; 80 __le16 max_sas_targets; 81 __le16 max_sas_expanders; 82 __le16 max_enclosures; 83 __le16 min_dev_handle; 84 __le16 max_dev_handle; 85 __le16 max_pc_ie_switches; 86 __le16 max_nvme; 87 __le16 max_pds; 88 __le16 max_vds; 89 __le16 max_host_pds; 90 __le16 max_advanced_host_pds; 91 __le16 max_raid_pds; 92 __le16 max_posted_cmd_buffers; 93 __le32 flags; 94 __le16 max_operational_request_queues; 95 __le16 max_operational_reply_queues; 96 __le16 shutdown_timeout; 97 __le16 reserved4e; 98 __le32 diag_trace_size; 99 __le32 diag_fw_size; 100 }; 101 102 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD (0x00000010) 103 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) 104 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_GRAN_MASK (0x00000001) 105 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_IOC_GRAN (0x00000000) 106 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_REPLY_Q_GRAN (0x00000001) 107 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 108 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 109 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 110 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 111 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 112 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 113 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 114 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 115 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 116 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_RAID (0x0100) 117 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0200) 118 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_RAID (0x0300) 119 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0400) 120 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 121 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 122 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 123 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 124 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 125 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 126 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 127 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 128 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 129 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 130 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 131 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 132 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 133 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 134 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 135 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 136 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 137 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 138 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 139 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 140 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 141 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 142 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 143 struct mpi3_mgmt_passthrough_request { 144 __le16 host_tag; 145 u8 ioc_use_only02; 146 u8 function; 147 __le16 ioc_use_only04; 148 u8 ioc_use_only06; 149 u8 msg_flags; 150 __le16 change_count; 151 __le16 reserved0a; 152 __le32 reserved0c[5]; 153 union mpi3_sge_union command_sgl; 154 union mpi3_sge_union response_sgl; 155 }; 156 157 struct mpi3_create_request_queue_request { 158 __le16 host_tag; 159 u8 ioc_use_only02; 160 u8 function; 161 __le16 ioc_use_only04; 162 u8 ioc_use_only06; 163 u8 msg_flags; 164 __le16 change_count; 165 u8 flags; 166 u8 burst; 167 __le16 size; 168 __le16 queue_id; 169 __le16 reply_queue_id; 170 __le16 reserved12; 171 __le32 reserved14; 172 __le64 base_address; 173 }; 174 175 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 176 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 177 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 178 struct mpi3_delete_request_queue_request { 179 __le16 host_tag; 180 u8 ioc_use_only02; 181 u8 function; 182 __le16 ioc_use_only04; 183 u8 ioc_use_only06; 184 u8 msg_flags; 185 __le16 change_count; 186 __le16 queue_id; 187 }; 188 189 struct mpi3_create_reply_queue_request { 190 __le16 host_tag; 191 u8 ioc_use_only02; 192 u8 function; 193 __le16 ioc_use_only04; 194 u8 ioc_use_only06; 195 u8 msg_flags; 196 __le16 change_count; 197 u8 flags; 198 u8 reserved0b; 199 __le16 size; 200 __le16 queue_id; 201 __le16 msix_index; 202 __le16 reserved12; 203 __le32 reserved14; 204 __le64 base_address; 205 }; 206 207 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 208 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 209 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 210 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 211 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 212 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 213 struct mpi3_delete_reply_queue_request { 214 __le16 host_tag; 215 u8 ioc_use_only02; 216 u8 function; 217 __le16 ioc_use_only04; 218 u8 ioc_use_only06; 219 u8 msg_flags; 220 __le16 change_count; 221 __le16 queue_id; 222 }; 223 224 struct mpi3_port_enable_request { 225 __le16 host_tag; 226 u8 ioc_use_only02; 227 u8 function; 228 __le16 ioc_use_only04; 229 u8 ioc_use_only06; 230 u8 msg_flags; 231 __le16 change_count; 232 __le16 reserved0a; 233 }; 234 235 #define MPI3_EVENT_LOG_DATA (0x01) 236 #define MPI3_EVENT_CHANGE (0x02) 237 #define MPI3_EVENT_GPIO_INTERRUPT (0x04) 238 #define MPI3_EVENT_TEMP_THRESHOLD (0x05) 239 #define MPI3_EVENT_CABLE_MGMT (0x06) 240 #define MPI3_EVENT_DEVICE_ADDED (0x07) 241 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 242 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 243 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 244 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 245 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 246 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 247 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 248 #define MPI3_EVENT_SAS_DISCOVERY (0x11) 249 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 250 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 251 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 252 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 253 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 254 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 255 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 256 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 257 #define MPI3_EVENT_PCIE_ENUMERATION (0x22) 258 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 259 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 260 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 261 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 262 struct mpi3_event_notification_request { 263 __le16 host_tag; 264 u8 ioc_use_only02; 265 u8 function; 266 __le16 ioc_use_only04; 267 u8 ioc_use_only06; 268 u8 msg_flags; 269 __le16 change_count; 270 __le16 reserved0a; 271 __le16 sas_broadcast_primitive_masks; 272 __le16 sas_notify_primitive_masks; 273 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 274 }; 275 276 struct mpi3_event_notification_reply { 277 __le16 host_tag; 278 u8 ioc_use_only02; 279 u8 function; 280 __le16 ioc_use_only04; 281 u8 ioc_use_only06; 282 u8 msg_flags; 283 __le16 ioc_use_only08; 284 __le16 ioc_status; 285 __le32 ioc_log_info; 286 u8 event_data_length; 287 u8 event; 288 __le16 ioc_change_count; 289 __le32 event_context; 290 __le32 event_data[1]; 291 }; 292 293 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 294 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 295 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 296 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 297 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 298 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 299 struct mpi3_event_data_gpio_interrupt { 300 u8 gpio_num; 301 u8 reserved01[3]; 302 }; 303 304 struct mpi3_event_data_temp_threshold { 305 __le16 status; 306 u8 sensor_num; 307 u8 reserved03; 308 __le16 current_temperature; 309 __le16 reserved06; 310 __le32 reserved08; 311 __le32 reserved0c; 312 }; 313 314 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD3_EXCEEDED (0x0008) 315 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD2_EXCEEDED (0x0004) 316 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD1_EXCEEDED (0x0002) 317 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD0_EXCEEDED (0x0001) 318 struct mpi3_event_data_cable_management { 319 __le32 active_cable_power_requirement; 320 u8 status; 321 u8 receptacle_id; 322 __le16 reserved06; 323 }; 324 325 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 326 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 327 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 328 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 329 struct mpi3_event_ack_request { 330 __le16 host_tag; 331 u8 ioc_use_only02; 332 u8 function; 333 __le16 ioc_use_only04; 334 u8 ioc_use_only06; 335 u8 msg_flags; 336 __le16 change_count; 337 __le16 reserved0a; 338 u8 event; 339 u8 reserved0d[3]; 340 __le32 event_context; 341 }; 342 343 struct mpi3_event_data_prepare_for_reset { 344 u8 reason_code; 345 u8 reserved01; 346 __le16 reserved02; 347 }; 348 349 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 350 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 351 struct mpi3_event_data_comp_image_activation { 352 __le32 reserved00; 353 }; 354 355 struct mpi3_event_data_device_status_change { 356 __le16 task_tag; 357 u8 reason_code; 358 u8 io_unit_port; 359 __le16 parent_dev_handle; 360 __le16 dev_handle; 361 __le64 wwid; 362 u8 lun[8]; 363 }; 364 365 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 366 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 367 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 368 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 369 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 370 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 371 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 372 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 373 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 374 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 375 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 376 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 377 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 378 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 379 struct mpi3_event_data_energy_pack_change { 380 __le32 reserved00; 381 __le16 shutdown_timeout; 382 __le16 reserved06; 383 }; 384 385 struct mpi3_event_data_sas_discovery { 386 u8 flags; 387 u8 reason_code; 388 u8 io_unit_port; 389 u8 reserved03; 390 __le32 discovery_status; 391 }; 392 393 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 394 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 395 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 396 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 397 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 398 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 399 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 400 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 401 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 402 #define MPI3_SAS_DISC_STATUS_SLOT_COUNT_MISMATCH (0x00002000) 403 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 404 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 405 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 406 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 407 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 408 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 409 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 410 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 411 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 412 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 413 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 414 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 415 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 416 struct mpi3_event_data_sas_broadcast_primitive { 417 u8 phy_num; 418 u8 io_unit_port; 419 u8 port_width; 420 u8 primitive; 421 }; 422 423 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 424 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 425 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 426 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 427 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 428 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 429 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 430 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 431 struct mpi3_event_data_sas_notify_primitive { 432 u8 phy_num; 433 u8 io_unit_port; 434 u8 reserved02; 435 u8 primitive; 436 }; 437 438 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 439 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 440 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 441 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 442 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT 443 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1) 444 #endif 445 struct mpi3_event_sas_topo_phy_entry { 446 __le16 attached_dev_handle; 447 u8 link_rate; 448 u8 status; 449 }; 450 451 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 452 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 453 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 454 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 455 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 456 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 457 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 458 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 459 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 460 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 461 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 462 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 463 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 464 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 465 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 466 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 467 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 468 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 469 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 470 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 471 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 472 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 473 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 474 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 475 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 476 struct mpi3_event_data_sas_topology_change_list { 477 __le16 enclosure_handle; 478 __le16 expander_dev_handle; 479 u8 num_phys; 480 u8 reserved05[3]; 481 u8 num_entries; 482 u8 start_phy_num; 483 u8 exp_status; 484 u8 io_unit_port; 485 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT]; 486 }; 487 488 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 489 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 490 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 491 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 492 struct mpi3_event_data_sas_phy_counter { 493 __le64 time_stamp; 494 __le32 reserved08; 495 u8 phy_event_code; 496 u8 phy_num; 497 __le16 reserved0e; 498 __le32 phy_event_info; 499 u8 counter_type; 500 u8 threshold_window; 501 u8 time_units; 502 u8 reserved17; 503 __le32 event_threshold; 504 __le16 threshold_flags; 505 __le16 reserved1e; 506 }; 507 508 struct mpi3_event_data_sas_device_disc_err { 509 __le16 dev_handle; 510 u8 reason_code; 511 u8 io_unit_port; 512 __le32 reserved04; 513 __le64 sas_address; 514 }; 515 516 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 517 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 518 struct mpi3_event_data_pcie_enumeration { 519 u8 flags; 520 u8 reason_code; 521 u8 io_unit_port; 522 u8 reserved03; 523 __le32 enumeration_status; 524 }; 525 526 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 527 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 528 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 529 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 530 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 531 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 532 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 533 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 534 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT 535 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1) 536 #endif 537 struct mpi3_event_pcie_topo_port_entry { 538 __le16 attached_dev_handle; 539 u8 port_status; 540 u8 reserved03; 541 u8 current_port_info; 542 u8 reserved05; 543 u8 previous_port_info; 544 u8 reserved07; 545 }; 546 547 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 548 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 549 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 550 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 551 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 552 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 553 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 554 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 555 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 556 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 557 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 558 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 559 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 560 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 561 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 562 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 563 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 564 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 565 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 566 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 567 struct mpi3_event_data_pcie_topology_change_list { 568 __le16 enclosure_handle; 569 __le16 switch_dev_handle; 570 u8 num_ports; 571 u8 reserved05[3]; 572 u8 num_entries; 573 u8 start_port_num; 574 u8 switch_status; 575 u8 io_unit_port; 576 __le32 reserved0c; 577 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT]; 578 }; 579 580 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 581 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 582 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 583 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 584 struct mpi3_event_data_sas_init_dev_status_change { 585 u8 reason_code; 586 u8 io_unit_port; 587 __le16 dev_handle; 588 __le32 reserved04; 589 __le64 sas_address; 590 }; 591 592 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 593 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 594 struct mpi3_event_data_sas_init_table_overflow { 595 __le16 max_init; 596 __le16 current_init; 597 __le32 reserved04; 598 __le64 sas_address; 599 }; 600 601 struct mpi3_event_data_hard_reset_received { 602 u8 reserved00; 603 u8 io_unit_port; 604 __le16 reserved02; 605 }; 606 607 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 608 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 609 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 610 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 611 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 612 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 613 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 614 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 615 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 616 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 617 #define MPI3_PEL_CLASS_DEBUG (0x00) 618 #define MPI3_PEL_CLASS_PROGRESS (0x01) 619 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 620 #define MPI3_PEL_CLASS_WARNING (0x03) 621 #define MPI3_PEL_CLASS_CRITICAL (0x04) 622 #define MPI3_PEL_CLASS_FATAL (0x05) 623 #define MPI3_PEL_CLASS_FAULT (0x06) 624 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 625 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 626 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 627 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 628 #define MPI3_PEL_ACTION_GET_LOG (0x03) 629 #define MPI3_PEL_ACTION_GET_COUNT (0x04) 630 #define MPI3_PEL_ACTION_WAIT (0x05) 631 #define MPI3_PEL_ACTION_ABORT (0x06) 632 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 633 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 634 #define MPI3_PEL_STATUS_SUCCESS (0x00) 635 #define MPI3_PEL_STATUS_NOT_FOUND (0x01) 636 #define MPI3_PEL_STATUS_ABORTED (0x02) 637 #define MPI3_PEL_STATUS_NOT_READY (0x03) 638 struct mpi3_pel_seq { 639 __le32 newest; 640 __le32 oldest; 641 __le32 clear; 642 __le32 shutdown; 643 __le32 boot; 644 __le32 last_acknowledged; 645 }; 646 647 struct mpi3_pel_entry { 648 __le32 sequence_number; 649 __le32 time_stamp[2]; 650 __le16 log_code; 651 __le16 arg_type; 652 __le16 locale; 653 u8 class; 654 u8 reserved13; 655 u8 ext_num; 656 u8 num_exts; 657 u8 arg_data_size; 658 u8 fixed_format_size; 659 __le32 reserved18[2]; 660 __le32 pel_info[24]; 661 }; 662 663 struct mpi3_pel_list { 664 __le32 log_count; 665 __le32 reserved04; 666 struct mpi3_pel_entry entry[1]; 667 }; 668 669 struct mpi3_pel_arg_map { 670 u8 arg_type; 671 u8 length; 672 __le16 start_location; 673 }; 674 675 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 676 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 677 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 678 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 679 struct mpi3_pel_print_string { 680 __le16 log_code; 681 __le16 string_length; 682 u8 num_arg_map; 683 u8 reserved05[3]; 684 struct mpi3_pel_arg_map arg_map[1]; 685 }; 686 687 struct mpi3_pel_print_string_list { 688 __le32 num_print_strings; 689 __le32 residual_bytes_remain; 690 __le32 reserved08[2]; 691 struct mpi3_pel_print_string print_string[1]; 692 }; 693 694 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 695 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 696 #endif 697 struct mpi3_pel_request { 698 __le16 host_tag; 699 u8 ioc_use_only02; 700 u8 function; 701 __le16 ioc_use_only04; 702 u8 ioc_use_only06; 703 u8 msg_flags; 704 __le16 change_count; 705 u8 action; 706 u8 reserved0b; 707 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 708 }; 709 710 struct mpi3_pel_req_action_get_sequence_numbers { 711 __le16 host_tag; 712 u8 ioc_use_only02; 713 u8 function; 714 __le16 ioc_use_only04; 715 u8 ioc_use_only06; 716 u8 msg_flags; 717 __le16 change_count; 718 u8 action; 719 u8 reserved0b; 720 __le32 reserved0c[5]; 721 union mpi3_sge_union sgl; 722 }; 723 724 struct mpi3_pel_req_action_clear_log_marker { 725 __le16 host_tag; 726 u8 ioc_use_only02; 727 u8 function; 728 __le16 ioc_use_only04; 729 u8 ioc_use_only06; 730 u8 msg_flags; 731 __le16 change_count; 732 u8 action; 733 u8 reserved0b; 734 u8 clear_type; 735 u8 reserved0d[3]; 736 }; 737 738 struct mpi3_pel_req_action_get_log { 739 __le16 host_tag; 740 u8 ioc_use_only02; 741 u8 function; 742 __le16 ioc_use_only04; 743 u8 ioc_use_only06; 744 u8 msg_flags; 745 __le16 change_count; 746 u8 action; 747 u8 reserved0b; 748 __le32 starting_sequence_number; 749 __le16 locale; 750 u8 class; 751 u8 reserved13; 752 __le32 reserved14[3]; 753 union mpi3_sge_union sgl; 754 }; 755 756 struct mpi3_pel_req_action_get_count { 757 __le16 host_tag; 758 u8 ioc_use_only02; 759 u8 function; 760 __le16 ioc_use_only04; 761 u8 ioc_use_only06; 762 u8 msg_flags; 763 __le16 change_count; 764 u8 action; 765 u8 reserved0b; 766 __le32 starting_sequence_number; 767 __le16 locale; 768 u8 class; 769 u8 reserved13; 770 __le32 reserved14[3]; 771 union mpi3_sge_union sgl; 772 }; 773 774 struct mpi3_pel_req_action_wait { 775 __le16 host_tag; 776 u8 ioc_use_only02; 777 u8 function; 778 __le16 ioc_use_only04; 779 u8 ioc_use_only06; 780 u8 msg_flags; 781 __le16 change_count; 782 u8 action; 783 u8 reserved0b; 784 __le32 starting_sequence_number; 785 __le16 locale; 786 u8 class; 787 u8 reserved13; 788 __le16 wait_time; 789 __le16 reserved16; 790 __le32 reserved18[2]; 791 }; 792 793 struct mpi3_pel_req_action_abort { 794 __le16 host_tag; 795 u8 ioc_use_only02; 796 u8 function; 797 __le16 ioc_use_only04; 798 u8 ioc_use_only06; 799 u8 msg_flags; 800 __le16 change_count; 801 u8 action; 802 u8 reserved0b; 803 __le32 reserved0c; 804 __le16 abort_host_tag; 805 __le16 reserved12; 806 __le32 reserved14; 807 }; 808 809 struct mpi3_pel_req_action_get_print_strings { 810 __le16 host_tag; 811 u8 ioc_use_only02; 812 u8 function; 813 __le16 ioc_use_only04; 814 u8 ioc_use_only06; 815 u8 msg_flags; 816 __le16 change_count; 817 u8 action; 818 u8 reserved0b; 819 __le32 reserved0c; 820 __le16 start_log_code; 821 __le16 reserved12; 822 __le32 reserved14[3]; 823 union mpi3_sge_union sgl; 824 }; 825 826 struct mpi3_pel_req_action_acknowledge { 827 __le16 host_tag; 828 u8 ioc_use_only02; 829 u8 function; 830 __le16 ioc_use_only04; 831 u8 ioc_use_only06; 832 u8 msg_flags; 833 __le16 change_count; 834 u8 action; 835 u8 reserved0b; 836 __le32 sequence_number; 837 __le32 reserved10; 838 }; 839 840 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT (0x01) 841 struct mpi3_pel_reply { 842 __le16 host_tag; 843 u8 ioc_use_only02; 844 u8 function; 845 __le16 ioc_use_only04; 846 u8 ioc_use_only06; 847 u8 msg_flags; 848 __le16 ioc_use_only08; 849 __le16 ioc_status; 850 __le32 ioc_log_info; 851 u8 action; 852 u8 reserved11; 853 __le16 reserved12; 854 __le16 pe_log_status; 855 __le16 reserved16; 856 __le32 transfer_length; 857 }; 858 859 struct mpi3_ci_download_request { 860 __le16 host_tag; 861 u8 ioc_use_only02; 862 u8 function; 863 __le16 ioc_use_only04; 864 u8 ioc_use_only06; 865 u8 msg_flags; 866 __le16 change_count; 867 u8 action; 868 u8 reserved0b; 869 __le32 signature1; 870 __le32 total_image_size; 871 __le32 image_offset; 872 __le32 segment_size; 873 __le32 reserved1c; 874 union mpi3_sge_union sgl; 875 }; 876 877 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 878 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 879 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 880 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 881 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 882 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 883 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 884 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 885 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 886 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 887 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 888 struct mpi3_ci_download_reply { 889 __le16 host_tag; 890 u8 ioc_use_only02; 891 u8 function; 892 __le16 ioc_use_only04; 893 u8 ioc_use_only06; 894 u8 msg_flags; 895 __le16 ioc_use_only08; 896 __le16 ioc_status; 897 __le32 ioc_log_info; 898 u8 flags; 899 u8 cache_dirty; 900 u8 pending_count; 901 u8 reserved13; 902 }; 903 904 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 905 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 906 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 907 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 908 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 909 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 910 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 911 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 912 struct mpi3_ci_upload_request { 913 __le16 host_tag; 914 u8 ioc_use_only02; 915 u8 function; 916 __le16 ioc_use_only04; 917 u8 ioc_use_only06; 918 u8 msg_flags; 919 __le16 change_count; 920 __le16 reserved0a; 921 __le32 signature1; 922 __le32 reserved10; 923 __le32 image_offset; 924 __le32 segment_size; 925 __le32 reserved1c; 926 union mpi3_sge_union sgl; 927 }; 928 929 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 930 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 931 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 932 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 933 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 934 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 935 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 936 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 937 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 938 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 939 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 940 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 941 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 942 #define MPI3_CTRL_OP_SAS_SEND_PRIMITIVE (0x20) 943 #define MPI3_CTRL_OP_SAS_CLEAR_ERROR_LOG (0x21) 944 #define MPI3_CTRL_OP_PCIE_CLEAR_ERROR_LOG (0x22) 945 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 946 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 947 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 948 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 949 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 950 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PHY_INDEX (0x00) 951 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 952 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 953 #define MPI3_CTRL_OP_SAS_CLEAR_ERR_LOG_PARAM8_PHY_INDEX (0x00) 954 #define MPI3_CTRL_OP_PCIE_CLEAR_ERR_LOG_PARAM8_PHY_INDEX (0x00) 955 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 956 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 957 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 958 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 959 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 960 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 961 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 962 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 963 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 964 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 965 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 966 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 967 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 968 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 969 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 970 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 971 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 972 struct mpi3_iounit_control_request { 973 __le16 host_tag; 974 u8 ioc_use_only02; 975 u8 function; 976 __le16 ioc_use_only04; 977 u8 ioc_use_only06; 978 u8 msg_flags; 979 __le16 change_count; 980 u8 reserved0a; 981 u8 operation; 982 __le32 reserved0c; 983 __le64 param64[2]; 984 __le32 param32[4]; 985 __le16 param16[4]; 986 u8 param8[8]; 987 }; 988 989 struct mpi3_iounit_control_reply { 990 __le16 host_tag; 991 u8 ioc_use_only02; 992 u8 function; 993 __le16 ioc_use_only04; 994 u8 ioc_use_only06; 995 u8 msg_flags; 996 __le16 ioc_use_only08; 997 __le16 ioc_status; 998 __le32 ioc_log_info; 999 __le64 value64[2]; 1000 __le32 value32[4]; 1001 __le16 value16[4]; 1002 u8 value8[8]; 1003 }; 1004 #endif 1005