1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2021 Broadcom Inc. All rights reserved. 4 * 5 */ 6 #ifndef MPI30_IOC_H 7 #define MPI30_IOC_H 1 8 struct mpi3_ioc_init_request { 9 __le16 host_tag; 10 u8 ioc_use_only02; 11 u8 function; 12 __le16 ioc_use_only04; 13 u8 ioc_use_only06; 14 u8 msg_flags; 15 __le16 change_count; 16 __le16 reserved0a; 17 union mpi3_version_union mpi_version; 18 __le64 time_stamp; 19 u8 reserved18; 20 u8 who_init; 21 __le16 reserved1a; 22 __le16 reply_free_queue_depth; 23 __le16 reserved1e; 24 __le64 reply_free_queue_address; 25 __le32 reserved28; 26 __le16 sense_buffer_free_queue_depth; 27 __le16 sense_buffer_length; 28 __le64 sense_buffer_free_queue_address; 29 __le64 driver_information_address; 30 }; 31 32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) 33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) 34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) 35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) 36 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) 37 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 38 #define MPI3_WHOINIT_ROM_BIOS (0x02) 39 #define MPI3_WHOINIT_HOST_DRIVER (0x03) 40 #define MPI3_WHOINIT_MANUFACTURER (0x04) 41 struct mpi3_driver_info_layout { 42 __le32 information_length; 43 u8 driver_signature[12]; 44 u8 os_name[16]; 45 u8 os_version[12]; 46 u8 driver_name[20]; 47 u8 driver_version[32]; 48 u8 driver_release_date[20]; 49 __le32 driver_capabilities; 50 }; 51 52 struct mpi3_ioc_facts_request { 53 __le16 host_tag; 54 u8 ioc_use_only02; 55 u8 function; 56 __le16 ioc_use_only04; 57 u8 ioc_use_only06; 58 u8 msg_flags; 59 __le16 change_count; 60 __le16 reserved0a; 61 __le32 reserved0c; 62 union mpi3_sge_union sgl; 63 }; 64 65 struct mpi3_ioc_facts_data { 66 __le16 ioc_facts_data_length; 67 __le16 reserved02; 68 union mpi3_version_union mpi_version; 69 struct mpi3_comp_image_version fw_version; 70 __le32 ioc_capabilities; 71 u8 ioc_number; 72 u8 who_init; 73 __le16 max_msix_vectors; 74 __le16 max_outstanding_request; 75 __le16 product_id; 76 __le16 ioc_request_frame_size; 77 __le16 reply_frame_size; 78 __le16 ioc_exceptions; 79 __le16 max_persistent_id; 80 u8 sge_modifier_mask; 81 u8 sge_modifier_value; 82 u8 sge_modifier_shift; 83 u8 protocol_flags; 84 __le16 max_sas_initiators; 85 __le16 reserved2a; 86 __le16 max_sas_expanders; 87 __le16 max_enclosures; 88 __le16 min_dev_handle; 89 __le16 max_dev_handle; 90 __le16 max_pcie_switches; 91 __le16 max_nvme; 92 __le16 reserved38; 93 __le16 max_vds; 94 __le16 max_host_pds; 95 __le16 max_adv_host_pds; 96 __le16 max_raid_pds; 97 __le16 max_posted_cmd_buffers; 98 __le32 flags; 99 __le16 max_operational_request_queues; 100 __le16 max_operational_reply_queues; 101 __le16 shutdown_timeout; 102 __le16 reserved4e; 103 __le32 diag_trace_size; 104 __le32 diag_fw_size; 105 __le32 diag_driver_size; 106 u8 max_host_pd_ns_count; 107 u8 max_adv_host_pd_ns_count; 108 u8 max_raidpd_ns_count; 109 u8 reserved5f; 110 }; 111 112 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) 113 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) 114 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x10000000) 115 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100) 116 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080) 117 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040) 118 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020) 119 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010) 120 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) 121 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002) 122 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) 123 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 124 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 125 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 126 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 127 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 128 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 129 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) 130 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) 131 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 132 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 133 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 134 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) 135 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) 136 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) 137 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) 138 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) 139 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) 140 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 141 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 142 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 143 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 144 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 145 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 146 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 147 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 148 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 149 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 150 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 151 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 152 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 153 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 154 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 155 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 156 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 157 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 158 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 159 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 160 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 161 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 162 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 163 struct mpi3_mgmt_passthrough_request { 164 __le16 host_tag; 165 u8 ioc_use_only02; 166 u8 function; 167 __le16 ioc_use_only04; 168 u8 ioc_use_only06; 169 u8 msg_flags; 170 __le16 change_count; 171 __le16 reserved0a; 172 __le32 reserved0c[5]; 173 union mpi3_sge_union command_sgl; 174 union mpi3_sge_union response_sgl; 175 }; 176 177 struct mpi3_create_request_queue_request { 178 __le16 host_tag; 179 u8 ioc_use_only02; 180 u8 function; 181 __le16 ioc_use_only04; 182 u8 ioc_use_only06; 183 u8 msg_flags; 184 __le16 change_count; 185 u8 flags; 186 u8 burst; 187 __le16 size; 188 __le16 queue_id; 189 __le16 reply_queue_id; 190 __le16 reserved12; 191 __le32 reserved14; 192 __le64 base_address; 193 }; 194 195 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 196 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 197 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 198 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) 199 struct mpi3_delete_request_queue_request { 200 __le16 host_tag; 201 u8 ioc_use_only02; 202 u8 function; 203 __le16 ioc_use_only04; 204 u8 ioc_use_only06; 205 u8 msg_flags; 206 __le16 change_count; 207 __le16 queue_id; 208 }; 209 210 struct mpi3_create_reply_queue_request { 211 __le16 host_tag; 212 u8 ioc_use_only02; 213 u8 function; 214 __le16 ioc_use_only04; 215 u8 ioc_use_only06; 216 u8 msg_flags; 217 __le16 change_count; 218 u8 flags; 219 u8 reserved0b; 220 __le16 size; 221 __le16 queue_id; 222 __le16 msix_index; 223 __le16 reserved12; 224 __le32 reserved14; 225 __le64 base_address; 226 }; 227 228 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 229 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 230 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 231 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 232 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 233 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 234 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) 235 struct mpi3_delete_reply_queue_request { 236 __le16 host_tag; 237 u8 ioc_use_only02; 238 u8 function; 239 __le16 ioc_use_only04; 240 u8 ioc_use_only06; 241 u8 msg_flags; 242 __le16 change_count; 243 __le16 queue_id; 244 }; 245 246 struct mpi3_port_enable_request { 247 __le16 host_tag; 248 u8 ioc_use_only02; 249 u8 function; 250 __le16 ioc_use_only04; 251 u8 ioc_use_only06; 252 u8 msg_flags; 253 __le16 change_count; 254 __le16 reserved0a; 255 }; 256 257 #define MPI3_EVENT_LOG_DATA (0x01) 258 #define MPI3_EVENT_CHANGE (0x02) 259 #define MPI3_EVENT_GPIO_INTERRUPT (0x04) 260 #define MPI3_EVENT_TEMP_THRESHOLD (0x05) 261 #define MPI3_EVENT_CABLE_MGMT (0x06) 262 #define MPI3_EVENT_DEVICE_ADDED (0x07) 263 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 264 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 265 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 266 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 267 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 268 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 269 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 270 #define MPI3_EVENT_SAS_DISCOVERY (0x11) 271 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 272 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 273 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 274 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 275 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 276 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 277 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 278 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 279 #define MPI3_EVENT_PCIE_ENUMERATION (0x22) 280 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) 281 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 282 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) 283 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 284 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 285 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 286 struct mpi3_event_notification_request { 287 __le16 host_tag; 288 u8 ioc_use_only02; 289 u8 function; 290 __le16 ioc_use_only04; 291 u8 ioc_use_only06; 292 u8 msg_flags; 293 __le16 change_count; 294 __le16 reserved0a; 295 __le16 sas_broadcast_primitive_masks; 296 __le16 sas_notify_primitive_masks; 297 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 298 }; 299 300 struct mpi3_event_notification_reply { 301 __le16 host_tag; 302 u8 ioc_use_only02; 303 u8 function; 304 __le16 ioc_use_only04; 305 u8 ioc_use_only06; 306 u8 msg_flags; 307 __le16 ioc_use_only08; 308 __le16 ioc_status; 309 __le32 ioc_log_info; 310 u8 event_data_length; 311 u8 event; 312 __le16 ioc_change_count; 313 __le32 event_context; 314 __le32 event_data[1]; 315 }; 316 317 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 318 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 319 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 320 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 321 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 322 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 323 struct mpi3_event_data_gpio_interrupt { 324 u8 gpio_num; 325 u8 reserved01[3]; 326 }; 327 328 struct mpi3_event_data_temp_threshold { 329 __le16 status; 330 u8 sensor_num; 331 u8 reserved03; 332 __le16 current_temperature; 333 __le16 reserved06; 334 __le32 reserved08; 335 __le32 reserved0c; 336 }; 337 338 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_FATAL_THRESHOLD_EXCEEDED (0x0004) 339 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_CRITICAL_THRESHOLD_EXCEEDED (0x0002) 340 #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_WARNING_THRESHOLD_EXCEEDED (0x0001) 341 struct mpi3_event_data_cable_management { 342 __le32 active_cable_power_requirement; 343 u8 status; 344 u8 receptacle_id; 345 __le16 reserved06; 346 }; 347 348 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 349 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 350 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 351 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 352 struct mpi3_event_ack_request { 353 __le16 host_tag; 354 u8 ioc_use_only02; 355 u8 function; 356 __le16 ioc_use_only04; 357 u8 ioc_use_only06; 358 u8 msg_flags; 359 __le16 change_count; 360 __le16 reserved0a; 361 u8 event; 362 u8 reserved0d[3]; 363 __le32 event_context; 364 }; 365 366 struct mpi3_event_data_prepare_for_reset { 367 u8 reason_code; 368 u8 reserved01; 369 __le16 reserved02; 370 }; 371 372 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 373 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 374 struct mpi3_event_data_comp_image_activation { 375 __le32 reserved00; 376 }; 377 378 struct mpi3_event_data_device_status_change { 379 __le16 task_tag; 380 u8 reason_code; 381 u8 io_unit_port; 382 __le16 parent_dev_handle; 383 __le16 dev_handle; 384 __le64 wwid; 385 u8 lun[8]; 386 }; 387 388 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 389 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 390 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 391 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 392 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 393 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 394 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 395 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 396 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 397 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 398 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 399 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 400 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 401 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 402 struct mpi3_event_data_energy_pack_change { 403 __le32 reserved00; 404 __le16 shutdown_timeout; 405 __le16 reserved06; 406 }; 407 408 struct mpi3_event_data_sas_discovery { 409 u8 flags; 410 u8 reason_code; 411 u8 io_unit_port; 412 u8 reserved03; 413 __le32 discovery_status; 414 }; 415 416 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 417 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 418 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 419 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 420 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 421 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 422 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 423 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 424 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) 425 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) 426 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 427 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) 428 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 429 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 430 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 431 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 432 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 433 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 434 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 435 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 436 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 437 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 438 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 439 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 440 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 441 struct mpi3_event_data_sas_broadcast_primitive { 442 u8 phy_num; 443 u8 io_unit_port; 444 u8 port_width; 445 u8 primitive; 446 }; 447 448 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 449 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 450 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 451 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 452 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 453 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 454 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 455 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 456 struct mpi3_event_data_sas_notify_primitive { 457 u8 phy_num; 458 u8 io_unit_port; 459 u8 reserved02; 460 u8 primitive; 461 }; 462 463 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 464 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 465 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 466 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 467 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT 468 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1) 469 #endif 470 struct mpi3_event_sas_topo_phy_entry { 471 __le16 attached_dev_handle; 472 u8 link_rate; 473 u8 status; 474 }; 475 476 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 477 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 478 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 479 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 480 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 481 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 482 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 483 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 484 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 485 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 486 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 487 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 488 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 489 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 490 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 491 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 492 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 493 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 494 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 495 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 496 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 497 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 498 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 499 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 500 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 501 struct mpi3_event_data_sas_topology_change_list { 502 __le16 enclosure_handle; 503 __le16 expander_dev_handle; 504 u8 num_phys; 505 u8 reserved05[3]; 506 u8 num_entries; 507 u8 start_phy_num; 508 u8 exp_status; 509 u8 io_unit_port; 510 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT]; 511 }; 512 513 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 514 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 515 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 516 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 517 struct mpi3_event_data_sas_phy_counter { 518 __le64 time_stamp; 519 __le32 reserved08; 520 u8 phy_event_code; 521 u8 phy_num; 522 __le16 reserved0e; 523 __le32 phy_event_info; 524 u8 counter_type; 525 u8 threshold_window; 526 u8 time_units; 527 u8 reserved17; 528 __le32 event_threshold; 529 __le16 threshold_flags; 530 __le16 reserved1e; 531 }; 532 533 struct mpi3_event_data_sas_device_disc_err { 534 __le16 dev_handle; 535 u8 reason_code; 536 u8 io_unit_port; 537 __le32 reserved04; 538 __le64 sas_address; 539 }; 540 541 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 542 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 543 struct mpi3_event_data_pcie_enumeration { 544 u8 flags; 545 u8 reason_code; 546 u8 io_unit_port; 547 u8 reserved03; 548 __le32 enumeration_status; 549 }; 550 551 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 552 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 553 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 554 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 555 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 556 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 557 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 558 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 559 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT 560 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1) 561 #endif 562 struct mpi3_event_pcie_topo_port_entry { 563 __le16 attached_dev_handle; 564 u8 port_status; 565 u8 reserved03; 566 u8 current_port_info; 567 u8 reserved05; 568 u8 previous_port_info; 569 u8 reserved07; 570 }; 571 572 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 573 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 574 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 575 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 576 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 577 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 578 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 579 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 580 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 581 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 582 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 583 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 584 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 585 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 586 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 587 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 588 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 589 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 590 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 591 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 592 struct mpi3_event_data_pcie_topology_change_list { 593 __le16 enclosure_handle; 594 __le16 switch_dev_handle; 595 u8 num_ports; 596 u8 reserved05[3]; 597 u8 num_entries; 598 u8 start_port_num; 599 u8 switch_status; 600 u8 io_unit_port; 601 __le32 reserved0c; 602 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT]; 603 }; 604 605 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 606 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 607 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 608 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 609 struct mpi3_event_data_pcie_error_threshold { 610 __le64 timestamp; 611 u8 reason_code; 612 u8 port; 613 __le16 switch_dev_handle; 614 u8 error; 615 u8 action; 616 __le16 threshold_count; 617 __le16 attached_dev_handle; 618 __le16 reserved12; 619 }; 620 621 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) 622 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) 623 struct mpi3_event_data_sas_init_dev_status_change { 624 u8 reason_code; 625 u8 io_unit_port; 626 __le16 dev_handle; 627 __le32 reserved04; 628 __le64 sas_address; 629 }; 630 631 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 632 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 633 struct mpi3_event_data_sas_init_table_overflow { 634 __le16 max_init; 635 __le16 current_init; 636 __le32 reserved04; 637 __le64 sas_address; 638 }; 639 640 struct mpi3_event_data_hard_reset_received { 641 u8 reserved00; 642 u8 io_unit_port; 643 __le16 reserved02; 644 }; 645 646 struct mpi3_event_data_diag_buffer_status_change { 647 u8 type; 648 u8 reason_code; 649 __le16 reserved02; 650 __le32 reserved04; 651 }; 652 653 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) 654 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) 655 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) 656 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 657 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 658 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 659 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 660 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 661 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 662 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 663 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 664 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 665 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 666 #define MPI3_PEL_CLASS_DEBUG (0x00) 667 #define MPI3_PEL_CLASS_PROGRESS (0x01) 668 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 669 #define MPI3_PEL_CLASS_WARNING (0x03) 670 #define MPI3_PEL_CLASS_CRITICAL (0x04) 671 #define MPI3_PEL_CLASS_FATAL (0x05) 672 #define MPI3_PEL_CLASS_FAULT (0x06) 673 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 674 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 675 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 676 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 677 #define MPI3_PEL_ACTION_GET_LOG (0x03) 678 #define MPI3_PEL_ACTION_GET_COUNT (0x04) 679 #define MPI3_PEL_ACTION_WAIT (0x05) 680 #define MPI3_PEL_ACTION_ABORT (0x06) 681 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 682 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 683 #define MPI3_PEL_STATUS_SUCCESS (0x00) 684 #define MPI3_PEL_STATUS_NOT_FOUND (0x01) 685 #define MPI3_PEL_STATUS_ABORTED (0x02) 686 #define MPI3_PEL_STATUS_NOT_READY (0x03) 687 struct mpi3_pel_seq { 688 __le32 newest; 689 __le32 oldest; 690 __le32 clear; 691 __le32 shutdown; 692 __le32 boot; 693 __le32 last_acknowledged; 694 }; 695 696 struct mpi3_pel_entry { 697 __le64 time_stamp; 698 __le32 sequence_number; 699 __le16 log_code; 700 __le16 arg_type; 701 __le16 locale; 702 u8 class; 703 u8 flags; 704 u8 ext_num; 705 u8 num_exts; 706 u8 arg_data_size; 707 u8 fixed_format_strings_size; 708 __le32 reserved18[2]; 709 __le32 pel_info[24]; 710 }; 711 712 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) 713 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) 714 struct mpi3_pel_list { 715 __le32 log_count; 716 __le32 reserved04; 717 struct mpi3_pel_entry entry[1]; 718 }; 719 720 struct mpi3_pel_arg_map { 721 u8 arg_type; 722 u8 length; 723 __le16 start_location; 724 }; 725 726 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 727 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 728 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 729 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 730 struct mpi3_pel_print_string { 731 __le16 log_code; 732 __le16 string_length; 733 u8 num_arg_map; 734 u8 reserved05[3]; 735 struct mpi3_pel_arg_map arg_map[1]; 736 }; 737 738 struct mpi3_pel_print_string_list { 739 __le32 num_print_strings; 740 __le32 residual_bytes_remain; 741 __le32 reserved08[2]; 742 struct mpi3_pel_print_string print_string[1]; 743 }; 744 745 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 746 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 747 #endif 748 struct mpi3_pel_request { 749 __le16 host_tag; 750 u8 ioc_use_only02; 751 u8 function; 752 __le16 ioc_use_only04; 753 u8 ioc_use_only06; 754 u8 msg_flags; 755 __le16 change_count; 756 u8 action; 757 u8 reserved0b; 758 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 759 }; 760 761 struct mpi3_pel_req_action_get_sequence_numbers { 762 __le16 host_tag; 763 u8 ioc_use_only02; 764 u8 function; 765 __le16 ioc_use_only04; 766 u8 ioc_use_only06; 767 u8 msg_flags; 768 __le16 change_count; 769 u8 action; 770 u8 reserved0b; 771 __le32 reserved0c[5]; 772 union mpi3_sge_union sgl; 773 }; 774 775 struct mpi3_pel_req_action_clear_log_marker { 776 __le16 host_tag; 777 u8 ioc_use_only02; 778 u8 function; 779 __le16 ioc_use_only04; 780 u8 ioc_use_only06; 781 u8 msg_flags; 782 __le16 change_count; 783 u8 action; 784 u8 reserved0b; 785 u8 clear_type; 786 u8 reserved0d[3]; 787 }; 788 789 struct mpi3_pel_req_action_get_log { 790 __le16 host_tag; 791 u8 ioc_use_only02; 792 u8 function; 793 __le16 ioc_use_only04; 794 u8 ioc_use_only06; 795 u8 msg_flags; 796 __le16 change_count; 797 u8 action; 798 u8 reserved0b; 799 __le32 starting_sequence_number; 800 __le16 locale; 801 u8 class; 802 u8 reserved13; 803 __le32 reserved14[3]; 804 union mpi3_sge_union sgl; 805 }; 806 807 struct mpi3_pel_req_action_get_count { 808 __le16 host_tag; 809 u8 ioc_use_only02; 810 u8 function; 811 __le16 ioc_use_only04; 812 u8 ioc_use_only06; 813 u8 msg_flags; 814 __le16 change_count; 815 u8 action; 816 u8 reserved0b; 817 __le32 starting_sequence_number; 818 __le16 locale; 819 u8 class; 820 u8 reserved13; 821 __le32 reserved14[3]; 822 union mpi3_sge_union sgl; 823 }; 824 825 struct mpi3_pel_req_action_wait { 826 __le16 host_tag; 827 u8 ioc_use_only02; 828 u8 function; 829 __le16 ioc_use_only04; 830 u8 ioc_use_only06; 831 u8 msg_flags; 832 __le16 change_count; 833 u8 action; 834 u8 reserved0b; 835 __le32 starting_sequence_number; 836 __le16 locale; 837 u8 class; 838 u8 reserved13; 839 __le16 wait_time; 840 __le16 reserved16; 841 __le32 reserved18[2]; 842 }; 843 844 struct mpi3_pel_req_action_abort { 845 __le16 host_tag; 846 u8 ioc_use_only02; 847 u8 function; 848 __le16 ioc_use_only04; 849 u8 ioc_use_only06; 850 u8 msg_flags; 851 __le16 change_count; 852 u8 action; 853 u8 reserved0b; 854 __le32 reserved0c; 855 __le16 abort_host_tag; 856 __le16 reserved12; 857 __le32 reserved14; 858 }; 859 860 struct mpi3_pel_req_action_get_print_strings { 861 __le16 host_tag; 862 u8 ioc_use_only02; 863 u8 function; 864 __le16 ioc_use_only04; 865 u8 ioc_use_only06; 866 u8 msg_flags; 867 __le16 change_count; 868 u8 action; 869 u8 reserved0b; 870 __le32 reserved0c; 871 __le16 start_log_code; 872 __le16 reserved12; 873 __le32 reserved14[3]; 874 union mpi3_sge_union sgl; 875 }; 876 877 struct mpi3_pel_req_action_acknowledge { 878 __le16 host_tag; 879 u8 ioc_use_only02; 880 u8 function; 881 __le16 ioc_use_only04; 882 u8 ioc_use_only06; 883 u8 msg_flags; 884 __le16 change_count; 885 u8 action; 886 u8 reserved0b; 887 __le32 sequence_number; 888 __le32 reserved10; 889 }; 890 891 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) 892 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) 893 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) 894 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) 895 struct mpi3_pel_reply { 896 __le16 host_tag; 897 u8 ioc_use_only02; 898 u8 function; 899 __le16 ioc_use_only04; 900 u8 ioc_use_only06; 901 u8 msg_flags; 902 __le16 ioc_use_only08; 903 __le16 ioc_status; 904 __le32 ioc_log_info; 905 u8 action; 906 u8 reserved11; 907 __le16 reserved12; 908 __le16 pe_log_status; 909 __le16 reserved16; 910 __le32 transfer_length; 911 }; 912 913 struct mpi3_ci_download_request { 914 __le16 host_tag; 915 u8 ioc_use_only02; 916 u8 function; 917 __le16 ioc_use_only04; 918 u8 ioc_use_only06; 919 u8 msg_flags; 920 __le16 change_count; 921 u8 action; 922 u8 reserved0b; 923 __le32 signature1; 924 __le32 total_image_size; 925 __le32 image_offset; 926 __le32 segment_size; 927 __le32 reserved1c; 928 union mpi3_sge_union sgl; 929 }; 930 931 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 932 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 933 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 934 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 935 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 936 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 937 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 938 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 939 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 940 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 941 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 942 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) 943 struct mpi3_ci_download_reply { 944 __le16 host_tag; 945 u8 ioc_use_only02; 946 u8 function; 947 __le16 ioc_use_only04; 948 u8 ioc_use_only06; 949 u8 msg_flags; 950 __le16 ioc_use_only08; 951 __le16 ioc_status; 952 __le32 ioc_log_info; 953 u8 flags; 954 u8 cache_dirty; 955 u8 pending_count; 956 u8 reserved13; 957 }; 958 959 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 960 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) 961 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 962 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 963 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 964 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 965 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 966 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 967 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 968 struct mpi3_ci_upload_request { 969 __le16 host_tag; 970 u8 ioc_use_only02; 971 u8 function; 972 __le16 ioc_use_only04; 973 u8 ioc_use_only06; 974 u8 msg_flags; 975 __le16 change_count; 976 __le16 reserved0a; 977 __le32 signature1; 978 __le32 reserved10; 979 __le32 image_offset; 980 __le32 segment_size; 981 __le32 reserved1c; 982 union mpi3_sge_union sgl; 983 }; 984 985 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 986 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 987 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 988 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 989 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 990 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 991 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 992 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 993 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 994 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 995 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 996 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 997 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 998 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) 999 #define MPI3_CTRL_OP_SAS_SEND_PRIMITIVE (0x20) 1000 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) 1001 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) 1002 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) 1003 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) 1004 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 1005 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 1006 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 1007 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 1008 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 1009 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) 1010 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PHY_INDEX (0x00) 1011 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 1012 #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 1013 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) 1014 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) 1015 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1016 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1017 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) 1018 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) 1019 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) 1020 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1021 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1022 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1023 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 1024 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 1025 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 1026 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 1027 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 1028 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 1029 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 1030 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 1031 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 1032 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 1033 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 1034 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) 1035 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 1036 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 1037 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 1038 #define MPI3_CTRL_ACTION_NOP (0x00) 1039 #define MPI3_CTRL_ACTION_LINK_RESET (0x01) 1040 #define MPI3_CTRL_ACTION_HARD_RESET (0x02) 1041 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) 1042 struct mpi3_iounit_control_request { 1043 __le16 host_tag; 1044 u8 ioc_use_only02; 1045 u8 function; 1046 __le16 ioc_use_only04; 1047 u8 ioc_use_only06; 1048 u8 msg_flags; 1049 __le16 change_count; 1050 u8 reserved0a; 1051 u8 operation; 1052 __le32 reserved0c; 1053 __le64 param64[2]; 1054 __le32 param32[4]; 1055 __le16 param16[4]; 1056 u8 param8[8]; 1057 }; 1058 1059 struct mpi3_iounit_control_reply { 1060 __le16 host_tag; 1061 u8 ioc_use_only02; 1062 u8 function; 1063 __le16 ioc_use_only04; 1064 u8 ioc_use_only06; 1065 u8 msg_flags; 1066 __le16 ioc_use_only08; 1067 __le16 ioc_status; 1068 __le32 ioc_log_info; 1069 __le64 value64[2]; 1070 __le32 value32[4]; 1071 __le16 value16[4]; 1072 u8 value8[8]; 1073 }; 1074 #endif 1075