1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  Copyright 2017-2022 Broadcom Inc. All rights reserved.
4  */
5 #ifndef MPI30_CNFG_H
6 #define MPI30_CNFG_H     1
7 #define MPI3_CONFIG_PAGETYPE_IO_UNIT                    (0x00)
8 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING              (0x01)
9 #define MPI3_CONFIG_PAGETYPE_IOC                        (0x02)
10 #define MPI3_CONFIG_PAGETYPE_DRIVER                     (0x03)
11 #define MPI3_CONFIG_PAGETYPE_SECURITY                   (0x04)
12 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE                  (0x11)
13 #define MPI3_CONFIG_PAGETYPE_DEVICE                     (0x12)
14 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT                (0x20)
15 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER               (0x21)
16 #define MPI3_CONFIG_PAGETYPE_SAS_PHY                    (0x23)
17 #define MPI3_CONFIG_PAGETYPE_SAS_PORT                   (0x24)
18 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT               (0x30)
19 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH                (0x31)
20 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK                  (0x33)
21 #define MPI3_CONFIG_PAGEATTR_MASK                       (0xf0)
22 #define MPI3_CONFIG_PAGEATTR_READ_ONLY                  (0x00)
23 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE                 (0x10)
24 #define MPI3_CONFIG_PAGEATTR_PERSISTENT                 (0x20)
25 #define MPI3_CONFIG_ACTION_PAGE_HEADER                  (0x00)
26 #define MPI3_CONFIG_ACTION_READ_DEFAULT                 (0x01)
27 #define MPI3_CONFIG_ACTION_READ_CURRENT                 (0x02)
28 #define MPI3_CONFIG_ACTION_WRITE_CURRENT                (0x03)
29 #define MPI3_CONFIG_ACTION_READ_PERSISTENT              (0x04)
30 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT             (0x05)
31 #define MPI3_DEVICE_PGAD_FORM_MASK                      (0xf0000000)
32 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
33 #define MPI3_DEVICE_PGAD_FORM_HANDLE                    (0x20000000)
34 #define MPI3_DEVICE_PGAD_HANDLE_MASK                    (0x0000ffff)
35 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK                  (0xf0000000)
36 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE       (0x00000000)
37 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM        (0x10000000)
38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE                (0x20000000)
39 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK                (0x00ff0000)
40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT               (16)
41 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK                (0x0000ffff)
42 #define MPI3_SAS_PHY_PGAD_FORM_MASK                     (0xf0000000)
43 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER               (0x00000000)
44 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK               (0x000000ff)
45 #define MPI3_SASPORT_PGAD_FORM_MASK                     (0xf0000000)
46 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT            (0x00000000)
47 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM                 (0x10000000)
48 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK              (0x000000ff)
49 #define MPI3_ENCLOS_PGAD_FORM_MASK                      (0xf0000000)
50 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
51 #define MPI3_ENCLOS_PGAD_FORM_HANDLE                    (0x10000000)
52 #define MPI3_ENCLOS_PGAD_HANDLE_MASK                    (0x0000ffff)
53 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK                 (0xf0000000)
54 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
55 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM      (0x10000000)
56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE               (0x20000000)
57 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK              (0x00ff0000)
58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT             (16)
59 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK               (0x0000ffff)
60 #define MPI3_PCIE_LINK_PGAD_FORM_MASK                   (0xf0000000)
61 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK          (0x00000000)
62 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM               (0x10000000)
63 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK                (0x000000ff)
64 #define MPI3_SECURITY_PGAD_FORM_MASK                    (0xf0000000)
65 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT           (0x00000000)
66 #define MPI3_SECURITY_PGAD_FORM_SOT_NUM                 (0x10000000)
67 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK              (0x0000ff00)
68 #define MPI3_SECURITY_PGAD_SLOT_MASK                    (0x000000ff)
69 struct mpi3_config_request {
70 	__le16             host_tag;
71 	u8                 ioc_use_only02;
72 	u8                 function;
73 	__le16             ioc_use_only04;
74 	u8                 ioc_use_only06;
75 	u8                 msg_flags;
76 	__le16             change_count;
77 	__le16             reserved0a;
78 	u8                 page_version;
79 	u8                 page_number;
80 	u8                 page_type;
81 	u8                 action;
82 	__le32             page_address;
83 	__le16             page_length;
84 	__le16             reserved16;
85 	__le32             reserved18[2];
86 	union mpi3_sge_union  sgl;
87 };
88 
89 struct mpi3_config_page_header {
90 	u8                 page_version;
91 	u8                 reserved01;
92 	u8                 page_number;
93 	u8                 page_attribute;
94 	__le16             page_length;
95 	u8                 page_type;
96 	u8                 reserved07;
97 };
98 
99 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK             (0xf0)
100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT            (4)
101 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK            (0x0f)
102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT           (0)
103 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
104 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
105 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
106 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
107 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
108 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
109 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
110 #define MPI3_SAS_NEG_LINK_RATE_1_5                      (0x08)
111 #define MPI3_SAS_NEG_LINK_RATE_3_0                      (0x09)
112 #define MPI3_SAS_NEG_LINK_RATE_6_0                      (0x0a)
113 #define MPI3_SAS_NEG_LINK_RATE_12_0                     (0x0b)
114 #define MPI3_SAS_NEG_LINK_RATE_22_5                     (0x0c)
115 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
116 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
117 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
118 #define MPI3_SAS_APHYINFO_REASON_MASK                   (0x0000000f)
119 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
120 #define MPI3_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
121 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
122 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
123 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
124 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
125 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
126 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
127 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
128 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC       (0x00000009)
129 #define MPI3_SAS_PHYINFO_STATUS_MASK                    (0xc0000000)
130 #define MPI3_SAS_PHYINFO_STATUS_SHIFT                   (30)
131 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE              (0x00000000)
132 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST               (0x40000000)
133 #define MPI3_SAS_PHYINFO_STATUS_VACANT                  (0x80000000)
134 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE     (0x00000000)
136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL    (0x08000000)
137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER    (0x10000000)
138 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT                 (0)
139 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK  (0x04000000)
140 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
141 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK         (0x02000000)
142 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT        (25)
143 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK          (0x01000000)
144 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT         (24)
145 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT                (0x00400000)
146 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN                  (0x00200000)
147 #define MPI3_SAS_PHYINFO_ZONING_ENABLED                       (0x00100000)
148 #define MPI3_SAS_PHYINFO_REASON_MASK                    (0x000f0000)
149 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
150 #define MPI3_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
151 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
152 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
153 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
154 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
155 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
156 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
157 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
158 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC        (0x00090000)
159 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
160 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
161 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
162 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK      (0x00000f00)
163 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT     (8)
164 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK         (0x000000f0)
165 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT       (0x00000000)
166 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE  (0x00000010)
167 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE        (0x00000020)
168 #define MPI3_SAS_PRATE_MAX_RATE_MASK                    (0xf0)
169 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
170 #define MPI3_SAS_PRATE_MAX_RATE_1_5                     (0x80)
171 #define MPI3_SAS_PRATE_MAX_RATE_3_0                     (0x90)
172 #define MPI3_SAS_PRATE_MAX_RATE_6_0                     (0xa0)
173 #define MPI3_SAS_PRATE_MAX_RATE_12_0                    (0xb0)
174 #define MPI3_SAS_PRATE_MAX_RATE_22_5                    (0xc0)
175 #define MPI3_SAS_PRATE_MIN_RATE_MASK                    (0x0f)
176 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
177 #define MPI3_SAS_PRATE_MIN_RATE_1_5                     (0x08)
178 #define MPI3_SAS_PRATE_MIN_RATE_3_0                     (0x09)
179 #define MPI3_SAS_PRATE_MIN_RATE_6_0                     (0x0a)
180 #define MPI3_SAS_PRATE_MIN_RATE_12_0                    (0x0b)
181 #define MPI3_SAS_PRATE_MIN_RATE_22_5                    (0x0c)
182 #define MPI3_SAS_HWRATE_MAX_RATE_MASK                   (0xf0)
183 #define MPI3_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
184 #define MPI3_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
185 #define MPI3_SAS_HWRATE_MAX_RATE_6_0                    (0xa0)
186 #define MPI3_SAS_HWRATE_MAX_RATE_12_0                   (0xb0)
187 #define MPI3_SAS_HWRATE_MAX_RATE_22_5                   (0xc0)
188 #define MPI3_SAS_HWRATE_MIN_RATE_MASK                   (0x0f)
189 #define MPI3_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
190 #define MPI3_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
191 #define MPI3_SAS_HWRATE_MIN_RATE_6_0                    (0x0a)
192 #define MPI3_SAS_HWRATE_MIN_RATE_12_0                   (0x0b)
193 #define MPI3_SAS_HWRATE_MIN_RATE_22_5                   (0x0c)
194 #define MPI3_SLOT_INVALID                               (0xffff)
195 #define MPI3_SLOT_INDEX_INVALID                         (0xffff)
196 #define MPI3_LINK_CHANGE_COUNT_INVALID                   (0xffff)
197 #define MPI3_RATE_CHANGE_COUNT_INVALID                   (0xffff)
198 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL              (0x0)
199 #define MPI3_TEMP_SENSOR_LOCATION_INLET                 (0x1)
200 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET                (0x2)
201 #define MPI3_TEMP_SENSOR_LOCATION_DRAM                  (0x3)
202 #define MPI3_MFGPAGE_VENDORID_BROADCOM                  (0x1000)
203 #define MPI3_MFGPAGE_DEVID_SAS4116                      (0x00a5)
204 struct mpi3_man_page0 {
205 	struct mpi3_config_page_header         header;
206 	u8                                 chip_revision[8];
207 	u8                                 chip_name[32];
208 	u8                                 board_name[32];
209 	u8                                 board_assembly[32];
210 	u8                                 board_tracer_number[32];
211 	__le32                             board_power;
212 	__le32                             reserved94;
213 	__le32                             reserved98;
214 	u8                                 oem;
215 	u8                                 profile_identifier;
216 	__le16                             flags;
217 	u8                                 board_mfg_day;
218 	u8                                 board_mfg_month;
219 	__le16                             board_mfg_year;
220 	u8                                 board_rework_day;
221 	u8                                 board_rework_month;
222 	__le16                             board_rework_year;
223 	u8                                 board_revision[8];
224 	u8                                 e_pack_fru[16];
225 	u8                                 product_name[256];
226 };
227 
228 #define MPI3_MAN0_PAGEVERSION       (0x00)
229 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT                       (0x0002)
230 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT                     (0x0001)
231 #define MPI3_MAN1_VPD_SIZE                                   (512)
232 struct mpi3_man_page1 {
233 	struct mpi3_config_page_header         header;
234 	__le32                             reserved08[2];
235 	u8                                 vpd[MPI3_MAN1_VPD_SIZE];
236 };
237 
238 #define MPI3_MAN1_PAGEVERSION                                 (0x00)
239 struct mpi3_man_page2 {
240 	struct mpi3_config_page_header         header;
241 	u8                                 flags;
242 	u8                                 reserved09[3];
243 	__le32                             reserved0c[3];
244 	u8                                 oem_board_tracer_number[32];
245 };
246 #define MPI3_MAN2_PAGEVERSION                                 (0x00)
247 #define MPI3_MAN2_FLAGS_TRACER_PRESENT                        (0x01)
248 struct mpi3_man5_phy_entry {
249 	__le64     ioc_wwid;
250 	__le64     device_name;
251 	__le64     sata_wwid;
252 };
253 
254 #ifndef MPI3_MAN5_PHY_MAX
255 #define MPI3_MAN5_PHY_MAX                                   (1)
256 #endif
257 struct mpi3_man_page5 {
258 	struct mpi3_config_page_header         header;
259 	u8                                 num_phys;
260 	u8                                 reserved09[3];
261 	__le32                             reserved0c;
262 	struct mpi3_man5_phy_entry             phy[MPI3_MAN5_PHY_MAX];
263 };
264 
265 #define MPI3_MAN5_PAGEVERSION                                (0x00)
266 struct mpi3_man6_gpio_entry {
267 	u8         function_code;
268 	u8         function_flags;
269 	__le16     flags;
270 	u8         param1;
271 	u8         param2;
272 	__le16     reserved06;
273 	__le32     param3;
274 };
275 
276 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC                                       (0x00)
277 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE                                     (0x01)
278 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT                                 (0x02)
279 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY                               (0x03)
280 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE                              (0x04)
281 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN                             (0x05)
282 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW                            (0x06)
283 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT                              (0x07)
284 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE                             (0x08)
285 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET                                   (0x0a)
286 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET                            (0x0b)
287 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT                                  (0x0c)
288 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE                            (0x0d)
289 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE                                  (0x0e)
290 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT                                   (0x0f)
291 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE                                     (0x10)
292 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE                                       (0x11)
293 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL                                (0x12)
294 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP                      (0x13)
295 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER                               (0x14)
296 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY                         (0x15)
297 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL                             (0x16)
298 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT                               (0x17)
299 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE                                   (0x18)
300 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK               (0x01)
301 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI              (0x00)
302 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID       (0x01)
303 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK                        (0xf0)
304 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC                     (0x00)
305 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT                  (0x10)
306 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT    (0x20)
307 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK                       (0x01)
308 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE                       (0x00)
309 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL                      (0x01)
310 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP                    (0x00)
311 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP            (0x01)
312 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT             (0x00)
313 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE        (0x01)
314 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE          (0x02)
315 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON                            (0x00)
316 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK                                   (0x0100)
317 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE                              (0x0100)
318 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE                              (0x0000)
319 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK                              (0x00c0)
320 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM                            (0x0000)
321 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM                             (0x0040)
322 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM                             (0x0080)
323 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM                             (0x00c0)
324 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK                                (0x0030)
325 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT                               (4)
326 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH                                      (0x0008)
327 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED                                   (0x0004)
328 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK                                   (0x0003)
329 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT                                  (0x0000)
330 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT                      (0x0001)
331 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT                     (0x0002)
332 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT                       (0x0003)
333 #ifndef MPI3_MAN6_GPIO_MAX
334 #define MPI3_MAN6_GPIO_MAX                                                    (1)
335 #endif
336 struct mpi3_man_page6 {
337 	struct mpi3_config_page_header         header;
338 	__le16                             flags;
339 	__le16                             reserved0a;
340 	u8                                 num_gpio;
341 	u8                                 reserved0d[3];
342 	struct mpi3_man6_gpio_entry            gpio[MPI3_MAN6_GPIO_MAX];
343 };
344 
345 #define MPI3_MAN6_PAGEVERSION                                                 (0x00)
346 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED                                (0x0001)
347 struct mpi3_man7_receptacle_info {
348 	__le32                             name[4];
349 	u8                                 location;
350 	u8                                 connector_type;
351 	u8                                 ped_clk;
352 	u8                                 connector_id;
353 	__le32                             reserved14;
354 };
355 
356 #define MPI3_MAN7_LOCATION_UNKNOWN                         (0x00)
357 #define MPI3_MAN7_LOCATION_INTERNAL                        (0x01)
358 #define MPI3_MAN7_LOCATION_EXTERNAL                        (0x02)
359 #define MPI3_MAN7_LOCATION_VIRTUAL                         (0x03)
360 #define MPI3_MAN7_LOCATION_HOST                            (0x04)
361 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO                   (0x00)
362 #define MPI3_MAN7_PEDCLK_ROUTING_MASK                      (0x10)
363 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT                    (0x00)
364 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER              (0x10)
365 #define MPI3_MAN7_PEDCLK_ID_MASK                           (0x0f)
366 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX
367 #define MPI3_MAN7_RECEPTACLE_INFO_MAX                      (1)
368 #endif
369 struct mpi3_man_page7 {
370 	struct mpi3_config_page_header         header;
371 	__le32                             flags;
372 	u8                                 num_receptacles;
373 	u8                                 reserved0d[3];
374 	__le32                             enclosure_name[4];
375 	struct mpi3_man7_receptacle_info       receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX];
376 };
377 
378 #define MPI3_MAN7_PAGEVERSION                              (0x00)
379 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK          (0x01)
380 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0             (0x00)
381 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1             (0x01)
382 struct mpi3_man8_phy_info {
383 	u8                                 receptacle_id;
384 	u8                                 connector_lane;
385 	__le16                             reserved02;
386 	__le16                             slotx1;
387 	__le16                             slotx2;
388 	__le16                             slotx4;
389 	__le16                             reserved0a;
390 	__le32                             reserved0c;
391 };
392 
393 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED    (0xff)
394 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED   (0xff)
395 #ifndef MPI3_MAN8_PHY_INFO_MAX
396 #define MPI3_MAN8_PHY_INFO_MAX                      (1)
397 #endif
398 struct mpi3_man_page8 {
399 	struct mpi3_config_page_header         header;
400 	__le32                             reserved08;
401 	u8                                 num_phys;
402 	u8                                 reserved0d[3];
403 	struct mpi3_man8_phy_info              phy_info[MPI3_MAN8_PHY_INFO_MAX];
404 };
405 
406 #define MPI3_MAN8_PAGEVERSION                   (0x00)
407 struct mpi3_man9_rsrc_entry {
408 	__le32     maximum;
409 	__le32     decrement;
410 	__le32     minimum;
411 	__le32     actual;
412 };
413 
414 enum mpi3_man9_resources {
415 	MPI3_MAN9_RSRC_OUTSTANDING_REQS    = 0,
416 	MPI3_MAN9_RSRC_TARGET_CMDS         = 1,
417 	MPI3_MAN9_RSRC_RESERVED02          = 2,
418 	MPI3_MAN9_RSRC_NVME                = 3,
419 	MPI3_MAN9_RSRC_INITIATORS          = 4,
420 	MPI3_MAN9_RSRC_VDS                 = 5,
421 	MPI3_MAN9_RSRC_ENCLOSURES          = 6,
422 	MPI3_MAN9_RSRC_ENCLOSURE_PHYS      = 7,
423 	MPI3_MAN9_RSRC_EXPANDERS           = 8,
424 	MPI3_MAN9_RSRC_PCIE_SWITCHES       = 9,
425 	MPI3_MAN9_RSRC_RESERVED10          = 10,
426 	MPI3_MAN9_RSRC_HOST_PD_DRIVES      = 11,
427 	MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES  = 12,
428 	MPI3_MAN9_RSRC_RAID_PD_DRIVES      = 13,
429 	MPI3_MAN9_RSRC_DRV_DIAG_BUF        = 14,
430 	MPI3_MAN9_RSRC_NAMESPACE_COUNT     = 15,
431 	MPI3_MAN9_RSRC_NUM_RESOURCES
432 };
433 
434 #define MPI3_MAN9_MIN_OUTSTANDING_REQS      (1)
435 #define MPI3_MAN9_MAX_OUTSTANDING_REQS      (65000)
436 #define MPI3_MAN9_MIN_TARGET_CMDS           (0)
437 #define MPI3_MAN9_MAX_TARGET_CMDS           (65535)
438 #define MPI3_MAN9_MIN_NVME_TARGETS          (0)
439 #define MPI3_MAN9_MIN_INITIATORS            (0)
440 #define MPI3_MAN9_MIN_VDS                   (0)
441 #define MPI3_MAN9_MIN_ENCLOSURES            (1)
442 #define MPI3_MAN9_MAX_ENCLOSURES            (65535)
443 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS        (0)
444 #define MPI3_MAN9_MIN_EXPANDERS             (0)
445 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
446 #define MPI3_MAN9_MIN_PCIE_SWITCHES         (0)
447 #define MPI3_MAN9_MIN_HOST_PD_DRIVES        (0)
448 #define MPI3_MAN9_ADV_HOST_PD_DRIVES        (0)
449 #define MPI3_MAN9_RAID_PD_DRIVES            (0)
450 #define MPI3_MAN9_DRIVER_DIAG_BUFFER        (0)
451 #define MPI3_MAN9_MIN_NAMESPACE_COUNT       (1)
452 #define MPI3_MAN9_MIN_EXPANDERS             (0)
453 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
454 struct mpi3_man_page9 {
455 	struct mpi3_config_page_header         header;
456 	u8                                 num_resources;
457 	u8                                 reserved09;
458 	__le16                             reserved0a;
459 	__le32                             reserved0c;
460 	__le32                             reserved10;
461 	__le32                             reserved14;
462 	__le32                             reserved18;
463 	__le32                             reserved1c;
464 	struct mpi3_man9_rsrc_entry            resource[MPI3_MAN9_RSRC_NUM_RESOURCES];
465 };
466 
467 #define MPI3_MAN9_PAGEVERSION                   (0x00)
468 struct mpi3_man10_istwi_ctrlr_entry {
469 	__le16     slave_address;
470 	__le16     flags;
471 	u8         scl_low_override;
472 	u8         scl_high_override;
473 	__le16     reserved06;
474 };
475 
476 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK         (0x000c)
477 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K         (0x0000)
478 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K         (0x0004)
479 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED          (0x0002)
480 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED         (0x0001)
481 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
482 #define MPI3_MAN10_ISTWI_CTRLR_MAX          (1)
483 #endif
484 struct mpi3_man_page10 {
485 	struct mpi3_config_page_header         header;
486 	__le32                             reserved08;
487 	u8                                 num_istwi_ctrl;
488 	u8                                 reserved0d[3];
489 	struct mpi3_man10_istwi_ctrlr_entry    istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX];
490 };
491 
492 #define MPI3_MAN10_PAGEVERSION                  (0x00)
493 struct mpi3_man11_mux_device_format {
494 	u8         max_channel;
495 	u8         reserved01[3];
496 	__le32     reserved04;
497 };
498 
499 struct mpi3_man11_temp_sensor_device_format {
500 	u8         type;
501 	u8         reserved01[3];
502 	u8         temp_channel[4];
503 };
504 
505 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654                (0x00)
506 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442                (0x01)
507 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476                (0x02)
508 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B                  (0x03)
509 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK       (0xe0)
510 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT      (5)
511 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED             (0x01)
512 struct mpi3_man11_seeprom_device_format {
513 	u8         size;
514 	u8         page_write_size;
515 	__le16     reserved02;
516 	__le32     reserved04;
517 };
518 
519 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS              (0x01)
520 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS              (0x02)
521 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS              (0x03)
522 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS              (0x04)
523 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS             (0x05)
524 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS             (0x06)
525 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS             (0x07)
526 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS            (0x08)
527 struct mpi3_man11_ddr_spd_device_format {
528 	u8         channel;
529 	u8         reserved01[3];
530 	__le32     reserved04;
531 };
532 
533 struct mpi3_man11_cable_mgmt_device_format {
534 	u8         type;
535 	u8         receptacle_id;
536 	__le16     reserved02;
537 	__le32     reserved04;
538 };
539 
540 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636           (0x00)
541 struct mpi3_man11_bkplane_spec_ubm_format {
542 	__le16     flags;
543 	__le16     reserved02;
544 };
545 
546 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
547 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING                 (0x0100)
548 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK                  (0x00f0)
549 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT                 (4)
550 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
551 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
552 struct mpi3_man11_bkplane_spec_non_ubm_format {
553 	__le16     flags;
554 	u8         reserved02;
555 	u8         type;
556 };
557 
558 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK                    (0xf000)
559 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT                   (12)
560 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
561 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK                (0x00c0)
562 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4                   (0x0000)
563 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2                   (0x0040)
564 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1                   (0x0080)
565 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK          (0x0030)
566 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO          (0x0000)
567 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG           (0x0010)
568 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
569 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
570 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP                            (0x00)
571 union mpi3_man11_bkplane_spec_format {
572 	struct mpi3_man11_bkplane_spec_ubm_format         ubm;
573 	struct mpi3_man11_bkplane_spec_non_ubm_format     non_ubm;
574 };
575 
576 struct mpi3_man11_bkplane_mgmt_device_format {
577 	u8                                        type;
578 	u8                                        receptacle_id;
579 	u8                                        reset_info;
580 	u8                                        reserved03;
581 	union mpi3_man11_bkplane_spec_format         backplane_mgmt_specific;
582 };
583 
584 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM            (0x00)
585 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM        (0x01)
586 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK       (0xf0)
587 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT      (4)
588 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK        (0x0f)
589 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT       (0)
590 struct mpi3_man11_gas_gauge_device_format {
591 	u8         type;
592 	u8         reserved01[3];
593 	__le32     reserved04;
594 };
595 
596 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD          (0x00)
597 struct mpi3_man11_mgmt_ctrlr_device_format {
598 	__le32     reserved00;
599 	__le32     reserved04;
600 };
601 struct mpi3_man11_board_fan_device_format {
602 	u8         flags;
603 	u8         reserved01;
604 	u8         min_fan_speed;
605 	u8         max_fan_speed;
606 	__le32     reserved04;
607 };
608 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK        (0x07)
609 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821     (0x00)
610 union mpi3_man11_device_specific_format {
611 	struct mpi3_man11_mux_device_format            mux;
612 	struct mpi3_man11_temp_sensor_device_format    temp_sensor;
613 	struct mpi3_man11_seeprom_device_format        seeprom;
614 	struct mpi3_man11_ddr_spd_device_format        ddr_spd;
615 	struct mpi3_man11_cable_mgmt_device_format     cable_mgmt;
616 	struct mpi3_man11_bkplane_mgmt_device_format   bkplane_mgmt;
617 	struct mpi3_man11_gas_gauge_device_format      gas_gauge;
618 	struct mpi3_man11_mgmt_ctrlr_device_format     mgmt_controller;
619 	struct mpi3_man11_board_fan_device_format      board_fan;
620 	__le32                                     words[2];
621 };
622 struct mpi3_man11_istwi_device_format {
623 	u8                                     device_type;
624 	u8                                     controller;
625 	u8                                     reserved02;
626 	u8                                     flags;
627 	__le16                                 device_address;
628 	u8                                     mux_channel;
629 	u8                                     mux_index;
630 	union mpi3_man11_device_specific_format   device_specific;
631 };
632 
633 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX                  (0x00)
634 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR          (0x01)
635 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM              (0x02)
636 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD              (0x03)
637 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT           (0x04)
638 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT       (0x05)
639 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE            (0x06)
640 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER      (0x07)
641 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN            (0x08)
642 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT            (0x01)
643 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
644 #define MPI3_MAN11_ISTWI_DEVICE_MAX             (1)
645 #endif
646 struct mpi3_man_page11 {
647 	struct mpi3_config_page_header         header;
648 	__le32                             reserved08;
649 	u8                                 num_istwi_dev;
650 	u8                                 reserved0d[3];
651 	struct mpi3_man11_istwi_device_format  istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX];
652 };
653 
654 #define MPI3_MAN11_PAGEVERSION                  (0x00)
655 #ifndef MPI3_MAN12_NUM_SGPIO_MAX
656 #define MPI3_MAN12_NUM_SGPIO_MAX                                     (1)
657 #endif
658 struct mpi3_man12_sgpio_info {
659 	u8                                 slot_count;
660 	u8                                 reserved01[3];
661 	__le32                             reserved04;
662 	u8                                 phy_order[32];
663 };
664 
665 struct mpi3_man_page12 {
666 	struct mpi3_config_page_header         header;
667 	__le32                             flags;
668 	__le32                             s_clock_freq;
669 	__le32                             activity_modulation;
670 	u8                                 num_sgpio;
671 	u8                                 reserved15[3];
672 	__le32                             reserved18;
673 	__le32                             reserved1c;
674 	__le32                             pattern[8];
675 	struct mpi3_man12_sgpio_info           sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX];
676 };
677 
678 #define MPI3_MAN12_PAGEVERSION                                       (0x00)
679 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED                      (0x0400)
680 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED                     (0x0200)
681 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED                           (0x0100)
682 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED                      (0x0004)
683 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK                      (0x0002)
684 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL                 (0x0000)
685 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN                (0x0002)
686 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK                          (0x0001)
687 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL                     (0x0000)
688 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN                    (0x0001)
689 #define MPI3_MAN12_SIO_CLK_FREQ_MIN                                  (32)
690 #define MPI3_MAN12_SIO_CLK_FREQ_MAX                                  (100000)
691 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK                (0x0000f000)
692 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT               (12)
693 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK                   (0x00000f00)
694 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT                  (8)
695 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK              (0x000000f0)
696 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT             (4)
697 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK               (0x0000000f)
698 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT              (0)
699 #define MPI3_MAN12_PATTERN_RATE_MASK                                 (0xe0000000)
700 #define MPI3_MAN12_PATTERN_RATE_2_HZ                                 (0x00000000)
701 #define MPI3_MAN12_PATTERN_RATE_4_HZ                                 (0x20000000)
702 #define MPI3_MAN12_PATTERN_RATE_8_HZ                                 (0x40000000)
703 #define MPI3_MAN12_PATTERN_RATE_16_HZ                                (0x60000000)
704 #define MPI3_MAN12_PATTERN_RATE_10_HZ                                (0x80000000)
705 #define MPI3_MAN12_PATTERN_RATE_20_HZ                                (0xa0000000)
706 #define MPI3_MAN12_PATTERN_RATE_40_HZ                                (0xc0000000)
707 #define MPI3_MAN12_PATTERN_LENGTH_MASK                               (0x1f000000)
708 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT                              (24)
709 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK                          (0x00ffffff)
710 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT                         (0)
711 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX
712 #define MPI3_MAN13_NUM_TRANSLATION_MAX                               (1)
713 #endif
714 struct mpi3_man13_translation_info {
715 	__le32                             slot_status;
716 	__le32                             mask;
717 	u8                                 activity;
718 	u8                                 locate;
719 	u8                                 error;
720 	u8                                 reserved0b;
721 };
722 
723 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT                     (0x20000000)
724 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF                (0x10000000)
725 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY           (0x00800000)
726 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE             (0x00400000)
727 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING            (0x00100000)
728 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT                    (0x00080000)
729 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL                   (0x00040000)
730 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY                  (0x00020000)
731 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK                        (0x00008000)
732 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE           (0x00004000)
733 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE                 (0x00002000)
734 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK         (0x00001000)
735 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY         (0x00000800)
736 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY           (0x00000400)
737 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP             (0x00000200)
738 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT       (0x00000100)
739 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE         (0x00000040)
740 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF                          (0x00)
741 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON                           (0x01)
742 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0                          (0x02)
743 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1                          (0x03)
744 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2                          (0x04)
745 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3                          (0x05)
746 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4                          (0x06)
747 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5                          (0x07)
748 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6                          (0x08)
749 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7                          (0x09)
750 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY                           (0x0a)
751 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL                     (0x0b)
752 struct mpi3_man_page13 {
753 	struct mpi3_config_page_header         header;
754 	u8                                 num_trans;
755 	u8                                 reserved09[3];
756 	__le32                             reserved0c;
757 	struct mpi3_man13_translation_info     translation[MPI3_MAN13_NUM_TRANSLATION_MAX];
758 };
759 
760 #define MPI3_MAN13_PAGEVERSION                                       (0x00)
761 struct mpi3_man_page14 {
762 	struct mpi3_config_page_header         header;
763 	__le32                             reserved08;
764 	u8                                 num_slot_groups;
765 	u8                                 num_slots;
766 	__le16                             max_cert_chain_length;
767 	__le32                             sealed_slots;
768 	__le32                             populated_slots;
769 	__le32                             mgmt_pt_updatable_slots;
770 };
771 #define MPI3_MAN14_PAGEVERSION                                       (0x00)
772 #define MPI3_MAN14_NUMSLOTS_MAX                                      (32)
773 #ifndef MPI3_MAN15_VERSION_RECORD_MAX
774 #define MPI3_MAN15_VERSION_RECORD_MAX      1
775 #endif
776 struct mpi3_man15_version_record {
777 	__le16                             spdm_version;
778 	__le16                             reserved02;
779 };
780 
781 struct mpi3_man_page15 {
782 	struct mpi3_config_page_header         header;
783 	u8                                 num_version_records;
784 	u8                                 reserved09[3];
785 	__le32                             reserved0c;
786 	struct mpi3_man15_version_record       version_record[MPI3_MAN15_VERSION_RECORD_MAX];
787 };
788 
789 #define MPI3_MAN15_PAGEVERSION                                       (0x00)
790 #ifndef MPI3_MAN16_CERT_ALGO_MAX
791 #define MPI3_MAN16_CERT_ALGO_MAX      1
792 #endif
793 struct mpi3_man16_certificate_algorithm {
794 	u8                                      slot_group;
795 	u8                                      reserved01[3];
796 	__le32                                  base_asym_algo;
797 	__le32                                  base_hash_algo;
798 	__le32                                  reserved0c[3];
799 };
800 
801 struct mpi3_man_page16 {
802 	struct mpi3_config_page_header              header;
803 	__le32                                  reserved08;
804 	u8                                      num_cert_algos;
805 	u8                                      reserved0d[3];
806 	struct mpi3_man16_certificate_algorithm     certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX];
807 };
808 
809 #define MPI3_MAN16_PAGEVERSION                                       (0x00)
810 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX
811 #define MPI3_MAN17_HASH_ALGORITHM_MAX      1
812 #endif
813 struct mpi3_man17_hash_algorithm {
814 	u8                                 meas_specification;
815 	u8                                 reserved01[3];
816 	__le32                             measurement_hash_algo;
817 	__le32                             reserved08[2];
818 };
819 
820 struct mpi3_man_page17 {
821 	struct mpi3_config_page_header         header;
822 	__le32                             reserved08;
823 	u8                                 num_hash_algos;
824 	u8                                 reserved0d[3];
825 	struct mpi3_man17_hash_algorithm       hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX];
826 };
827 
828 #define MPI3_MAN17_PAGEVERSION                                       (0x00)
829 struct mpi3_man_page20 {
830 	struct mpi3_config_page_header         header;
831 	__le32                             reserved08;
832 	__le32                             nonpremium_features;
833 	u8                                 allowed_personalities;
834 	u8                                 reserved11[3];
835 };
836 
837 #define MPI3_MAN20_PAGEVERSION                                       (0x00)
838 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK                           (0x02)
839 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED                        (0x02)
840 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED                    (0x00)
841 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK                           (0x01)
842 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED                        (0x01)
843 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED                    (0x00)
844 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK               (0x01)
845 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED            (0x00)
846 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED           (0x01)
847 struct mpi3_man_page21 {
848 	struct mpi3_config_page_header         header;
849 	__le32                             reserved08;
850 	__le32                             flags;
851 };
852 
853 #define MPI3_MAN21_PAGEVERSION                                       (0x00)
854 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK                     (0x00000060)
855 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK                    (0x00000000)
856 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW                    (0x00000020)
857 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN                     (0x00000040)
858 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK              (0x00000008)
859 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW             (0x00000000)
860 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT           (0x00000008)
861 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK                          (0x00000001)
862 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT                       (0x00000000)
863 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC                  (0x00000001)
864 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX
865 #define MPI3_MAN_PROD_SPECIFIC_MAX                      (1)
866 #endif
867 struct mpi3_man_page_product_specific {
868 	struct mpi3_config_page_header         header;
869 	__le32                             product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX];
870 };
871 
872 struct mpi3_io_unit_page0 {
873 	struct mpi3_config_page_header         header;
874 	__le64                             unique_value;
875 	__le32                             nvdata_version_default;
876 	__le32                             nvdata_version_persistent;
877 };
878 
879 #define MPI3_IOUNIT0_PAGEVERSION                (0x00)
880 struct mpi3_io_unit_page1 {
881 	struct mpi3_config_page_header         header;
882 	__le32                             flags;
883 	u8                                 dmd_io_delay;
884 	u8                                 dmd_report_pcie;
885 	u8                                 dmd_report_sata;
886 	u8                                 dmd_report_sas;
887 };
888 
889 #define MPI3_IOUNIT1_PAGEVERSION                (0x00)
890 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK                   (0x00000030)
891 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE                 (0x00000000)
892 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE                (0x00000010)
893 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY              (0x00000020)
894 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK                (0x00000008)
895 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER                       (0x00000004)
896 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK                   (0x00000003)
897 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE                 (0x00000000)
898 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE                (0x00000001)
899 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED              (0x00000002)
900 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK                    (0x7f)
901 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC                        (0x80)
902 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX
903 #define MPI3_IO_UNIT2_GPIO_VAL_MAX      (1)
904 #endif
905 struct mpi3_io_unit_page2 {
906 	struct mpi3_config_page_header         header;
907 	u8                                 gpio_count;
908 	u8                                 reserved09[3];
909 	__le16                             gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX];
910 };
911 
912 #define MPI3_IOUNIT2_PAGEVERSION                (0x00)
913 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK         (0xfffc)
914 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT        (2)
915 #define MPI3_IOUNIT2_GPIO_SETTING_MASK          (0x0001)
916 #define MPI3_IOUNIT2_GPIO_SETTING_OFF           (0x0000)
917 #define MPI3_IOUNIT2_GPIO_SETTING_ON            (0x0001)
918 struct mpi3_io_unit3_sensor {
919 	__le16             flags;
920 	u8                 threshold_margin;
921 	u8                 reserved03;
922 	__le16             threshold[3];
923 	__le16             reserved0a;
924 	__le32             reserved0c;
925 	__le32             reserved10;
926 	__le32             reserved14;
927 };
928 
929 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED           (0x0010)
930 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED          (0x0008)
931 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED        (0x0004)
932 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED       (0x0002)
933 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED         (0x0001)
934 #ifndef MPI3_IO_UNIT3_SENSOR_MAX
935 #define MPI3_IO_UNIT3_SENSOR_MAX                                (1)
936 #endif
937 struct mpi3_io_unit_page3 {
938 	struct mpi3_config_page_header         header;
939 	__le32                             reserved08;
940 	u8                                 num_sensors;
941 	u8                                 nominal_poll_interval;
942 	u8                                 warning_poll_interval;
943 	u8                                 reserved0f;
944 	struct mpi3_io_unit3_sensor            sensor[MPI3_IO_UNIT3_SENSOR_MAX];
945 };
946 
947 #define MPI3_IOUNIT3_PAGEVERSION                (0x00)
948 struct mpi3_io_unit4_sensor {
949 	__le16             current_temperature;
950 	__le16             reserved02;
951 	u8                 flags;
952 	u8                 reserved05[3];
953 	__le16             istwi_index;
954 	u8                 channel;
955 	u8                 reserved0b;
956 	__le32             reserved0c;
957 };
958 
959 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK          (0xe0)
960 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT         (5)
961 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID        (0x01)
962 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL    (0xffff)
963 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED        (0xff)
964 #ifndef MPI3_IO_UNIT4_SENSOR_MAX
965 #define MPI3_IO_UNIT4_SENSOR_MAX                                (1)
966 #endif
967 struct mpi3_io_unit_page4 {
968 	struct mpi3_config_page_header         header;
969 	__le32                             reserved08;
970 	u8                                 num_sensors;
971 	u8                                 reserved0d[3];
972 	struct mpi3_io_unit4_sensor            sensor[MPI3_IO_UNIT4_SENSOR_MAX];
973 };
974 
975 #define MPI3_IOUNIT4_PAGEVERSION                (0x00)
976 struct mpi3_io_unit5_spinup_group {
977 	u8                 max_target_spinup;
978 	u8                 spinup_delay;
979 	u8                 spinup_flags;
980 	u8                 reserved03;
981 };
982 
983 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE       (0x01)
984 #ifndef MPI3_IO_UNIT5_PHY_MAX
985 #define MPI3_IO_UNIT5_PHY_MAX       (4)
986 #endif
987 struct mpi3_io_unit_page5 {
988 	struct mpi3_config_page_header         header;
989 	struct mpi3_io_unit5_spinup_group      spinup_group_parameters[4];
990 	__le32                             reserved18;
991 	__le32                             reserved1c;
992 	__le16                             device_shutdown;
993 	__le16                             reserved22;
994 	u8                                 pcie_device_wait_time;
995 	u8                                 sata_device_wait_time;
996 	u8                                 spinup_encl_drive_count;
997 	u8                                 spinup_encl_delay;
998 	u8                                 num_phys;
999 	u8                                 pe_initial_spinup_delay;
1000 	u8                                 topology_stable_time;
1001 	u8                                 flags;
1002 	u8                                 phy[MPI3_IO_UNIT5_PHY_MAX];
1003 };
1004 
1005 #define MPI3_IOUNIT5_PAGEVERSION                           (0x00)
1006 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION             (0x00)
1007 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED       (0x01)
1008 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED     (0x02)
1009 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED       (0x02)
1010 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER   (0x03)
1011 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH     (0x03)
1012 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK         (0x0300)
1013 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT        (8)
1014 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK          (0x00c0)
1015 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT         (6)
1016 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK         (0x0030)
1017 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT        (4)
1018 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK         (0x000c)
1019 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT        (2)
1020 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK          (0x0003)
1021 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT         (0)
1022 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK                   (0x0c)
1023 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED          (0x00)
1024 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED          (0x04)
1025 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED         (0x08)
1026 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED                (0x0c)
1027 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP            (0x02)
1028 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE                (0x01)
1029 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK                 (0x03)
1030 struct mpi3_io_unit_page6 {
1031 	struct mpi3_config_page_header         header;
1032 	__le32                             board_power_requirement;
1033 	__le32                             pci_slot_power_allocation;
1034 	u8                                 flags;
1035 	u8                                 reserved11[3];
1036 };
1037 
1038 #define MPI3_IOUNIT6_PAGEVERSION                (0x00)
1039 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC    (0x01)
1040 #ifndef MPI3_IOUNIT8_DIGEST_MAX
1041 #define MPI3_IOUNIT8_DIGEST_MAX                   (1)
1042 #endif
1043 union mpi3_iounit8_digest {
1044 	__le32                             dword[16];
1045 	__le16                             word[32];
1046 	u8                                 byte[64];
1047 };
1048 
1049 struct mpi3_io_unit_page8 {
1050 	struct mpi3_config_page_header         header;
1051 	u8                                 sb_mode;
1052 	u8                                 sb_state;
1053 	__le16                             reserved0a;
1054 	u8                                 num_slots;
1055 	u8                                 slots_available;
1056 	u8                                 current_key_encryption_algo;
1057 	u8                                 key_digest_hash_algo;
1058 	union mpi3_version_union              current_svn;
1059 	__le32                             reserved14;
1060 	__le32                             current_key[128];
1061 	union mpi3_iounit8_digest             digest[MPI3_IOUNIT8_DIGEST_MAX];
1062 };
1063 
1064 #define MPI3_IOUNIT8_PAGEVERSION                  (0x00)
1065 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG          (0x04)
1066 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE           (0x02)
1067 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE         (0x01)
1068 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING   (0x04)
1069 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING   (0x02)
1070 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED  (0x01)
1071 struct mpi3_io_unit_page9 {
1072 	struct mpi3_config_page_header         header;
1073 	__le32                             flags;
1074 	__le16                             first_device;
1075 	__le16                             reserved0e;
1076 };
1077 
1078 #define MPI3_IOUNIT9_PAGEVERSION                                  (0x00)
1079 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK               (0x00000006)
1080 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT              (1)
1081 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE               (0x00000000)
1082 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE         (0x00000002)
1083 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE     (0x00000004)
1084 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED                        (0x00000001)
1085 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN                          (0xffff)
1086 struct mpi3_io_unit_page10 {
1087 	struct mpi3_config_page_header         header;
1088 	u8                                 flags;
1089 	u8                                 reserved09[3];
1090 	__le32                             silicon_id;
1091 	u8                                 fw_version_minor;
1092 	u8                                 fw_version_major;
1093 	u8                                 hw_version_minor;
1094 	u8                                 hw_version_major;
1095 	u8                                 part_number[16];
1096 };
1097 #define MPI3_IOUNIT10_PAGEVERSION                  (0x00)
1098 #define MPI3_IOUNIT10_FLAGS_VALID                  (0x01)
1099 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK          (0x02)
1100 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION  (0x00)
1101 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02)
1102 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED          (0x80)
1103 #ifndef MPI3_IOUNIT11_PROFILE_MAX
1104 #define MPI3_IOUNIT11_PROFILE_MAX                   (1)
1105 #endif
1106 struct mpi3_iounit11_profile {
1107 	u8                                 profile_identifier;
1108 	u8                                 reserved01[3];
1109 	__le16                             max_vds;
1110 	__le16                             max_host_pds;
1111 	__le16                             max_adv_host_pds;
1112 	__le16                             max_raid_pds;
1113 	__le16                             max_nvme;
1114 	__le16                             max_outstanding_requests;
1115 	__le16                             subsystem_id;
1116 	__le16                             reserved12;
1117 	__le32                             reserved14[2];
1118 };
1119 struct mpi3_io_unit_page11 {
1120 	struct mpi3_config_page_header         header;
1121 	__le32                             reserved08;
1122 	u8                                 num_profiles;
1123 	u8                                 current_profile_identifier;
1124 	__le16                             reserved0e;
1125 	struct mpi3_iounit11_profile           profile[MPI3_IOUNIT11_PROFILE_MAX];
1126 };
1127 #define MPI3_IOUNIT11_PAGEVERSION                  (0x00)
1128 #ifndef MPI3_IOUNIT12_BUCKET_MAX
1129 #define MPI3_IOUNIT12_BUCKET_MAX                   (1)
1130 #endif
1131 struct mpi3_iounit12_bucket {
1132 	u8                                 coalescing_depth;
1133 	u8                                 coalescing_timeout;
1134 	__le16                             io_count_low_boundary;
1135 	__le32                             reserved04;
1136 };
1137 struct mpi3_io_unit_page12 {
1138 	struct mpi3_config_page_header         header;
1139 	__le32                             flags;
1140 	__le32                             reserved0c[4];
1141 	u8                                 num_buckets;
1142 	u8                                 reserved1d[3];
1143 	struct mpi3_iounit12_bucket            bucket[MPI3_IOUNIT12_BUCKET_MAX];
1144 };
1145 #define MPI3_IOUNIT12_PAGEVERSION                  (0x00)
1146 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK         (0x00000300)
1147 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT        (8)
1148 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8            (0x00000000)
1149 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16           (0x00000100)
1150 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32           (0x00000200)
1151 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64           (0x00000300)
1152 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK        (0x00000003)
1153 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED    (0x00000000)
1154 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US       (0x00000001)
1155 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS         (0x00000002)
1156 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS         (0x00000003)
1157 #ifndef MPI3_IOUNIT13_FUNC_MAX
1158 #define MPI3_IOUNIT13_FUNC_MAX                                     (1)
1159 #endif
1160 struct mpi3_iounit13_allowed_function {
1161 	__le16                             sub_function;
1162 	u8                                 function_code;
1163 	u8                                 fuction_flags;
1164 };
1165 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED                 (0x04)
1166 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED                   (0x02)
1167 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED     (0x01)
1168 struct mpi3_io_unit_page13 {
1169 	struct mpi3_config_page_header         header;
1170 	__le16                             flags;
1171 	__le16                             reserved0a;
1172 	u8                                 num_allowed_functions;
1173 	u8                                 reserved0d[3];
1174 	struct mpi3_iounit13_allowed_function  allowed_function[MPI3_IOUNIT13_FUNC_MAX];
1175 };
1176 #define MPI3_IOUNIT13_PAGEVERSION                                  (0x00)
1177 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED                          (0x0002)
1178 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED                            (0x0001)
1179 struct mpi3_ioc_page0 {
1180 	struct mpi3_config_page_header         header;
1181 	__le32                             reserved08;
1182 	__le16                             vendor_id;
1183 	__le16                             device_id;
1184 	u8                                 revision_id;
1185 	u8                                 reserved11[3];
1186 	__le32                             class_code;
1187 	__le16                             subsystem_vendor_id;
1188 	__le16                             subsystem_id;
1189 };
1190 
1191 #define MPI3_IOC0_PAGEVERSION               (0x00)
1192 struct mpi3_ioc_page1 {
1193 	struct mpi3_config_page_header         header;
1194 	__le32                             coalescing_timeout;
1195 	u8                                 coalescing_depth;
1196 	u8                                 obsolete;
1197 	__le16                             reserved0e;
1198 };
1199 #define MPI3_IOC1_PAGEVERSION               (0x00)
1200 #ifndef MPI3_IOC2_EVENTMASK_WORDS
1201 #define MPI3_IOC2_EVENTMASK_WORDS           (4)
1202 #endif
1203 struct mpi3_ioc_page2 {
1204 	struct mpi3_config_page_header         header;
1205 	__le32                             reserved08;
1206 	__le16                             sas_broadcast_primitive_masks;
1207 	__le16                             sas_notify_primitive_masks;
1208 	__le32                             event_masks[MPI3_IOC2_EVENTMASK_WORDS];
1209 };
1210 
1211 #define MPI3_IOC2_PAGEVERSION               (0x00)
1212 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED               (0x0010)
1213 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED                 (0x0008)
1214 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED                 (0x0004)
1215 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED              (0x0002)
1216 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED                 (0x0001)
1217 struct mpi3_allowed_cmd_scsi {
1218 	__le16                             service_action;
1219 	u8                                 operation_code;
1220 	u8                                 command_flags;
1221 };
1222 
1223 struct mpi3_allowed_cmd_ata {
1224 	u8                                 subcommand;
1225 	u8                                 reserved01;
1226 	u8                                 command;
1227 	u8                                 command_flags;
1228 };
1229 
1230 struct mpi3_allowed_cmd_nvme {
1231 	u8                                 reserved00;
1232 	u8                                 nvme_cmd_flags;
1233 	u8                                 op_code;
1234 	u8                                 command_flags;
1235 };
1236 
1237 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK     (0x80)
1238 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO       (0x00)
1239 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN    (0x80)
1240 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK        (0x3f)
1241 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM         (0x00)
1242 union mpi3_allowed_cmd {
1243 	struct mpi3_allowed_cmd_scsi           scsi;
1244 	struct mpi3_allowed_cmd_ata            ata;
1245 	struct mpi3_allowed_cmd_nvme           nvme;
1246 };
1247 
1248 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED    (0x20)
1249 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED      (0x10)
1250 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED      (0x08)
1251 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED   (0x04)
1252 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED      (0x02)
1253 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED    (0x01)
1254 #ifndef MPI3_ALLOWED_CMDS_MAX
1255 #define MPI3_ALLOWED_CMDS_MAX           (1)
1256 #endif
1257 struct mpi3_driver_page0 {
1258 	struct mpi3_config_page_header         header;
1259 	__le32                             bsd_options;
1260 	u8                                 ssu_timeout;
1261 	u8                                 io_timeout;
1262 	u8                                 tur_retries;
1263 	u8                                 tur_interval;
1264 	u8                                 reserved10;
1265 	u8                                 security_key_timeout;
1266 	__le16                             reserved12;
1267 	__le32                             reserved14;
1268 	__le32                             reserved18;
1269 };
1270 #define MPI3_DRIVER0_PAGEVERSION               (0x00)
1271 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE           (0x00000008)
1272 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
1273 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK              (0x00000003)
1274 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS      (0x00000000)
1275 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY          (0x00000001)
1276 struct mpi3_driver_page1 {
1277 	struct mpi3_config_page_header         header;
1278 	__le32                             flags;
1279 	__le32                             reserved0c;
1280 	__le16                             host_diag_trace_max_size;
1281 	__le16                             host_diag_trace_min_size;
1282 	__le16                             host_diag_trace_decrement_size;
1283 	__le16                             reserved16;
1284 	__le16                             host_diag_fw_max_size;
1285 	__le16                             host_diag_fw_min_size;
1286 	__le16                             host_diag_fw_decrement_size;
1287 	__le16                             reserved1e;
1288 	__le16                             host_diag_driver_max_size;
1289 	__le16                             host_diag_driver_min_size;
1290 	__le16                             host_diag_driver_decrement_size;
1291 	__le16                             reserved26;
1292 };
1293 
1294 #define MPI3_DRIVER1_PAGEVERSION               (0x00)
1295 #ifndef MPI3_DRIVER2_TRIGGER_MAX
1296 #define MPI3_DRIVER2_TRIGGER_MAX           (1)
1297 #endif
1298 struct mpi3_driver2_trigger_event {
1299 	u8                                 type;
1300 	u8                                 flags;
1301 	u8                                 reserved02;
1302 	u8                                 event;
1303 	__le32                             reserved04[3];
1304 };
1305 
1306 struct mpi3_driver2_trigger_scsi_sense {
1307 	u8                                 type;
1308 	u8                                 flags;
1309 	__le16                             reserved02;
1310 	u8                                 ascq;
1311 	u8                                 asc;
1312 	u8                                 sense_key;
1313 	u8                                 reserved07;
1314 	__le32                             reserved08[2];
1315 };
1316 
1317 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL                        (0xff)
1318 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL                         (0xff)
1319 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL                   (0xff)
1320 struct mpi3_driver2_trigger_reply {
1321 	u8                                 type;
1322 	u8                                 flags;
1323 	__le16                             ioc_status;
1324 	__le32                             ioc_log_info;
1325 	__le32                             ioc_log_info_mask;
1326 	__le32                             reserved0c;
1327 };
1328 
1329 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL                        (0xffff)
1330 union mpi3_driver2_trigger_element {
1331 	struct mpi3_driver2_trigger_event             event;
1332 	struct mpi3_driver2_trigger_scsi_sense        scsi_sense;
1333 	struct mpi3_driver2_trigger_reply             reply;
1334 };
1335 
1336 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT                                       (0x00)
1337 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE                                  (0x01)
1338 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY                                       (0x02)
1339 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE                         (0x02)
1340 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE                            (0x01)
1341 struct mpi3_driver_page2 {
1342 	struct mpi3_config_page_header         header;
1343 	__le64                             master_trigger;
1344 	__le32                             reserved10[3];
1345 	u8                                 num_triggers;
1346 	u8                                 reserved1d[3];
1347 	union mpi3_driver2_trigger_element    trigger[MPI3_DRIVER2_TRIGGER_MAX];
1348 };
1349 
1350 #define MPI3_DRIVER2_PAGEVERSION               (0x00)
1351 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_TRACE_RELEASE                       (0x8000000000000000ULL)
1352 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_FW_RELEASE                          (0x4000000000000000ULL)
1353 #define MPI3_DRIVER2_MASTERTRIGGER_SNAPDUMP                                 (0x2000000000000000ULL)
1354 #define MPI3_DRIVER2_MASTERTRIGGER_DEVICE_REMOVAL_ENABLED                   (0x0000000000000004ULL)
1355 #define MPI3_DRIVER2_MASTERTRIGGER_TASK_MANAGEMENT_ENABLED                  (0x0000000000000002ULL)
1356 struct mpi3_driver_page10 {
1357 	struct mpi3_config_page_header         header;
1358 	__le16                             flags;
1359 	__le16                             reserved0a;
1360 	u8                                 num_allowed_commands;
1361 	u8                                 reserved0d[3];
1362 	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1363 };
1364 
1365 #define MPI3_DRIVER10_PAGEVERSION               (0x00)
1366 struct mpi3_driver_page20 {
1367 	struct mpi3_config_page_header         header;
1368 	__le16                             flags;
1369 	__le16                             reserved0a;
1370 	u8                                 num_allowed_commands;
1371 	u8                                 reserved0d[3];
1372 	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1373 };
1374 
1375 #define MPI3_DRIVER20_PAGEVERSION               (0x00)
1376 struct mpi3_driver_page30 {
1377 	struct mpi3_config_page_header         header;
1378 	__le16                             flags;
1379 	__le16                             reserved0a;
1380 	u8                                 num_allowed_commands;
1381 	u8                                 reserved0d[3];
1382 	union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1383 };
1384 
1385 #define MPI3_DRIVER30_PAGEVERSION               (0x00)
1386 union mpi3_security_mac {
1387 	__le32                             dword[16];
1388 	__le16                             word[32];
1389 	u8                                 byte[64];
1390 };
1391 
1392 union mpi3_security_nonce {
1393 	__le32                             dword[16];
1394 	__le16                             word[32];
1395 	u8                                 byte[64];
1396 };
1397 
1398 union mpi3_security0_cert_chain {
1399 	__le32                             dword[1024];
1400 	__le16                             word[2048];
1401 	u8                                 byte[4096];
1402 };
1403 
1404 struct mpi3_security_page0 {
1405 	struct mpi3_config_page_header         header;
1406 	u8                                 slot_num_group;
1407 	u8                                 slot_num;
1408 	__le16                             cert_chain_length;
1409 	u8                                 cert_chain_flags;
1410 	u8                                 reserved0d[3];
1411 	__le32                             base_asym_algo;
1412 	__le32                             base_hash_algo;
1413 	__le32                             reserved18[4];
1414 	union mpi3_security_mac               mac;
1415 	union mpi3_security_nonce             nonce;
1416 	union mpi3_security0_cert_chain       certificate_chain;
1417 };
1418 
1419 #define MPI3_SECURITY0_PAGEVERSION               (0x00)
1420 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK       (0x0e)
1421 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED     (0x00)
1422 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS   (0x02)
1423 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM       (0x04)
1424 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED              (0x01)
1425 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX
1426 #define MPI3_SECURITY1_KEY_RECORD_MAX      1
1427 #endif
1428 #ifndef MPI3_SECURITY1_PAD_MAX
1429 #define MPI3_SECURITY1_PAD_MAX      1
1430 #endif
1431 union mpi3_security1_key_data {
1432 	__le32                             dword[128];
1433 	__le16                             word[256];
1434 	u8                                 byte[512];
1435 };
1436 
1437 struct mpi3_security1_key_record {
1438 	u8                                 flags;
1439 	u8                                 consumer;
1440 	__le16                             key_data_size;
1441 	__le32                             additional_key_data;
1442 	__le32                             reserved08[2];
1443 	union mpi3_security1_key_data         key_data;
1444 };
1445 
1446 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK            (0x1f)
1447 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID       (0x00)
1448 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC            (0x01)
1449 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES             (0x02)
1450 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE   (0x03)
1451 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC    (0x04)
1452 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID         (0x00)
1453 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE         (0x01)
1454 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN        (0x02)
1455 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY        (0x03)
1456 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD     (0x04)
1457 struct mpi3_security_page1 {
1458 	struct mpi3_config_page_header         header;
1459 	__le32                             reserved08[2];
1460 	union mpi3_security_mac               mac;
1461 	union mpi3_security_nonce             nonce;
1462 	u8                                 num_keys;
1463 	u8                                 reserved91[3];
1464 	__le32                             reserved94[3];
1465 	struct mpi3_security1_key_record       key_record[MPI3_SECURITY1_KEY_RECORD_MAX];
1466 	u8                                 pad[MPI3_SECURITY1_PAD_MAX];
1467 };
1468 
1469 #define MPI3_SECURITY1_PAGEVERSION               (0x00)
1470 struct mpi3_sas_io_unit0_phy_data {
1471 	u8                 io_unit_port;
1472 	u8                 port_flags;
1473 	u8                 phy_flags;
1474 	u8                 negotiated_link_rate;
1475 	__le16             controller_phy_device_info;
1476 	__le16             reserved06;
1477 	__le16             attached_dev_handle;
1478 	__le16             controller_dev_handle;
1479 	__le32             discovery_status;
1480 	__le32             reserved10;
1481 };
1482 
1483 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX
1484 #define MPI3_SAS_IO_UNIT0_PHY_MAX           (1)
1485 #endif
1486 struct mpi3_sas_io_unit_page0 {
1487 	struct mpi3_config_page_header         header;
1488 	__le32                             reserved08;
1489 	u8                                 num_phys;
1490 	u8                                 init_status;
1491 	__le16                             reserved0e;
1492 	struct mpi3_sas_io_unit0_phy_data      phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX];
1493 };
1494 
1495 #define MPI3_SASIOUNIT0_PAGEVERSION                          (0x00)
1496 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS                 (0x00)
1497 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION      (0x01)
1498 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED      (0x02)
1499 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS              (0x04)
1500 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG        (0x05)
1501 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED         (0x06)
1502 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN      (0xf0)
1503 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX      (0xff)
1504 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS           (0x08)
1505 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK      (0x03)
1506 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1   (0x00)
1507 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC   (0x01)
1508 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
1509 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT        (0x40)
1510 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT        (0x20)
1511 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED                (0x08)
1512 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY                 (0x02)
1513 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY                    (0x01)
1514 struct mpi3_sas_io_unit1_phy_data {
1515 	u8                 io_unit_port;
1516 	u8                 port_flags;
1517 	u8                 phy_flags;
1518 	u8                 max_min_link_rate;
1519 	__le16             controller_phy_device_info;
1520 	__le16             max_target_port_connect_time;
1521 	__le32             reserved08;
1522 };
1523 
1524 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX
1525 #define MPI3_SAS_IO_UNIT1_PHY_MAX           (1)
1526 #endif
1527 struct mpi3_sas_io_unit_page1 {
1528 	struct mpi3_config_page_header         header;
1529 	__le16                             control_flags;
1530 	__le16                             sas_narrow_max_queue_depth;
1531 	__le16                             additional_control_flags;
1532 	__le16                             sas_wide_max_queue_depth;
1533 	u8                                 num_phys;
1534 	u8                                 sata_max_q_depth;
1535 	__le16                             reserved12;
1536 	struct mpi3_sas_io_unit1_phy_data      phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX];
1537 };
1538 
1539 #define MPI3_SASIOUNIT1_PAGEVERSION                                 (0x00)
1540 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST         (0x8000)
1541 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
1542 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
1543 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
1544 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
1545 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
1546 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
1547 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
1548 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
1549 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK                     (0x0001)
1550 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME              (0x0000)
1551 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS              (0x0001)
1552 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
1553 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
1554 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
1555 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
1556 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
1557 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
1558 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
1559 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
1560 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
1561 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
1562 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
1563 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
1564 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
1565 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK                          (0xf0)
1566 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT                         (4)
1567 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0                           (0xa0)
1568 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0                          (0xb0)
1569 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5                          (0xc0)
1570 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK                          (0x0f)
1571 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0                           (0x0a)
1572 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0                          (0x0b)
1573 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5                          (0x0c)
1574 struct mpi3_sas_io_unit2_phy_pm_settings {
1575 	u8                 control_flags;
1576 	u8                 reserved01;
1577 	__le16             inactivity_timer_exponent;
1578 	u8                 sata_partial_timeout;
1579 	u8                 reserved05;
1580 	u8                 sata_slumber_timeout;
1581 	u8                 reserved07;
1582 	u8                 sas_partial_timeout;
1583 	u8                 reserved09;
1584 	u8                 sas_slumber_timeout;
1585 	u8                 reserved0b;
1586 };
1587 
1588 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX
1589 #define MPI3_SAS_IO_UNIT2_PHY_MAX           (1)
1590 #endif
1591 struct mpi3_sas_io_unit_page2 {
1592 	struct mpi3_config_page_header             header;
1593 	u8                                     num_phys;
1594 	u8                                     reserved09[3];
1595 	__le32                                 reserved0c;
1596 	struct mpi3_sas_io_unit2_phy_pm_settings   sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX];
1597 };
1598 
1599 #define MPI3_SASIOUNIT2_PAGEVERSION                     (0x00)
1600 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
1601 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
1602 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
1603 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
1604 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK            (0x7000)
1605 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT           (12)
1606 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK            (0x0700)
1607 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT           (8)
1608 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK           (0x0070)
1609 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT          (4)
1610 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK           (0x0007)
1611 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT          (0)
1612 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS             (7)
1613 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND              (6)
1614 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS    (5)
1615 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS        (4)
1616 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND         (3)
1617 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS    (2)
1618 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS        (1)
1619 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND         (0)
1620 struct mpi3_sas_io_unit_page3 {
1621 	struct mpi3_config_page_header         header;
1622 	__le32                             reserved08;
1623 	__le32                             power_management_capabilities;
1624 };
1625 
1626 #define MPI3_SASIOUNIT3_PAGEVERSION                     (0x00)
1627 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
1628 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
1629 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
1630 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
1631 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
1632 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
1633 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
1634 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
1635 struct mpi3_sas_expander_page0 {
1636 	struct mpi3_config_page_header         header;
1637 	u8                                 io_unit_port;
1638 	u8                                 report_gen_length;
1639 	__le16                             enclosure_handle;
1640 	__le32                             reserved0c;
1641 	__le64                             sas_address;
1642 	__le32                             discovery_status;
1643 	__le16                             dev_handle;
1644 	__le16                             parent_dev_handle;
1645 	__le16                             expander_change_count;
1646 	__le16                             expander_route_indexes;
1647 	u8                                 num_phys;
1648 	u8                                 sas_level;
1649 	__le16                             flags;
1650 	__le16                             stp_bus_inactivity_time_limit;
1651 	__le16                             stp_max_connect_time_limit;
1652 	__le16                             stp_smp_nexus_loss_time;
1653 	__le16                             max_num_routed_sas_addresses;
1654 	__le64                             active_zone_manager_sas_address;
1655 	__le16                             zone_lock_inactivity_limit;
1656 	__le16                             reserved3a;
1657 	u8                                 time_to_reduced_func;
1658 	u8                                 initial_time_to_reduced_func;
1659 	u8                                 max_reduced_func_time;
1660 	u8                                 exp_status;
1661 };
1662 
1663 #define MPI3_SASEXPANDER0_PAGEVERSION                       (0x00)
1664 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY       (0x2000)
1665 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED                 (0x1000)
1666 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES     (0x0800)
1667 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES      (0x0400)
1668 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT              (0x0200)
1669 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING              (0x0100)
1670 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT      (0x0080)
1671 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE        (0x0010)
1672 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG               (0x0004)
1673 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS          (0x0002)
1674 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG          (0x0001)
1675 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING                 (0x02)
1676 #define MPI3_SASEXPANDER0_ES_RESPONDING                     (0x03)
1677 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING           (0x04)
1678 struct mpi3_sas_expander_page1 {
1679 	struct mpi3_config_page_header         header;
1680 	u8                                 io_unit_port;
1681 	u8                                 reserved09[3];
1682 	u8                                 num_phys;
1683 	u8                                 phy;
1684 	__le16                             num_table_entries_programmed;
1685 	u8                                 programmed_link_rate;
1686 	u8                                 hw_link_rate;
1687 	__le16                             attached_dev_handle;
1688 	__le32                             phy_info;
1689 	__le16                             attached_device_info;
1690 	__le16                             reserved1a;
1691 	__le16                             expander_dev_handle;
1692 	u8                                 change_count;
1693 	u8                                 negotiated_link_rate;
1694 	u8                                 phy_identifier;
1695 	u8                                 attached_phy_identifier;
1696 	u8                                 reserved22;
1697 	u8                                 discovery_info;
1698 	__le32                             attached_phy_info;
1699 	u8                                 zone_group;
1700 	u8                                 self_config_status;
1701 	__le16                             reserved2a;
1702 	__le16                             slot;
1703 	__le16                             slot_index;
1704 };
1705 
1706 #define MPI3_SASEXPANDER1_PAGEVERSION                   (0x00)
1707 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED     (0x04)
1708 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
1709 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
1710 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
1711 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS                               (1)
1712 #endif
1713 struct mpi3_sasexpander2_phy_element {
1714 	u8                                 link_change_count;
1715 	u8                                 reserved01;
1716 	__le16                             rate_change_count;
1717 	__le32                             reserved04;
1718 };
1719 
1720 struct mpi3_sas_expander_page2 {
1721 	struct mpi3_config_page_header         header;
1722 	u8                                 num_phys;
1723 	u8                                 reserved09;
1724 	__le16                             dev_handle;
1725 	__le32                             reserved0c;
1726 	struct mpi3_sasexpander2_phy_element   phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
1727 };
1728 
1729 #define MPI3_SASEXPANDER2_PAGEVERSION                   (0x00)
1730 struct mpi3_sas_port_page0 {
1731 	struct mpi3_config_page_header         header;
1732 	u8                                 port_number;
1733 	u8                                 reserved09;
1734 	u8                                 port_width;
1735 	u8                                 reserved0b;
1736 	u8                                 zone_group;
1737 	u8                                 reserved0d[3];
1738 	__le64                             sas_address;
1739 	__le16                             device_info;
1740 	__le16                             reserved1a;
1741 	__le32                             reserved1c;
1742 };
1743 
1744 #define MPI3_SASPORT0_PAGEVERSION                       (0x00)
1745 struct mpi3_sas_phy_page0 {
1746 	struct mpi3_config_page_header         header;
1747 	__le16                             owner_dev_handle;
1748 	__le16                             reserved0a;
1749 	__le16                             attached_dev_handle;
1750 	u8                                 attached_phy_identifier;
1751 	u8                                 reserved0f;
1752 	__le32                             attached_phy_info;
1753 	u8                                 programmed_link_rate;
1754 	u8                                 hw_link_rate;
1755 	u8                                 change_count;
1756 	u8                                 flags;
1757 	__le32                             phy_info;
1758 	u8                                 negotiated_link_rate;
1759 	u8                                 reserved1d[3];
1760 	__le16                             slot;
1761 	__le16                             slot_index;
1762 };
1763 
1764 #define MPI3_SASPHY0_PAGEVERSION                        (0x00)
1765 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC      (0x01)
1766 struct mpi3_sas_phy_page1 {
1767 	struct mpi3_config_page_header         header;
1768 	__le32                             reserved08;
1769 	__le32                             invalid_dword_count;
1770 	__le32                             running_disparity_error_count;
1771 	__le32                             loss_dword_synch_count;
1772 	__le32                             phy_reset_problem_count;
1773 };
1774 
1775 #define MPI3_SASPHY1_PAGEVERSION                        (0x00)
1776 struct mpi3_sas_phy2_phy_event {
1777 	u8         phy_event_code;
1778 	u8         reserved01[3];
1779 	__le32     phy_event_info;
1780 };
1781 
1782 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX
1783 #define MPI3_SAS_PHY2_PHY_EVENT_MAX         (1)
1784 #endif
1785 struct mpi3_sas_phy_page2 {
1786 	struct mpi3_config_page_header         header;
1787 	__le32                             reserved08;
1788 	u8                                 num_phy_events;
1789 	u8                                 reserved0d[3];
1790 	struct mpi3_sas_phy2_phy_event         phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX];
1791 };
1792 
1793 #define MPI3_SASPHY2_PAGEVERSION                        (0x00)
1794 struct mpi3_sas_phy3_phy_event_config {
1795 	u8         phy_event_code;
1796 	u8         reserved01[3];
1797 	u8         counter_type;
1798 	u8         threshold_window;
1799 	u8         time_units;
1800 	u8         reserved07;
1801 	__le32     event_threshold;
1802 	__le16     threshold_flags;
1803 	__le16     reserved0e;
1804 };
1805 
1806 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
1807 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
1808 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
1809 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
1810 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
1811 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
1812 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
1813 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS             (0x07)
1814 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC        (0x08)
1815 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
1816 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
1817 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
1818 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
1819 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
1820 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
1821 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
1822 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
1823 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
1824 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
1825 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION                  (0x2a)
1826 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2b)
1827 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2c)
1828 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2d)
1829 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2e)
1830 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN                (0x2f)
1831 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
1832 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
1833 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
1834 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
1835 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
1836 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
1837 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
1838 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
1839 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
1840 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
1841 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
1842 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
1843 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xd0)
1844 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xd1)
1845 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP                      (0xd2)
1846 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xd3)
1847 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xd4)
1848 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xd5)
1849 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xd6)
1850 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START               (0xd7)
1851 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xd8)
1852 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xd9)
1853 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xda)
1854 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xdb)
1855 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xdc)
1856 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
1857 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
1858 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
1859 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
1860 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
1861 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
1862 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
1863 #define MPI3_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
1864 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
1865 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX
1866 #define MPI3_SAS_PHY3_PHY_EVENT_MAX         (1)
1867 #endif
1868 struct mpi3_sas_phy_page3 {
1869 	struct mpi3_config_page_header         header;
1870 	__le32                             reserved08;
1871 	u8                                 num_phy_events;
1872 	u8                                 reserved0d[3];
1873 	struct mpi3_sas_phy3_phy_event_config  phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX];
1874 };
1875 
1876 #define MPI3_SASPHY3_PAGEVERSION                        (0x00)
1877 struct mpi3_sas_phy_page4 {
1878 	struct mpi3_config_page_header         header;
1879 	u8                                 reserved08[3];
1880 	u8                                 flags;
1881 	u8                                 initial_frame[28];
1882 };
1883 
1884 #define MPI3_SASPHY4_PAGEVERSION                        (0x00)
1885 #define MPI3_SASPHY4_FLAGS_FRAME_VALID                  (0x02)
1886 #define MPI3_SASPHY4_FLAGS_SATA_FRAME                   (0x01)
1887 #define MPI3_PCIE_LINK_RETIMERS_MASK                    (0x30)
1888 #define MPI3_PCIE_LINK_RETIMERS_SHIFT                   (4)
1889 #define MPI3_PCIE_NEG_LINK_RATE_MASK                    (0x0f)
1890 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN                 (0x00)
1891 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED            (0x01)
1892 #define MPI3_PCIE_NEG_LINK_RATE_2_5                     (0x02)
1893 #define MPI3_PCIE_NEG_LINK_RATE_5_0                     (0x03)
1894 #define MPI3_PCIE_NEG_LINK_RATE_8_0                     (0x04)
1895 #define MPI3_PCIE_NEG_LINK_RATE_16_0                    (0x05)
1896 #define MPI3_PCIE_NEG_LINK_RATE_32_0                    (0x06)
1897 #define MPI3_PCIE_ASPM_ENABLE_NONE                      (0x0)
1898 #define MPI3_PCIE_ASPM_ENABLE_L0S                       (0x1)
1899 #define MPI3_PCIE_ASPM_ENABLE_L1                        (0x2)
1900 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1                    (0x3)
1901 #define MPI3_PCIE_ASPM_SUPPORT_NONE                     (0x0)
1902 #define MPI3_PCIE_ASPM_SUPPORT_L0S                      (0x1)
1903 #define MPI3_PCIE_ASPM_SUPPORT_L1                       (0x2)
1904 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1                   (0x3)
1905 struct mpi3_pcie_io_unit0_phy_data {
1906 	u8         link;
1907 	u8         link_flags;
1908 	u8         phy_flags;
1909 	u8         negotiated_link_rate;
1910 	__le16     attached_dev_handle;
1911 	__le16     controller_dev_handle;
1912 	__le32     enumeration_status;
1913 	u8         io_unit_port;
1914 	u8         reserved0d[3];
1915 };
1916 
1917 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK      (0x10)
1918 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1   (0x00)
1919 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE   (0x10)
1920 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS        (0x08)
1921 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED          (0x08)
1922 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY              (0x01)
1923 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED   (0x80000000)
1924 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED       (0x40000000)
1925 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED      (0x20000000)
1926 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES      (0x10000000)
1927 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX
1928 #define MPI3_PCIE_IO_UNIT0_PHY_MAX      (1)
1929 #endif
1930 struct mpi3_pcie_io_unit_page0 {
1931 	struct mpi3_config_page_header         header;
1932 	__le32                             reserved08;
1933 	u8                                 num_phys;
1934 	u8                                 init_status;
1935 	u8                                 aspm;
1936 	u8                                 reserved0f;
1937 	struct mpi3_pcie_io_unit0_phy_data     phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
1938 };
1939 
1940 #define MPI3_PCIEIOUNIT0_PAGEVERSION                        (0x00)
1941 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS               (0x00)
1942 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION    (0x01)
1943 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED    (0x02)
1944 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED   (0x03)
1945 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS            (0x04)
1946 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG      (0x05)
1947 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH      (0x06)
1948 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE    (0x07)
1949 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE       (0x08)
1950 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START         (0xf0)
1951 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END           (0xff)
1952 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK            (0xc0)
1953 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT              (6)
1954 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK            (0x30)
1955 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT              (4)
1956 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK           (0x0c)
1957 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT             (2)
1958 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK           (0x03)
1959 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT             (0)
1960 struct mpi3_pcie_io_unit1_phy_data {
1961 	u8         link;
1962 	u8         link_flags;
1963 	u8         phy_flags;
1964 	u8         max_min_link_rate;
1965 	__le32     reserved04;
1966 	__le32     reserved08;
1967 };
1968 
1969 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK                     (0x03)
1970 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK      (0x00)
1971 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS                  (0x01)
1972 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS                  (0x02)
1973 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                             (0x08)
1974 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK                               (0xf0)
1975 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT                                 (4)
1976 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5                                (0x20)
1977 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0                                (0x30)
1978 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0                                (0x40)
1979 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0                               (0x50)
1980 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0                               (0x60)
1981 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
1982 #define MPI3_PCIE_IO_UNIT1_PHY_MAX                                           (1)
1983 #endif
1984 struct mpi3_pcie_io_unit_page1 {
1985 	struct mpi3_config_page_header         header;
1986 	__le32                             control_flags;
1987 	__le32                             reserved0c;
1988 	u8                                 num_phys;
1989 	u8                                 reserved11;
1990 	u8                                 aspm;
1991 	u8                                 reserved13;
1992 	struct mpi3_pcie_io_unit1_phy_data     phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
1993 };
1994 
1995 #define MPI3_PCIEIOUNIT1_PAGEVERSION                                           (0x00)
1996 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK                     (0xe0000000)
1997 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE                     (0x00000000)
1998 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT                 (0x20000000)
1999 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT                   (0x40000000)
2000 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR          (0x60000000)
2001 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK                    (0x1c000000)
2002 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE                    (0x00000000)
2003 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT                (0x04000000)
2004 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT                  (0x08000000)
2005 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR         (0x0c000000)
2006 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE                   (0x00000080)
2007 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE                  (0x00000040)
2008 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK                (0x00000030)
2009 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT               (4)
2010 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED  (0x00000000)
2011 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED        (0x00000010)
2012 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED        (0x00000020)
2013 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK                 (0x0000000f)
2014 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE        (0x00000000)
2015 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5              (0x00000002)
2016 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0              (0x00000003)
2017 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0              (0x00000004)
2018 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0             (0x00000005)
2019 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0             (0x00000006)
2020 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK                                 (0x0c)
2021 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT                                   (2)
2022 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK                                 (0x03)
2023 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT                                   (0)
2024 struct mpi3_pcie_io_unit_page2 {
2025 	struct mpi3_config_page_header         header;
2026 	__le16                             nvme_max_q_dx1;
2027 	__le16                             nvme_max_q_dx2;
2028 	u8                                 nvme_abort_to;
2029 	u8                                 reserved0d;
2030 	__le16                             nvme_max_q_dx4;
2031 };
2032 
2033 #define MPI3_PCIEIOUNIT2_PAGEVERSION                        (0x00)
2034 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR               (0)
2035 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY                     (1)
2036 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG        (2)
2037 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP                     (3)
2038 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP                      (4)
2039 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX                    (5)
2040 struct mpi3_pcie_io_unit3_error {
2041 	__le16                             threshold_count;
2042 	__le16                             reserved02;
2043 };
2044 
2045 struct mpi3_pcie_io_unit_page3 {
2046 	struct mpi3_config_page_header         header;
2047 	u8                                 threshold_window;
2048 	u8                                 threshold_action;
2049 	u8                                 escalation_count;
2050 	u8                                 escalation_action;
2051 	u8                                 num_errors;
2052 	u8                                 reserved0d[3];
2053 	struct mpi3_pcie_io_unit3_error        error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
2054 };
2055 
2056 #define MPI3_PCIEIOUNIT3_PAGEVERSION                        (0x00)
2057 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION                   (0x00)
2058 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET                   (0x01)
2059 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY       (0x02)
2060 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS  (0x03)
2061 struct mpi3_pcie_switch_page0 {
2062 	struct mpi3_config_page_header     header;
2063 	u8                             io_unit_port;
2064 	u8                             switch_status;
2065 	u8                             reserved0a[2];
2066 	__le16                         dev_handle;
2067 	__le16                         parent_dev_handle;
2068 	u8                             num_ports;
2069 	u8                             pcie_level;
2070 	__le16                         reserved12;
2071 	__le32                         reserved14;
2072 	__le32                         reserved18;
2073 	__le32                         reserved1c;
2074 };
2075 
2076 #define MPI3_PCIESWITCH0_PAGEVERSION                  (0x00)
2077 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING            (0x02)
2078 #define MPI3_PCIESWITCH0_SS_RESPONDING                (0x03)
2079 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING      (0x04)
2080 struct mpi3_pcie_switch_page1 {
2081 	struct mpi3_config_page_header     header;
2082 	u8                             io_unit_port;
2083 	u8                             flags;
2084 	__le16                         reserved0a;
2085 	u8                             num_ports;
2086 	u8                             port_num;
2087 	__le16                         attached_dev_handle;
2088 	__le16                         switch_dev_handle;
2089 	u8                             negotiated_port_width;
2090 	u8                             negotiated_link_rate;
2091 	__le16                         slot;
2092 	__le16                         slot_index;
2093 	__le32                         reserved18;
2094 };
2095 
2096 #define MPI3_PCIESWITCH1_PAGEVERSION        (0x00)
2097 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK     (0x0c)
2098 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT    (2)
2099 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK     (0x03)
2100 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT    (0)
2101 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
2102 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS                               (1)
2103 #endif
2104 struct mpi3_pcieswitch2_port_element {
2105 	__le16                             link_change_count;
2106 	__le16                             rate_change_count;
2107 	__le32                             reserved04;
2108 };
2109 
2110 struct mpi3_pcie_switch_page2 {
2111 	struct mpi3_config_page_header         header;
2112 	u8                                 num_ports;
2113 	u8                                 reserved09;
2114 	__le16                             dev_handle;
2115 	__le32                             reserved0c;
2116 	struct mpi3_pcieswitch2_port_element   port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
2117 };
2118 
2119 #define MPI3_PCIESWITCH2_PAGEVERSION        (0x00)
2120 struct mpi3_pcie_link_page0 {
2121 	struct mpi3_config_page_header     header;
2122 	u8                             link;
2123 	u8                             reserved09[3];
2124 	__le32                         reserved0c;
2125 	__le32                         receiver_error_count;
2126 	__le32                         recovery_count;
2127 	__le32                         corr_error_msg_count;
2128 	__le32                         non_fatal_error_msg_count;
2129 	__le32                         fatal_error_msg_count;
2130 	__le32                         non_fatal_error_count;
2131 	__le32                         fatal_error_count;
2132 	__le32                         bad_dllp_count;
2133 	__le32                         bad_tlp_count;
2134 };
2135 
2136 #define MPI3_PCIELINK0_PAGEVERSION          (0x00)
2137 struct mpi3_enclosure_page0 {
2138 	struct mpi3_config_page_header         header;
2139 	__le64                             enclosure_logical_id;
2140 	__le16                             flags;
2141 	__le16                             enclosure_handle;
2142 	__le16                             num_slots;
2143 	__le16                             reserved16;
2144 	u8                                 io_unit_port;
2145 	u8                                 enclosure_level;
2146 	__le16                             sep_dev_handle;
2147 	u8                                 chassis_slot;
2148 	u8                                 reserved1d[3];
2149 };
2150 
2151 #define MPI3_ENCLOSURE0_PAGEVERSION                     (0x00)
2152 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK                (0xc000)
2153 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL             (0x0000)
2154 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS                 (0x4000)
2155 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE                (0x8000)
2156 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID            (0x0020)
2157 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK         (0x0010)
2158 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND            (0x0000)
2159 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT              (0x0010)
2160 #define MPI3_ENCLS0_FLAGS_MNG_MASK                      (0x000f)
2161 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN                   (0x0000)
2162 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES                   (0x0001)
2163 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE             (0x0002)
2164 #define MPI3_DEVICE_DEVFORM_SAS_SATA                    (0x00)
2165 #define MPI3_DEVICE_DEVFORM_PCIE                        (0x01)
2166 #define MPI3_DEVICE_DEVFORM_VD                          (0x02)
2167 struct mpi3_device0_sas_sata_format {
2168 	__le64     sas_address;
2169 	__le16     flags;
2170 	__le16     device_info;
2171 	u8         phy_num;
2172 	u8         attached_phy_identifier;
2173 	u8         max_port_connections;
2174 	u8         zone_group;
2175 };
2176 
2177 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
2178 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP          (0x0200)
2179 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP          (0x0100)
2180 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY         (0x0080)
2181 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE          (0x0040)
2182 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV           (0x0020)
2183 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA            (0x0010)
2184 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP           (0x0008)
2185 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP             (0x0004)
2186 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP             (0x0002)
2187 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP          (0x0001)
2188 struct mpi3_device0_pcie_format {
2189 	u8         supported_link_rates;
2190 	u8         max_port_width;
2191 	u8         negotiated_port_width;
2192 	u8         negotiated_link_rate;
2193 	u8         port_num;
2194 	u8         controller_reset_to;
2195 	__le16     device_info;
2196 	__le32     maximum_data_transfer_size;
2197 	__le32     capabilities;
2198 	__le16     noiob;
2199 	u8         nvme_abort_to;
2200 	u8         page_size;
2201 	__le16     shutdown_latency;
2202 	u8         recovery_info;
2203 	u8         reserved17;
2204 };
2205 
2206 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP           (0x10)
2207 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP           (0x08)
2208 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP            (0x04)
2209 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP            (0x02)
2210 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP            (0x01)
2211 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK             (0x0007)
2212 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE        (0x0000)
2213 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE      (0x0001)
2214 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE    (0x0002)
2215 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE      (0x0003)
2216 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK             (0x0030)
2217 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT            (4)
2218 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK           (0x00c0)
2219 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT          (6)
2220 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0              (0x0000)
2221 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1              (0x0040)
2222 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2              (0x0080)
2223 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3              (0x00c0)
2224 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED    (0x00000020)
2225 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED            (0x00000010)
2226 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED      (0x00000008)
2227 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL                (0x00000004)
2228 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP                (0x00000000)
2229 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP           (0x00000002)
2230 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP                      (0x00000001)
2231 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK                     (0x000000c0)
2232 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT                    (6)
2233 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK               (0xe0)
2234 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT            (0x00)
2235 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT             (0x20)
2236 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK               (0x1f)
2237 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS              (0x00)
2238 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1          (0x01)
2239 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS        (0x02)
2240 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION         (0x03)
2241 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ        (0x04)
2242 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ        (0x05)
2243 struct mpi3_device0_vd_format {
2244 	u8         vd_state;
2245 	u8         raid_level;
2246 	__le16     device_info;
2247 	__le16     flags;
2248 	__le16     io_throttle_group;
2249 	__le16     io_throttle_group_low;
2250 	__le16     io_throttle_group_high;
2251 	__le32     reserved0c;
2252 };
2253 #define MPI3_DEVICE0_VD_STATE_OFFLINE                       (0x00)
2254 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED            (0x01)
2255 #define MPI3_DEVICE0_VD_STATE_DEGRADED                      (0x02)
2256 #define MPI3_DEVICE0_VD_STATE_OPTIMAL                       (0x03)
2257 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0                    (0)
2258 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1                    (1)
2259 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5                    (5)
2260 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6                    (6)
2261 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10                   (10)
2262 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50                   (50)
2263 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60                   (60)
2264 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD                     (0x0010)
2265 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD                     (0x0008)
2266 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME                    (0x0004)
2267 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA                    (0x0002)
2268 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS                     (0x0001)
2269 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK     (0xf000)
2270 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT    (12)
2271 union mpi3_device0_dev_spec_format {
2272 	struct mpi3_device0_sas_sata_format        sas_sata_format;
2273 	struct mpi3_device0_pcie_format            pcie_format;
2274 	struct mpi3_device0_vd_format              vd_format;
2275 };
2276 
2277 struct mpi3_device_page0 {
2278 	struct mpi3_config_page_header         header;
2279 	__le16                             dev_handle;
2280 	__le16                             parent_dev_handle;
2281 	__le16                             slot;
2282 	__le16                             enclosure_handle;
2283 	__le64                             wwid;
2284 	__le16                             persistent_id;
2285 	u8                                 io_unit_port;
2286 	u8                                 access_status;
2287 	__le16                             flags;
2288 	__le16                             reserved1e;
2289 	__le16                             slot_index;
2290 	__le16                             queue_depth;
2291 	u8                                 reserved24[3];
2292 	u8                                 device_form;
2293 	union mpi3_device0_dev_spec_format    device_specific;
2294 };
2295 
2296 #define MPI3_DEVICE0_PAGEVERSION                        (0x00)
2297 #define MPI3_DEVICE0_PARENT_INVALID                     (0xffff)
2298 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE      (0x0000)
2299 #define MPI3_DEVICE0_WWID_INVALID                       (0xffffffffffffffff)
2300 #define MPI3_DEVICE0_PERSISTENTID_INVALID               (0xffff)
2301 #define MPI3_DEVICE0_IOUNITPORT_INVALID                 (0xff)
2302 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS                              (0x00)
2303 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION                   (0x01)
2304 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED                        (0x02)
2305 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED                         (0x03)
2306 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED                           (0x04)
2307 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY                   (0x05)
2308 #define MPI3_DEVICE0_ASTATUS_PREPARE                                (0x06)
2309 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE                              (0x07)
2310 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX                            (0x0f)
2311 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN                            (0x10)
2312 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE                  (0x11)
2313 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE              (0x12)
2314 #define MPI3_DEVICE0_ASTATUS_SAS_MAX                                (0x1f)
2315 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN                            (0x20)
2316 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT               (0x21)
2317 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG                               (0x22)
2318 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION                     (0x23)
2319 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER                        (0x24)
2320 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN                             (0x25)
2321 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN                            (0x26)
2322 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN                            (0x27)
2323 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION                   (0x28)
2324 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE                    (0x29)
2325 #define MPI3_DEVICE0_ASTATUS_SIF_MAX                                (0x2f)
2326 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN                           (0x30)
2327 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS                  (0x31)
2328 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED                       (0x32)
2329 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED                     (0x33)
2330 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED                     (0x34)
2331 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX                               (0x3f)
2332 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN                           (0x40)
2333 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT                     (0x41)
2334 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED                (0x42)
2335 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED                   (0x43)
2336 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED                    (0x44)
2337 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED                  (0x45)
2338 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED                   (0x46)
2339 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED           (0x47)
2340 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT                      (0x48)
2341 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS               (0x49)
2342 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER                (0x4a)
2343 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE                   (0x4b)
2344 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE                 (0x4c)
2345 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION                 (0x4d)
2346 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME                   (0x4e)
2347 #define MPI3_DEVICE0_ASTATUS_NVME_BAR                               (0x4f)
2348 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR                     (0x50)
2349 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS             (0x51)
2350 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS                   (0x52)
2351 #define MPI3_DEVICE0_ASTATUS_NVME_MAX                               (0x5f)
2352 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN                             (0x80)
2353 #define MPI3_DEVICE0_ASTATUS_VD_MAX                                 (0x8f)
2354 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE        (0x0080)
2355 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED       (0x0010)
2356 #define MPI3_DEVICE0_FLAGS_HIDDEN                       (0x0008)
2357 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL           (0x0004)
2358 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED      (0x0002)
2359 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2360 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE         (0x0000)
2361 struct mpi3_device1_sas_sata_format {
2362 	__le32                             reserved00;
2363 };
2364 struct mpi3_device1_pcie_format {
2365 	__le16                             vendor_id;
2366 	__le16                             device_id;
2367 	__le16                             subsystem_vendor_id;
2368 	__le16                             subsystem_id;
2369 	__le32                             reserved08;
2370 	u8                                 revision_id;
2371 	u8                                 reserved0d;
2372 	__le16                             pci_parameters;
2373 };
2374 
2375 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B              (0x0)
2376 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B              (0x1)
2377 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B              (0x2)
2378 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B             (0x3)
2379 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B             (0x4)
2380 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B             (0x5)
2381 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK           (0x01c0)
2382 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT          (6)
2383 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK       (0x0038)
2384 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT      (3)
2385 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK       (0x0007)
2386 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT      (0)
2387 struct mpi3_device1_vd_format {
2388 	__le32                             reserved00;
2389 };
2390 
2391 union mpi3_device1_dev_spec_format {
2392 	struct mpi3_device1_sas_sata_format    sas_sata_format;
2393 	struct mpi3_device1_pcie_format        pcie_format;
2394 	struct mpi3_device1_vd_format          vd_format;
2395 };
2396 
2397 struct mpi3_device_page1 {
2398 	struct mpi3_config_page_header         header;
2399 	__le16                             dev_handle;
2400 	__le16                             reserved0a;
2401 	__le16                             link_change_count;
2402 	__le16                             rate_change_count;
2403 	__le16                             tm_count;
2404 	__le16                             reserved12;
2405 	__le32                             reserved14[10];
2406 	u8                                 reserved3c[3];
2407 	u8                                 device_form;
2408 	union mpi3_device1_dev_spec_format    device_specific;
2409 };
2410 
2411 #define MPI3_DEVICE1_PAGEVERSION                            (0x00)
2412 #define MPI3_DEVICE1_COUNTER_MAX                            (0xfffe)
2413 #define MPI3_DEVICE1_COUNTER_INVALID                        (0xffff)
2414 #endif
2415