1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2017-2021 Broadcom Inc. All rights reserved. 4 * 5 */ 6 #ifndef MPI30_CNFG_H 7 #define MPI30_CNFG_H 1 8 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 9 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 10 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 11 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 12 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 13 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 14 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 15 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 16 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 17 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 18 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 19 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 20 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 21 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 22 #define MPI3_CONFIG_PAGEATTR_MASK (0xf0) 23 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 24 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 25 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 26 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 27 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 28 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 29 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 30 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 31 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 32 #define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000) 33 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 34 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 35 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff) 36 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000) 37 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 39 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000) 41 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 42 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff) 43 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000) 44 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 45 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff) 46 #define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000) 47 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 48 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 49 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff) 50 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000) 51 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 52 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 53 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff) 54 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000) 55 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 57 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000) 59 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 60 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff) 61 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000) 62 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 63 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 64 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff) 65 #define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000) 66 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 67 #define MPI3_SECURITY_PGAD_FORM_SOT_NUM (0x10000000) 68 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00) 69 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff) 70 struct mpi3_config_request { 71 __le16 host_tag; 72 u8 ioc_use_only02; 73 u8 function; 74 __le16 ioc_use_only04; 75 u8 ioc_use_only06; 76 u8 msg_flags; 77 __le16 change_count; 78 __le16 reserved0a; 79 u8 page_version; 80 u8 page_number; 81 u8 page_type; 82 u8 action; 83 __le32 page_address; 84 __le16 page_length; 85 __le16 reserved16; 86 __le32 reserved18[2]; 87 union mpi3_sge_union sgl; 88 }; 89 90 struct mpi3_config_page_header { 91 u8 page_version; 92 u8 reserved01; 93 u8 page_number; 94 u8 page_attribute; 95 __le16 page_length; 96 u8 page_type; 97 u8 reserved07; 98 }; 99 100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0) 101 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f) 103 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 104 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 105 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 106 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 107 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 108 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 109 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 110 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 111 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 112 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a) 113 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b) 114 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c) 115 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 116 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 117 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 118 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f) 119 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 120 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 121 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 122 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 123 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 124 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 125 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 126 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 127 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 128 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 129 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000) 130 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 131 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 132 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 133 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 134 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 138 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000) 139 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 140 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 141 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 142 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 143 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 144 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 145 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 146 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 147 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 148 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 149 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 150 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 151 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 152 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00) 153 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 154 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0) 155 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 156 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 157 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 158 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0) 159 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 160 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 161 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 162 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0) 163 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0) 164 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0) 165 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f) 166 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 167 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 168 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 169 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a) 170 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b) 171 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c) 172 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0) 173 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 174 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 175 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0) 176 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0) 177 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0) 178 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f) 179 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 180 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 181 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a) 182 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b) 183 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c) 184 #define MPI3_SLOT_INVALID (0xffff) 185 #define MPI3_SLOT_INDEX_INVALID (0xffff) 186 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xffff) 187 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xffff) 188 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 189 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 190 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 191 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 192 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 193 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5) 194 struct mpi3_man_page0 { 195 struct mpi3_config_page_header header; 196 u8 chip_revision[8]; 197 u8 chip_name[32]; 198 u8 board_name[32]; 199 u8 board_assembly[32]; 200 u8 board_tracer_number[32]; 201 __le32 board_power; 202 __le32 reserved94; 203 __le32 reserved98; 204 u8 oem; 205 u8 profile_identifier; 206 __le16 flags; 207 u8 board_mfg_day; 208 u8 board_mfg_month; 209 __le16 board_mfg_year; 210 u8 board_rework_day; 211 u8 board_rework_month; 212 __le16 board_rework_year; 213 __le64 board_revision; 214 u8 e_pack_fru[16]; 215 u8 product_name[256]; 216 }; 217 218 #define MPI3_MAN0_PAGEVERSION (0x00) 219 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 220 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 221 #define MPI3_MAN1_VPD_SIZE (512) 222 struct mpi3_man_page1 { 223 struct mpi3_config_page_header header; 224 __le32 reserved08[2]; 225 u8 vpd[MPI3_MAN1_VPD_SIZE]; 226 }; 227 228 #define MPI3_MAN1_PAGEVERSION (0x00) 229 struct mpi3_man5_phy_entry { 230 __le64 ioc_wwid; 231 __le64 device_name; 232 __le64 sata_wwid; 233 }; 234 235 #ifndef MPI3_MAN5_PHY_MAX 236 #define MPI3_MAN5_PHY_MAX (1) 237 #endif 238 struct mpi3_man_page5 { 239 struct mpi3_config_page_header header; 240 u8 num_phys; 241 u8 reserved09[3]; 242 __le32 reserved0c; 243 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX]; 244 }; 245 246 #define MPI3_MAN5_PAGEVERSION (0x00) 247 struct mpi3_man6_gpio_entry { 248 u8 function_code; 249 u8 function_flags; 250 __le16 flags; 251 u8 param1; 252 u8 param2; 253 __le16 reserved06; 254 __le32 param3; 255 }; 256 257 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 258 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 259 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 260 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 261 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 262 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 263 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 264 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 265 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 266 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a) 267 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b) 268 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c) 269 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0d) 270 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e) 271 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f) 272 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 273 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 274 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 275 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 276 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 277 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 278 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 279 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 280 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 281 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 282 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 283 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 284 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0) 285 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 286 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 287 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 288 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 289 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 290 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 291 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 292 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 293 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 294 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 295 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 296 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 297 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 298 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 299 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 300 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0) 301 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 302 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 303 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 304 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0) 305 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 306 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 307 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 308 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 309 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 310 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 311 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 312 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 313 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 314 #ifndef MPI3_MAN6_GPIO_MAX 315 #define MPI3_MAN6_GPIO_MAX (1) 316 #endif 317 struct mpi3_man_page6 { 318 struct mpi3_config_page_header header; 319 __le16 flags; 320 __le16 reserved0a; 321 u8 num_gpio; 322 u8 reserved0d[3]; 323 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX]; 324 }; 325 326 #define MPI3_MAN6_PAGEVERSION (0x00) 327 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 328 struct mpi3_man7_receptacle_info { 329 __le32 name[4]; 330 u8 location; 331 u8 connector_type; 332 u8 ped_clk; 333 u8 connector_id; 334 __le32 reserved14; 335 }; 336 337 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 338 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 339 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 340 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 341 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 342 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 343 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 344 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0f) 345 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 346 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 347 #endif 348 struct mpi3_man_page7 { 349 struct mpi3_config_page_header header; 350 __le32 flags; 351 u8 num_receptacles; 352 u8 reserved0d[3]; 353 __le32 enclosure_name[4]; 354 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX]; 355 }; 356 357 #define MPI3_MAN7_PAGEVERSION (0x00) 358 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 359 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 360 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 361 struct mpi3_man8_phy_info { 362 u8 receptacle_id; 363 u8 connector_lane; 364 __le16 reserved02; 365 __le16 slotx1; 366 __le16 slotx2; 367 __le16 slotx4; 368 __le16 reserved0a; 369 __le32 reserved0c; 370 }; 371 372 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_HOST_PHY (0xff) 373 #ifndef MPI3_MAN8_PHY_INFO_MAX 374 #define MPI3_MAN8_PHY_INFO_MAX (1) 375 #endif 376 struct mpi3_man_page8 { 377 struct mpi3_config_page_header header; 378 __le32 reserved08; 379 u8 num_phys; 380 u8 reserved0d[3]; 381 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX]; 382 }; 383 384 #define MPI3_MAN8_PAGEVERSION (0x00) 385 struct mpi3_man9_rsrc_entry { 386 __le32 maximum; 387 __le32 decrement; 388 __le32 minimum; 389 __le32 actual; 390 }; 391 392 enum mpi3_man9_resources { 393 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 394 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 395 MPI3_MAN9_RSRC_RESERVED02 = 2, 396 MPI3_MAN9_RSRC_NVME = 3, 397 MPI3_MAN9_RSRC_INITIATORS = 4, 398 MPI3_MAN9_RSRC_VDS = 5, 399 MPI3_MAN9_RSRC_ENCLOSURES = 6, 400 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 401 MPI3_MAN9_RSRC_EXPANDERS = 8, 402 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 403 MPI3_MAN9_RSRC_RESERVED10 = 10, 404 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 405 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 406 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 407 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 408 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 409 MPI3_MAN9_RSRC_NUM_RESOURCES 410 }; 411 412 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 413 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 414 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 415 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 416 #define MPI3_MAN9_MIN_NVME_TARGETS (0) 417 #define MPI3_MAN9_MIN_INITIATORS (0) 418 #define MPI3_MAN9_MIN_VDS (0) 419 #define MPI3_MAN9_MIN_ENCLOSURES (1) 420 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 421 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 422 #define MPI3_MAN9_MIN_EXPANDERS (0) 423 #define MPI3_MAN9_MAX_EXPANDERS (65535) 424 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 425 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 426 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 427 #define MPI3_MAN9_RAID_PD_DRIVES (0) 428 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 429 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 430 #define MPI3_MAN9_MIN_EXPANDERS (0) 431 #define MPI3_MAN9_MAX_EXPANDERS (65535) 432 struct mpi3_man_page9 { 433 struct mpi3_config_page_header header; 434 u8 num_resources; 435 u8 reserved09; 436 __le16 reserved0a; 437 __le32 reserved0c; 438 __le32 reserved10; 439 __le32 reserved14; 440 __le32 reserved18; 441 __le32 reserved1c; 442 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; 443 }; 444 445 #define MPI3_MAN9_PAGEVERSION (0x00) 446 struct mpi3_man10_istwi_ctrlr_entry { 447 __le16 slave_address; 448 __le16 flags; 449 u8 scl_low_override; 450 u8 scl_high_override; 451 __le16 reserved06; 452 }; 453 454 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c) 455 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000) 456 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004) 457 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED (0x0002) 458 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED (0x0001) 459 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 460 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 461 #endif 462 struct mpi3_man_page10 { 463 struct mpi3_config_page_header header; 464 __le32 reserved08; 465 u8 num_istwi_ctrl; 466 u8 reserved0d[3]; 467 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX]; 468 }; 469 470 #define MPI3_MAN10_PAGEVERSION (0x00) 471 struct mpi3_man11_mux_device_format { 472 u8 max_channel; 473 u8 reserved01[3]; 474 __le32 reserved04; 475 }; 476 477 struct mpi3_man11_temp_sensor_device_format { 478 u8 type; 479 u8 reserved01[3]; 480 u8 temp_channel[4]; 481 }; 482 483 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 484 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 485 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 486 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 487 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xe0) 488 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 489 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 490 struct mpi3_man11_seeprom_device_format { 491 u8 size; 492 u8 page_write_size; 493 __le16 reserved02; 494 __le32 reserved04; 495 }; 496 497 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 498 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 499 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 500 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 501 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 502 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 503 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 504 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 505 struct mpi3_man11_ddr_spd_device_format { 506 u8 channel; 507 u8 reserved01[3]; 508 __le32 reserved04; 509 }; 510 511 struct mpi3_man11_cable_mgmt_device_format { 512 u8 type; 513 u8 receptacle_id; 514 __le16 reserved02; 515 __le32 reserved04; 516 }; 517 518 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 519 struct mpi3_man11_bkplane_spec_ubm_format { 520 __le16 flags; 521 __le16 reserved02; 522 }; 523 524 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 525 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 526 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0) 527 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 528 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 529 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 530 struct mpi3_man11_bkplane_spec_non_ubm_format { 531 __le16 flags; 532 u8 reserved02; 533 u8 type; 534 }; 535 536 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000) 537 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 538 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 539 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 540 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 541 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 542 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 543 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 544 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 545 union mpi3_man11_bkplane_spec_format { 546 struct mpi3_man11_bkplane_spec_ubm_format ubm; 547 struct mpi3_man11_bkplane_spec_non_ubm_format non_ubm; 548 }; 549 550 struct mpi3_man11_bkplane_mgmt_device_format { 551 u8 type; 552 u8 receptacle_id; 553 u8 reset_info; 554 u8 reserved03; 555 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific; 556 }; 557 558 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 559 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 560 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xf0) 561 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 562 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0f) 563 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 564 struct mpi3_man11_gas_gauge_device_format { 565 u8 type; 566 u8 reserved01[3]; 567 __le32 reserved04; 568 }; 569 570 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 571 struct mpi3_man11_mgmt_ctrlr_device_format { 572 __le32 reserved00; 573 __le32 reserved04; 574 }; 575 struct mpi3_man11_board_fan_device_format { 576 u8 flags; 577 u8 reserved01; 578 u8 min_fan_speed; 579 u8 max_fan_speed; 580 __le32 reserved04; 581 }; 582 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 583 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 584 union mpi3_man11_device_specific_format { 585 struct mpi3_man11_mux_device_format mux; 586 struct mpi3_man11_temp_sensor_device_format temp_sensor; 587 struct mpi3_man11_seeprom_device_format seeprom; 588 struct mpi3_man11_ddr_spd_device_format ddr_spd; 589 struct mpi3_man11_cable_mgmt_device_format cable_mgmt; 590 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt; 591 struct mpi3_man11_gas_gauge_device_format gas_gauge; 592 struct mpi3_man11_mgmt_ctrlr_device_format mgmt_controller; 593 struct mpi3_man11_board_fan_device_format board_fan; 594 __le32 words[2]; 595 }; 596 struct mpi3_man11_istwi_device_format { 597 u8 device_type; 598 u8 controller; 599 u8 reserved02; 600 u8 flags; 601 __le16 device_address; 602 u8 mux_channel; 603 u8 mux_index; 604 union mpi3_man11_device_specific_format device_specific; 605 }; 606 607 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 608 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 609 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 610 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 611 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 612 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 613 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 614 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 615 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 616 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 617 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 618 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 619 #endif 620 struct mpi3_man_page11 { 621 struct mpi3_config_page_header header; 622 __le32 reserved08; 623 u8 num_istwi_dev; 624 u8 reserved0d[3]; 625 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX]; 626 }; 627 628 #define MPI3_MAN11_PAGEVERSION (0x00) 629 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 630 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 631 #endif 632 struct mpi3_man12_sgpio_info { 633 u8 slot_count; 634 u8 reserved01[3]; 635 __le32 reserved04; 636 u8 phy_order[32]; 637 }; 638 639 struct mpi3_man_page12 { 640 struct mpi3_config_page_header header; 641 __le32 flags; 642 __le32 s_clock_freq; 643 __le32 activity_modulation; 644 u8 num_sgpio; 645 u8 reserved15[3]; 646 __le32 reserved18; 647 __le32 reserved1c; 648 __le32 pattern[8]; 649 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX]; 650 }; 651 652 #define MPI3_MAN12_PAGEVERSION (0x00) 653 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 654 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 655 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 656 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 657 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 658 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 659 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 660 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 661 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 662 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 663 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) 664 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) 665 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000) 666 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 667 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00) 668 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 669 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0) 670 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 671 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f) 672 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 673 #define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000) 674 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 675 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 676 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 677 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 678 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 679 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000) 680 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000) 681 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000) 682 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 683 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff) 684 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 685 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 686 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 687 #endif 688 struct mpi3_man13_translation_info { 689 __le32 slot_status; 690 __le32 mask; 691 u8 activity; 692 u8 locate; 693 u8 error; 694 u8 reserved0b; 695 }; 696 697 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 698 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 699 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 700 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 701 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 702 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 703 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 704 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 705 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 706 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 707 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 708 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 709 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 710 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 711 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 712 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 713 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 714 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 715 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 716 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 717 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 718 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 719 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 720 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 721 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 722 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 723 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 724 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a) 725 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b) 726 struct mpi3_man_page13 { 727 struct mpi3_config_page_header header; 728 u8 num_trans; 729 u8 reserved09[3]; 730 __le32 reserved0c; 731 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; 732 }; 733 734 #define MPI3_MAN13_PAGEVERSION (0x00) 735 struct mpi3_man_page14 { 736 struct mpi3_config_page_header header; 737 __le32 reserved08; 738 u8 num_slot_groups; 739 u8 num_slots; 740 __le16 max_cert_chain_length; 741 __le32 sealed_slots; 742 __le32 populated_slots; 743 __le32 mgmt_pt_updatable_slots; 744 }; 745 #define MPI3_MAN14_PAGEVERSION (0x00) 746 #define MPI3_MAN14_NUMSLOTS_MAX (32) 747 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 748 #define MPI3_MAN15_VERSION_RECORD_MAX 1 749 #endif 750 struct mpi3_man15_version_record { 751 __le16 spdm_version; 752 __le16 reserved02; 753 }; 754 755 struct mpi3_man_page15 { 756 struct mpi3_config_page_header header; 757 u8 num_version_records; 758 u8 reserved09[3]; 759 __le32 reserved0c; 760 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX]; 761 }; 762 763 #define MPI3_MAN15_PAGEVERSION (0x00) 764 #ifndef MPI3_MAN16_CERT_ALGO_MAX 765 #define MPI3_MAN16_CERT_ALGO_MAX 1 766 #endif 767 struct mpi3_man16_certificate_algorithm { 768 u8 slot_group; 769 u8 reserved01[3]; 770 __le32 base_asym_algo; 771 __le32 base_hash_algo; 772 __le32 reserved0c[3]; 773 }; 774 775 struct mpi3_man_page16 { 776 struct mpi3_config_page_header header; 777 __le32 reserved08; 778 u8 num_cert_algos; 779 u8 reserved0d[3]; 780 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX]; 781 }; 782 783 #define MPI3_MAN16_PAGEVERSION (0x00) 784 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 785 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 786 #endif 787 struct mpi3_man17_hash_algorithm { 788 u8 meas_specification; 789 u8 reserved01[3]; 790 __le32 measurement_hash_algo; 791 __le32 reserved08[2]; 792 }; 793 794 struct mpi3_man_page17 { 795 struct mpi3_config_page_header header; 796 __le32 reserved08; 797 u8 num_hash_algos; 798 u8 reserved0d[3]; 799 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; 800 }; 801 802 #define MPI3_MAN17_PAGEVERSION (0x00) 803 struct mpi3_man_page20 { 804 struct mpi3_config_page_header header; 805 __le32 reserved08; 806 __le32 nonpremium_features; 807 u8 allowed_personalities; 808 u8 reserved11[3]; 809 }; 810 811 #define MPI3_MAN20_PAGEVERSION (0x00) 812 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 813 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 814 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 815 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 816 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 817 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 818 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 819 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 820 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 821 struct mpi3_man_page21 { 822 struct mpi3_config_page_header header; 823 __le32 reserved08; 824 __le32 flags; 825 }; 826 827 #define MPI3_MAN21_PAGEVERSION (0x00) 828 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_MASK (0x80) 829 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_ENABLED (0x80) 830 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_DISABLED (0x00) 831 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x60) 832 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00) 833 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x20) 834 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x40) 835 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x08) 836 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00) 837 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x08) 838 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x01) 839 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00) 840 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x01) 841 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 842 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 843 #endif 844 struct mpi3_man_page_product_specific { 845 struct mpi3_config_page_header header; 846 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX]; 847 }; 848 849 struct mpi3_io_unit_page0 { 850 struct mpi3_config_page_header header; 851 __le64 unique_value; 852 __le32 nvdata_version_default; 853 __le32 nvdata_version_persistent; 854 }; 855 856 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 857 struct mpi3_io_unit_page1 { 858 struct mpi3_config_page_header header; 859 __le32 flags; 860 u8 dmd_io_delay; 861 u8 dmd_report_pcie; 862 u8 dmd_report_sata; 863 u8 dmd_report_sas; 864 }; 865 866 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 867 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 868 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 869 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 870 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 871 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 872 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 873 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 874 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 875 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 876 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 877 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f) 878 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 879 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 880 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 881 #endif 882 struct mpi3_io_unit_page2 { 883 struct mpi3_config_page_header header; 884 u8 gpio_count; 885 u8 reserved09[3]; 886 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX]; 887 }; 888 889 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 890 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc) 891 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 892 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 893 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 894 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 895 struct mpi3_io_unit3_sensor { 896 __le16 flags; 897 u8 threshold_margin; 898 u8 reserved03; 899 __le16 threshold[3]; 900 __le16 reserved0a; 901 __le32 reserved0c; 902 __le32 reserved10; 903 __le32 reserved14; 904 }; 905 906 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 907 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 908 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 909 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 910 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 911 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 912 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 913 #endif 914 struct mpi3_io_unit_page3 { 915 struct mpi3_config_page_header header; 916 __le32 reserved08; 917 u8 num_sensors; 918 u8 nominal_poll_interval; 919 u8 warning_poll_interval; 920 u8 reserved0f; 921 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX]; 922 }; 923 924 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 925 struct mpi3_io_unit4_sensor { 926 __le16 current_temperature; 927 __le16 reserved02; 928 u8 flags; 929 u8 reserved05[3]; 930 __le16 istwi_index; 931 u8 channel; 932 u8 reserved0b; 933 __le32 reserved0c; 934 }; 935 936 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xe0) 937 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 938 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 939 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xffff) 940 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xff) 941 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 942 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 943 #endif 944 struct mpi3_io_unit_page4 { 945 struct mpi3_config_page_header header; 946 __le32 reserved08; 947 u8 num_sensors; 948 u8 reserved0d[3]; 949 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX]; 950 }; 951 952 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 953 struct mpi3_io_unit5_spinup_group { 954 u8 max_target_spinup; 955 u8 spinup_delay; 956 u8 spinup_flags; 957 u8 reserved03; 958 }; 959 960 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 961 #ifndef MPI3_IO_UNIT5_PHY_MAX 962 #define MPI3_IO_UNIT5_PHY_MAX (4) 963 #endif 964 struct mpi3_io_unit_page5 { 965 struct mpi3_config_page_header header; 966 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4]; 967 __le32 reserved18; 968 __le32 reserved1c; 969 __le16 device_shutdown; 970 __le16 reserved22; 971 u8 pcie_device_wait_time; 972 u8 sata_device_wait_time; 973 u8 spinup_encl_drive_count; 974 u8 spinup_encl_delay; 975 u8 num_phys; 976 u8 pe_initial_spinup_delay; 977 u8 topology_stable_time; 978 u8 flags; 979 u8 phy[MPI3_IO_UNIT5_PHY_MAX]; 980 }; 981 982 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 983 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 984 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 985 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 986 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 987 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 988 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 989 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 990 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 991 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00c0) 992 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 993 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 994 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 995 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c) 996 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 997 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 998 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAA_SSD_SHIFT (0) 999 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1000 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1001 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1002 struct mpi3_io_unit_page6 { 1003 struct mpi3_config_page_header header; 1004 __le32 board_power_requirement; 1005 __le32 pci_slot_power_allocation; 1006 u8 flags; 1007 u8 reserved11[3]; 1008 }; 1009 1010 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 1011 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1012 #ifndef MPI3_IOUNIT8_DIGEST_MAX 1013 #define MPI3_IOUNIT8_DIGEST_MAX (1) 1014 #endif 1015 union mpi3_iounit8_digest { 1016 __le32 dword[16]; 1017 __le16 word[32]; 1018 u8 byte[64]; 1019 }; 1020 1021 struct mpi3_io_unit_page8 { 1022 struct mpi3_config_page_header header; 1023 u8 sb_mode; 1024 u8 sb_state; 1025 __le16 reserved0a; 1026 u8 num_slots; 1027 u8 slots_available; 1028 u8 current_key_encryption_algo; 1029 u8 key_digest_hash_algo; 1030 __le32 reserved10[2]; 1031 __le32 current_key[128]; 1032 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX]; 1033 }; 1034 1035 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 1036 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1037 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1038 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1039 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1040 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1041 struct mpi3_io_unit_page9 { 1042 struct mpi3_config_page_header header; 1043 __le32 flags; 1044 __le16 first_device; 1045 __le16 reserved0e; 1046 }; 1047 1048 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 1049 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x01) 1050 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff) 1051 struct mpi3_io_unit_page10 { 1052 struct mpi3_config_page_header header; 1053 u8 flags; 1054 u8 reserved09[3]; 1055 __le32 silicon_id; 1056 u8 fw_version_minor; 1057 u8 fw_version_major; 1058 u8 hw_version_minor; 1059 u8 hw_version_major; 1060 u8 part_number[16]; 1061 }; 1062 #define MPI3_IOUNIT10_PAGEVERSION (0x00) 1063 #define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1064 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1065 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1066 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1067 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1068 #ifndef MPI3_IOUNIT11_PROFILE_MAX 1069 #define MPI3_IOUNIT11_PROFILE_MAX (1) 1070 #endif 1071 struct mpi3_iounit11_profile { 1072 u8 profile_identifier; 1073 u8 reserved01[3]; 1074 __le16 max_vds; 1075 __le16 max_host_pds; 1076 __le16 max_adv_host_pds; 1077 __le16 max_raid_pds; 1078 __le16 max_nvme; 1079 __le16 max_outstanding_requests; 1080 __le16 subsystem_id; 1081 __le16 reserved12; 1082 __le32 reserved14[2]; 1083 }; 1084 struct mpi3_io_unit_page11 { 1085 struct mpi3_config_page_header header; 1086 __le32 reserved08; 1087 u8 num_profiles; 1088 u8 current_profile_identifier; 1089 __le16 reserved0e; 1090 struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX]; 1091 }; 1092 #define MPI3_IOUNIT11_PAGEVERSION (0x00) 1093 struct mpi3_ioc_page0 { 1094 struct mpi3_config_page_header header; 1095 __le32 reserved08; 1096 __le16 vendor_id; 1097 __le16 device_id; 1098 u8 revision_id; 1099 u8 reserved11[3]; 1100 __le32 class_code; 1101 __le16 subsystem_vendor_id; 1102 __le16 subsystem_id; 1103 }; 1104 1105 #define MPI3_IOC0_PAGEVERSION (0x00) 1106 struct mpi3_ioc_page1 { 1107 struct mpi3_config_page_header header; 1108 __le32 coalescing_timeout; 1109 u8 coalescing_depth; 1110 u8 obsolete; 1111 __le16 reserved0e; 1112 }; 1113 #define MPI3_IOC1_PAGEVERSION (0x00) 1114 #ifndef MPI3_IOC2_EVENTMASK_WORDS 1115 #define MPI3_IOC2_EVENTMASK_WORDS (4) 1116 #endif 1117 struct mpi3_ioc_page2 { 1118 struct mpi3_config_page_header header; 1119 __le32 reserved08; 1120 __le16 sas_broadcast_primitive_masks; 1121 __le16 sas_notify_primitive_masks; 1122 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS]; 1123 }; 1124 1125 #define MPI3_IOC2_PAGEVERSION (0x00) 1126 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 1127 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 1128 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 1129 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 1130 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 1131 struct mpi3_allowed_cmd_scsi { 1132 __le16 service_action; 1133 u8 operation_code; 1134 u8 command_flags; 1135 }; 1136 1137 struct mpi3_allowed_cmd_ata { 1138 u8 subcommand; 1139 u8 reserved01; 1140 u8 command; 1141 u8 command_flags; 1142 }; 1143 1144 struct mpi3_allowed_cmd_nvme { 1145 u8 reserved00; 1146 u8 nvme_cmd_flags; 1147 u8 op_code; 1148 u8 command_flags; 1149 }; 1150 1151 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 1152 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 1153 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 1154 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3f) 1155 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 1156 union mpi3_allowed_cmd { 1157 struct mpi3_allowed_cmd_scsi scsi; 1158 struct mpi3_allowed_cmd_ata ata; 1159 struct mpi3_allowed_cmd_nvme nvme; 1160 }; 1161 1162 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 1163 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 1164 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 1165 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 1166 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 1167 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 1168 #ifndef MPI3_ALLOWED_CMDS_MAX 1169 #define MPI3_ALLOWED_CMDS_MAX (1) 1170 #endif 1171 struct mpi3_driver_page0 { 1172 struct mpi3_config_page_header header; 1173 __le32 bsd_options; 1174 u8 ssu_timeout; 1175 u8 io_timeout; 1176 u8 tur_retries; 1177 u8 tur_interval; 1178 u8 reserved10; 1179 u8 security_key_timeout; 1180 __le16 reserved12; 1181 __le32 reserved14; 1182 __le32 reserved18; 1183 }; 1184 #define MPI3_DRIVER0_PAGEVERSION (0x00) 1185 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 1186 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 1187 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 1188 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 1189 struct mpi3_driver_page1 { 1190 struct mpi3_config_page_header header; 1191 __le32 flags; 1192 __le32 reserved0c; 1193 __le16 host_diag_trace_max_size; 1194 __le16 host_diag_trace_min_size; 1195 __le16 host_diag_trace_decrement_size; 1196 __le16 reserved16; 1197 __le16 host_diag_fw_max_size; 1198 __le16 host_diag_fw_min_size; 1199 __le16 host_diag_fw_decrement_size; 1200 __le16 reserved1e; 1201 __le16 host_diag_driver_max_size; 1202 __le16 host_diag_driver_min_size; 1203 __le16 host_diag_driver_decrement_size; 1204 __le16 reserved26; 1205 }; 1206 1207 #define MPI3_DRIVER1_PAGEVERSION (0x00) 1208 #ifndef MPI3_DRIVER2_TRIGGER_MAX 1209 #define MPI3_DRIVER2_TRIGGER_MAX (1) 1210 #endif 1211 struct mpi3_driver2_trigger_event { 1212 u8 type; 1213 u8 flags; 1214 u8 reserved02; 1215 u8 event; 1216 __le32 reserved04[3]; 1217 }; 1218 1219 struct mpi3_driver2_trigger_scsi_sense { 1220 u8 type; 1221 u8 flags; 1222 __le16 reserved02; 1223 u8 ascq; 1224 u8 asc; 1225 u8 sense_key; 1226 u8 reserved07; 1227 __le32 reserved08[2]; 1228 }; 1229 1230 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xff) 1231 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xff) 1232 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xff) 1233 struct mpi3_driver2_trigger_reply { 1234 u8 type; 1235 u8 flags; 1236 __le16 ioc_status; 1237 __le32 ioc_log_info; 1238 __le32 ioc_log_info_mask; 1239 __le32 reserved0c; 1240 }; 1241 1242 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xffff) 1243 union mpi3_driver2_trigger_element { 1244 struct mpi3_driver2_trigger_event event; 1245 struct mpi3_driver2_trigger_scsi_sense scsi_sense; 1246 struct mpi3_driver2_trigger_reply reply; 1247 }; 1248 1249 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 1250 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 1251 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 1252 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 1253 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 1254 struct mpi3_driver_page2 { 1255 struct mpi3_config_page_header header; 1256 __le64 master_trigger; 1257 __le32 reserved10[3]; 1258 u8 num_triggers; 1259 u8 reserved1d[3]; 1260 union mpi3_driver2_trigger_element trigger[MPI3_DRIVER2_TRIGGER_MAX]; 1261 }; 1262 1263 #define MPI3_DRIVER2_PAGEVERSION (0x00) 1264 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 1265 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 1266 #define MPI3_DRIVER2_MASTERTRIGGER_SNAPDUMP (0x2000000000000000ULL) 1267 #define MPI3_DRIVER2_MASTERTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 1268 #define MPI3_DRIVER2_MASTERTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 1269 struct mpi3_driver_page10 { 1270 struct mpi3_config_page_header header; 1271 __le16 flags; 1272 __le16 reserved0a; 1273 u8 num_allowed_commands; 1274 u8 reserved0d[3]; 1275 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1276 }; 1277 1278 #define MPI3_DRIVER10_PAGEVERSION (0x00) 1279 struct mpi3_driver_page20 { 1280 struct mpi3_config_page_header header; 1281 __le16 flags; 1282 __le16 reserved0a; 1283 u8 num_allowed_commands; 1284 u8 reserved0d[3]; 1285 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1286 }; 1287 1288 #define MPI3_DRIVER20_PAGEVERSION (0x00) 1289 struct mpi3_driver_page30 { 1290 struct mpi3_config_page_header header; 1291 __le16 flags; 1292 __le16 reserved0a; 1293 u8 num_allowed_commands; 1294 u8 reserved0d[3]; 1295 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1296 }; 1297 1298 #define MPI3_DRIVER30_PAGEVERSION (0x00) 1299 union mpi3_security_mac { 1300 __le32 dword[16]; 1301 __le16 word[32]; 1302 u8 byte[64]; 1303 }; 1304 1305 union mpi3_security_nonce { 1306 __le32 dword[16]; 1307 __le16 word[32]; 1308 u8 byte[64]; 1309 }; 1310 1311 union mpi3_security0_cert_chain { 1312 __le32 dword[1024]; 1313 __le16 word[2048]; 1314 u8 byte[4096]; 1315 }; 1316 1317 struct mpi3_security_page0 { 1318 struct mpi3_config_page_header header; 1319 u8 slot_num_group; 1320 u8 slot_num; 1321 __le16 cert_chain_length; 1322 u8 cert_chain_flags; 1323 u8 reserved0d[3]; 1324 __le32 base_asym_algo; 1325 __le32 base_hash_algo; 1326 __le32 reserved18[4]; 1327 union mpi3_security_mac mac; 1328 union mpi3_security_nonce nonce; 1329 union mpi3_security0_cert_chain certificate_chain; 1330 }; 1331 1332 #define MPI3_SECURITY0_PAGEVERSION (0x00) 1333 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e) 1334 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 1335 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 1336 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 1337 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 1338 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 1339 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 1340 #endif 1341 #ifndef MPI3_SECURITY1_PAD_MAX 1342 #define MPI3_SECURITY1_PAD_MAX 1 1343 #endif 1344 union mpi3_security1_key_data { 1345 __le32 dword[128]; 1346 __le16 word[256]; 1347 u8 byte[512]; 1348 }; 1349 1350 struct mpi3_security1_key_record { 1351 u8 flags; 1352 u8 consumer; 1353 __le16 key_data_size; 1354 __le32 additional_key_data; 1355 __le32 reserved08[2]; 1356 union mpi3_security1_key_data key_data; 1357 }; 1358 1359 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f) 1360 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 1361 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 1362 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 1363 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 1364 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 1365 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 1366 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 1367 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 1368 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 1369 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 1370 struct mpi3_security_page1 { 1371 struct mpi3_config_page_header header; 1372 __le32 reserved08[2]; 1373 union mpi3_security_mac mac; 1374 union mpi3_security_nonce nonce; 1375 u8 num_keys; 1376 u8 reserved91[3]; 1377 __le32 reserved94[3]; 1378 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX]; 1379 u8 pad[MPI3_SECURITY1_PAD_MAX]; 1380 }; 1381 1382 #define MPI3_SECURITY1_PAGEVERSION (0x00) 1383 struct mpi3_sas_io_unit0_phy_data { 1384 u8 io_unit_port; 1385 u8 port_flags; 1386 u8 phy_flags; 1387 u8 negotiated_link_rate; 1388 __le16 controller_phy_device_info; 1389 __le16 reserved06; 1390 __le16 attached_dev_handle; 1391 __le16 controller_dev_handle; 1392 __le32 discovery_status; 1393 __le32 reserved10; 1394 }; 1395 1396 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX 1397 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) 1398 #endif 1399 struct mpi3_sas_io_unit_page0 { 1400 struct mpi3_config_page_header header; 1401 __le32 reserved08; 1402 u8 num_phys; 1403 u8 init_status; 1404 __le16 reserved0e; 1405 struct mpi3_sas_io_unit0_phy_data phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX]; 1406 }; 1407 1408 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 1409 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 1410 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 1411 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 1412 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 1413 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 1414 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 1415 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xf0) 1416 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xff) 1417 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 1418 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 1419 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 1420 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 1421 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 1422 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1423 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1424 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1425 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 1426 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 1427 struct mpi3_sas_io_unit1_phy_data { 1428 u8 io_unit_port; 1429 u8 port_flags; 1430 u8 phy_flags; 1431 u8 max_min_link_rate; 1432 __le16 controller_phy_device_info; 1433 __le16 max_target_port_connect_time; 1434 __le32 reserved08; 1435 }; 1436 1437 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX 1438 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) 1439 #endif 1440 struct mpi3_sas_io_unit_page1 { 1441 struct mpi3_config_page_header header; 1442 __le16 control_flags; 1443 __le16 sas_narrow_max_queue_depth; 1444 __le16 additional_control_flags; 1445 __le16 sas_wide_max_queue_depth; 1446 u8 num_phys; 1447 u8 sata_max_q_depth; 1448 __le16 reserved12; 1449 struct mpi3_sas_io_unit1_phy_data phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX]; 1450 }; 1451 1452 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 1453 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 1454 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1455 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1456 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1457 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1458 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1459 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1460 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1461 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1462 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 1463 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 1464 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 1465 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 1466 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1467 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1468 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1469 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1470 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1471 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1472 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1473 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1474 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1475 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1476 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1477 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1478 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1479 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1480 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0) 1481 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0) 1482 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0) 1483 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f) 1484 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a) 1485 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b) 1486 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c) 1487 struct mpi3_sas_io_unit2_phy_pm_settings { 1488 u8 control_flags; 1489 u8 reserved01; 1490 __le16 inactivity_timer_exponent; 1491 u8 sata_partial_timeout; 1492 u8 reserved05; 1493 u8 sata_slumber_timeout; 1494 u8 reserved07; 1495 u8 sas_partial_timeout; 1496 u8 reserved09; 1497 u8 sas_slumber_timeout; 1498 u8 reserved0b; 1499 }; 1500 1501 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 1502 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 1503 #endif 1504 struct mpi3_sas_io_unit_page2 { 1505 struct mpi3_config_page_header header; 1506 u8 num_phys; 1507 u8 reserved09[3]; 1508 __le32 reserved0c; 1509 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX]; 1510 }; 1511 1512 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 1513 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1514 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1515 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1516 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1517 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 1518 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 1519 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 1520 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 1521 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 1522 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 1523 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 1524 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 1525 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 1526 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 1527 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 1528 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 1529 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 1530 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 1531 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 1532 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 1533 struct mpi3_sas_io_unit_page3 { 1534 struct mpi3_config_page_header header; 1535 __le32 reserved08; 1536 __le32 power_management_capabilities; 1537 }; 1538 1539 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 1540 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 1541 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 1542 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 1543 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 1544 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 1545 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 1546 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 1547 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 1548 struct mpi3_sas_expander_page0 { 1549 struct mpi3_config_page_header header; 1550 u8 io_unit_port; 1551 u8 report_gen_length; 1552 __le16 enclosure_handle; 1553 __le32 reserved0c; 1554 __le64 sas_address; 1555 __le32 discovery_status; 1556 __le16 dev_handle; 1557 __le16 parent_dev_handle; 1558 __le16 expander_change_count; 1559 __le16 expander_route_indexes; 1560 u8 num_phys; 1561 u8 sas_level; 1562 __le16 flags; 1563 __le16 stp_bus_inactivity_time_limit; 1564 __le16 stp_max_connect_time_limit; 1565 __le16 stp_smp_nexus_loss_time; 1566 __le16 max_num_routed_sas_addresses; 1567 __le64 active_zone_manager_sas_address; 1568 __le16 zone_lock_inactivity_limit; 1569 __le16 reserved3a; 1570 u8 time_to_reduced_func; 1571 u8 initial_time_to_reduced_func; 1572 u8 max_reduced_func_time; 1573 u8 exp_status; 1574 }; 1575 1576 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 1577 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 1578 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1579 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1580 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1581 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1582 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1583 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1584 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1585 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1586 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1587 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1588 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 1589 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 1590 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 1591 struct mpi3_sas_expander_page1 { 1592 struct mpi3_config_page_header header; 1593 u8 io_unit_port; 1594 u8 reserved09[3]; 1595 u8 num_phys; 1596 u8 phy; 1597 __le16 num_table_entries_programmed; 1598 u8 programmed_link_rate; 1599 u8 hw_link_rate; 1600 __le16 attached_dev_handle; 1601 __le32 phy_info; 1602 __le16 attached_device_info; 1603 __le16 reserved1a; 1604 __le16 expander_dev_handle; 1605 u8 change_count; 1606 u8 negotiated_link_rate; 1607 u8 phy_identifier; 1608 u8 attached_phy_identifier; 1609 u8 reserved22; 1610 u8 discovery_info; 1611 __le32 attached_phy_info; 1612 u8 zone_group; 1613 u8 self_config_status; 1614 __le16 reserved2a; 1615 __le16 slot; 1616 __le16 slot_index; 1617 }; 1618 1619 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 1620 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 1621 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 1622 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 1623 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 1624 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 1625 #endif 1626 struct mpi3_sasexpander2_phy_element { 1627 u8 link_change_count; 1628 u8 reserved01; 1629 __le16 rate_change_count; 1630 __le32 reserved04; 1631 }; 1632 1633 struct mpi3_sas_expander_page2 { 1634 struct mpi3_config_page_header header; 1635 u8 num_phys; 1636 u8 reserved09; 1637 __le16 dev_handle; 1638 __le32 reserved0c; 1639 struct mpi3_sasexpander2_phy_element phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; 1640 }; 1641 1642 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 1643 struct mpi3_sas_port_page0 { 1644 struct mpi3_config_page_header header; 1645 u8 port_number; 1646 u8 reserved09; 1647 u8 port_width; 1648 u8 reserved0b; 1649 u8 zone_group; 1650 u8 reserved0d[3]; 1651 __le64 sas_address; 1652 __le16 device_info; 1653 __le16 reserved1a; 1654 __le32 reserved1c; 1655 }; 1656 1657 #define MPI3_SASPORT0_PAGEVERSION (0x00) 1658 struct mpi3_sas_phy_page0 { 1659 struct mpi3_config_page_header header; 1660 __le16 owner_dev_handle; 1661 __le16 reserved0a; 1662 __le16 attached_dev_handle; 1663 u8 attached_phy_identifier; 1664 u8 reserved0f; 1665 __le32 attached_phy_info; 1666 u8 programmed_link_rate; 1667 u8 hw_link_rate; 1668 u8 change_count; 1669 u8 flags; 1670 __le32 phy_info; 1671 u8 negotiated_link_rate; 1672 u8 reserved1d[3]; 1673 __le16 slot; 1674 __le16 slot_index; 1675 }; 1676 1677 #define MPI3_SASPHY0_PAGEVERSION (0x00) 1678 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 1679 struct mpi3_sas_phy_page1 { 1680 struct mpi3_config_page_header header; 1681 __le32 reserved08; 1682 __le32 invalid_dword_count; 1683 __le32 running_disparity_error_count; 1684 __le32 loss_dword_synch_count; 1685 __le32 phy_reset_problem_count; 1686 }; 1687 1688 #define MPI3_SASPHY1_PAGEVERSION (0x00) 1689 struct mpi3_sas_phy2_phy_event { 1690 u8 phy_event_code; 1691 u8 reserved01[3]; 1692 __le32 phy_event_info; 1693 }; 1694 1695 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 1696 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 1697 #endif 1698 struct mpi3_sas_phy_page2 { 1699 struct mpi3_config_page_header header; 1700 __le32 reserved08; 1701 u8 num_phy_events; 1702 u8 reserved0d[3]; 1703 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX]; 1704 }; 1705 1706 #define MPI3_SASPHY2_PAGEVERSION (0x00) 1707 struct mpi3_sas_phy3_phy_event_config { 1708 u8 phy_event_code; 1709 u8 reserved01[3]; 1710 u8 counter_type; 1711 u8 threshold_window; 1712 u8 time_units; 1713 u8 reserved07; 1714 __le32 event_threshold; 1715 __le16 threshold_flags; 1716 __le16 reserved0e; 1717 }; 1718 1719 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 1720 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 1721 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 1722 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 1723 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 1724 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 1725 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 1726 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 1727 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 1728 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 1729 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 1730 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 1731 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 1732 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 1733 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 1734 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 1735 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 1736 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 1737 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 1738 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a) 1739 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b) 1740 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c) 1741 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d) 1742 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e) 1743 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f) 1744 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 1745 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 1746 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 1747 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 1748 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 1749 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 1750 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 1751 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 1752 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 1753 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 1754 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 1755 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 1756 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0) 1757 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1) 1758 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2) 1759 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3) 1760 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4) 1761 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5) 1762 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6) 1763 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7) 1764 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8) 1765 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9) 1766 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda) 1767 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb) 1768 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc) 1769 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 1770 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 1771 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 1772 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 1773 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 1774 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 1775 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 1776 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 1777 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 1778 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 1779 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 1780 #endif 1781 struct mpi3_sas_phy_page3 { 1782 struct mpi3_config_page_header header; 1783 __le32 reserved08; 1784 u8 num_phy_events; 1785 u8 reserved0d[3]; 1786 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX]; 1787 }; 1788 1789 #define MPI3_SASPHY3_PAGEVERSION (0x00) 1790 struct mpi3_sas_phy_page4 { 1791 struct mpi3_config_page_header header; 1792 u8 reserved08[3]; 1793 u8 flags; 1794 u8 initial_frame[28]; 1795 }; 1796 1797 #define MPI3_SASPHY4_PAGEVERSION (0x00) 1798 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 1799 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 1800 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 1801 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 1802 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f) 1803 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 1804 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 1805 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 1806 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 1807 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 1808 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 1809 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 1810 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 1811 #define MPI3_PCIE_ASPM_ENABLE_L0S (0x1) 1812 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 1813 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1 (0x3) 1814 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 1815 #define MPI3_PCIE_ASPM_SUPPORT_L0S (0x1) 1816 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 1817 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 (0x3) 1818 struct mpi3_pcie_io_unit0_phy_data { 1819 u8 link; 1820 u8 link_flags; 1821 u8 phy_flags; 1822 u8 negotiated_link_rate; 1823 __le16 attached_dev_handle; 1824 __le16 controller_dev_handle; 1825 __le32 enumeration_status; 1826 u8 io_unit_port; 1827 u8 reserved0d[3]; 1828 }; 1829 1830 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 1831 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 1832 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 1833 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 1834 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1835 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 1836 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 1837 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 1838 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 1839 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 1840 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 1841 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 1842 #endif 1843 struct mpi3_pcie_io_unit_page0 { 1844 struct mpi3_config_page_header header; 1845 __le32 reserved08; 1846 u8 num_phys; 1847 u8 init_status; 1848 u8 aspm; 1849 u8 reserved0f; 1850 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX]; 1851 }; 1852 1853 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 1854 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 1855 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 1856 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 1857 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 1858 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 1859 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 1860 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 1861 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 1862 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 1863 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0) 1864 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff) 1865 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xc0) 1866 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 1867 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 1868 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 1869 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0c) 1870 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 1871 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 1872 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 1873 struct mpi3_pcie_io_unit1_phy_data { 1874 u8 link; 1875 u8 link_flags; 1876 u8 phy_flags; 1877 u8 max_min_link_rate; 1878 __le32 reserved04; 1879 __le32 reserved08; 1880 }; 1881 1882 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 1883 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 1884 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 1885 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 1886 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1887 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1888 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1889 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 1890 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 1891 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 1892 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 1893 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 1894 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 1895 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 1896 #endif 1897 struct mpi3_pcie_io_unit_page1 { 1898 struct mpi3_config_page_header header; 1899 __le32 control_flags; 1900 __le32 reserved0c; 1901 u8 num_phys; 1902 u8 reserved11; 1903 u8 aspm; 1904 u8 reserved13; 1905 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX]; 1906 }; 1907 1908 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 1909 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x80) 1910 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x40) 1911 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x30) 1912 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 1913 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00) 1914 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x10) 1915 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x20) 1916 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0f) 1917 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x02) 1918 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x03) 1919 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x04) 1920 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x05) 1921 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x06) 1922 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c) 1923 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 1924 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 1925 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 1926 struct mpi3_pcie_io_unit_page2 { 1927 struct mpi3_config_page_header header; 1928 __le16 nvme_max_q_dx1; 1929 __le16 nvme_max_q_dx2; 1930 u8 nvme_abort_to; 1931 u8 reserved0d; 1932 __le16 nvme_max_q_dx4; 1933 }; 1934 1935 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 1936 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 1937 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 1938 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 1939 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 1940 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 1941 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 1942 struct mpi3_pcie_io_unit3_error { 1943 __le16 threshold_count; 1944 __le16 reserved02; 1945 }; 1946 1947 struct mpi3_pcie_io_unit_page3 { 1948 struct mpi3_config_page_header header; 1949 u8 threshold_window; 1950 u8 threshold_action; 1951 u8 escalation_count; 1952 u8 escalation_action; 1953 u8 num_errors; 1954 u8 reserved0d[3]; 1955 struct mpi3_pcie_io_unit3_error error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; 1956 }; 1957 1958 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 1959 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 1960 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 1961 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 1962 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 1963 struct mpi3_pcie_switch_page0 { 1964 struct mpi3_config_page_header header; 1965 u8 io_unit_port; 1966 u8 switch_status; 1967 u8 reserved0a[2]; 1968 __le16 dev_handle; 1969 __le16 parent_dev_handle; 1970 u8 num_ports; 1971 u8 pcie_level; 1972 __le16 reserved12; 1973 __le32 reserved14; 1974 __le32 reserved18; 1975 __le32 reserved1c; 1976 }; 1977 1978 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 1979 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 1980 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 1981 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 1982 struct mpi3_pcie_switch_page1 { 1983 struct mpi3_config_page_header header; 1984 u8 io_unit_port; 1985 u8 flags; 1986 __le16 reserved0a; 1987 u8 num_ports; 1988 u8 port_num; 1989 __le16 attached_dev_handle; 1990 __le16 switch_dev_handle; 1991 u8 negotiated_port_width; 1992 u8 negotiated_link_rate; 1993 __le16 slot; 1994 __le16 slot_index; 1995 __le32 reserved18; 1996 }; 1997 1998 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 1999 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0c) 2000 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 2001 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 2002 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 2003 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 2004 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 2005 #endif 2006 struct mpi3_pcieswitch2_port_element { 2007 __le16 link_change_count; 2008 __le16 rate_change_count; 2009 __le32 reserved04; 2010 }; 2011 2012 struct mpi3_pcie_switch_page2 { 2013 struct mpi3_config_page_header header; 2014 u8 num_ports; 2015 u8 reserved09; 2016 __le16 dev_handle; 2017 __le32 reserved0c; 2018 struct mpi3_pcieswitch2_port_element port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; 2019 }; 2020 2021 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 2022 struct mpi3_pcie_link_page0 { 2023 struct mpi3_config_page_header header; 2024 u8 link; 2025 u8 reserved09[3]; 2026 __le32 reserved0c; 2027 __le32 receiver_error_count; 2028 __le32 recovery_count; 2029 __le32 corr_error_msg_count; 2030 __le32 non_fatal_error_msg_count; 2031 __le32 fatal_error_msg_count; 2032 __le32 non_fatal_error_count; 2033 __le32 fatal_error_count; 2034 __le32 bad_dllp_count; 2035 __le32 bad_tlp_count; 2036 }; 2037 2038 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 2039 struct mpi3_enclosure_page0 { 2040 struct mpi3_config_page_header header; 2041 __le64 enclosure_logical_id; 2042 __le16 flags; 2043 __le16 enclosure_handle; 2044 __le16 num_slots; 2045 __le16 reserved16; 2046 u8 io_unit_port; 2047 u8 enclosure_level; 2048 __le16 sep_dev_handle; 2049 u8 chassis_slot; 2050 u8 reserved1d[3]; 2051 }; 2052 2053 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 2054 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000) 2055 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 2056 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 2057 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 2058 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 2059 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 2060 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 2061 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 2062 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f) 2063 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2064 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2065 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 2066 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 2067 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 2068 #define MPI3_DEVICE_DEVFORM_VD (0x02) 2069 struct mpi3_device0_sas_sata_format { 2070 __le64 sas_address; 2071 __le16 flags; 2072 __le16 device_info; 2073 u8 phy_num; 2074 u8 attached_phy_identifier; 2075 u8 max_port_connections; 2076 u8 zone_group; 2077 }; 2078 2079 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 2080 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 2081 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 2082 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 2083 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 2084 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 2085 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 2086 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 2087 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 2088 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 2089 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 2090 struct mpi3_device0_pcie_format { 2091 u8 supported_link_rates; 2092 u8 max_port_width; 2093 u8 negotiated_port_width; 2094 u8 negotiated_link_rate; 2095 u8 port_num; 2096 u8 controller_reset_to; 2097 __le16 device_info; 2098 __le32 maximum_data_transfer_size; 2099 __le32 capabilities; 2100 __le16 noiob; 2101 u8 nvme_abort_to; 2102 u8 page_size; 2103 __le16 shutdown_latency; 2104 u8 recovery_info; 2105 u8 reserved17; 2106 }; 2107 2108 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 2109 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 2110 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 2111 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 2112 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 2113 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 2114 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 2115 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 2116 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 2117 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 2118 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 2119 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 2120 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00c0) 2121 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 2122 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 2123 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 2124 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 2125 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00c0) 2126 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 2127 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 2128 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 2129 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 2130 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 2131 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 2132 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 2133 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000c0) 2134 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 2135 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xe0) 2136 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 2137 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 2138 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1f) 2139 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 2140 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 2141 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 2142 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 2143 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 2144 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 2145 struct mpi3_device0_vd_format { 2146 u8 vd_state; 2147 u8 raid_level; 2148 __le16 device_info; 2149 __le16 flags; 2150 __le16 io_throttle_group; 2151 __le16 io_throttle_group_low; 2152 __le16 io_throttle_group_high; 2153 __le32 reserved0c; 2154 }; 2155 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 2156 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 2157 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 2158 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 2159 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 2160 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 2161 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 2162 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 2163 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 2164 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 2165 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 2166 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 2167 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 2168 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 2169 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 2170 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 2171 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000) 2172 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_MASK (0x0003) 2173 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_NONE (0x0000) 2174 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_HOST (0x0001) 2175 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_IOC (0x0002) 2176 union mpi3_device0_dev_spec_format { 2177 struct mpi3_device0_sas_sata_format sas_sata_format; 2178 struct mpi3_device0_pcie_format pcie_format; 2179 struct mpi3_device0_vd_format vd_format; 2180 }; 2181 2182 struct mpi3_device_page0 { 2183 struct mpi3_config_page_header header; 2184 __le16 dev_handle; 2185 __le16 parent_dev_handle; 2186 __le16 slot; 2187 __le16 enclosure_handle; 2188 __le64 wwid; 2189 __le16 persistent_id; 2190 u8 io_unit_port; 2191 u8 access_status; 2192 __le16 flags; 2193 __le16 reserved1e; 2194 __le16 slot_index; 2195 __le16 queue_depth; 2196 u8 reserved24[3]; 2197 u8 device_form; 2198 union mpi3_device0_dev_spec_format device_specific; 2199 }; 2200 2201 #define MPI3_DEVICE0_PAGEVERSION (0x00) 2202 #define MPI3_DEVICE0_PARENT_INVALID (0xffff) 2203 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 2204 #define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff) 2205 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff) 2206 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff) 2207 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2208 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 2209 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 2210 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 2211 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 2212 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 2213 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 2214 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 2215 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0f) 2216 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 2217 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 2218 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 2219 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1f) 2220 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 2221 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 2222 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 2223 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 2224 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 2225 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 2226 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 2227 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 2228 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 2229 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 2230 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f) 2231 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 2232 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 2233 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 2234 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 2235 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 2236 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3f) 2237 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 2238 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 2239 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 2240 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 2241 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 2242 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 2243 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 2244 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 2245 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 2246 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 2247 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4a) 2248 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4b) 2249 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4c) 2250 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4d) 2251 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4e) 2252 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4f) 2253 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 2254 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 2255 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 2256 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f) 2257 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 2258 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f) 2259 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 2260 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 2261 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 2262 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 2263 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 2264 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2265 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 2266 struct mpi3_device1_sas_sata_format { 2267 __le32 reserved00; 2268 }; 2269 struct mpi3_device1_pcie_format { 2270 __le16 vendor_id; 2271 __le16 device_id; 2272 __le16 subsystem_vendor_id; 2273 __le16 subsystem_id; 2274 __le32 reserved08; 2275 u8 revision_id; 2276 u8 reserved0d; 2277 __le16 pci_parameters; 2278 }; 2279 2280 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 2281 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 2282 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 2283 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 2284 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 2285 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 2286 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0) 2287 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 2288 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 2289 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 2290 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 2291 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 2292 struct mpi3_device1_vd_format { 2293 __le32 reserved00; 2294 }; 2295 2296 union mpi3_device1_dev_spec_format { 2297 struct mpi3_device1_sas_sata_format sas_sata_format; 2298 struct mpi3_device1_pcie_format pcie_format; 2299 struct mpi3_device1_vd_format vd_format; 2300 }; 2301 2302 struct mpi3_device_page1 { 2303 struct mpi3_config_page_header header; 2304 __le16 dev_handle; 2305 __le16 reserved0a; 2306 __le16 link_change_count; 2307 __le16 rate_change_count; 2308 __le16 tm_count; 2309 __le16 reserved12; 2310 __le32 reserved14[10]; 2311 u8 reserved3c[3]; 2312 u8 device_form; 2313 union mpi3_device1_dev_spec_format device_specific; 2314 }; 2315 2316 #define MPI3_DEVICE1_PAGEVERSION (0x00) 2317 #define MPI3_DEVICE1_COUNTER_MAX (0xfffe) 2318 #define MPI3_DEVICE1_COUNTER_INVALID (0xffff) 2319 #endif 2320