1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2017-2021 Broadcom Inc. All rights reserved. 4 * 5 */ 6 #ifndef MPI30_CNFG_H 7 #define MPI30_CNFG_H 1 8 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 9 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 10 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 11 #define MPI3_CONFIG_PAGETYPE_UEFI_BSD (0x03) 12 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 13 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 14 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 15 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 16 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 17 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 18 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 19 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 20 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 21 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 22 #define MPI3_CONFIG_PAGEATTR_MASK (0xf0) 23 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 24 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 25 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 26 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 27 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 28 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 29 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 30 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 31 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 32 #define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000) 33 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 34 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 35 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff) 36 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000) 37 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 39 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000) 41 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 42 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff) 43 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000) 44 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 45 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff) 46 #define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000) 47 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 48 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 49 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff) 50 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000) 51 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 52 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 53 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff) 54 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000) 55 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 57 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000) 59 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 60 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff) 61 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000) 62 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 63 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 64 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff) 65 #define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000) 66 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 67 #define MPI3_SECURITY_PGAD_FORM_SOT_NUM (0x10000000) 68 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00) 69 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff) 70 struct mpi3_config_request { 71 __le16 host_tag; 72 u8 ioc_use_only02; 73 u8 function; 74 __le16 ioc_use_only04; 75 u8 ioc_use_only06; 76 u8 msg_flags; 77 __le16 change_count; 78 __le16 reserved0a; 79 u8 page_version; 80 u8 page_number; 81 u8 page_type; 82 u8 action; 83 __le32 page_address; 84 __le16 page_length; 85 __le16 reserved16; 86 __le32 reserved18[2]; 87 union mpi3_sge_union sgl; 88 }; 89 90 struct mpi3_config_page_header { 91 u8 page_version; 92 u8 reserved01; 93 u8 page_number; 94 u8 page_attribute; 95 __le16 page_length; 96 u8 page_type; 97 u8 reserved07; 98 }; 99 100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0) 101 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f) 103 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 104 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 105 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 106 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 107 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 108 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 109 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 110 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 111 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 112 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a) 113 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b) 114 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c) 115 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 116 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 117 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 118 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f) 119 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 120 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 121 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 122 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 123 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 124 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 125 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 126 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 127 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 128 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 129 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000) 130 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 131 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 132 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 133 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 134 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 138 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000) 139 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 140 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 141 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 142 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 143 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 144 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 145 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 146 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 147 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 148 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 149 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 150 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 151 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 152 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00) 153 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 154 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0) 155 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 156 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 157 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 158 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0) 159 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 160 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 161 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 162 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0) 163 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0) 164 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0) 165 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f) 166 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 167 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 168 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 169 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a) 170 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b) 171 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c) 172 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0) 173 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 174 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 175 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0) 176 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0) 177 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0) 178 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f) 179 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 180 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 181 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a) 182 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b) 183 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c) 184 #define MPI3_SLOT_INVALID (0xffff) 185 #define MPI3_SLOT_INDEX_INVALID (0xffff) 186 struct mpi3_man_page0 { 187 struct mpi3_config_page_header header; 188 u8 chip_revision[8]; 189 u8 chip_name[32]; 190 u8 board_name[32]; 191 u8 board_assembly[32]; 192 u8 board_tracer_number[32]; 193 __le32 board_power; 194 __le32 reserved94; 195 __le32 reserved98; 196 u8 oem; 197 u8 sub_oem; 198 __le16 reserved9e; 199 u8 board_mfg_day; 200 u8 board_mfg_month; 201 __le16 board_mfg_year; 202 u8 board_rework_day; 203 u8 board_rework_month; 204 __le16 board_rework_year; 205 __le64 board_revision; 206 u8 e_pack_fru[16]; 207 u8 product_name[256]; 208 }; 209 210 #define MPI3_MAN0_PAGEVERSION (0x00) 211 #define MPI3_MAN1_VPD_SIZE (512) 212 struct mpi3_man_page1 { 213 struct mpi3_config_page_header header; 214 __le32 reserved08[2]; 215 u8 vpd[MPI3_MAN1_VPD_SIZE]; 216 }; 217 218 #define MPI3_MAN1_PAGEVERSION (0x00) 219 struct mpi3_man5_phy_entry { 220 __le64 ioc_wwid; 221 __le64 device_name; 222 __le64 sata_wwid; 223 }; 224 225 #ifndef MPI3_MAN5_PHY_MAX 226 #define MPI3_MAN5_PHY_MAX (1) 227 #endif 228 struct mpi3_man_page5 { 229 struct mpi3_config_page_header header; 230 u8 num_phys; 231 u8 reserved09[3]; 232 __le32 reserved0c; 233 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX]; 234 }; 235 236 #define MPI3_MAN5_PAGEVERSION (0x00) 237 struct mpi3_man6_gpio_entry { 238 u8 function_code; 239 u8 reserved01; 240 __le16 flags; 241 u8 param1; 242 u8 param2; 243 __le16 reserved06; 244 __le32 param3; 245 }; 246 247 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 248 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 249 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 250 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 251 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 252 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 253 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 254 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 255 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 256 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_MUX_RESET (0x09) 257 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a) 258 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b) 259 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c) 260 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ATTN (0x0d) 261 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e) 262 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f) 263 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 264 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 265 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 266 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0) 267 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 268 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 269 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 270 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 271 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 272 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 273 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 274 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 275 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 276 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 277 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 278 #define MPI3_MAN6_GPIO_ISTWI_MUX_RESET_PARAM2_SPEC_MUX (0x00) 279 #define MPI3_MAN6_GPIO_ISTWI_MUX_RESET_PARAM2_ALL_MUXES (0x01) 280 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 281 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 282 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 283 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 284 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0) 285 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 286 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 287 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 288 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0) 289 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 290 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 291 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 292 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 293 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 294 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 295 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 296 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 297 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 298 #ifndef MPI3_MAN6_GPIO_MAX 299 #define MPI3_MAN6_GPIO_MAX (1) 300 #endif 301 struct mpi3_man_page6 { 302 struct mpi3_config_page_header header; 303 __le16 flags; 304 __le16 reserved0a; 305 u8 num_gpio; 306 u8 reserved0d[3]; 307 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX]; 308 }; 309 310 #define MPI3_MAN6_PAGEVERSION (0x00) 311 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 312 struct mpi3_man7_receptacle_info { 313 __le32 name[4]; 314 u8 location; 315 u8 connector_type; 316 u8 ped_clk; 317 u8 connector_id; 318 __le32 reserved14; 319 }; 320 321 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 322 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 323 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 324 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 325 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 326 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 327 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 328 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0f) 329 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 330 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 331 #endif 332 struct mpi3_man_page7 { 333 struct mpi3_config_page_header header; 334 __le32 flags; 335 u8 num_receptacles; 336 u8 reserved0d[3]; 337 __le32 enclosure_name[4]; 338 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX]; 339 }; 340 341 #define MPI3_MAN7_PAGEVERSION (0x00) 342 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 343 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 344 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 345 struct mpi3_man8_phy_info { 346 u8 receptacle_id; 347 u8 connector_lane; 348 __le16 reserved02; 349 __le16 slotx1; 350 __le16 slotx2; 351 __le16 slotx4; 352 __le16 reserved0a; 353 __le32 reserved0c; 354 }; 355 356 #ifndef MPI3_MAN8_PHY_INFO_MAX 357 #define MPI3_MAN8_PHY_INFO_MAX (1) 358 #endif 359 struct mpi3_man_page8 { 360 struct mpi3_config_page_header header; 361 __le32 reserved08; 362 u8 num_phys; 363 u8 reserved0d[3]; 364 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX]; 365 }; 366 367 #define MPI3_MAN8_PAGEVERSION (0x00) 368 struct mpi3_man9_rsrc_entry { 369 __le32 maximum; 370 __le32 decrement; 371 __le32 minimum; 372 __le32 actual; 373 }; 374 375 enum mpi3_man9_resources { 376 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 377 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 378 MPI3_MAN9_RSRC_SAS_TARGETS = 2, 379 MPI3_MAN9_RSRC_PCIE_TARGETS = 3, 380 MPI3_MAN9_RSRC_INITIATORS = 4, 381 MPI3_MAN9_RSRC_VDS = 5, 382 MPI3_MAN9_RSRC_ENCLOSURES = 6, 383 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 384 MPI3_MAN9_RSRC_EXPANDERS = 8, 385 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 386 MPI3_MAN9_RSRC_PDS = 10, 387 MPI3_MAN9_RSRC_HOST_PDS = 11, 388 MPI3_MAN9_RSRC_ADV_HOST_PDS = 12, 389 MPI3_MAN9_RSRC_RAID_PDS = 13, 390 MPI3_MAN9_RSRC_NUM_RESOURCES 391 }; 392 393 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 394 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 395 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 396 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 397 #define MPI3_MAN9_MIN_SAS_TARGETS (0) 398 #define MPI3_MAN9_MAX_SAS_TARGETS (65535) 399 #define MPI3_MAN9_MIN_PCIE_TARGETS (0) 400 #define MPI3_MAN9_MIN_INITIATORS (0) 401 #define MPI3_MAN9_MAX_INITIATORS (65535) 402 #define MPI3_MAN9_MIN_ENCLOSURES (0) 403 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 404 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 405 #define MPI3_MAN9_MIN_EXPANDERS (0) 406 #define MPI3_MAN9_MAX_EXPANDERS (65535) 407 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 408 struct mpi3_man_page9 { 409 struct mpi3_config_page_header header; 410 u8 num_resources; 411 u8 reserved09; 412 __le16 reserved0a; 413 __le32 reserved0c; 414 __le32 reserved10; 415 __le32 reserved14; 416 __le32 reserved18; 417 __le32 reserved1c; 418 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; 419 }; 420 421 #define MPI3_MAN9_PAGEVERSION (0x00) 422 struct mpi3_man10_istwi_ctrlr_entry { 423 __le16 slave_address; 424 __le16 flags; 425 __le32 reserved04; 426 }; 427 428 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED (0x0002) 429 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED (0x0001) 430 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 431 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 432 #endif 433 struct mpi3_man_page10 { 434 struct mpi3_config_page_header header; 435 __le32 reserved08; 436 u8 num_istwi_ctrl; 437 u8 reserved0d[3]; 438 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX]; 439 }; 440 441 #define MPI3_MAN10_PAGEVERSION (0x00) 442 struct mpi3_man11_mux_device_format { 443 u8 max_channel; 444 u8 reserved01[3]; 445 __le32 reserved04; 446 }; 447 448 struct mpi3_man11_temp_sensor_device_format { 449 u8 type; 450 u8 reserved01[3]; 451 u8 temp_channel[4]; 452 }; 453 454 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 455 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 456 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 457 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 458 struct mpi3_man11_seeprom_device_format { 459 u8 size; 460 u8 page_write_size; 461 __le16 reserved02; 462 __le32 reserved04; 463 }; 464 465 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 466 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 467 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 468 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 469 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 470 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 471 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 472 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 473 struct mpi3_man11_ddr_spd_device_format { 474 u8 channel; 475 u8 reserved01[3]; 476 __le32 reserved04; 477 }; 478 479 struct mpi3_man11_cable_mgmt_device_format { 480 u8 type; 481 u8 receptacle_id; 482 __le16 reserved02; 483 __le32 reserved04; 484 }; 485 486 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 487 struct mpi3_man11_bkplane_spec_ubm_format { 488 __le16 flags; 489 __le16 reserved02; 490 }; 491 492 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 493 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 494 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0) 495 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 496 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 497 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 498 struct mpi3_man11_bkplane_spec_vpp_format { 499 __le16 flags; 500 __le16 reserved02; 501 }; 502 503 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0040) 504 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_MASK (0x0030) 505 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 506 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_PRESENCE_DETECT_REG (0x0010) 507 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_POLL_INTERVAL_MASK (0x000f) 508 #define MPI3_MAN11_BKPLANE_VPP_FLAGS_POLL_INTERVAL_SHIFT (0) 509 union mpi3_man11_bkplane_spec_format { 510 struct mpi3_man11_bkplane_spec_ubm_format ubm; 511 struct mpi3_man11_bkplane_spec_vpp_format vpp; 512 }; 513 514 struct mpi3_man11_bkplane_mgmt_device_format { 515 u8 type; 516 u8 receptacle_id; 517 __le16 reserved02; 518 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific; 519 }; 520 521 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 522 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_VPP (0x01) 523 struct mpi3_man11_gas_gauge_device_format { 524 u8 type; 525 u8 reserved01[3]; 526 __le32 reserved04; 527 }; 528 529 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 530 union mpi3_man11_device_specific_format { 531 struct mpi3_man11_mux_device_format mux; 532 struct mpi3_man11_temp_sensor_device_format temp_sensor; 533 struct mpi3_man11_seeprom_device_format seeprom; 534 struct mpi3_man11_ddr_spd_device_format ddr_spd; 535 struct mpi3_man11_cable_mgmt_device_format cable_mgmt; 536 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt; 537 struct mpi3_man11_gas_gauge_device_format gas_gauge; 538 __le32 words[2]; 539 }; 540 541 struct mpi3_man11_istwi_device_format { 542 u8 device_type; 543 u8 controller; 544 u8 reserved02; 545 u8 flags; 546 __le16 device_address; 547 u8 mux_channel; 548 u8 mux_index; 549 union mpi3_man11_device_specific_format device_specific; 550 }; 551 552 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 553 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 554 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 555 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 556 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 557 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 558 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 559 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 560 #define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_MASK (0x06) 561 #define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_100KHZ (0x00) 562 #define MPI3_MAN11_ISTWI_FLAGS_BUS_SPEED_400KHZ (0x02) 563 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 564 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 565 #endif 566 struct mpi3_man_page11 { 567 struct mpi3_config_page_header header; 568 __le32 reserved08; 569 u8 num_istwi_dev; 570 u8 reserved0d[3]; 571 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX]; 572 }; 573 574 #define MPI3_MAN11_PAGEVERSION (0x00) 575 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 576 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 577 #endif 578 struct mpi3_man12_sgpio_info { 579 u8 slot_count; 580 u8 reserved01[3]; 581 __le32 reserved04; 582 u8 phy_order[32]; 583 }; 584 585 struct mpi3_man_page12 { 586 struct mpi3_config_page_header header; 587 __le32 flags; 588 __le32 s_clock_freq; 589 __le32 activity_modulation; 590 u8 num_sgpio; 591 u8 reserved15[3]; 592 __le32 reserved18; 593 __le32 reserved1c; 594 __le32 pattern[8]; 595 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX]; 596 }; 597 598 #define MPI3_MAN12_PAGEVERSION (0x00) 599 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 600 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 601 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 602 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 603 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 604 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 605 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 606 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 607 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 608 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 609 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) 610 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) 611 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000) 612 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 613 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00) 614 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 615 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0) 616 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 617 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f) 618 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 619 #define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000) 620 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 621 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 622 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 623 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 624 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 625 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000) 626 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000) 627 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000) 628 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 629 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff) 630 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 631 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 632 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 633 #endif 634 struct mpi3_man13_translation_info { 635 __le32 slot_status; 636 __le32 mask; 637 u8 activity; 638 u8 locate; 639 u8 error; 640 u8 reserved0b; 641 }; 642 643 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 644 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 645 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 646 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 647 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 648 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 649 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 650 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 651 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 652 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 653 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 654 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 655 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 656 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 657 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 658 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 659 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 660 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 661 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 662 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 663 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 664 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 665 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 666 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 667 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 668 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 669 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 670 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a) 671 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b) 672 struct mpi3_man_page13 { 673 struct mpi3_config_page_header header; 674 u8 num_trans; 675 u8 reserved09[3]; 676 __le32 reserved0c; 677 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; 678 }; 679 680 #define MPI3_MAN13_PAGEVERSION (0x00) 681 struct mpi3_man_page14 { 682 struct mpi3_config_page_header header; 683 __le16 flags; 684 __le16 reserved0a; 685 u8 num_slot_groups; 686 u8 num_slots; 687 __le16 max_cert_chain_length; 688 __le32 sealed_slots; 689 }; 690 691 #define MPI3_MAN14_PAGEVERSION (0x00) 692 #define MPI3_MAN14_FLAGS_AUTH_SESSION_REQ (0x01) 693 #define MPI3_MAN14_FLAGS_AUTH_API_MASK (0x0e) 694 #define MPI3_MAN14_FLAGS_AUTH_API_NONE (0x00) 695 #define MPI3_MAN14_FLAGS_AUTH_API_CEREBUS (0x02) 696 #define MPI3_MAN14_FLAGS_AUTH_API_DMTF_PMCI (0x04) 697 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 698 #define MPI3_MAN15_VERSION_RECORD_MAX 1 699 #endif 700 struct mpi3_man15_version_record { 701 __le16 spdm_version; 702 __le16 reserved02; 703 }; 704 705 struct mpi3_man_page15 { 706 struct mpi3_config_page_header header; 707 u8 num_version_records; 708 u8 reserved09[3]; 709 __le32 reserved0c; 710 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX]; 711 }; 712 713 #define MPI3_MAN15_PAGEVERSION (0x00) 714 #ifndef MPI3_MAN16_CERT_ALGO_MAX 715 #define MPI3_MAN16_CERT_ALGO_MAX 1 716 #endif 717 struct mpi3_man16_certificate_algorithm { 718 u8 slot_group; 719 u8 reserved01[3]; 720 __le32 base_asym_algo; 721 __le32 base_hash_algo; 722 __le32 reserved0c[3]; 723 }; 724 725 struct mpi3_man_page16 { 726 struct mpi3_config_page_header header; 727 __le32 reserved08; 728 u8 num_cert_algos; 729 u8 reserved0d[3]; 730 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX]; 731 }; 732 733 #define MPI3_MAN16_PAGEVERSION (0x00) 734 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 735 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 736 #endif 737 struct mpi3_man17_hash_algorithm { 738 u8 meas_specification; 739 u8 reserved01[3]; 740 __le32 measurement_hash_algo; 741 __le32 reserved08[2]; 742 }; 743 744 struct mpi3_man_page17 { 745 struct mpi3_config_page_header header; 746 __le32 reserved08; 747 u8 num_hash_algos; 748 u8 reserved0d[3]; 749 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; 750 }; 751 752 #define MPI3_MAN17_PAGEVERSION (0x00) 753 struct mpi3_man_page20 { 754 struct mpi3_config_page_header header; 755 __le32 reserved08; 756 __le32 nonpremium_features; 757 u8 allowed_personalities; 758 u8 reserved11[3]; 759 }; 760 761 #define MPI3_MAN20_PAGEVERSION (0x00) 762 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 763 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 764 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 765 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 766 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 767 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 768 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 769 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 770 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 771 struct mpi3_man_page21 { 772 struct mpi3_config_page_header header; 773 __le32 reserved08; 774 __le32 flags; 775 }; 776 777 #define MPI3_MAN21_PAGEVERSION (0x00) 778 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_MASK (0x80) 779 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_ENABLED (0x80) 780 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_DISABLED (0x00) 781 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x60) 782 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00) 783 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x20) 784 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x40) 785 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x08) 786 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00) 787 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x08) 788 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x01) 789 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00) 790 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x01) 791 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 792 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 793 #endif 794 struct mpi3_man_page_product_specific { 795 struct mpi3_config_page_header header; 796 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX]; 797 }; 798 799 struct mpi3_io_unit_page0 { 800 struct mpi3_config_page_header header; 801 __le64 unique_value; 802 __le32 nvdata_version_default; 803 __le32 nvdata_version_persistent; 804 }; 805 806 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 807 struct mpi3_io_unit_page1 { 808 struct mpi3_config_page_header header; 809 __le32 flags; 810 u8 dmd_io_delay; 811 u8 dmd_report_pc_ie; 812 u8 dmd_report_sata; 813 u8 dmd_report_sas; 814 }; 815 816 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 817 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 818 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 819 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 820 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 821 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 822 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 823 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 824 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 825 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 826 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 827 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f) 828 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 829 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 830 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 831 #endif 832 struct mpi3_io_unit_page2 { 833 struct mpi3_config_page_header header; 834 u8 gpio_count; 835 u8 reserved09[3]; 836 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX]; 837 }; 838 839 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 840 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc) 841 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 842 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 843 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 844 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 845 struct mpi3_io_unit3_sensor { 846 __le16 flags; 847 __le16 reserved02; 848 __le16 threshold[4]; 849 __le32 reserved0c; 850 __le32 reserved10; 851 __le32 reserved14; 852 }; 853 854 #define MPI3_IOUNIT3_SENSOR_FLAGS_T3_ENABLE (0x0008) 855 #define MPI3_IOUNIT3_SENSOR_FLAGS_T2_ENABLE (0x0004) 856 #define MPI3_IOUNIT3_SENSOR_FLAGS_T1_ENABLE (0x0002) 857 #define MPI3_IOUNIT3_SENSOR_FLAGS_T0_ENABLE (0x0001) 858 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 859 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 860 #endif 861 struct mpi3_io_unit_page3 { 862 struct mpi3_config_page_header header; 863 __le32 reserved08; 864 u8 num_sensors; 865 u8 polling_interval; 866 __le16 reserved0e; 867 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX]; 868 }; 869 870 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 871 struct mpi3_io_unit4_sensor { 872 __le16 current_temperature; 873 __le16 reserved02; 874 u8 flags; 875 u8 reserved05[3]; 876 __le32 reserved08; 877 __le32 reserved0c; 878 }; 879 880 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 881 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 882 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 883 #endif 884 struct mpi3_io_unit_page4 { 885 struct mpi3_config_page_header header; 886 __le32 reserved08; 887 u8 num_sensors; 888 u8 reserved0d[3]; 889 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX]; 890 }; 891 892 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 893 struct mpi3_io_unit5_spinup_group { 894 u8 max_target_spinup; 895 u8 spinup_delay; 896 u8 spinup_flags; 897 u8 reserved03; 898 }; 899 900 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 901 #ifndef MPI3_IO_UNIT5_PHY_MAX 902 #define MPI3_IO_UNIT5_PHY_MAX (4) 903 #endif 904 struct mpi3_io_unit_page5 { 905 struct mpi3_config_page_header header; 906 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4]; 907 __le32 reserved18; 908 __le32 reserved1c; 909 __le32 reserved20; 910 u8 reserved24; 911 u8 sata_device_wait_time; 912 u8 spinup_encl_drive_count; 913 u8 spinup_encl_delay; 914 u8 num_phys; 915 u8 pe_initial_spinup_delay; 916 u8 topology_stable_time; 917 u8 flags; 918 u8 phy[MPI3_IO_UNIT5_PHY_MAX]; 919 }; 920 921 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 922 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 923 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 924 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 925 struct mpi3_io_unit_page6 { 926 struct mpi3_config_page_header header; 927 __le32 board_power_requirement; 928 __le32 pci_slot_power_allocation; 929 u8 flags; 930 u8 reserved11[3]; 931 }; 932 933 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 934 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 935 struct mpi3_io_unit_page7 { 936 struct mpi3_config_page_header header; 937 __le32 reserved08; 938 }; 939 940 #define MPI3_IOUNIT7_PAGEVERSION (0x00) 941 #ifndef MPI3_IOUNIT8_DIGEST_MAX 942 #define MPI3_IOUNIT8_DIGEST_MAX (1) 943 #endif 944 union mpi3_iounit8_digest { 945 __le32 dword[16]; 946 __le16 word[32]; 947 u8 byte[64]; 948 }; 949 950 struct mpi3_io_unit_page8 { 951 struct mpi3_config_page_header header; 952 u8 sb_mode; 953 u8 sb_state; 954 __le16 reserved0a; 955 u8 num_slots; 956 u8 slots_available; 957 u8 current_key_encryption_algo; 958 u8 key_digest_hash_algo; 959 __le32 reserved10[2]; 960 __le32 current_key[128]; 961 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX]; 962 }; 963 964 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 965 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 966 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 967 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 968 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 969 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 970 struct mpi3_io_unit_page9 { 971 struct mpi3_config_page_header header; 972 __le32 flags; 973 __le16 first_device; 974 __le16 reserved0e; 975 }; 976 977 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 978 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x01) 979 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff) 980 struct mpi3_ioc_page0 { 981 struct mpi3_config_page_header header; 982 __le32 reserved08; 983 __le16 vendor_id; 984 __le16 device_id; 985 u8 revision_id; 986 u8 reserved11[3]; 987 __le32 class_code; 988 __le16 subsystem_vendor_id; 989 __le16 subsystem_id; 990 }; 991 992 #define MPI3_IOC0_PAGEVERSION (0x00) 993 struct mpi3_ioc_page1 { 994 struct mpi3_config_page_header header; 995 __le32 coalescing_timeout; 996 u8 coalescing_depth; 997 u8 pci_slot_num; 998 __le16 reserved0e; 999 }; 1000 1001 #define MPI3_IOC1_PAGEVERSION (0x00) 1002 #define MPI3_IOC1_PCISLOTNUM_UNKNOWN (0xff) 1003 #ifndef MPI3_IOC2_EVENTMASK_WORDS 1004 #define MPI3_IOC2_EVENTMASK_WORDS (4) 1005 #endif 1006 struct mpi3_ioc_page2 { 1007 struct mpi3_config_page_header header; 1008 __le32 reserved08; 1009 __le16 sas_broadcast_primitive_masks; 1010 __le16 sas_notify_primitive_masks; 1011 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS]; 1012 }; 1013 1014 #define MPI3_IOC2_PAGEVERSION (0x00) 1015 struct mpi3_uefibsd_page0 { 1016 struct mpi3_config_page_header header; 1017 __le32 bsd_options; 1018 u8 ssu_timeout; 1019 u8 io_timeout; 1020 u8 tur_retries; 1021 u8 tur_interval; 1022 u8 reserved10; 1023 u8 security_key_timeout; 1024 __le16 reserved12; 1025 __le32 reserved14; 1026 __le32 reserved18; 1027 }; 1028 1029 #define MPI3_UEFIBSD_PAGEVERSION (0x00) 1030 #define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_MASK (0x00000003) 1031 #define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 1032 #define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 1033 #define MPI3_UEFIBSD_BSDOPTS_REGISTRATION_NONE (0x00000002) 1034 #define MPI3_UEFIBSD_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 1035 #define MPI3_UEFIBSD_BSDOPTS_EN_ADV_ADAPTER_CONFIG (0x00000008) 1036 union mpi3_security_mac { 1037 __le32 dword[16]; 1038 __le16 word[32]; 1039 u8 byte[64]; 1040 }; 1041 1042 union mpi3_security_nonce { 1043 __le32 dword[16]; 1044 __le16 word[32]; 1045 u8 byte[64]; 1046 }; 1047 1048 union mpi3_security0_cert_chain { 1049 __le32 dword[1024]; 1050 __le16 word[2048]; 1051 u8 byte[4096]; 1052 }; 1053 1054 struct mpi3_security_page0 { 1055 struct mpi3_config_page_header header; 1056 u8 slot_num_group; 1057 u8 slot_num; 1058 __le16 cert_chain_length; 1059 u8 cert_chain_flags; 1060 u8 reserved0d[3]; 1061 __le32 base_asym_algo; 1062 __le32 base_hash_algo; 1063 __le32 reserved18[4]; 1064 union mpi3_security_mac mac; 1065 union mpi3_security_nonce nonce; 1066 union mpi3_security0_cert_chain certificate_chain; 1067 }; 1068 1069 #define MPI3_SECURITY0_PAGEVERSION (0x00) 1070 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e) 1071 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 1072 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 1073 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 1074 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 1075 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 1076 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 1077 #endif 1078 #ifndef MPI3_SECURITY1_PAD_MAX 1079 #define MPI3_SECURITY1_PAD_MAX 1 1080 #endif 1081 union mpi3_security1_key_data { 1082 __le32 dword[128]; 1083 __le16 word[256]; 1084 u8 byte[512]; 1085 }; 1086 1087 struct mpi3_security1_key_record { 1088 u8 flags; 1089 u8 consumer; 1090 __le16 key_data_size; 1091 __le32 additional_key_data; 1092 __le32 reserved08[2]; 1093 union mpi3_security1_key_data key_data; 1094 }; 1095 1096 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f) 1097 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 1098 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 1099 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 1100 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 1101 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 1102 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 1103 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 1104 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 1105 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_AUTH_DEV_KEY (0x03) 1106 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 1107 struct mpi3_security_page1 { 1108 struct mpi3_config_page_header header; 1109 __le32 reserved08[2]; 1110 union mpi3_security_mac mac; 1111 union mpi3_security_nonce nonce; 1112 u8 num_keys; 1113 u8 reserved91[3]; 1114 __le32 reserved94[3]; 1115 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX]; 1116 u8 pad[MPI3_SECURITY1_PAD_MAX]; 1117 }; 1118 1119 #define MPI3_SECURITY1_PAGEVERSION (0x00) 1120 struct mpi3_sas_io_unit0_phy_data { 1121 u8 io_unit_port; 1122 u8 port_flags; 1123 u8 phy_flags; 1124 u8 negotiated_link_rate; 1125 __le16 controller_phy_device_info; 1126 __le16 reserved06; 1127 __le16 attached_dev_handle; 1128 __le16 controller_dev_handle; 1129 __le32 discovery_status; 1130 __le32 reserved10; 1131 }; 1132 1133 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX 1134 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) 1135 #endif 1136 struct mpi3_sas_io_unit_page0 { 1137 struct mpi3_config_page_header header; 1138 __le32 reserved08; 1139 u8 num_phys; 1140 u8 reserved0d[3]; 1141 struct mpi3_sas_io_unit0_phy_data phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX]; 1142 }; 1143 1144 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 1145 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 1146 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1147 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1148 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1149 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1150 struct mpi3_sas_io_unit1_phy_data { 1151 u8 io_unit_port; 1152 u8 port_flags; 1153 u8 phy_flags; 1154 u8 max_min_link_rate; 1155 __le16 controller_phy_device_info; 1156 __le16 max_target_port_connect_time; 1157 __le32 reserved08; 1158 }; 1159 1160 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX 1161 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) 1162 #endif 1163 struct mpi3_sas_io_unit_page1 { 1164 struct mpi3_config_page_header header; 1165 __le16 control_flags; 1166 __le16 sas_narrow_max_queue_depth; 1167 __le16 additional_control_flags; 1168 __le16 sas_wide_max_queue_depth; 1169 u8 num_phys; 1170 u8 sata_max_q_depth; 1171 __le16 reserved12; 1172 struct mpi3_sas_io_unit1_phy_data phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX]; 1173 }; 1174 1175 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 1176 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 1177 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1178 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1179 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1180 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1181 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1182 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1183 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1184 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1185 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 1186 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 1187 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 1188 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 1189 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1190 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1191 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1192 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1193 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1194 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1195 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1196 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1197 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1198 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1199 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1200 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1201 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1202 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1203 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0) 1204 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0) 1205 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0) 1206 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f) 1207 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a) 1208 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b) 1209 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c) 1210 struct mpi3_sas_io_unit2_phy_pm_settings { 1211 u8 control_flags; 1212 u8 reserved01; 1213 __le16 inactivity_timer_exponent; 1214 u8 sata_partial_timeout; 1215 u8 reserved05; 1216 u8 sata_slumber_timeout; 1217 u8 reserved07; 1218 u8 sas_partial_timeout; 1219 u8 reserved09; 1220 u8 sas_slumber_timeout; 1221 u8 reserved0b; 1222 }; 1223 1224 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 1225 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 1226 #endif 1227 struct mpi3_sas_io_unit_page2 { 1228 struct mpi3_config_page_header header; 1229 u8 num_phys; 1230 u8 reserved09[3]; 1231 __le32 reserved0c; 1232 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX]; 1233 }; 1234 1235 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 1236 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1237 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1238 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1239 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1240 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 1241 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 1242 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 1243 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 1244 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 1245 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 1246 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 1247 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 1248 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 1249 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 1250 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 1251 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 1252 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 1253 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 1254 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 1255 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 1256 struct mpi3_sas_io_unit_page3 { 1257 struct mpi3_config_page_header header; 1258 __le32 reserved08; 1259 __le32 power_management_capabilities; 1260 }; 1261 1262 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 1263 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 1264 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 1265 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 1266 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 1267 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 1268 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 1269 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 1270 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 1271 struct mpi3_sas_expander_page0 { 1272 struct mpi3_config_page_header header; 1273 u8 io_unit_port; 1274 u8 report_gen_length; 1275 __le16 enclosure_handle; 1276 __le32 reserved0c; 1277 __le64 sas_address; 1278 __le32 discovery_status; 1279 __le16 dev_handle; 1280 __le16 parent_dev_handle; 1281 __le16 expander_change_count; 1282 __le16 expander_route_indexes; 1283 u8 num_phys; 1284 u8 sas_level; 1285 __le16 flags; 1286 __le16 stp_bus_inactivity_time_limit; 1287 __le16 stp_max_connect_time_limit; 1288 __le16 stp_smp_nexus_loss_time; 1289 __le16 max_num_routed_sas_addresses; 1290 __le64 active_zone_manager_sas_address; 1291 __le16 zone_lock_inactivity_limit; 1292 __le16 reserved3a; 1293 u8 time_to_reduced_func; 1294 u8 initial_time_to_reduced_func; 1295 u8 max_reduced_func_time; 1296 u8 exp_status; 1297 }; 1298 1299 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 1300 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 1301 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1302 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1303 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1304 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1305 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1306 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1307 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1308 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1309 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1310 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1311 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 1312 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 1313 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 1314 struct mpi3_sas_expander_page1 { 1315 struct mpi3_config_page_header header; 1316 u8 io_unit_port; 1317 u8 reserved09[3]; 1318 u8 num_phys; 1319 u8 phy; 1320 __le16 num_table_entries_programmed; 1321 u8 programmed_link_rate; 1322 u8 hw_link_rate; 1323 __le16 attached_dev_handle; 1324 __le32 phy_info; 1325 __le16 attached_device_info; 1326 __le16 reserved1a; 1327 __le16 expander_dev_handle; 1328 u8 change_count; 1329 u8 negotiated_link_rate; 1330 u8 phy_identifier; 1331 u8 attached_phy_identifier; 1332 u8 reserved22; 1333 u8 discovery_info; 1334 __le32 attached_phy_info; 1335 u8 zone_group; 1336 u8 self_config_status; 1337 __le16 reserved2a; 1338 __le16 slot; 1339 __le16 slot_index; 1340 }; 1341 1342 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 1343 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 1344 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 1345 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 1346 struct mpi3_sas_port_page0 { 1347 struct mpi3_config_page_header header; 1348 u8 port_number; 1349 u8 reserved09; 1350 u8 port_width; 1351 u8 reserved0b; 1352 u8 zone_group; 1353 u8 reserved0d[3]; 1354 __le64 sas_address; 1355 __le16 device_info; 1356 __le16 reserved1a; 1357 __le32 reserved1c; 1358 }; 1359 1360 #define MPI3_SASPORT0_PAGEVERSION (0x00) 1361 struct mpi3_sas_phy_page0 { 1362 struct mpi3_config_page_header header; 1363 __le16 owner_dev_handle; 1364 __le16 reserved0a; 1365 __le16 attached_dev_handle; 1366 u8 attached_phy_identifier; 1367 u8 reserved0f; 1368 __le32 attached_phy_info; 1369 u8 programmed_link_rate; 1370 u8 hw_link_rate; 1371 u8 change_count; 1372 u8 flags; 1373 __le32 phy_info; 1374 u8 negotiated_link_rate; 1375 u8 reserved1d[3]; 1376 __le16 slot; 1377 __le16 slot_index; 1378 }; 1379 1380 #define MPI3_SASPHY0_PAGEVERSION (0x00) 1381 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 1382 struct mpi3_sas_phy_page1 { 1383 struct mpi3_config_page_header header; 1384 __le32 reserved08; 1385 __le32 invalid_dword_count; 1386 __le32 running_disparity_error_count; 1387 __le32 loss_dword_synch_count; 1388 __le32 phy_reset_problem_count; 1389 }; 1390 1391 #define MPI3_SASPHY1_PAGEVERSION (0x00) 1392 struct mpi3_sas_phy2_phy_event { 1393 u8 phy_event_code; 1394 u8 reserved01[3]; 1395 __le32 phy_event_info; 1396 }; 1397 1398 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 1399 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 1400 #endif 1401 struct mpi3_sas_phy_page2 { 1402 struct mpi3_config_page_header header; 1403 __le32 reserved08; 1404 u8 num_phy_events; 1405 u8 reserved0d[3]; 1406 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX]; 1407 }; 1408 1409 #define MPI3_SASPHY2_PAGEVERSION (0x00) 1410 struct mpi3_sas_phy3_phy_event_config { 1411 u8 phy_event_code; 1412 u8 reserved01[3]; 1413 u8 counter_type; 1414 u8 threshold_window; 1415 u8 time_units; 1416 u8 reserved07; 1417 __le32 event_threshold; 1418 __le16 threshold_flags; 1419 __le16 reserved0e; 1420 }; 1421 1422 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 1423 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 1424 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 1425 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 1426 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 1427 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 1428 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 1429 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 1430 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 1431 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 1432 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 1433 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 1434 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 1435 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 1436 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 1437 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 1438 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 1439 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 1440 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 1441 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a) 1442 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b) 1443 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c) 1444 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d) 1445 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e) 1446 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f) 1447 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 1448 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 1449 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 1450 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 1451 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 1452 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 1453 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 1454 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 1455 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 1456 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 1457 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 1458 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 1459 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0) 1460 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1) 1461 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2) 1462 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3) 1463 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4) 1464 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5) 1465 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6) 1466 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7) 1467 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8) 1468 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9) 1469 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda) 1470 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb) 1471 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc) 1472 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 1473 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 1474 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 1475 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 1476 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 1477 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 1478 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 1479 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 1480 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 1481 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 1482 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 1483 #endif 1484 struct mpi3_sas_phy_page3 { 1485 struct mpi3_config_page_header header; 1486 __le32 reserved08; 1487 u8 num_phy_events; 1488 u8 reserved0d[3]; 1489 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX]; 1490 }; 1491 1492 #define MPI3_SASPHY3_PAGEVERSION (0x00) 1493 struct mpi3_sas_phy_page4 { 1494 struct mpi3_config_page_header header; 1495 u8 reserved08[3]; 1496 u8 flags; 1497 u8 initial_frame[28]; 1498 }; 1499 1500 #define MPI3_SASPHY4_PAGEVERSION (0x00) 1501 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 1502 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 1503 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 1504 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 1505 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f) 1506 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 1507 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 1508 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 1509 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 1510 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 1511 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 1512 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 1513 struct mpi3_pcie_io_unit0_phy_data { 1514 u8 link; 1515 u8 link_flags; 1516 u8 phy_flags; 1517 u8 negotiated_link_rate; 1518 __le16 attached_dev_handle; 1519 __le16 controller_dev_handle; 1520 __le32 enumeration_status; 1521 u8 io_unit_port; 1522 u8 reserved0d[3]; 1523 }; 1524 1525 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 1526 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 1527 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 1528 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 1529 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1530 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 1531 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 1532 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 1533 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 1534 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 1535 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 1536 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 1537 #endif 1538 struct mpi3_pcie_io_unit_page0 { 1539 struct mpi3_config_page_header header; 1540 __le32 reserved08; 1541 u8 num_phys; 1542 u8 init_status; 1543 __le16 reserved0e; 1544 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX]; 1545 }; 1546 1547 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 1548 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 1549 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 1550 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 1551 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 1552 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 1553 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 1554 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 1555 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 1556 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 1557 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0) 1558 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff) 1559 struct mpi3_pcie_io_unit1_phy_data { 1560 u8 link; 1561 u8 link_flags; 1562 u8 phy_flags; 1563 u8 max_min_link_rate; 1564 __le32 reserved04; 1565 __le32 reserved08; 1566 }; 1567 1568 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 1569 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 1570 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 1571 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 1572 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1573 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1574 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1575 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 1576 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 1577 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 1578 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 1579 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 1580 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 1581 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 1582 #endif 1583 struct mpi3_pcie_io_unit_page1 { 1584 struct mpi3_config_page_header header; 1585 __le32 control_flags; 1586 __le32 reserved0c; 1587 u8 num_phys; 1588 u8 reserved11; 1589 __le16 reserved12; 1590 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX]; 1591 }; 1592 1593 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 1594 struct mpi3_pcie_io_unit_page2 { 1595 struct mpi3_config_page_header header; 1596 __le16 nv_me_max_queue_depth; 1597 __le16 reserved0a; 1598 u8 nv_me_abort_to; 1599 u8 reserved0d; 1600 __le16 reserved0e; 1601 }; 1602 1603 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 1604 struct mpi3_pcie_switch_page0 { 1605 struct mpi3_config_page_header header; 1606 u8 io_unit_port; 1607 u8 switch_status; 1608 u8 reserved0a[2]; 1609 __le16 dev_handle; 1610 __le16 parent_dev_handle; 1611 u8 num_ports; 1612 u8 pc_ie_level; 1613 __le16 reserved12; 1614 __le32 reserved14; 1615 __le32 reserved18; 1616 __le32 reserved1c; 1617 }; 1618 1619 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 1620 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 1621 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 1622 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 1623 struct mpi3_pcie_switch_page1 { 1624 struct mpi3_config_page_header header; 1625 u8 io_unit_port; 1626 u8 reserved09[3]; 1627 u8 num_ports; 1628 u8 port_num; 1629 __le16 attached_dev_handle; 1630 __le16 switch_dev_handle; 1631 u8 negotiated_port_width; 1632 u8 negotiated_link_rate; 1633 __le16 slot; 1634 __le16 slot_index; 1635 __le32 reserved18; 1636 }; 1637 1638 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 1639 struct mpi3_pcie_link_page0 { 1640 struct mpi3_config_page_header header; 1641 u8 link; 1642 u8 reserved09[3]; 1643 __le32 correctable_error_count; 1644 __le16 n_fatal_error_count; 1645 __le16 reserved12; 1646 __le16 fatal_error_count; 1647 __le16 reserved16; 1648 }; 1649 1650 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 1651 struct mpi3_enclosure_page0 { 1652 struct mpi3_config_page_header header; 1653 __le64 enclosure_logical_id; 1654 __le16 flags; 1655 __le16 enclosure_handle; 1656 __le16 num_slots; 1657 __le16 start_slot; 1658 u8 io_unit_port; 1659 u8 enclosure_level; 1660 __le16 sep_dev_handle; 1661 __le32 reserved1c; 1662 }; 1663 1664 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 1665 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000) 1666 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 1667 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 1668 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 1669 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 1670 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 1671 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 1672 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f) 1673 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 1674 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 1675 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 1676 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 1677 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 1678 #define MPI3_DEVICE_DEVFORM_VD (0x02) 1679 struct mpi3_device0_sas_sata_format { 1680 __le64 sas_address; 1681 __le16 flags; 1682 __le16 device_info; 1683 u8 phy_num; 1684 u8 attached_phy_identifier; 1685 u8 max_port_connections; 1686 u8 zone_group; 1687 }; 1688 1689 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 1690 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 1691 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 1692 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 1693 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 1694 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 1695 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 1696 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 1697 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 1698 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 1699 struct mpi3_device0_pcie_format { 1700 u8 supported_link_rates; 1701 u8 max_port_width; 1702 u8 negotiated_port_width; 1703 u8 negotiated_link_rate; 1704 u8 port_num; 1705 u8 controller_reset_to; 1706 __le16 device_info; 1707 __le32 maximum_data_transfer_size; 1708 __le32 capabilities; 1709 __le16 noiob; 1710 u8 nv_me_abort_to; 1711 u8 page_size; 1712 __le16 shutdown_latency; 1713 __le16 reserved16; 1714 }; 1715 1716 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 1717 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 1718 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 1719 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 1720 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 1721 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0003) 1722 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 1723 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 1724 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 1725 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 1726 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 1727 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 1728 #define MPI3_DEVICE0_PCIE_CAP_NVME_SGL_ENABLED (0x00000004) 1729 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 1730 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 1731 struct mpi3_device0_vd_format { 1732 u8 vd_state; 1733 u8 raid_level; 1734 __le16 device_info; 1735 __le16 flags; 1736 __le16 reserved06; 1737 __le32 reserved08[2]; 1738 }; 1739 1740 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 1741 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 1742 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 1743 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 1744 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 1745 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 1746 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 1747 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 1748 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 1749 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 1750 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 1751 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 1752 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 1753 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 1754 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 1755 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 1756 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_MASK (0x0003) 1757 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_NONE (0x0000) 1758 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_HOST (0x0001) 1759 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_IOC (0x0002) 1760 union mpi3_device0_dev_spec_format { 1761 struct mpi3_device0_sas_sata_format sas_sata_format; 1762 struct mpi3_device0_pcie_format pcie_format; 1763 struct mpi3_device0_vd_format vd_format; 1764 }; 1765 1766 struct mpi3_device_page0 { 1767 struct mpi3_config_page_header header; 1768 __le16 dev_handle; 1769 __le16 parent_dev_handle; 1770 __le16 slot; 1771 __le16 enclosure_handle; 1772 __le64 wwid; 1773 __le16 persistent_id; 1774 u8 io_unit_port; 1775 u8 access_status; 1776 __le16 flags; 1777 __le16 reserved1e; 1778 __le16 slot_index; 1779 __le16 queue_depth; 1780 u8 reserved24[3]; 1781 u8 device_form; 1782 union mpi3_device0_dev_spec_format device_specific; 1783 }; 1784 1785 #define MPI3_DEVICE0_PAGEVERSION (0x00) 1786 #define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff) 1787 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff) 1788 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff) 1789 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 1790 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 1791 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 1792 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 1793 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 1794 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 1795 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 1796 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 1797 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 1798 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 1799 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 1800 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 1801 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 1802 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 1803 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 1804 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 1805 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 1806 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 1807 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 1808 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f) 1809 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 1810 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 1811 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 1812 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 1813 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 1814 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 1815 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 1816 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 1817 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 1818 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 1819 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 1820 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 1821 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 1822 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 1823 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x50) 1824 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 1825 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 1826 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_MASK (0x0006) 1827 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_NOT_DIR_ATTACHED (0x0000) 1828 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 1829 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 1830 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 1831 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 1832 struct mpi3_device1_sas_sata_format { 1833 __le32 reserved00; 1834 }; 1835 1836 struct mpi3_device1_pcie_format { 1837 __le16 vendor_id; 1838 __le16 device_id; 1839 __le16 subsystem_vendor_id; 1840 __le16 subsystem_id; 1841 __le32 reserved08; 1842 u8 revision_id; 1843 u8 reserved0d; 1844 __le16 pci_parameters; 1845 }; 1846 1847 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 1848 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 1849 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 1850 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 1851 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 1852 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 1853 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0) 1854 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 1855 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 1856 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 1857 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 1858 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 1859 struct mpi3_device1_vd_format { 1860 __le32 reserved00; 1861 }; 1862 1863 union mpi3_device1_dev_spec_format { 1864 struct mpi3_device1_sas_sata_format sas_sata_format; 1865 struct mpi3_device1_pcie_format pcie_format; 1866 struct mpi3_device1_vd_format vd_format; 1867 }; 1868 1869 struct mpi3_device_page1 { 1870 struct mpi3_config_page_header header; 1871 __le16 dev_handle; 1872 __le16 reserved0a; 1873 __le32 reserved0c[12]; 1874 u8 reserved3c[3]; 1875 u8 device_form; 1876 union mpi3_device1_dev_spec_format device_specific; 1877 }; 1878 1879 #define MPI3_DEVICE1_PAGEVERSION (0x00) 1880 #endif 1881