1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mesh.h: definitions for the driver for the MESH SCSI bus adaptor 4 * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers. 5 * 6 * Copyright (C) 1996 Paul Mackerras. 7 */ 8 #ifndef _MESH_H 9 #define _MESH_H 10 11 struct mesh_cmd_priv { 12 int this_residual; 13 int message; 14 int status; 15 }; 16 17 static inline struct mesh_cmd_priv *mesh_priv(struct scsi_cmnd *cmd) 18 { 19 return scsi_cmd_priv(cmd); 20 } 21 22 /* 23 * Registers in the MESH controller. 24 */ 25 26 struct mesh_regs { 27 unsigned char count_lo; 28 char pad0[15]; 29 unsigned char count_hi; 30 char pad1[15]; 31 unsigned char fifo; 32 char pad2[15]; 33 unsigned char sequence; 34 char pad3[15]; 35 unsigned char bus_status0; 36 char pad4[15]; 37 unsigned char bus_status1; 38 char pad5[15]; 39 unsigned char fifo_count; 40 char pad6[15]; 41 unsigned char exception; 42 char pad7[15]; 43 unsigned char error; 44 char pad8[15]; 45 unsigned char intr_mask; 46 char pad9[15]; 47 unsigned char interrupt; 48 char pad10[15]; 49 unsigned char source_id; 50 char pad11[15]; 51 unsigned char dest_id; 52 char pad12[15]; 53 unsigned char sync_params; 54 char pad13[15]; 55 unsigned char mesh_id; 56 char pad14[15]; 57 unsigned char sel_timeout; 58 char pad15[15]; 59 }; 60 61 /* Bits in the sequence register. */ 62 #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */ 63 #define SEQ_TARGET 0x40 /* put the controller into target mode */ 64 #define SEQ_ATN 0x20 /* assert ATN signal */ 65 #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */ 66 #define SEQ_CMD 0x0f /* command bits: */ 67 #define SEQ_ARBITRATE 1 /* get the bus */ 68 #define SEQ_SELECT 2 /* select a target */ 69 #define SEQ_COMMAND 3 /* send a command */ 70 #define SEQ_STATUS 4 /* receive status */ 71 #define SEQ_DATAOUT 5 /* send data */ 72 #define SEQ_DATAIN 6 /* receive data */ 73 #define SEQ_MSGOUT 7 /* send a message */ 74 #define SEQ_MSGIN 8 /* receive a message */ 75 #define SEQ_BUSFREE 9 /* look for bus free */ 76 #define SEQ_ENBPARITY 0x0a /* enable parity checking */ 77 #define SEQ_DISPARITY 0x0b /* disable parity checking */ 78 #define SEQ_ENBRESEL 0x0c /* enable reselection */ 79 #define SEQ_DISRESEL 0x0d /* disable reselection */ 80 #define SEQ_RESETMESH 0x0e /* reset the controller */ 81 #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */ 82 83 /* Bits in the bus_status0 and bus_status1 registers: 84 these correspond directly to the SCSI bus control signals. */ 85 #define BS0_REQ 0x20 86 #define BS0_ACK 0x10 87 #define BS0_ATN 0x08 88 #define BS0_MSG 0x04 89 #define BS0_CD 0x02 90 #define BS0_IO 0x01 91 #define BS1_RST 0x80 92 #define BS1_BSY 0x40 93 #define BS1_SEL 0x20 94 95 /* Bus phases defined by the bits in bus_status0 */ 96 #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO) 97 #define BP_DATAOUT 0 98 #define BP_DATAIN BS0_IO 99 #define BP_COMMAND BS0_CD 100 #define BP_STATUS (BS0_CD+BS0_IO) 101 #define BP_MSGOUT (BS0_MSG+BS0_CD) 102 #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO) 103 104 /* Bits in the exception register. */ 105 #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */ 106 #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */ 107 #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */ 108 #define EXC_ARBLOST 0x04 /* we lost arbitration */ 109 #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */ 110 #define EXC_SELTO 0x01 /* selection timeout */ 111 112 /* Bits in the error register */ 113 #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */ 114 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */ 115 #define ERR_SEQERR 0x10 /* we did something the chip didn't like */ 116 #define ERR_PARITY 0x01 /* parity error was detected */ 117 118 /* Bits in the interrupt and intr_mask registers */ 119 #define INT_ERROR 0x04 /* error interrupt */ 120 #define INT_EXCEPTION 0x02 /* exception interrupt */ 121 #define INT_CMDDONE 0x01 /* command done interrupt */ 122 123 /* Fields in the sync_params register */ 124 #define SYNC_OFF(x) ((x) >> 4) /* offset field */ 125 #define SYNC_PER(x) ((x) & 0xf) /* period field */ 126 #define SYNC_PARAMS(o, p) (((o) << 4) | (p)) 127 #define ASYNC_PARAMS 2 /* sync_params value for async xfers */ 128 129 /* 130 * Assuming a clock frequency of 50MHz: 131 * 132 * The transfer period with SYNC_PER(sync_params) == x 133 * is (x + 2) * 40ns, except that x == 0 gives 100ns. 134 * 135 * The units of the sel_timeout register are 10ms. 136 */ 137 138 139 #endif /* _MESH_H */ 140