xref: /openbmc/linux/drivers/scsi/mesh.c (revision 36fe4655)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
4  * bus adaptor found on Power Macintosh computers.
5  * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
6  * controller.
7  *
8  * Paul Mackerras, August 1996.
9  * Copyright (C) 1996 Paul Mackerras.
10  *
11  * Apr. 21 2002  - BenH		Rework bus reset code for new error handler
12  *                              Add delay after initial bus reset
13  *                              Add module parameters
14  *
15  * Sep. 27 2003  - BenH		Move to new driver model, fix some write posting
16  *				issues
17  * To do:
18  * - handle aborts correctly
19  * - retry arbitration if lost (unless higher levels do this for us)
20  * - power down the chip when no device is detected
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
27 #include <linux/blkdev.h>
28 #include <linux/proc_fs.h>
29 #include <linux/stat.h>
30 #include <linux/interrupt.h>
31 #include <linux/reboot.h>
32 #include <linux/spinlock.h>
33 #include <linux/pci.h>
34 #include <linux/pgtable.h>
35 #include <asm/dbdma.h>
36 #include <asm/io.h>
37 #include <asm/prom.h>
38 #include <asm/irq.h>
39 #include <asm/hydra.h>
40 #include <asm/processor.h>
41 #include <asm/machdep.h>
42 #include <asm/pmac_feature.h>
43 #include <asm/macio.h>
44 
45 #include <scsi/scsi.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_host.h>
49 
50 #include "mesh.h"
51 
52 #if 1
53 #undef KERN_DEBUG
54 #define KERN_DEBUG KERN_WARNING
55 #endif
56 
57 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
58 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
59 MODULE_LICENSE("GPL");
60 
61 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
62 static int sync_targets = 0xff;
63 static int resel_targets = 0xff;
64 static int debug_targets = 0;	/* print debug for these targets */
65 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
66 
67 module_param(sync_rate, int, 0);
68 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
69 module_param(sync_targets, int, 0);
70 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
71 module_param(resel_targets, int, 0);
72 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
73 module_param(debug_targets, int, 0644);
74 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
75 module_param(init_reset_delay, int, 0);
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
77 
78 static int mesh_sync_period = 100;
79 static int mesh_sync_offset = 0;
80 static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
81 
82 #define ALLOW_SYNC(tgt)		((sync_targets >> (tgt)) & 1)
83 #define ALLOW_RESEL(tgt)	((resel_targets >> (tgt)) & 1)
84 #define ALLOW_DEBUG(tgt)	((debug_targets >> (tgt)) & 1)
85 #define DEBUG_TARGET(cmd)	((cmd) && ALLOW_DEBUG((cmd)->device->id))
86 
87 #undef MESH_DBG
88 #define N_DBG_LOG	50
89 #define N_DBG_SLOG	20
90 #define NUM_DBG_EVENTS	13
91 #undef	DBG_USE_TB		/* bombs on 601 */
92 
93 struct dbglog {
94 	char	*fmt;
95 	u32	tb;
96 	u8	phase;
97 	u8	bs0;
98 	u8	bs1;
99 	u8	tgt;
100 	int	d;
101 };
102 
103 enum mesh_phase {
104 	idle,
105 	arbitrating,
106 	selecting,
107 	commanding,
108 	dataing,
109 	statusing,
110 	busfreeing,
111 	disconnecting,
112 	reselecting,
113 	sleeping
114 };
115 
116 enum msg_phase {
117 	msg_none,
118 	msg_out,
119 	msg_out_xxx,
120 	msg_out_last,
121 	msg_in,
122 	msg_in_bad,
123 };
124 
125 enum sdtr_phase {
126 	do_sdtr,
127 	sdtr_sent,
128 	sdtr_done
129 };
130 
131 struct mesh_target {
132 	enum sdtr_phase sdtr_state;
133 	int	sync_params;
134 	int	data_goes_out;		/* guess as to data direction */
135 	struct scsi_cmnd *current_req;
136 	u32	saved_ptr;
137 #ifdef MESH_DBG
138 	int	log_ix;
139 	int	n_log;
140 	struct dbglog log[N_DBG_LOG];
141 #endif
142 };
143 
144 struct mesh_state {
145 	volatile struct	mesh_regs __iomem *mesh;
146 	int	meshintr;
147 	volatile struct	dbdma_regs __iomem *dma;
148 	int	dmaintr;
149 	struct	Scsi_Host *host;
150 	struct	mesh_state *next;
151 	struct scsi_cmnd *request_q;
152 	struct scsi_cmnd *request_qtail;
153 	enum mesh_phase phase;		/* what we're currently trying to do */
154 	enum msg_phase msgphase;
155 	int	conn_tgt;		/* target we're connected to */
156 	struct scsi_cmnd *current_req;		/* req we're currently working on */
157 	int	data_ptr;
158 	int	dma_started;
159 	int	dma_count;
160 	int	stat;
161 	int	aborting;
162 	int	expect_reply;
163 	int	n_msgin;
164 	u8	msgin[16];
165 	int	n_msgout;
166 	int	last_n_msgout;
167 	u8	msgout[16];
168 	struct dbdma_cmd *dma_cmds;	/* space for dbdma commands, aligned */
169 	dma_addr_t dma_cmd_bus;
170 	void	*dma_cmd_space;
171 	int	dma_cmd_size;
172 	int	clk_freq;
173 	struct mesh_target tgts[8];
174 	struct macio_dev *mdev;
175 	struct pci_dev* pdev;
176 #ifdef MESH_DBG
177 	int	log_ix;
178 	int	n_log;
179 	struct dbglog log[N_DBG_SLOG];
180 #endif
181 };
182 
183 /*
184  * Driver is too messy, we need a few prototypes...
185  */
186 static void mesh_done(struct mesh_state *ms, int start_next);
187 static void mesh_interrupt(struct mesh_state *ms);
188 static void cmd_complete(struct mesh_state *ms);
189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
190 static void halt_dma(struct mesh_state *ms);
191 static void phase_mismatch(struct mesh_state *ms);
192 
193 
194 /*
195  * Some debugging & logging routines
196  */
197 
198 #ifdef MESH_DBG
199 
200 static inline u32 readtb(void)
201 {
202 	u32 tb;
203 
204 #ifdef DBG_USE_TB
205 	/* Beware: if you enable this, it will crash on 601s. */
206 	asm ("mftb %0" : "=r" (tb) : );
207 #else
208 	tb = 0;
209 #endif
210 	return tb;
211 }
212 
213 static void dlog(struct mesh_state *ms, char *fmt, int a)
214 {
215 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
216 	struct dbglog *tlp, *slp;
217 
218 	tlp = &tp->log[tp->log_ix];
219 	slp = &ms->log[ms->log_ix];
220 	tlp->fmt = fmt;
221 	tlp->tb = readtb();
222 	tlp->phase = (ms->msgphase << 4) + ms->phase;
223 	tlp->bs0 = ms->mesh->bus_status0;
224 	tlp->bs1 = ms->mesh->bus_status1;
225 	tlp->tgt = ms->conn_tgt;
226 	tlp->d = a;
227 	*slp = *tlp;
228 	if (++tp->log_ix >= N_DBG_LOG)
229 		tp->log_ix = 0;
230 	if (tp->n_log < N_DBG_LOG)
231 		++tp->n_log;
232 	if (++ms->log_ix >= N_DBG_SLOG)
233 		ms->log_ix = 0;
234 	if (ms->n_log < N_DBG_SLOG)
235 		++ms->n_log;
236 }
237 
238 static void dumplog(struct mesh_state *ms, int t)
239 {
240 	struct mesh_target *tp = &ms->tgts[t];
241 	struct dbglog *lp;
242 	int i;
243 
244 	if (tp->n_log == 0)
245 		return;
246 	i = tp->log_ix - tp->n_log;
247 	if (i < 0)
248 		i += N_DBG_LOG;
249 	tp->n_log = 0;
250 	do {
251 		lp = &tp->log[i];
252 		printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
253 		       t, lp->bs1, lp->bs0, lp->phase);
254 #ifdef DBG_USE_TB
255 		printk("tb=%10u ", lp->tb);
256 #endif
257 		printk(lp->fmt, lp->d);
258 		printk("\n");
259 		if (++i >= N_DBG_LOG)
260 			i = 0;
261 	} while (i != tp->log_ix);
262 }
263 
264 static void dumpslog(struct mesh_state *ms)
265 {
266 	struct dbglog *lp;
267 	int i;
268 
269 	if (ms->n_log == 0)
270 		return;
271 	i = ms->log_ix - ms->n_log;
272 	if (i < 0)
273 		i += N_DBG_SLOG;
274 	ms->n_log = 0;
275 	do {
276 		lp = &ms->log[i];
277 		printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
278 		       lp->bs1, lp->bs0, lp->phase, lp->tgt);
279 #ifdef DBG_USE_TB
280 		printk("tb=%10u ", lp->tb);
281 #endif
282 		printk(lp->fmt, lp->d);
283 		printk("\n");
284 		if (++i >= N_DBG_SLOG)
285 			i = 0;
286 	} while (i != ms->log_ix);
287 }
288 
289 #else
290 
291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
292 {}
293 static inline void dumplog(struct mesh_state *ms, int tgt)
294 {}
295 static inline void dumpslog(struct mesh_state *ms)
296 {}
297 
298 #endif /* MESH_DBG */
299 
300 #define MKWORD(a, b, c, d)	(((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
301 
302 static void
303 mesh_dump_regs(struct mesh_state *ms)
304 {
305 	volatile struct mesh_regs __iomem *mr = ms->mesh;
306 	volatile struct dbdma_regs __iomem *md = ms->dma;
307 	int t;
308 	struct mesh_target *tp;
309 
310 	printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
311 	       ms, mr, md);
312 	printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
313 	       "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
314 	       (mr->count_hi << 8) + mr->count_lo, mr->sequence,
315 	       (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
316 	       mr->exception, mr->error, mr->intr_mask, mr->interrupt,
317 	       mr->sync_params);
318 	while(in_8(&mr->fifo_count))
319 		printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
320 	printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
321 	       in_le32(&md->status), in_le32(&md->cmdptr));
322 	printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
323 	       ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
324 	printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
325 	       ms->dma_started, ms->dma_count, ms->n_msgout);
326 	for (t = 0; t < 8; ++t) {
327 		tp = &ms->tgts[t];
328 		if (tp->current_req == NULL)
329 			continue;
330 		printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
331 		       t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
332 	}
333 }
334 
335 
336 /*
337  * Flush write buffers on the bus path to the mesh
338  */
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
340 {
341 	(void)in_8(&mr->mesh_id);
342 }
343 
344 
345 /*
346  * Complete a SCSI command
347  */
348 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
349 {
350 	(*cmd->scsi_done)(cmd);
351 }
352 
353 
354 /* Called with  meshinterrupt disabled, initialize the chipset
355  * and eventually do the initial bus reset. The lock must not be
356  * held since we can schedule.
357  */
358 static void mesh_init(struct mesh_state *ms)
359 {
360 	volatile struct mesh_regs __iomem *mr = ms->mesh;
361 	volatile struct dbdma_regs __iomem *md = ms->dma;
362 
363 	mesh_flush_io(mr);
364 	udelay(100);
365 
366 	/* Reset controller */
367 	out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);	/* stop dma */
368 	out_8(&mr->exception, 0xff);	/* clear all exception bits */
369 	out_8(&mr->error, 0xff);	/* clear all error bits */
370 	out_8(&mr->sequence, SEQ_RESETMESH);
371 	mesh_flush_io(mr);
372 	udelay(10);
373 	out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
374 	out_8(&mr->source_id, ms->host->this_id);
375 	out_8(&mr->sel_timeout, 25);	/* 250ms */
376 	out_8(&mr->sync_params, ASYNC_PARAMS);
377 
378 	if (init_reset_delay) {
379 		printk(KERN_INFO "mesh: performing initial bus reset...\n");
380 
381 		/* Reset bus */
382 		out_8(&mr->bus_status1, BS1_RST);	/* assert RST */
383 		mesh_flush_io(mr);
384 		udelay(30);			/* leave it on for >= 25us */
385 		out_8(&mr->bus_status1, 0);	/* negate RST */
386 		mesh_flush_io(mr);
387 
388 		/* Wait for bus to come back */
389 		msleep(init_reset_delay);
390 	}
391 
392 	/* Reconfigure controller */
393 	out_8(&mr->interrupt, 0xff);	/* clear all interrupt bits */
394 	out_8(&mr->sequence, SEQ_FLUSHFIFO);
395 	mesh_flush_io(mr);
396 	udelay(1);
397 	out_8(&mr->sync_params, ASYNC_PARAMS);
398 	out_8(&mr->sequence, SEQ_ENBRESEL);
399 
400 	ms->phase = idle;
401 	ms->msgphase = msg_none;
402 }
403 
404 
405 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
406 {
407 	volatile struct mesh_regs __iomem *mr = ms->mesh;
408 	int t, id;
409 
410 	id = cmd->device->id;
411 	ms->current_req = cmd;
412 	ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
413 	ms->tgts[id].current_req = cmd;
414 
415 #if 1
416 	if (DEBUG_TARGET(cmd)) {
417 		int i;
418 		printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
419 		for (i = 0; i < cmd->cmd_len; ++i)
420 			printk(" %x", cmd->cmnd[i]);
421 		printk(" use_sg=%d buffer=%p bufflen=%u\n",
422 		       scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
423 	}
424 #endif
425 	if (ms->dma_started)
426 		panic("mesh: double DMA start !\n");
427 
428 	ms->phase = arbitrating;
429 	ms->msgphase = msg_none;
430 	ms->data_ptr = 0;
431 	ms->dma_started = 0;
432 	ms->n_msgout = 0;
433 	ms->last_n_msgout = 0;
434 	ms->expect_reply = 0;
435 	ms->conn_tgt = id;
436 	ms->tgts[id].saved_ptr = 0;
437 	ms->stat = DID_OK;
438 	ms->aborting = 0;
439 #ifdef MESH_DBG
440 	ms->tgts[id].n_log = 0;
441 	dlog(ms, "start cmd=%x", (int) cmd);
442 #endif
443 
444 	/* Off we go */
445 	dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
446 	     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
447 	out_8(&mr->interrupt, INT_CMDDONE);
448 	out_8(&mr->sequence, SEQ_ENBRESEL);
449 	mesh_flush_io(mr);
450 	udelay(1);
451 
452 	if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
453 		/*
454 		 * Some other device has the bus or is arbitrating for it -
455 		 * probably a target which is about to reselect us.
456 		 */
457 		dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
458 		     MKWORD(mr->interrupt, mr->exception,
459 			    mr->error, mr->fifo_count));
460 		for (t = 100; t > 0; --t) {
461 			if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
462 				break;
463 			if (in_8(&mr->interrupt) != 0) {
464 				dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
465 				     MKWORD(mr->interrupt, mr->exception,
466 					    mr->error, mr->fifo_count));
467 				mesh_interrupt(ms);
468 				if (ms->phase != arbitrating)
469 					return;
470 			}
471 			udelay(1);
472 		}
473 		if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
474 			/* XXX should try again in a little while */
475 			ms->stat = DID_BUS_BUSY;
476 			ms->phase = idle;
477 			mesh_done(ms, 0);
478 			return;
479 		}
480 	}
481 
482 	/*
483 	 * Apparently the mesh has a bug where it will assert both its
484 	 * own bit and the target's bit on the bus during arbitration.
485 	 */
486 	out_8(&mr->dest_id, mr->source_id);
487 
488 	/*
489 	 * There appears to be a race with reselection sometimes,
490 	 * where a target reselects us just as we issue the
491 	 * arbitrate command.  It seems that then the arbitrate
492 	 * command just hangs waiting for the bus to be free
493 	 * without giving us a reselection exception.
494 	 * The only way I have found to get it to respond correctly
495 	 * is this: disable reselection before issuing the arbitrate
496 	 * command, then after issuing it, if it looks like a target
497 	 * is trying to reselect us, reset the mesh and then enable
498 	 * reselection.
499 	 */
500 	out_8(&mr->sequence, SEQ_DISRESEL);
501 	if (in_8(&mr->interrupt) != 0) {
502 		dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
503 		     MKWORD(mr->interrupt, mr->exception,
504 			    mr->error, mr->fifo_count));
505 		mesh_interrupt(ms);
506 		if (ms->phase != arbitrating)
507 			return;
508 		dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
509 		     MKWORD(mr->interrupt, mr->exception,
510 			    mr->error, mr->fifo_count));
511 	}
512 
513 	out_8(&mr->sequence, SEQ_ARBITRATE);
514 
515 	for (t = 230; t > 0; --t) {
516 		if (in_8(&mr->interrupt) != 0)
517 			break;
518 		udelay(1);
519 	}
520 	dlog(ms, "after arb, intr/exc/err/fc=%.8x",
521 	     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
522 	if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
523 	    && (in_8(&mr->bus_status0) & BS0_IO)) {
524 		/* looks like a reselection - try resetting the mesh */
525 		dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
526 		     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
527 		out_8(&mr->sequence, SEQ_RESETMESH);
528 		mesh_flush_io(mr);
529 		udelay(10);
530 		out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
531 		out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
532 		out_8(&mr->sequence, SEQ_ENBRESEL);
533 		mesh_flush_io(mr);
534 		for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
535 			udelay(1);
536 		dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
537 		     MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
538 #ifndef MESH_MULTIPLE_HOSTS
539 		if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
540 		    && (in_8(&mr->bus_status0) & BS0_IO)) {
541 			printk(KERN_ERR "mesh: controller not responding"
542 			       " to reselection!\n");
543 			/*
544 			 * If this is a target reselecting us, and the
545 			 * mesh isn't responding, the higher levels of
546 			 * the scsi code will eventually time out and
547 			 * reset the bus.
548 			 */
549 		}
550 #endif
551 	}
552 }
553 
554 /*
555  * Start the next command for a MESH.
556  * Should be called with interrupts disabled.
557  */
558 static void mesh_start(struct mesh_state *ms)
559 {
560 	struct scsi_cmnd *cmd, *prev, *next;
561 
562 	if (ms->phase != idle || ms->current_req != NULL) {
563 		printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
564 		       ms->phase, ms);
565 		return;
566 	}
567 
568 	while (ms->phase == idle) {
569 		prev = NULL;
570 		for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
571 			if (cmd == NULL)
572 				return;
573 			if (ms->tgts[cmd->device->id].current_req == NULL)
574 				break;
575 			prev = cmd;
576 		}
577 		next = (struct scsi_cmnd *) cmd->host_scribble;
578 		if (prev == NULL)
579 			ms->request_q = next;
580 		else
581 			prev->host_scribble = (void *) next;
582 		if (next == NULL)
583 			ms->request_qtail = prev;
584 
585 		mesh_start_cmd(ms, cmd);
586 	}
587 }
588 
589 static void mesh_done(struct mesh_state *ms, int start_next)
590 {
591 	struct scsi_cmnd *cmd;
592 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
593 
594 	cmd = ms->current_req;
595 	ms->current_req = NULL;
596 	tp->current_req = NULL;
597 	if (cmd) {
598 		cmd->result = (ms->stat << 16) | cmd->SCp.Status;
599 		if (ms->stat == DID_OK)
600 			cmd->result |= cmd->SCp.Message << 8;
601 		if (DEBUG_TARGET(cmd)) {
602 			printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
603 			       cmd->result, ms->data_ptr, scsi_bufflen(cmd));
604 #if 0
605 			/* needs to use sg? */
606 			if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
607 			    && cmd->request_buffer != 0) {
608 				unsigned char *b = cmd->request_buffer;
609 				printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
610 				       b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
611 			}
612 #endif
613 		}
614 		cmd->SCp.this_residual -= ms->data_ptr;
615 		mesh_completed(ms, cmd);
616 	}
617 	if (start_next) {
618 		out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
619 		mesh_flush_io(ms->mesh);
620 		udelay(1);
621 		ms->phase = idle;
622 		mesh_start(ms);
623 	}
624 }
625 
626 static inline void add_sdtr_msg(struct mesh_state *ms)
627 {
628 	int i = ms->n_msgout;
629 
630 	ms->msgout[i] = EXTENDED_MESSAGE;
631 	ms->msgout[i+1] = 3;
632 	ms->msgout[i+2] = EXTENDED_SDTR;
633 	ms->msgout[i+3] = mesh_sync_period/4;
634 	ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
635 	ms->n_msgout = i + 5;
636 }
637 
638 static void set_sdtr(struct mesh_state *ms, int period, int offset)
639 {
640 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
641 	volatile struct mesh_regs __iomem *mr = ms->mesh;
642 	int v, tr;
643 
644 	tp->sdtr_state = sdtr_done;
645 	if (offset == 0) {
646 		/* asynchronous */
647 		if (SYNC_OFF(tp->sync_params))
648 			printk(KERN_INFO "mesh: target %d now asynchronous\n",
649 			       ms->conn_tgt);
650 		tp->sync_params = ASYNC_PARAMS;
651 		out_8(&mr->sync_params, ASYNC_PARAMS);
652 		return;
653 	}
654 	/*
655 	 * We need to compute ceil(clk_freq * period / 500e6) - 2
656 	 * without incurring overflow.
657 	 */
658 	v = (ms->clk_freq / 5000) * period;
659 	if (v <= 250000) {
660 		/* special case: sync_period == 5 * clk_period */
661 		v = 0;
662 		/* units of tr are 100kB/s */
663 		tr = (ms->clk_freq + 250000) / 500000;
664 	} else {
665 		/* sync_period == (v + 2) * 2 * clk_period */
666 		v = (v + 99999) / 100000 - 2;
667 		if (v > 15)
668 			v = 15;	/* oops */
669 		tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
670 	}
671 	if (offset > 15)
672 		offset = 15;	/* can't happen */
673 	tp->sync_params = SYNC_PARAMS(offset, v);
674 	out_8(&mr->sync_params, tp->sync_params);
675 	printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
676 	       ms->conn_tgt, tr/10, tr%10);
677 }
678 
679 static void start_phase(struct mesh_state *ms)
680 {
681 	int i, seq, nb;
682 	volatile struct mesh_regs __iomem *mr = ms->mesh;
683 	volatile struct dbdma_regs __iomem *md = ms->dma;
684 	struct scsi_cmnd *cmd = ms->current_req;
685 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
686 
687 	dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
688 	     MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
689 	out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
690 	seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
691 	switch (ms->msgphase) {
692 	case msg_none:
693 		break;
694 
695 	case msg_in:
696 		out_8(&mr->count_hi, 0);
697 		out_8(&mr->count_lo, 1);
698 		out_8(&mr->sequence, SEQ_MSGIN + seq);
699 		ms->n_msgin = 0;
700 		return;
701 
702 	case msg_out:
703 		/*
704 		 * To make sure ATN drops before we assert ACK for
705 		 * the last byte of the message, we have to do the
706 		 * last byte specially.
707 		 */
708 		if (ms->n_msgout <= 0) {
709 			printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
710 			       ms->n_msgout);
711 			mesh_dump_regs(ms);
712 			ms->msgphase = msg_none;
713 			break;
714 		}
715 		if (ALLOW_DEBUG(ms->conn_tgt)) {
716 			printk(KERN_DEBUG "mesh: sending %d msg bytes:",
717 			       ms->n_msgout);
718 			for (i = 0; i < ms->n_msgout; ++i)
719 				printk(" %x", ms->msgout[i]);
720 			printk("\n");
721 		}
722 		dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
723 						ms->msgout[1], ms->msgout[2]));
724 		out_8(&mr->count_hi, 0);
725 		out_8(&mr->sequence, SEQ_FLUSHFIFO);
726 		mesh_flush_io(mr);
727 		udelay(1);
728 		/*
729 		 * If ATN is not already asserted, we assert it, then
730 		 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
731 		 */
732 		if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
733 			dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
734 			out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
735 			mesh_flush_io(mr);
736 			udelay(1);
737 			out_8(&mr->count_lo, 1);
738 			out_8(&mr->sequence, SEQ_MSGOUT + seq);
739 			out_8(&mr->bus_status0, 0); /* release explicit ATN */
740 			dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
741 		}
742 		if (ms->n_msgout == 1) {
743 			/*
744 			 * We can't issue the SEQ_MSGOUT without ATN
745 			 * until the target has asserted REQ.  The logic
746 			 * in cmd_complete handles both situations:
747 			 * REQ already asserted or not.
748 			 */
749 			cmd_complete(ms);
750 		} else {
751 			out_8(&mr->count_lo, ms->n_msgout - 1);
752 			out_8(&mr->sequence, SEQ_MSGOUT + seq);
753 			for (i = 0; i < ms->n_msgout - 1; ++i)
754 				out_8(&mr->fifo, ms->msgout[i]);
755 		}
756 		return;
757 
758 	default:
759 		printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
760 		       ms->msgphase);
761 	}
762 
763 	switch (ms->phase) {
764 	case selecting:
765 		out_8(&mr->dest_id, ms->conn_tgt);
766 		out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
767 		break;
768 	case commanding:
769 		out_8(&mr->sync_params, tp->sync_params);
770 		out_8(&mr->count_hi, 0);
771 		if (cmd) {
772 			out_8(&mr->count_lo, cmd->cmd_len);
773 			out_8(&mr->sequence, SEQ_COMMAND + seq);
774 			for (i = 0; i < cmd->cmd_len; ++i)
775 				out_8(&mr->fifo, cmd->cmnd[i]);
776 		} else {
777 			out_8(&mr->count_lo, 6);
778 			out_8(&mr->sequence, SEQ_COMMAND + seq);
779 			for (i = 0; i < 6; ++i)
780 				out_8(&mr->fifo, 0);
781 		}
782 		break;
783 	case dataing:
784 		/* transfer data, if any */
785 		if (!ms->dma_started) {
786 			set_dma_cmds(ms, cmd);
787 			out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
788 			out_le32(&md->control, (RUN << 16) | RUN);
789 			ms->dma_started = 1;
790 		}
791 		nb = ms->dma_count;
792 		if (nb > 0xfff0)
793 			nb = 0xfff0;
794 		ms->dma_count -= nb;
795 		ms->data_ptr += nb;
796 		out_8(&mr->count_lo, nb);
797 		out_8(&mr->count_hi, nb >> 8);
798 		out_8(&mr->sequence, (tp->data_goes_out?
799 				SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
800 		break;
801 	case statusing:
802 		out_8(&mr->count_hi, 0);
803 		out_8(&mr->count_lo, 1);
804 		out_8(&mr->sequence, SEQ_STATUS + seq);
805 		break;
806 	case busfreeing:
807 	case disconnecting:
808 		out_8(&mr->sequence, SEQ_ENBRESEL);
809 		mesh_flush_io(mr);
810 		udelay(1);
811 		dlog(ms, "enbresel intr/exc/err/fc=%.8x",
812 		     MKWORD(mr->interrupt, mr->exception, mr->error,
813 			    mr->fifo_count));
814 		out_8(&mr->sequence, SEQ_BUSFREE);
815 		break;
816 	default:
817 		printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
818 		       ms->phase);
819 		dumpslog(ms);
820 	}
821 
822 }
823 
824 static inline void get_msgin(struct mesh_state *ms)
825 {
826 	volatile struct mesh_regs __iomem *mr = ms->mesh;
827 	int i, n;
828 
829 	n = mr->fifo_count;
830 	if (n != 0) {
831 		i = ms->n_msgin;
832 		ms->n_msgin = i + n;
833 		for (; n > 0; --n)
834 			ms->msgin[i++] = in_8(&mr->fifo);
835 	}
836 }
837 
838 static inline int msgin_length(struct mesh_state *ms)
839 {
840 	int b, n;
841 
842 	n = 1;
843 	if (ms->n_msgin > 0) {
844 		b = ms->msgin[0];
845 		if (b == 1) {
846 			/* extended message */
847 			n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
848 		} else if (0x20 <= b && b <= 0x2f) {
849 			/* 2-byte message */
850 			n = 2;
851 		}
852 	}
853 	return n;
854 }
855 
856 static void reselected(struct mesh_state *ms)
857 {
858 	volatile struct mesh_regs __iomem *mr = ms->mesh;
859 	struct scsi_cmnd *cmd;
860 	struct mesh_target *tp;
861 	int b, t, prev;
862 
863 	switch (ms->phase) {
864 	case idle:
865 		break;
866 	case arbitrating:
867 		if ((cmd = ms->current_req) != NULL) {
868 			/* put the command back on the queue */
869 			cmd->host_scribble = (void *) ms->request_q;
870 			if (ms->request_q == NULL)
871 				ms->request_qtail = cmd;
872 			ms->request_q = cmd;
873 			tp = &ms->tgts[cmd->device->id];
874 			tp->current_req = NULL;
875 		}
876 		break;
877 	case busfreeing:
878 		ms->phase = reselecting;
879 		mesh_done(ms, 0);
880 		break;
881 	case disconnecting:
882 		break;
883 	default:
884 		printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
885 		       ms->msgphase, ms->phase, ms->conn_tgt);
886 		dumplog(ms, ms->conn_tgt);
887 		dumpslog(ms);
888 	}
889 
890 	if (ms->dma_started) {
891 		printk(KERN_ERR "mesh: reselected with DMA started !\n");
892 		halt_dma(ms);
893 	}
894 	ms->current_req = NULL;
895 	ms->phase = dataing;
896 	ms->msgphase = msg_in;
897 	ms->n_msgout = 0;
898 	ms->last_n_msgout = 0;
899 	prev = ms->conn_tgt;
900 
901 	/*
902 	 * We seem to get abortive reselections sometimes.
903 	 */
904 	while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
905 		static int mesh_aborted_resels;
906 		mesh_aborted_resels++;
907 		out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
908 		mesh_flush_io(mr);
909 		udelay(1);
910 		out_8(&mr->sequence, SEQ_ENBRESEL);
911 		mesh_flush_io(mr);
912 		udelay(5);
913 		dlog(ms, "extra resel err/exc/fc = %.6x",
914 		     MKWORD(0, mr->error, mr->exception, mr->fifo_count));
915 	}
916 	out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
917        	mesh_flush_io(mr);
918 	udelay(1);
919 	out_8(&mr->sequence, SEQ_ENBRESEL);
920        	mesh_flush_io(mr);
921 	udelay(1);
922 	out_8(&mr->sync_params, ASYNC_PARAMS);
923 
924 	/*
925 	 * Find out who reselected us.
926 	 */
927 	if (in_8(&mr->fifo_count) == 0) {
928 		printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
929 		ms->conn_tgt = ms->host->this_id;
930 		goto bogus;
931 	}
932 	/* get the last byte in the fifo */
933 	do {
934 		b = in_8(&mr->fifo);
935 		dlog(ms, "reseldata %x", b);
936 	} while (in_8(&mr->fifo_count));
937 	for (t = 0; t < 8; ++t)
938 		if ((b & (1 << t)) != 0 && t != ms->host->this_id)
939 			break;
940 	if (b != (1 << t) + (1 << ms->host->this_id)) {
941 		printk(KERN_ERR "mesh: bad reselection data %x\n", b);
942 		ms->conn_tgt = ms->host->this_id;
943 		goto bogus;
944 	}
945 
946 
947 	/*
948 	 * Set up to continue with that target's transfer.
949 	 */
950 	ms->conn_tgt = t;
951 	tp = &ms->tgts[t];
952 	out_8(&mr->sync_params, tp->sync_params);
953 	if (ALLOW_DEBUG(t)) {
954 		printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
955 		printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
956 		       tp->saved_ptr, tp->data_goes_out, tp->current_req);
957 	}
958 	ms->current_req = tp->current_req;
959 	if (tp->current_req == NULL) {
960 		printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
961 		goto bogus;
962 	}
963 	ms->data_ptr = tp->saved_ptr;
964 	dlog(ms, "resel prev tgt=%d", prev);
965 	dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
966 	start_phase(ms);
967 	return;
968 
969 bogus:
970 	dumplog(ms, ms->conn_tgt);
971 	dumpslog(ms);
972 	ms->data_ptr = 0;
973 	ms->aborting = 1;
974 	start_phase(ms);
975 }
976 
977 static void do_abort(struct mesh_state *ms)
978 {
979 	ms->msgout[0] = ABORT;
980 	ms->n_msgout = 1;
981 	ms->aborting = 1;
982 	ms->stat = DID_ABORT;
983 	dlog(ms, "abort", 0);
984 }
985 
986 static void handle_reset(struct mesh_state *ms)
987 {
988 	int tgt;
989 	struct mesh_target *tp;
990 	struct scsi_cmnd *cmd;
991 	volatile struct mesh_regs __iomem *mr = ms->mesh;
992 
993 	for (tgt = 0; tgt < 8; ++tgt) {
994 		tp = &ms->tgts[tgt];
995 		if ((cmd = tp->current_req) != NULL) {
996 			cmd->result = DID_RESET << 16;
997 			tp->current_req = NULL;
998 			mesh_completed(ms, cmd);
999 		}
1000 		ms->tgts[tgt].sdtr_state = do_sdtr;
1001 		ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1002 	}
1003 	ms->current_req = NULL;
1004 	while ((cmd = ms->request_q) != NULL) {
1005 		ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1006 		cmd->result = DID_RESET << 16;
1007 		mesh_completed(ms, cmd);
1008 	}
1009 	ms->phase = idle;
1010 	ms->msgphase = msg_none;
1011 	out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1012 	out_8(&mr->sequence, SEQ_FLUSHFIFO);
1013        	mesh_flush_io(mr);
1014 	udelay(1);
1015 	out_8(&mr->sync_params, ASYNC_PARAMS);
1016 	out_8(&mr->sequence, SEQ_ENBRESEL);
1017 }
1018 
1019 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1020 {
1021 	unsigned long flags;
1022 	struct mesh_state *ms = dev_id;
1023 	struct Scsi_Host *dev = ms->host;
1024 
1025 	spin_lock_irqsave(dev->host_lock, flags);
1026 	mesh_interrupt(ms);
1027 	spin_unlock_irqrestore(dev->host_lock, flags);
1028 	return IRQ_HANDLED;
1029 }
1030 
1031 static void handle_error(struct mesh_state *ms)
1032 {
1033 	int err, exc, count;
1034 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1035 
1036 	err = in_8(&mr->error);
1037 	exc = in_8(&mr->exception);
1038 	out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1039 	dlog(ms, "error err/exc/fc/cl=%.8x",
1040 	     MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1041 	if (err & ERR_SCSIRESET) {
1042 		/* SCSI bus was reset */
1043 		printk(KERN_INFO "mesh: SCSI bus reset detected: "
1044 		       "waiting for end...");
1045 		while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1046 			udelay(1);
1047 		printk("done\n");
1048 		if (ms->dma_started)
1049 			halt_dma(ms);
1050 		handle_reset(ms);
1051 		/* request_q is empty, no point in mesh_start() */
1052 		return;
1053 	}
1054 	if (err & ERR_UNEXPDISC) {
1055 		/* Unexpected disconnect */
1056 		if (exc & EXC_RESELECTED) {
1057 			reselected(ms);
1058 			return;
1059 		}
1060 		if (!ms->aborting) {
1061 			printk(KERN_WARNING "mesh: target %d aborted\n",
1062 			       ms->conn_tgt);
1063 			dumplog(ms, ms->conn_tgt);
1064 			dumpslog(ms);
1065 		}
1066 		out_8(&mr->interrupt, INT_CMDDONE);
1067 		ms->stat = DID_ABORT;
1068 		mesh_done(ms, 1);
1069 		return;
1070 	}
1071 	if (err & ERR_PARITY) {
1072 		if (ms->msgphase == msg_in) {
1073 			printk(KERN_ERR "mesh: msg parity error, target %d\n",
1074 			       ms->conn_tgt);
1075 			ms->msgout[0] = MSG_PARITY_ERROR;
1076 			ms->n_msgout = 1;
1077 			ms->msgphase = msg_in_bad;
1078 			cmd_complete(ms);
1079 			return;
1080 		}
1081 		if (ms->stat == DID_OK) {
1082 			printk(KERN_ERR "mesh: parity error, target %d\n",
1083 			       ms->conn_tgt);
1084 			ms->stat = DID_PARITY;
1085 		}
1086 		count = (mr->count_hi << 8) + mr->count_lo;
1087 		if (count == 0) {
1088 			cmd_complete(ms);
1089 		} else {
1090 			/* reissue the data transfer command */
1091 			out_8(&mr->sequence, mr->sequence);
1092 		}
1093 		return;
1094 	}
1095 	if (err & ERR_SEQERR) {
1096 		if (exc & EXC_RESELECTED) {
1097 			/* This can happen if we issue a command to
1098 			   get the bus just after the target reselects us. */
1099 			static int mesh_resel_seqerr;
1100 			mesh_resel_seqerr++;
1101 			reselected(ms);
1102 			return;
1103 		}
1104 		if (exc == EXC_PHASEMM) {
1105 			static int mesh_phasemm_seqerr;
1106 			mesh_phasemm_seqerr++;
1107 			phase_mismatch(ms);
1108 			return;
1109 		}
1110 		printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1111 		       err, exc);
1112 	} else {
1113 		printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1114 	}
1115 	mesh_dump_regs(ms);
1116 	dumplog(ms, ms->conn_tgt);
1117 	if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1118 		/* try to do what the target wants */
1119 		do_abort(ms);
1120 		phase_mismatch(ms);
1121 		return;
1122 	}
1123 	ms->stat = DID_ERROR;
1124 	mesh_done(ms, 1);
1125 }
1126 
1127 static void handle_exception(struct mesh_state *ms)
1128 {
1129 	int exc;
1130 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1131 
1132 	exc = in_8(&mr->exception);
1133 	out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1134 	if (exc & EXC_RESELECTED) {
1135 		static int mesh_resel_exc;
1136 		mesh_resel_exc++;
1137 		reselected(ms);
1138 	} else if (exc == EXC_ARBLOST) {
1139 		printk(KERN_DEBUG "mesh: lost arbitration\n");
1140 		ms->stat = DID_BUS_BUSY;
1141 		mesh_done(ms, 1);
1142 	} else if (exc == EXC_SELTO) {
1143 		/* selection timed out */
1144 		ms->stat = DID_BAD_TARGET;
1145 		mesh_done(ms, 1);
1146 	} else if (exc == EXC_PHASEMM) {
1147 		/* target wants to do something different:
1148 		   find out what it wants and do it. */
1149 		phase_mismatch(ms);
1150 	} else {
1151 		printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1152 		mesh_dump_regs(ms);
1153 		dumplog(ms, ms->conn_tgt);
1154 		do_abort(ms);
1155 		phase_mismatch(ms);
1156 	}
1157 }
1158 
1159 static void handle_msgin(struct mesh_state *ms)
1160 {
1161 	int i, code;
1162 	struct scsi_cmnd *cmd = ms->current_req;
1163 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1164 
1165 	if (ms->n_msgin == 0)
1166 		return;
1167 	code = ms->msgin[0];
1168 	if (ALLOW_DEBUG(ms->conn_tgt)) {
1169 		printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1170 		for (i = 0; i < ms->n_msgin; ++i)
1171 			printk(" %x", ms->msgin[i]);
1172 		printk("\n");
1173 	}
1174 	dlog(ms, "msgin msg=%.8x",
1175 	     MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1176 
1177 	ms->expect_reply = 0;
1178 	ms->n_msgout = 0;
1179 	if (ms->n_msgin < msgin_length(ms))
1180 		goto reject;
1181 	if (cmd)
1182 		cmd->SCp.Message = code;
1183 	switch (code) {
1184 	case COMMAND_COMPLETE:
1185 		break;
1186 	case EXTENDED_MESSAGE:
1187 		switch (ms->msgin[2]) {
1188 		case EXTENDED_MODIFY_DATA_POINTER:
1189 			ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1190 				+ (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1191 			break;
1192 		case EXTENDED_SDTR:
1193 			if (tp->sdtr_state != sdtr_sent) {
1194 				/* reply with an SDTR */
1195 				add_sdtr_msg(ms);
1196 				/* limit period to at least his value,
1197 				   offset to no more than his */
1198 				if (ms->msgout[3] < ms->msgin[3])
1199 					ms->msgout[3] = ms->msgin[3];
1200 				if (ms->msgout[4] > ms->msgin[4])
1201 					ms->msgout[4] = ms->msgin[4];
1202 				set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1203 				ms->msgphase = msg_out;
1204 			} else {
1205 				set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1206 			}
1207 			break;
1208 		default:
1209 			goto reject;
1210 		}
1211 		break;
1212 	case SAVE_POINTERS:
1213 		tp->saved_ptr = ms->data_ptr;
1214 		break;
1215 	case RESTORE_POINTERS:
1216 		ms->data_ptr = tp->saved_ptr;
1217 		break;
1218 	case DISCONNECT:
1219 		ms->phase = disconnecting;
1220 		break;
1221 	case ABORT:
1222 		break;
1223 	case MESSAGE_REJECT:
1224 		if (tp->sdtr_state == sdtr_sent)
1225 			set_sdtr(ms, 0, 0);
1226 		break;
1227 	case NOP:
1228 		break;
1229 	default:
1230 		if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1231 			if (cmd == NULL) {
1232 				do_abort(ms);
1233 				ms->msgphase = msg_out;
1234 			} else if (code != cmd->device->lun + IDENTIFY_BASE) {
1235 				printk(KERN_WARNING "mesh: lun mismatch "
1236 				       "(%d != %llu) on reselection from "
1237 				       "target %d\n", code - IDENTIFY_BASE,
1238 				       cmd->device->lun, ms->conn_tgt);
1239 			}
1240 			break;
1241 		}
1242 		goto reject;
1243 	}
1244 	return;
1245 
1246  reject:
1247 	printk(KERN_WARNING "mesh: rejecting message from target %d:",
1248 	       ms->conn_tgt);
1249 	for (i = 0; i < ms->n_msgin; ++i)
1250 		printk(" %x", ms->msgin[i]);
1251 	printk("\n");
1252 	ms->msgout[0] = MESSAGE_REJECT;
1253 	ms->n_msgout = 1;
1254 	ms->msgphase = msg_out;
1255 }
1256 
1257 /*
1258  * Set up DMA commands for transferring data.
1259  */
1260 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1261 {
1262 	int i, dma_cmd, total, off, dtot;
1263 	struct scatterlist *scl;
1264 	struct dbdma_cmd *dcmds;
1265 
1266 	dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1267 		OUTPUT_MORE: INPUT_MORE;
1268 	dcmds = ms->dma_cmds;
1269 	dtot = 0;
1270 	if (cmd) {
1271 		int nseg;
1272 
1273 		cmd->SCp.this_residual = scsi_bufflen(cmd);
1274 
1275 		nseg = scsi_dma_map(cmd);
1276 		BUG_ON(nseg < 0);
1277 
1278 		if (nseg) {
1279 			total = 0;
1280 			off = ms->data_ptr;
1281 
1282 			scsi_for_each_sg(cmd, scl, nseg, i) {
1283 				u32 dma_addr = sg_dma_address(scl);
1284 				u32 dma_len = sg_dma_len(scl);
1285 
1286 				total += scl->length;
1287 				if (off >= dma_len) {
1288 					off -= dma_len;
1289 					continue;
1290 				}
1291 				if (dma_len > 0xffff)
1292 					panic("mesh: scatterlist element >= 64k");
1293 				dcmds->req_count = cpu_to_le16(dma_len - off);
1294 				dcmds->command = cpu_to_le16(dma_cmd);
1295 				dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1296 				dcmds->xfer_status = 0;
1297 				++dcmds;
1298 				dtot += dma_len - off;
1299 				off = 0;
1300 			}
1301 		}
1302 	}
1303 	if (dtot == 0) {
1304 		/* Either the target has overrun our buffer,
1305 		   or the caller didn't provide a buffer. */
1306 		static char mesh_extra_buf[64];
1307 
1308 		dtot = sizeof(mesh_extra_buf);
1309 		dcmds->req_count = cpu_to_le16(dtot);
1310 		dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1311 		dcmds->xfer_status = 0;
1312 		++dcmds;
1313 	}
1314 	dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1315 	dcmds[-1].command = cpu_to_le16(dma_cmd);
1316 	memset(dcmds, 0, sizeof(*dcmds));
1317 	dcmds->command = cpu_to_le16(DBDMA_STOP);
1318 	ms->dma_count = dtot;
1319 }
1320 
1321 static void halt_dma(struct mesh_state *ms)
1322 {
1323 	volatile struct dbdma_regs __iomem *md = ms->dma;
1324 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1325 	struct scsi_cmnd *cmd = ms->current_req;
1326 	int t, nb;
1327 
1328 	if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1329 		/* wait a little while until the fifo drains */
1330 		t = 50;
1331 		while (t > 0 && in_8(&mr->fifo_count) != 0
1332 		       && (in_le32(&md->status) & ACTIVE) != 0) {
1333 			--t;
1334 			udelay(1);
1335 		}
1336 	}
1337 	out_le32(&md->control, RUN << 16);	/* turn off RUN bit */
1338 	nb = (mr->count_hi << 8) + mr->count_lo;
1339 	dlog(ms, "halt_dma fc/count=%.6x",
1340 	     MKWORD(0, mr->fifo_count, 0, nb));
1341 	if (ms->tgts[ms->conn_tgt].data_goes_out)
1342 		nb += mr->fifo_count;
1343 	/* nb is the number of bytes not yet transferred
1344 	   to/from the target. */
1345 	ms->data_ptr -= nb;
1346 	dlog(ms, "data_ptr %x", ms->data_ptr);
1347 	if (ms->data_ptr < 0) {
1348 		printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1349 		       ms->data_ptr, nb, ms);
1350 		ms->data_ptr = 0;
1351 #ifdef MESH_DBG
1352 		dumplog(ms, ms->conn_tgt);
1353 		dumpslog(ms);
1354 #endif /* MESH_DBG */
1355 	} else if (cmd && scsi_bufflen(cmd) &&
1356 		   ms->data_ptr > scsi_bufflen(cmd)) {
1357 		printk(KERN_DEBUG "mesh: target %d overrun, "
1358 		       "data_ptr=%x total=%x goes_out=%d\n",
1359 		       ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1360 		       ms->tgts[ms->conn_tgt].data_goes_out);
1361 	}
1362 	if (cmd)
1363 		scsi_dma_unmap(cmd);
1364 	ms->dma_started = 0;
1365 }
1366 
1367 static void phase_mismatch(struct mesh_state *ms)
1368 {
1369 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1370 	int phase;
1371 
1372 	dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1373 	     MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1374 	phase = in_8(&mr->bus_status0) & BS0_PHASE;
1375 	if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1376 		/* output the last byte of the message, without ATN */
1377 		out_8(&mr->count_lo, 1);
1378 		out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1379 		mesh_flush_io(mr);
1380 		udelay(1);
1381 		out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1382 		ms->msgphase = msg_out_last;
1383 		return;
1384 	}
1385 
1386 	if (ms->msgphase == msg_in) {
1387 		get_msgin(ms);
1388 		if (ms->n_msgin)
1389 			handle_msgin(ms);
1390 	}
1391 
1392 	if (ms->dma_started)
1393 		halt_dma(ms);
1394 	if (mr->fifo_count) {
1395 		out_8(&mr->sequence, SEQ_FLUSHFIFO);
1396 		mesh_flush_io(mr);
1397 		udelay(1);
1398 	}
1399 
1400 	ms->msgphase = msg_none;
1401 	switch (phase) {
1402 	case BP_DATAIN:
1403 		ms->tgts[ms->conn_tgt].data_goes_out = 0;
1404 		ms->phase = dataing;
1405 		break;
1406 	case BP_DATAOUT:
1407 		ms->tgts[ms->conn_tgt].data_goes_out = 1;
1408 		ms->phase = dataing;
1409 		break;
1410 	case BP_COMMAND:
1411 		ms->phase = commanding;
1412 		break;
1413 	case BP_STATUS:
1414 		ms->phase = statusing;
1415 		break;
1416 	case BP_MSGIN:
1417 		ms->msgphase = msg_in;
1418 		ms->n_msgin = 0;
1419 		break;
1420 	case BP_MSGOUT:
1421 		ms->msgphase = msg_out;
1422 		if (ms->n_msgout == 0) {
1423 			if (ms->aborting) {
1424 				do_abort(ms);
1425 			} else {
1426 				if (ms->last_n_msgout == 0) {
1427 					printk(KERN_DEBUG
1428 					       "mesh: no msg to repeat\n");
1429 					ms->msgout[0] = NOP;
1430 					ms->last_n_msgout = 1;
1431 				}
1432 				ms->n_msgout = ms->last_n_msgout;
1433 			}
1434 		}
1435 		break;
1436 	default:
1437 		printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1438 		ms->stat = DID_ERROR;
1439 		mesh_done(ms, 1);
1440 		return;
1441 	}
1442 
1443 	start_phase(ms);
1444 }
1445 
1446 static void cmd_complete(struct mesh_state *ms)
1447 {
1448 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1449 	struct scsi_cmnd *cmd = ms->current_req;
1450 	struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1451 	int seq, n, t;
1452 
1453 	dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1454 	seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1455 	switch (ms->msgphase) {
1456 	case msg_out_xxx:
1457 		/* huh?  we expected a phase mismatch */
1458 		ms->n_msgin = 0;
1459 		ms->msgphase = msg_in;
1460 		fallthrough;
1461 
1462 	case msg_in:
1463 		/* should have some message bytes in fifo */
1464 		get_msgin(ms);
1465 		n = msgin_length(ms);
1466 		if (ms->n_msgin < n) {
1467 			out_8(&mr->count_lo, n - ms->n_msgin);
1468 			out_8(&mr->sequence, SEQ_MSGIN + seq);
1469 		} else {
1470 			ms->msgphase = msg_none;
1471 			handle_msgin(ms);
1472 			start_phase(ms);
1473 		}
1474 		break;
1475 
1476 	case msg_in_bad:
1477 		out_8(&mr->sequence, SEQ_FLUSHFIFO);
1478 		mesh_flush_io(mr);
1479 		udelay(1);
1480 		out_8(&mr->count_lo, 1);
1481 		out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1482 		break;
1483 
1484 	case msg_out:
1485 		/*
1486 		 * To get the right timing on ATN wrt ACK, we have
1487 		 * to get the MESH to drop ACK, wait until REQ gets
1488 		 * asserted, then drop ATN.  To do this we first
1489 		 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1490 		 * then change the command to a SEQ_MSGOUT w/o ATN.
1491 		 * If we don't see REQ in a reasonable time, we
1492 		 * change the command to SEQ_MSGIN with ATN,
1493 		 * wait for the phase mismatch interrupt, then
1494 		 * issue the SEQ_MSGOUT without ATN.
1495 		 */
1496 		out_8(&mr->count_lo, 1);
1497 		out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1498 		t = 30;		/* wait up to 30us */
1499 		while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1500 			udelay(1);
1501 		dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1502 		     MKWORD(mr->error, mr->exception,
1503 			    mr->fifo_count, mr->count_lo));
1504 		if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1505 			/* whoops, target didn't do what we expected */
1506 			ms->last_n_msgout = ms->n_msgout;
1507 			ms->n_msgout = 0;
1508 			if (in_8(&mr->interrupt) & INT_ERROR) {
1509 				printk(KERN_ERR "mesh: error %x in msg_out\n",
1510 				       in_8(&mr->error));
1511 				handle_error(ms);
1512 				return;
1513 			}
1514 			if (in_8(&mr->exception) != EXC_PHASEMM)
1515 				printk(KERN_ERR "mesh: exc %x in msg_out\n",
1516 				       in_8(&mr->exception));
1517 			else
1518 				printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1519 				       in_8(&mr->bus_status0));
1520 			handle_exception(ms);
1521 			return;
1522 		}
1523 		if (in_8(&mr->bus_status0) & BS0_REQ) {
1524 			out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1525 			mesh_flush_io(mr);
1526 			udelay(1);
1527 			out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1528 			ms->msgphase = msg_out_last;
1529 		} else {
1530 			out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1531 			ms->msgphase = msg_out_xxx;
1532 		}
1533 		break;
1534 
1535 	case msg_out_last:
1536 		ms->last_n_msgout = ms->n_msgout;
1537 		ms->n_msgout = 0;
1538 		ms->msgphase = ms->expect_reply? msg_in: msg_none;
1539 		start_phase(ms);
1540 		break;
1541 
1542 	case msg_none:
1543 		switch (ms->phase) {
1544 		case idle:
1545 			printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1546 			dumpslog(ms);
1547 			return;
1548 		case selecting:
1549 			dlog(ms, "Selecting phase at command completion",0);
1550 			ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1551 						 (cmd? cmd->device->lun: 0));
1552 			ms->n_msgout = 1;
1553 			ms->expect_reply = 0;
1554 			if (ms->aborting) {
1555 				ms->msgout[0] = ABORT;
1556 				ms->n_msgout++;
1557 			} else if (tp->sdtr_state == do_sdtr) {
1558 				/* add SDTR message */
1559 				add_sdtr_msg(ms);
1560 				ms->expect_reply = 1;
1561 				tp->sdtr_state = sdtr_sent;
1562 			}
1563 			ms->msgphase = msg_out;
1564 			/*
1565 			 * We need to wait for REQ before dropping ATN.
1566 			 * We wait for at most 30us, then fall back to
1567 			 * a scheme where we issue a SEQ_COMMAND with ATN,
1568 			 * which will give us a phase mismatch interrupt
1569 			 * when REQ does come, and then we send the message.
1570 			 */
1571 			t = 230;		/* wait up to 230us */
1572 			while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1573 				if (--t < 0) {
1574 					dlog(ms, "impatient for req", ms->n_msgout);
1575 					ms->msgphase = msg_none;
1576 					break;
1577 				}
1578 				udelay(1);
1579 			}
1580 			break;
1581 		case dataing:
1582 			if (ms->dma_count != 0) {
1583 				start_phase(ms);
1584 				return;
1585 			}
1586 			/*
1587 			 * We can get a phase mismatch here if the target
1588 			 * changes to the status phase, even though we have
1589 			 * had a command complete interrupt.  Then, if we
1590 			 * issue the SEQ_STATUS command, we'll get a sequence
1591 			 * error interrupt.  Which isn't so bad except that
1592 			 * occasionally the mesh actually executes the
1593 			 * SEQ_STATUS *as well as* giving us the sequence
1594 			 * error and phase mismatch exception.
1595 			 */
1596 			out_8(&mr->sequence, 0);
1597 			out_8(&mr->interrupt,
1598 			      INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1599 			halt_dma(ms);
1600 			break;
1601 		case statusing:
1602 			if (cmd) {
1603 				cmd->SCp.Status = mr->fifo;
1604 				if (DEBUG_TARGET(cmd))
1605 					printk(KERN_DEBUG "mesh: status is %x\n",
1606 					       cmd->SCp.Status);
1607 			}
1608 			ms->msgphase = msg_in;
1609 			break;
1610 		case busfreeing:
1611 			mesh_done(ms, 1);
1612 			return;
1613 		case disconnecting:
1614 			ms->current_req = NULL;
1615 			ms->phase = idle;
1616 			mesh_start(ms);
1617 			return;
1618 		default:
1619 			break;
1620 		}
1621 		++ms->phase;
1622 		start_phase(ms);
1623 		break;
1624 	}
1625 }
1626 
1627 
1628 /*
1629  * Called by midlayer with host locked to queue a new
1630  * request
1631  */
1632 static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1633 {
1634 	struct mesh_state *ms;
1635 
1636 	cmd->scsi_done = done;
1637 	cmd->host_scribble = NULL;
1638 
1639 	ms = (struct mesh_state *) cmd->device->host->hostdata;
1640 
1641 	if (ms->request_q == NULL)
1642 		ms->request_q = cmd;
1643 	else
1644 		ms->request_qtail->host_scribble = (void *) cmd;
1645 	ms->request_qtail = cmd;
1646 
1647 	if (ms->phase == idle)
1648 		mesh_start(ms);
1649 
1650 	return 0;
1651 }
1652 
1653 static DEF_SCSI_QCMD(mesh_queue)
1654 
1655 /*
1656  * Called to handle interrupts, either call by the interrupt
1657  * handler (do_mesh_interrupt) or by other functions in
1658  * exceptional circumstances
1659  */
1660 static void mesh_interrupt(struct mesh_state *ms)
1661 {
1662 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1663 	int intr;
1664 
1665 #if 0
1666 	if (ALLOW_DEBUG(ms->conn_tgt))
1667 		printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1668 		       "phase=%d msgphase=%d\n", mr->bus_status0,
1669 		       mr->interrupt, mr->exception, mr->error,
1670 		       ms->phase, ms->msgphase);
1671 #endif
1672 	while ((intr = in_8(&mr->interrupt)) != 0) {
1673 		dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1674 		     MKWORD(intr, mr->error, mr->exception, mr->sequence));
1675 		if (intr & INT_ERROR) {
1676 			handle_error(ms);
1677 		} else if (intr & INT_EXCEPTION) {
1678 			handle_exception(ms);
1679 		} else if (intr & INT_CMDDONE) {
1680 			out_8(&mr->interrupt, INT_CMDDONE);
1681 			cmd_complete(ms);
1682 		}
1683 	}
1684 }
1685 
1686 /* Todo: here we can at least try to remove the command from the
1687  * queue if it isn't connected yet, and for pending command, assert
1688  * ATN until the bus gets freed.
1689  */
1690 static int mesh_abort(struct scsi_cmnd *cmd)
1691 {
1692 	struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1693 
1694 	printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1695 	mesh_dump_regs(ms);
1696 	dumplog(ms, cmd->device->id);
1697 	dumpslog(ms);
1698 	return FAILED;
1699 }
1700 
1701 /*
1702  * Called by the midlayer with the lock held to reset the
1703  * SCSI host and bus.
1704  * The midlayer will wait for devices to come back, we don't need
1705  * to do that ourselves
1706  */
1707 static int mesh_host_reset(struct scsi_cmnd *cmd)
1708 {
1709 	struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1710 	volatile struct mesh_regs __iomem *mr = ms->mesh;
1711 	volatile struct dbdma_regs __iomem *md = ms->dma;
1712 	unsigned long flags;
1713 
1714 	printk(KERN_DEBUG "mesh_host_reset\n");
1715 
1716 	spin_lock_irqsave(ms->host->host_lock, flags);
1717 
1718 	if (ms->dma_started)
1719 		halt_dma(ms);
1720 
1721 	/* Reset the controller & dbdma channel */
1722 	out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);	/* stop dma */
1723 	out_8(&mr->exception, 0xff);	/* clear all exception bits */
1724 	out_8(&mr->error, 0xff);	/* clear all error bits */
1725 	out_8(&mr->sequence, SEQ_RESETMESH);
1726        	mesh_flush_io(mr);
1727 	udelay(1);
1728 	out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1729 	out_8(&mr->source_id, ms->host->this_id);
1730 	out_8(&mr->sel_timeout, 25);	/* 250ms */
1731 	out_8(&mr->sync_params, ASYNC_PARAMS);
1732 
1733 	/* Reset the bus */
1734 	out_8(&mr->bus_status1, BS1_RST);	/* assert RST */
1735        	mesh_flush_io(mr);
1736 	udelay(30);			/* leave it on for >= 25us */
1737 	out_8(&mr->bus_status1, 0);	/* negate RST */
1738 
1739 	/* Complete pending commands */
1740 	handle_reset(ms);
1741 
1742 	spin_unlock_irqrestore(ms->host->host_lock, flags);
1743 	return SUCCESS;
1744 }
1745 
1746 static void set_mesh_power(struct mesh_state *ms, int state)
1747 {
1748 	if (!machine_is(powermac))
1749 		return;
1750 	if (state) {
1751 		pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1752 		msleep(200);
1753 	} else {
1754 		pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1755 		msleep(10);
1756 	}
1757 }
1758 
1759 
1760 #ifdef CONFIG_PM
1761 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1762 {
1763 	struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1764 	unsigned long flags;
1765 
1766 	switch (mesg.event) {
1767 	case PM_EVENT_SUSPEND:
1768 	case PM_EVENT_HIBERNATE:
1769 	case PM_EVENT_FREEZE:
1770 		break;
1771 	default:
1772 		return 0;
1773 	}
1774 	if (ms->phase == sleeping)
1775 		return 0;
1776 
1777 	scsi_block_requests(ms->host);
1778 	spin_lock_irqsave(ms->host->host_lock, flags);
1779 	while(ms->phase != idle) {
1780 		spin_unlock_irqrestore(ms->host->host_lock, flags);
1781 		msleep(10);
1782 		spin_lock_irqsave(ms->host->host_lock, flags);
1783 	}
1784 	ms->phase = sleeping;
1785 	spin_unlock_irqrestore(ms->host->host_lock, flags);
1786 	disable_irq(ms->meshintr);
1787 	set_mesh_power(ms, 0);
1788 
1789 	return 0;
1790 }
1791 
1792 static int mesh_resume(struct macio_dev *mdev)
1793 {
1794 	struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1795 	unsigned long flags;
1796 
1797 	if (ms->phase != sleeping)
1798 		return 0;
1799 
1800 	set_mesh_power(ms, 1);
1801 	mesh_init(ms);
1802 	spin_lock_irqsave(ms->host->host_lock, flags);
1803 	mesh_start(ms);
1804 	spin_unlock_irqrestore(ms->host->host_lock, flags);
1805 	enable_irq(ms->meshintr);
1806 	scsi_unblock_requests(ms->host);
1807 
1808 	return 0;
1809 }
1810 
1811 #endif /* CONFIG_PM */
1812 
1813 /*
1814  * If we leave drives set for synchronous transfers (especially
1815  * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1816  * So, on reboot we reset the SCSI bus.
1817  */
1818 static int mesh_shutdown(struct macio_dev *mdev)
1819 {
1820 	struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1821 	volatile struct mesh_regs __iomem *mr;
1822 	unsigned long flags;
1823 
1824        	printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1825 	spin_lock_irqsave(ms->host->host_lock, flags);
1826        	mr = ms->mesh;
1827 	out_8(&mr->intr_mask, 0);
1828 	out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1829 	out_8(&mr->bus_status1, BS1_RST);
1830 	mesh_flush_io(mr);
1831 	udelay(30);
1832 	out_8(&mr->bus_status1, 0);
1833 	spin_unlock_irqrestore(ms->host->host_lock, flags);
1834 
1835 	return 0;
1836 }
1837 
1838 static struct scsi_host_template mesh_template = {
1839 	.proc_name			= "mesh",
1840 	.name				= "MESH",
1841 	.queuecommand			= mesh_queue,
1842 	.eh_abort_handler		= mesh_abort,
1843 	.eh_host_reset_handler		= mesh_host_reset,
1844 	.can_queue			= 20,
1845 	.this_id			= 7,
1846 	.sg_tablesize			= SG_ALL,
1847 	.cmd_per_lun			= 2,
1848 	.max_segment_size		= 65535,
1849 };
1850 
1851 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1852 {
1853 	struct device_node *mesh = macio_get_of_node(mdev);
1854 	struct pci_dev* pdev = macio_get_pci_dev(mdev);
1855 	int tgt, minper;
1856 	const int *cfp;
1857 	struct mesh_state *ms;
1858 	struct Scsi_Host *mesh_host;
1859 	void *dma_cmd_space;
1860 	dma_addr_t dma_cmd_bus;
1861 
1862 	switch (mdev->bus->chip->type) {
1863 	case macio_heathrow:
1864 	case macio_gatwick:
1865 	case macio_paddington:
1866 		use_active_neg = 0;
1867 		break;
1868 	default:
1869 		use_active_neg = SEQ_ACTIVE_NEG;
1870 	}
1871 
1872 	if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1873        		printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1874 	       	       " (got %d,%d)\n", macio_resource_count(mdev),
1875 		       macio_irq_count(mdev));
1876 		return -ENODEV;
1877 	}
1878 
1879 	if (macio_request_resources(mdev, "mesh") != 0) {
1880        		printk(KERN_ERR "mesh: unable to request memory resources");
1881 		return -EBUSY;
1882 	}
1883        	mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1884 	if (mesh_host == NULL) {
1885 		printk(KERN_ERR "mesh: couldn't register host");
1886 		goto out_release;
1887 	}
1888 
1889 	/* Old junk for root discovery, that will die ultimately */
1890 #if !defined(MODULE)
1891        	note_scsi_host(mesh, mesh_host);
1892 #endif
1893 
1894 	mesh_host->base = macio_resource_start(mdev, 0);
1895 	mesh_host->irq = macio_irq(mdev, 0);
1896        	ms = (struct mesh_state *) mesh_host->hostdata;
1897 	macio_set_drvdata(mdev, ms);
1898 	ms->host = mesh_host;
1899 	ms->mdev = mdev;
1900 	ms->pdev = pdev;
1901 
1902 	ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1903 	if (ms->mesh == NULL) {
1904 		printk(KERN_ERR "mesh: can't map registers\n");
1905 		goto out_free;
1906 	}
1907 	ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1908 	if (ms->dma == NULL) {
1909 		printk(KERN_ERR "mesh: can't map registers\n");
1910 		iounmap(ms->mesh);
1911 		goto out_free;
1912 	}
1913 
1914        	ms->meshintr = macio_irq(mdev, 0);
1915        	ms->dmaintr = macio_irq(mdev, 1);
1916 
1917        	/* Space for dma command list: +1 for stop command,
1918        	 * +1 to allow for aligning.
1919 	 */
1920 	ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1921 
1922 	/* We use the PCI APIs for now until the generic one gets fixed
1923 	 * enough or until we get some macio-specific versions
1924 	 */
1925 	dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
1926 					   ms->dma_cmd_size, &dma_cmd_bus,
1927 					   GFP_KERNEL);
1928 	if (dma_cmd_space == NULL) {
1929 		printk(KERN_ERR "mesh: can't allocate DMA table\n");
1930 		goto out_unmap;
1931 	}
1932 
1933 	ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1934        	ms->dma_cmd_space = dma_cmd_space;
1935 	ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1936 		- (unsigned long)dma_cmd_space;
1937 	ms->current_req = NULL;
1938        	for (tgt = 0; tgt < 8; ++tgt) {
1939 	       	ms->tgts[tgt].sdtr_state = do_sdtr;
1940 	       	ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1941 	       	ms->tgts[tgt].current_req = NULL;
1942        	}
1943 
1944 	if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1945        		ms->clk_freq = *cfp;
1946 	else {
1947        		printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1948 	       	ms->clk_freq = 50000000;
1949        	}
1950 
1951        	/* The maximum sync rate is clock / 5; increase
1952        	 * mesh_sync_period if necessary.
1953 	 */
1954 	minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1955 	if (mesh_sync_period < minper)
1956 		mesh_sync_period = minper;
1957 
1958 	/* Power up the chip */
1959 	set_mesh_power(ms, 1);
1960 
1961 	/* Set it up */
1962        	mesh_init(ms);
1963 
1964 	/* Request interrupt */
1965        	if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1966 	       	printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1967 		goto out_shutdown;
1968 	}
1969 
1970 	/* Add scsi host & scan */
1971 	if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1972 		goto out_release_irq;
1973 	scsi_scan_host(mesh_host);
1974 
1975 	return 0;
1976 
1977  out_release_irq:
1978 	free_irq(ms->meshintr, ms);
1979  out_shutdown:
1980 	/* shutdown & reset bus in case of error or macos can be confused
1981 	 * at reboot if the bus was set to synchronous mode already
1982 	 */
1983 	mesh_shutdown(mdev);
1984 	set_mesh_power(ms, 0);
1985 	dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
1986 			    ms->dma_cmd_space, ms->dma_cmd_bus);
1987  out_unmap:
1988 	iounmap(ms->dma);
1989 	iounmap(ms->mesh);
1990  out_free:
1991 	scsi_host_put(mesh_host);
1992  out_release:
1993 	macio_release_resources(mdev);
1994 
1995 	return -ENODEV;
1996 }
1997 
1998 static int mesh_remove(struct macio_dev *mdev)
1999 {
2000 	struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
2001 	struct Scsi_Host *mesh_host = ms->host;
2002 
2003 	scsi_remove_host(mesh_host);
2004 
2005 	free_irq(ms->meshintr, ms);
2006 
2007 	/* Reset scsi bus */
2008 	mesh_shutdown(mdev);
2009 
2010 	/* Shut down chip & termination */
2011 	set_mesh_power(ms, 0);
2012 
2013 	/* Unmap registers & dma controller */
2014 	iounmap(ms->mesh);
2015        	iounmap(ms->dma);
2016 
2017 	/* Free DMA commands memory */
2018 	dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
2019 			    ms->dma_cmd_space, ms->dma_cmd_bus);
2020 
2021 	/* Release memory resources */
2022 	macio_release_resources(mdev);
2023 
2024 	scsi_host_put(mesh_host);
2025 
2026 	return 0;
2027 }
2028 
2029 
2030 static struct of_device_id mesh_match[] =
2031 {
2032 	{
2033 	.name 		= "mesh",
2034 	},
2035 	{
2036 	.type		= "scsi",
2037 	.compatible	= "chrp,mesh0"
2038 	},
2039 	{},
2040 };
2041 MODULE_DEVICE_TABLE (of, mesh_match);
2042 
2043 static struct macio_driver mesh_driver =
2044 {
2045 	.driver = {
2046 		.name 		= "mesh",
2047 		.owner		= THIS_MODULE,
2048 		.of_match_table	= mesh_match,
2049 	},
2050 	.probe		= mesh_probe,
2051 	.remove		= mesh_remove,
2052 	.shutdown	= mesh_shutdown,
2053 #ifdef CONFIG_PM
2054 	.suspend	= mesh_suspend,
2055 	.resume		= mesh_resume,
2056 #endif
2057 };
2058 
2059 
2060 static int __init init_mesh(void)
2061 {
2062 
2063 	/* Calculate sync rate from module parameters */
2064 	if (sync_rate > 10)
2065 		sync_rate = 10;
2066 	if (sync_rate > 0) {
2067 		printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2068 		mesh_sync_period = 1000 / sync_rate;	/* ns */
2069 		mesh_sync_offset = 15;
2070 	} else
2071 		printk(KERN_INFO "mesh: configured for asynchronous\n");
2072 
2073 	return macio_register_driver(&mesh_driver);
2074 }
2075 
2076 static void __exit exit_mesh(void)
2077 {
2078 	return macio_unregister_driver(&mesh_driver);
2079 }
2080 
2081 module_init(init_mesh);
2082 module_exit(exit_mesh);
2083