1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas_fusion.h 21 * 22 * Authors: Avago Technologies 23 * Manoj Jose 24 * Sumant Patro 25 * Kashyap Desai <kashyap.desai@avagotech.com> 26 * Sumit Saxena <sumit.saxena@avagotech.com> 27 * 28 * Send feedback to: megaraidlinux.pdl@avagotech.com 29 * 30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 31 * San Jose, California 95131 32 */ 33 34 #ifndef _MEGARAID_SAS_FUSION_H_ 35 #define _MEGARAID_SAS_FUSION_H_ 36 37 /* Fusion defines */ 38 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 40 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 41 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 42 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 43 #define MEGASAS_LOAD_BALANCE_FLAG 0x1 44 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 45 #define HOST_DIAG_WRITE_ENABLE 0x80 46 #define HOST_DIAG_RESET_ADAPTER 0x4 47 #define MEGASAS_FUSION_MAX_RESET_TRIES 3 48 #define MAX_MSIX_QUEUES_FUSION 128 49 50 /* Invader defines */ 51 #define MPI2_TYPE_CUDA 0x2 52 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 53 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 54 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 55 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 56 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 57 58 /* T10 PI defines */ 59 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 60 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 61 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 62 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 63 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 64 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 65 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 66 67 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 68 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 69 70 /* 71 * Raid context flags 72 */ 73 74 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 75 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 76 enum MR_RAID_FLAGS_IO_SUB_TYPE { 77 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 78 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 79 }; 80 81 /* 82 * Request descriptor types 83 */ 84 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 85 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 86 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 87 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 88 89 #define MEGASAS_FP_CMD_LEN 16 90 #define MEGASAS_FUSION_IN_RESET 0 91 #define THRESHOLD_REPLY_COUNT 50 92 93 /* 94 * Raid Context structure which describes MegaRAID specific IO Parameters 95 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 96 */ 97 98 struct RAID_CONTEXT { 99 #if defined(__BIG_ENDIAN_BITFIELD) 100 u8 nseg:4; 101 u8 Type:4; 102 #else 103 u8 Type:4; 104 u8 nseg:4; 105 #endif 106 u8 resvd0; 107 u16 timeoutValue; 108 u8 regLockFlags; 109 u8 resvd1; 110 u16 VirtualDiskTgtId; 111 u64 regLockRowLBA; 112 u32 regLockLength; 113 u16 nextLMId; 114 u8 exStatus; 115 u8 status; 116 u8 RAIDFlags; 117 u8 numSGE; 118 u16 configSeqNum; 119 u8 spanArm; 120 u8 resvd2[3]; 121 }; 122 123 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 124 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 125 126 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 127 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 128 129 /* 130 * define region lock types 131 */ 132 enum REGION_TYPE { 133 REGION_TYPE_UNUSED = 0, 134 REGION_TYPE_SHARED_READ = 1, 135 REGION_TYPE_SHARED_WRITE = 2, 136 REGION_TYPE_EXCLUSIVE = 3, 137 }; 138 139 /* MPI2 defines */ 140 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 141 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 142 #define MPI2_VERSION_MAJOR (0x02) 143 #define MPI2_VERSION_MINOR (0x00) 144 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 145 #define MPI2_VERSION_MAJOR_SHIFT (8) 146 #define MPI2_VERSION_MINOR_MASK (0x00FF) 147 #define MPI2_VERSION_MINOR_SHIFT (0) 148 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 149 MPI2_VERSION_MINOR) 150 #define MPI2_HEADER_VERSION_UNIT (0x10) 151 #define MPI2_HEADER_VERSION_DEV (0x00) 152 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 153 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 154 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 155 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 156 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 157 MPI2_HEADER_VERSION_DEV) 158 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 159 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 160 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 161 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 162 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 163 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 164 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 165 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 166 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 167 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 168 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 169 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 170 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 171 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 172 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 173 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 174 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 175 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 176 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 177 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 178 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 179 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 180 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 181 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 182 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 183 184 struct MPI25_IEEE_SGE_CHAIN64 { 185 u64 Address; 186 u32 Length; 187 u16 Reserved1; 188 u8 NextChainOffset; 189 u8 Flags; 190 }; 191 192 struct MPI2_SGE_SIMPLE_UNION { 193 u32 FlagsLength; 194 union { 195 u32 Address32; 196 u64 Address64; 197 } u; 198 }; 199 200 struct MPI2_SCSI_IO_CDB_EEDP32 { 201 u8 CDB[20]; /* 0x00 */ 202 u32 PrimaryReferenceTag; /* 0x14 */ 203 u16 PrimaryApplicationTag; /* 0x18 */ 204 u16 PrimaryApplicationTagMask; /* 0x1A */ 205 u32 TransferLength; /* 0x1C */ 206 }; 207 208 struct MPI2_SGE_CHAIN_UNION { 209 u16 Length; 210 u8 NextChainOffset; 211 u8 Flags; 212 union { 213 u32 Address32; 214 u64 Address64; 215 } u; 216 }; 217 218 struct MPI2_IEEE_SGE_SIMPLE32 { 219 u32 Address; 220 u32 FlagsLength; 221 }; 222 223 struct MPI2_IEEE_SGE_CHAIN32 { 224 u32 Address; 225 u32 FlagsLength; 226 }; 227 228 struct MPI2_IEEE_SGE_SIMPLE64 { 229 u64 Address; 230 u32 Length; 231 u16 Reserved1; 232 u8 Reserved2; 233 u8 Flags; 234 }; 235 236 struct MPI2_IEEE_SGE_CHAIN64 { 237 u64 Address; 238 u32 Length; 239 u16 Reserved1; 240 u8 Reserved2; 241 u8 Flags; 242 }; 243 244 union MPI2_IEEE_SGE_SIMPLE_UNION { 245 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 246 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 247 }; 248 249 union MPI2_IEEE_SGE_CHAIN_UNION { 250 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 251 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 252 }; 253 254 union MPI2_SGE_IO_UNION { 255 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 256 struct MPI2_SGE_CHAIN_UNION MpiChain; 257 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 258 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 259 }; 260 261 union MPI2_SCSI_IO_CDB_UNION { 262 u8 CDB32[32]; 263 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 264 struct MPI2_SGE_SIMPLE_UNION SGE; 265 }; 266 267 /* 268 * RAID SCSI IO Request Message 269 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 270 */ 271 struct MPI2_RAID_SCSI_IO_REQUEST { 272 u16 DevHandle; /* 0x00 */ 273 u8 ChainOffset; /* 0x02 */ 274 u8 Function; /* 0x03 */ 275 u16 Reserved1; /* 0x04 */ 276 u8 Reserved2; /* 0x06 */ 277 u8 MsgFlags; /* 0x07 */ 278 u8 VP_ID; /* 0x08 */ 279 u8 VF_ID; /* 0x09 */ 280 u16 Reserved3; /* 0x0A */ 281 u32 SenseBufferLowAddress; /* 0x0C */ 282 u16 SGLFlags; /* 0x10 */ 283 u8 SenseBufferLength; /* 0x12 */ 284 u8 Reserved4; /* 0x13 */ 285 u8 SGLOffset0; /* 0x14 */ 286 u8 SGLOffset1; /* 0x15 */ 287 u8 SGLOffset2; /* 0x16 */ 288 u8 SGLOffset3; /* 0x17 */ 289 u32 SkipCount; /* 0x18 */ 290 u32 DataLength; /* 0x1C */ 291 u32 BidirectionalDataLength; /* 0x20 */ 292 u16 IoFlags; /* 0x24 */ 293 u16 EEDPFlags; /* 0x26 */ 294 u32 EEDPBlockSize; /* 0x28 */ 295 u32 SecondaryReferenceTag; /* 0x2C */ 296 u16 SecondaryApplicationTag; /* 0x30 */ 297 u16 ApplicationTagTranslationMask; /* 0x32 */ 298 u8 LUN[8]; /* 0x34 */ 299 u32 Control; /* 0x3C */ 300 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 301 struct RAID_CONTEXT RaidContext; /* 0x60 */ 302 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 303 }; 304 305 /* 306 * MPT RAID MFA IO Descriptor. 307 */ 308 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 309 #if defined(__BIG_ENDIAN_BITFIELD) 310 u32 MessageAddress1:24; /* bits 31:8*/ 311 u32 RequestFlags:8; 312 #else 313 u32 RequestFlags:8; 314 u32 MessageAddress1:24; /* bits 31:8*/ 315 #endif 316 u32 MessageAddress2; /* bits 61:32 */ 317 }; 318 319 /* Default Request Descriptor */ 320 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 321 u8 RequestFlags; /* 0x00 */ 322 u8 MSIxIndex; /* 0x01 */ 323 u16 SMID; /* 0x02 */ 324 u16 LMID; /* 0x04 */ 325 u16 DescriptorTypeDependent; /* 0x06 */ 326 }; 327 328 /* High Priority Request Descriptor */ 329 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 330 u8 RequestFlags; /* 0x00 */ 331 u8 MSIxIndex; /* 0x01 */ 332 u16 SMID; /* 0x02 */ 333 u16 LMID; /* 0x04 */ 334 u16 Reserved1; /* 0x06 */ 335 }; 336 337 /* SCSI IO Request Descriptor */ 338 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 339 u8 RequestFlags; /* 0x00 */ 340 u8 MSIxIndex; /* 0x01 */ 341 u16 SMID; /* 0x02 */ 342 u16 LMID; /* 0x04 */ 343 u16 DevHandle; /* 0x06 */ 344 }; 345 346 /* SCSI Target Request Descriptor */ 347 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 348 u8 RequestFlags; /* 0x00 */ 349 u8 MSIxIndex; /* 0x01 */ 350 u16 SMID; /* 0x02 */ 351 u16 LMID; /* 0x04 */ 352 u16 IoIndex; /* 0x06 */ 353 }; 354 355 /* RAID Accelerator Request Descriptor */ 356 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 357 u8 RequestFlags; /* 0x00 */ 358 u8 MSIxIndex; /* 0x01 */ 359 u16 SMID; /* 0x02 */ 360 u16 LMID; /* 0x04 */ 361 u16 Reserved; /* 0x06 */ 362 }; 363 364 /* union of Request Descriptors */ 365 union MEGASAS_REQUEST_DESCRIPTOR_UNION { 366 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 367 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 368 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 369 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 370 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 371 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 372 union { 373 struct { 374 u32 low; 375 u32 high; 376 } u; 377 u64 Words; 378 }; 379 }; 380 381 /* Default Reply Descriptor */ 382 struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 383 u8 ReplyFlags; /* 0x00 */ 384 u8 MSIxIndex; /* 0x01 */ 385 u16 DescriptorTypeDependent1; /* 0x02 */ 386 u32 DescriptorTypeDependent2; /* 0x04 */ 387 }; 388 389 /* Address Reply Descriptor */ 390 struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 391 u8 ReplyFlags; /* 0x00 */ 392 u8 MSIxIndex; /* 0x01 */ 393 u16 SMID; /* 0x02 */ 394 u32 ReplyFrameAddress; /* 0x04 */ 395 }; 396 397 /* SCSI IO Success Reply Descriptor */ 398 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 399 u8 ReplyFlags; /* 0x00 */ 400 u8 MSIxIndex; /* 0x01 */ 401 u16 SMID; /* 0x02 */ 402 u16 TaskTag; /* 0x04 */ 403 u16 Reserved1; /* 0x06 */ 404 }; 405 406 /* TargetAssist Success Reply Descriptor */ 407 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 408 u8 ReplyFlags; /* 0x00 */ 409 u8 MSIxIndex; /* 0x01 */ 410 u16 SMID; /* 0x02 */ 411 u8 SequenceNumber; /* 0x04 */ 412 u8 Reserved1; /* 0x05 */ 413 u16 IoIndex; /* 0x06 */ 414 }; 415 416 /* Target Command Buffer Reply Descriptor */ 417 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 418 u8 ReplyFlags; /* 0x00 */ 419 u8 MSIxIndex; /* 0x01 */ 420 u8 VP_ID; /* 0x02 */ 421 u8 Flags; /* 0x03 */ 422 u16 InitiatorDevHandle; /* 0x04 */ 423 u16 IoIndex; /* 0x06 */ 424 }; 425 426 /* RAID Accelerator Success Reply Descriptor */ 427 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 428 u8 ReplyFlags; /* 0x00 */ 429 u8 MSIxIndex; /* 0x01 */ 430 u16 SMID; /* 0x02 */ 431 u32 Reserved; /* 0x04 */ 432 }; 433 434 /* union of Reply Descriptors */ 435 union MPI2_REPLY_DESCRIPTORS_UNION { 436 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 437 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 438 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 439 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 440 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 441 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 442 RAIDAcceleratorSuccess; 443 u64 Words; 444 }; 445 446 /* IOCInit Request message */ 447 struct MPI2_IOC_INIT_REQUEST { 448 u8 WhoInit; /* 0x00 */ 449 u8 Reserved1; /* 0x01 */ 450 u8 ChainOffset; /* 0x02 */ 451 u8 Function; /* 0x03 */ 452 u16 Reserved2; /* 0x04 */ 453 u8 Reserved3; /* 0x06 */ 454 u8 MsgFlags; /* 0x07 */ 455 u8 VP_ID; /* 0x08 */ 456 u8 VF_ID; /* 0x09 */ 457 u16 Reserved4; /* 0x0A */ 458 u16 MsgVersion; /* 0x0C */ 459 u16 HeaderVersion; /* 0x0E */ 460 u32 Reserved5; /* 0x10 */ 461 u16 Reserved6; /* 0x14 */ 462 u8 Reserved7; /* 0x16 */ 463 u8 HostMSIxVectors; /* 0x17 */ 464 u16 Reserved8; /* 0x18 */ 465 u16 SystemRequestFrameSize; /* 0x1A */ 466 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 467 u16 ReplyFreeQueueDepth; /* 0x1E */ 468 u32 SenseBufferAddressHigh; /* 0x20 */ 469 u32 SystemReplyAddressHigh; /* 0x24 */ 470 u64 SystemRequestFrameBaseAddress; /* 0x28 */ 471 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 472 u64 ReplyFreeQueueAddress; /* 0x38 */ 473 u64 TimeStamp; /* 0x40 */ 474 }; 475 476 /* mrpriv defines */ 477 #define MR_PD_INVALID 0xFFFF 478 #define MAX_SPAN_DEPTH 8 479 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 480 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 481 #define MAX_ROW_SIZE 32 482 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 483 #define MAX_LOGICAL_DRIVES 64 484 #define MAX_LOGICAL_DRIVES_EXT 256 485 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 486 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 487 #define MAX_ARRAYS 128 488 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 489 #define MAX_ARRAYS_EXT 256 490 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT) 491 #define MAX_PHYSICAL_DEVICES 256 492 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 493 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 494 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ 495 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 496 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 497 498 struct MR_DEV_HANDLE_INFO { 499 u16 curDevHdl; 500 u8 validHandles; 501 u8 reserved; 502 u16 devHandle[2]; 503 }; 504 505 struct MR_ARRAY_INFO { 506 u16 pd[MAX_RAIDMAP_ROW_SIZE]; 507 }; 508 509 struct MR_QUAD_ELEMENT { 510 u64 logStart; 511 u64 logEnd; 512 u64 offsetInSpan; 513 u32 diff; 514 u32 reserved1; 515 }; 516 517 struct MR_SPAN_INFO { 518 u32 noElements; 519 u32 reserved1; 520 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 521 }; 522 523 struct MR_LD_SPAN { 524 u64 startBlk; 525 u64 numBlks; 526 u16 arrayRef; 527 u8 spanRowSize; 528 u8 spanRowDataSize; 529 u8 reserved[4]; 530 }; 531 532 struct MR_SPAN_BLOCK_INFO { 533 u64 num_rows; 534 struct MR_LD_SPAN span; 535 struct MR_SPAN_INFO block_span_info; 536 }; 537 538 struct MR_LD_RAID { 539 struct { 540 #if defined(__BIG_ENDIAN_BITFIELD) 541 u32 reserved4:7; 542 u32 fpNonRWCapable:1; 543 u32 fpReadAcrossStripe:1; 544 u32 fpWriteAcrossStripe:1; 545 u32 fpReadCapable:1; 546 u32 fpWriteCapable:1; 547 u32 encryptionType:8; 548 u32 pdPiMode:4; 549 u32 ldPiMode:4; 550 u32 reserved5:3; 551 u32 fpCapable:1; 552 #else 553 u32 fpCapable:1; 554 u32 reserved5:3; 555 u32 ldPiMode:4; 556 u32 pdPiMode:4; 557 u32 encryptionType:8; 558 u32 fpWriteCapable:1; 559 u32 fpReadCapable:1; 560 u32 fpWriteAcrossStripe:1; 561 u32 fpReadAcrossStripe:1; 562 u32 fpNonRWCapable:1; 563 u32 reserved4:7; 564 #endif 565 } capability; 566 u32 reserved6; 567 u64 size; 568 u8 spanDepth; 569 u8 level; 570 u8 stripeShift; 571 u8 rowSize; 572 u8 rowDataSize; 573 u8 writeMode; 574 u8 PRL; 575 u8 SRL; 576 u16 targetId; 577 u8 ldState; 578 u8 regTypeReqOnWrite; 579 u8 modFactor; 580 u8 regTypeReqOnRead; 581 u16 seqNum; 582 583 struct { 584 u32 ldSyncRequired:1; 585 u32 reserved:31; 586 } flags; 587 588 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ 589 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ 590 u8 reserved3[0x80-0x2D]; /* 0x2D */ 591 }; 592 593 struct MR_LD_SPAN_MAP { 594 struct MR_LD_RAID ldRaid; 595 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 596 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 597 }; 598 599 struct MR_FW_RAID_MAP { 600 u32 totalSize; 601 union { 602 struct { 603 u32 maxLd; 604 u32 maxSpanDepth; 605 u32 maxRowSize; 606 u32 maxPdCount; 607 u32 maxArrays; 608 } validationInfo; 609 u32 version[5]; 610 }; 611 612 u32 ldCount; 613 u32 Reserved1; 614 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 615 MAX_RAIDMAP_VIEWS]; 616 u8 fpPdIoTimeoutSec; 617 u8 reserved2[7]; 618 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 619 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 620 struct MR_LD_SPAN_MAP ldSpanMap[1]; 621 }; 622 623 struct IO_REQUEST_INFO { 624 u64 ldStartBlock; 625 u32 numBlocks; 626 u16 ldTgtId; 627 u8 isRead; 628 u16 devHandle; 629 u64 pdBlock; 630 u8 fpOkForIo; 631 u8 IoforUnevenSpan; 632 u8 start_span; 633 u8 reserved; 634 u64 start_row; 635 u8 span_arm; /* span[7:5], arm[4:0] */ 636 u8 pd_after_lb; 637 }; 638 639 struct MR_LD_TARGET_SYNC { 640 u8 targetId; 641 u8 reserved; 642 u16 seqNum; 643 }; 644 645 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 646 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 647 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 648 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 649 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 650 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 651 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 652 653 struct megasas_register_set; 654 struct megasas_instance; 655 656 union desc_word { 657 u64 word; 658 struct { 659 u32 low; 660 u32 high; 661 } u; 662 }; 663 664 struct megasas_cmd_fusion { 665 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 666 dma_addr_t io_request_phys_addr; 667 668 union MPI2_SGE_IO_UNION *sg_frame; 669 dma_addr_t sg_frame_phys_addr; 670 671 u8 *sense; 672 dma_addr_t sense_phys_addr; 673 674 struct list_head list; 675 struct scsi_cmnd *scmd; 676 struct megasas_instance *instance; 677 678 u8 retry_for_fw_reset; 679 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 680 681 /* 682 * Context for a MFI frame. 683 * Used to get the mfi cmd from list when a MFI cmd is completed 684 */ 685 u32 sync_cmd_idx; 686 u32 index; 687 u8 flags; 688 u8 pd_r1_lb; 689 }; 690 691 struct LD_LOAD_BALANCE_INFO { 692 u8 loadBalanceFlag; 693 u8 reserved1; 694 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 695 u64 last_accessed_block[MAX_PHYSICAL_DEVICES]; 696 }; 697 698 /* SPAN_SET is info caclulated from span info from Raid map per LD */ 699 typedef struct _LD_SPAN_SET { 700 u64 log_start_lba; 701 u64 log_end_lba; 702 u64 span_row_start; 703 u64 span_row_end; 704 u64 data_strip_start; 705 u64 data_strip_end; 706 u64 data_row_start; 707 u64 data_row_end; 708 u8 strip_offset[MAX_SPAN_DEPTH]; 709 u32 span_row_data_width; 710 u32 diff; 711 u32 reserved[2]; 712 } LD_SPAN_SET, *PLD_SPAN_SET; 713 714 typedef struct LOG_BLOCK_SPAN_INFO { 715 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 716 } LD_SPAN_INFO, *PLD_SPAN_INFO; 717 718 struct MR_FW_RAID_MAP_ALL { 719 struct MR_FW_RAID_MAP raidMap; 720 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 721 } __attribute__ ((packed)); 722 723 struct MR_DRV_RAID_MAP { 724 /* total size of this structure, including this field. 725 * This feild will be manupulated by driver for ext raid map, 726 * else pick the value from firmware raid map. 727 */ 728 u32 totalSize; 729 730 union { 731 struct { 732 u32 maxLd; 733 u32 maxSpanDepth; 734 u32 maxRowSize; 735 u32 maxPdCount; 736 u32 maxArrays; 737 } validationInfo; 738 u32 version[5]; 739 }; 740 741 /* timeout value used by driver in FP IOs*/ 742 u8 fpPdIoTimeoutSec; 743 u8 reserved2[7]; 744 745 u16 ldCount; 746 u16 arCount; 747 u16 spanCount; 748 u16 reserve3; 749 750 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 751 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 752 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 753 struct MR_LD_SPAN_MAP ldSpanMap[1]; 754 755 }; 756 757 /* Driver raid map size is same as raid map ext 758 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 759 * And it is mainly for code re-use purpose. 760 */ 761 struct MR_DRV_RAID_MAP_ALL { 762 763 struct MR_DRV_RAID_MAP raidMap; 764 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 765 } __packed; 766 767 768 769 struct MR_FW_RAID_MAP_EXT { 770 /* Not usred in new map */ 771 u32 reserved; 772 773 union { 774 struct { 775 u32 maxLd; 776 u32 maxSpanDepth; 777 u32 maxRowSize; 778 u32 maxPdCount; 779 u32 maxArrays; 780 } validationInfo; 781 u32 version[5]; 782 }; 783 784 u8 fpPdIoTimeoutSec; 785 u8 reserved2[7]; 786 787 u16 ldCount; 788 u16 arCount; 789 u16 spanCount; 790 u16 reserve3; 791 792 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 793 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 794 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 795 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 796 }; 797 798 struct fusion_context { 799 struct megasas_cmd_fusion **cmd_list; 800 struct list_head cmd_pool; 801 802 spinlock_t mpt_pool_lock; 803 804 dma_addr_t req_frames_desc_phys; 805 u8 *req_frames_desc; 806 807 struct dma_pool *io_request_frames_pool; 808 dma_addr_t io_request_frames_phys; 809 u8 *io_request_frames; 810 811 struct dma_pool *sg_dma_pool; 812 struct dma_pool *sense_dma_pool; 813 814 dma_addr_t reply_frames_desc_phys; 815 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; 816 struct dma_pool *reply_frames_desc_pool; 817 818 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; 819 820 u32 reply_q_depth; 821 u32 request_alloc_sz; 822 u32 reply_alloc_sz; 823 u32 io_frames_alloc_sz; 824 825 u16 max_sge_in_main_msg; 826 u16 max_sge_in_chain; 827 828 u8 chain_offset_io_request; 829 u8 chain_offset_mfi_pthru; 830 831 struct MR_FW_RAID_MAP_ALL *ld_map[2]; 832 dma_addr_t ld_map_phys[2]; 833 834 /*Non dma-able memory. Driver local copy.*/ 835 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 836 837 u32 max_map_sz; 838 u32 current_map_sz; 839 u32 drv_map_sz; 840 u32 drv_map_pages; 841 u8 fast_path_io; 842 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 843 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 844 }; 845 846 union desc_value { 847 u64 word; 848 struct { 849 u32 low; 850 u32 high; 851 } u; 852 }; 853 854 855 #endif /* _MEGARAID_SAS_FUSION_H_ */ 856