1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas_fusion.h 21 * 22 * Authors: Avago Technologies 23 * Manoj Jose 24 * Sumant Patro 25 * Kashyap Desai <kashyap.desai@avagotech.com> 26 * Sumit Saxena <sumit.saxena@avagotech.com> 27 * 28 * Send feedback to: megaraidlinux.pdl@avagotech.com 29 * 30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 31 * San Jose, California 95131 32 */ 33 34 #ifndef _MEGARAID_SAS_FUSION_H_ 35 #define _MEGARAID_SAS_FUSION_H_ 36 37 /* Fusion defines */ 38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 40 #define MEGASAS_MAX_CHAIN_SHIFT 5 41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 42 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 43 #define MEGASAS_256K_IO 128 44 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 48 #define MEGASAS_LOAD_BALANCE_FLAG 0x1 49 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 50 #define HOST_DIAG_WRITE_ENABLE 0x80 51 #define HOST_DIAG_RESET_ADAPTER 0x4 52 #define MEGASAS_FUSION_MAX_RESET_TRIES 3 53 #define MAX_MSIX_QUEUES_FUSION 128 54 55 /* Invader defines */ 56 #define MPI2_TYPE_CUDA 0x2 57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 62 63 /* T10 PI defines */ 64 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 65 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 66 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 67 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 68 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 69 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 70 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 71 72 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 73 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 74 75 /* 76 * Raid context flags 77 */ 78 79 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 80 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 81 enum MR_RAID_FLAGS_IO_SUB_TYPE { 82 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 83 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 84 }; 85 86 /* 87 * Request descriptor types 88 */ 89 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 90 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 91 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 92 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 93 94 #define MEGASAS_FP_CMD_LEN 16 95 #define MEGASAS_FUSION_IN_RESET 0 96 #define THRESHOLD_REPLY_COUNT 50 97 #define JBOD_MAPS_COUNT 2 98 99 enum MR_FUSION_ADAPTER_TYPE { 100 THUNDERBOLT_SERIES = 0, 101 INVADER_SERIES = 1, 102 }; 103 104 /* 105 * Raid Context structure which describes MegaRAID specific IO Parameters 106 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 107 */ 108 109 struct RAID_CONTEXT { 110 #if defined(__BIG_ENDIAN_BITFIELD) 111 u8 nseg:4; 112 u8 Type:4; 113 #else 114 u8 Type:4; 115 u8 nseg:4; 116 #endif 117 u8 resvd0; 118 __le16 timeoutValue; 119 u8 regLockFlags; 120 u8 resvd1; 121 __le16 VirtualDiskTgtId; 122 __le64 regLockRowLBA; 123 __le32 regLockLength; 124 __le16 nextLMId; 125 u8 exStatus; 126 u8 status; 127 u8 RAIDFlags; 128 u8 numSGE; 129 __le16 configSeqNum; 130 u8 spanArm; 131 u8 priority; 132 u8 numSGEExt; 133 u8 resvd2; 134 }; 135 136 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 137 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 138 139 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 140 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 141 142 /* 143 * define region lock types 144 */ 145 enum REGION_TYPE { 146 REGION_TYPE_UNUSED = 0, 147 REGION_TYPE_SHARED_READ = 1, 148 REGION_TYPE_SHARED_WRITE = 2, 149 REGION_TYPE_EXCLUSIVE = 3, 150 }; 151 152 /* MPI2 defines */ 153 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 154 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 155 #define MPI2_VERSION_MAJOR (0x02) 156 #define MPI2_VERSION_MINOR (0x00) 157 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 158 #define MPI2_VERSION_MAJOR_SHIFT (8) 159 #define MPI2_VERSION_MINOR_MASK (0x00FF) 160 #define MPI2_VERSION_MINOR_SHIFT (0) 161 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 162 MPI2_VERSION_MINOR) 163 #define MPI2_HEADER_VERSION_UNIT (0x10) 164 #define MPI2_HEADER_VERSION_DEV (0x00) 165 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 166 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 167 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 168 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 169 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 170 MPI2_HEADER_VERSION_DEV) 171 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 172 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 173 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 174 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 175 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 176 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 177 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 178 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 179 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 180 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 181 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 182 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 183 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 184 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 185 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 186 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 187 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 188 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 189 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 190 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 191 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 192 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 193 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 194 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 195 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 196 197 struct MPI25_IEEE_SGE_CHAIN64 { 198 __le64 Address; 199 __le32 Length; 200 __le16 Reserved1; 201 u8 NextChainOffset; 202 u8 Flags; 203 }; 204 205 struct MPI2_SGE_SIMPLE_UNION { 206 __le32 FlagsLength; 207 union { 208 __le32 Address32; 209 __le64 Address64; 210 } u; 211 }; 212 213 struct MPI2_SCSI_IO_CDB_EEDP32 { 214 u8 CDB[20]; /* 0x00 */ 215 __be32 PrimaryReferenceTag; /* 0x14 */ 216 __be16 PrimaryApplicationTag; /* 0x18 */ 217 __be16 PrimaryApplicationTagMask; /* 0x1A */ 218 __le32 TransferLength; /* 0x1C */ 219 }; 220 221 struct MPI2_SGE_CHAIN_UNION { 222 __le16 Length; 223 u8 NextChainOffset; 224 u8 Flags; 225 union { 226 __le32 Address32; 227 __le64 Address64; 228 } u; 229 }; 230 231 struct MPI2_IEEE_SGE_SIMPLE32 { 232 __le32 Address; 233 __le32 FlagsLength; 234 }; 235 236 struct MPI2_IEEE_SGE_CHAIN32 { 237 __le32 Address; 238 __le32 FlagsLength; 239 }; 240 241 struct MPI2_IEEE_SGE_SIMPLE64 { 242 __le64 Address; 243 __le32 Length; 244 __le16 Reserved1; 245 u8 Reserved2; 246 u8 Flags; 247 }; 248 249 struct MPI2_IEEE_SGE_CHAIN64 { 250 __le64 Address; 251 __le32 Length; 252 __le16 Reserved1; 253 u8 Reserved2; 254 u8 Flags; 255 }; 256 257 union MPI2_IEEE_SGE_SIMPLE_UNION { 258 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 259 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 260 }; 261 262 union MPI2_IEEE_SGE_CHAIN_UNION { 263 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 264 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 265 }; 266 267 union MPI2_SGE_IO_UNION { 268 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 269 struct MPI2_SGE_CHAIN_UNION MpiChain; 270 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 271 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 272 }; 273 274 union MPI2_SCSI_IO_CDB_UNION { 275 u8 CDB32[32]; 276 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 277 struct MPI2_SGE_SIMPLE_UNION SGE; 278 }; 279 280 /* 281 * RAID SCSI IO Request Message 282 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 283 */ 284 struct MPI2_RAID_SCSI_IO_REQUEST { 285 __le16 DevHandle; /* 0x00 */ 286 u8 ChainOffset; /* 0x02 */ 287 u8 Function; /* 0x03 */ 288 __le16 Reserved1; /* 0x04 */ 289 u8 Reserved2; /* 0x06 */ 290 u8 MsgFlags; /* 0x07 */ 291 u8 VP_ID; /* 0x08 */ 292 u8 VF_ID; /* 0x09 */ 293 __le16 Reserved3; /* 0x0A */ 294 __le32 SenseBufferLowAddress; /* 0x0C */ 295 __le16 SGLFlags; /* 0x10 */ 296 u8 SenseBufferLength; /* 0x12 */ 297 u8 Reserved4; /* 0x13 */ 298 u8 SGLOffset0; /* 0x14 */ 299 u8 SGLOffset1; /* 0x15 */ 300 u8 SGLOffset2; /* 0x16 */ 301 u8 SGLOffset3; /* 0x17 */ 302 __le32 SkipCount; /* 0x18 */ 303 __le32 DataLength; /* 0x1C */ 304 __le32 BidirectionalDataLength; /* 0x20 */ 305 __le16 IoFlags; /* 0x24 */ 306 __le16 EEDPFlags; /* 0x26 */ 307 __le32 EEDPBlockSize; /* 0x28 */ 308 __le32 SecondaryReferenceTag; /* 0x2C */ 309 __le16 SecondaryApplicationTag; /* 0x30 */ 310 __le16 ApplicationTagTranslationMask; /* 0x32 */ 311 u8 LUN[8]; /* 0x34 */ 312 __le32 Control; /* 0x3C */ 313 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 314 struct RAID_CONTEXT RaidContext; /* 0x60 */ 315 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 316 }; 317 318 /* 319 * MPT RAID MFA IO Descriptor. 320 */ 321 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 322 u32 RequestFlags:8; 323 u32 MessageAddress1:24; 324 u32 MessageAddress2; 325 }; 326 327 /* Default Request Descriptor */ 328 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 329 u8 RequestFlags; /* 0x00 */ 330 u8 MSIxIndex; /* 0x01 */ 331 __le16 SMID; /* 0x02 */ 332 __le16 LMID; /* 0x04 */ 333 __le16 DescriptorTypeDependent; /* 0x06 */ 334 }; 335 336 /* High Priority Request Descriptor */ 337 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 338 u8 RequestFlags; /* 0x00 */ 339 u8 MSIxIndex; /* 0x01 */ 340 __le16 SMID; /* 0x02 */ 341 __le16 LMID; /* 0x04 */ 342 __le16 Reserved1; /* 0x06 */ 343 }; 344 345 /* SCSI IO Request Descriptor */ 346 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 347 u8 RequestFlags; /* 0x00 */ 348 u8 MSIxIndex; /* 0x01 */ 349 __le16 SMID; /* 0x02 */ 350 __le16 LMID; /* 0x04 */ 351 __le16 DevHandle; /* 0x06 */ 352 }; 353 354 /* SCSI Target Request Descriptor */ 355 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 356 u8 RequestFlags; /* 0x00 */ 357 u8 MSIxIndex; /* 0x01 */ 358 __le16 SMID; /* 0x02 */ 359 __le16 LMID; /* 0x04 */ 360 __le16 IoIndex; /* 0x06 */ 361 }; 362 363 /* RAID Accelerator Request Descriptor */ 364 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 365 u8 RequestFlags; /* 0x00 */ 366 u8 MSIxIndex; /* 0x01 */ 367 __le16 SMID; /* 0x02 */ 368 __le16 LMID; /* 0x04 */ 369 __le16 Reserved; /* 0x06 */ 370 }; 371 372 /* union of Request Descriptors */ 373 union MEGASAS_REQUEST_DESCRIPTOR_UNION { 374 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 375 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 376 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 377 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 378 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 379 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 380 union { 381 struct { 382 __le32 low; 383 __le32 high; 384 } u; 385 __le64 Words; 386 }; 387 }; 388 389 /* Default Reply Descriptor */ 390 struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 391 u8 ReplyFlags; /* 0x00 */ 392 u8 MSIxIndex; /* 0x01 */ 393 __le16 DescriptorTypeDependent1; /* 0x02 */ 394 __le32 DescriptorTypeDependent2; /* 0x04 */ 395 }; 396 397 /* Address Reply Descriptor */ 398 struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 399 u8 ReplyFlags; /* 0x00 */ 400 u8 MSIxIndex; /* 0x01 */ 401 __le16 SMID; /* 0x02 */ 402 __le32 ReplyFrameAddress; /* 0x04 */ 403 }; 404 405 /* SCSI IO Success Reply Descriptor */ 406 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 407 u8 ReplyFlags; /* 0x00 */ 408 u8 MSIxIndex; /* 0x01 */ 409 __le16 SMID; /* 0x02 */ 410 __le16 TaskTag; /* 0x04 */ 411 __le16 Reserved1; /* 0x06 */ 412 }; 413 414 /* TargetAssist Success Reply Descriptor */ 415 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 416 u8 ReplyFlags; /* 0x00 */ 417 u8 MSIxIndex; /* 0x01 */ 418 __le16 SMID; /* 0x02 */ 419 u8 SequenceNumber; /* 0x04 */ 420 u8 Reserved1; /* 0x05 */ 421 __le16 IoIndex; /* 0x06 */ 422 }; 423 424 /* Target Command Buffer Reply Descriptor */ 425 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 426 u8 ReplyFlags; /* 0x00 */ 427 u8 MSIxIndex; /* 0x01 */ 428 u8 VP_ID; /* 0x02 */ 429 u8 Flags; /* 0x03 */ 430 __le16 InitiatorDevHandle; /* 0x04 */ 431 __le16 IoIndex; /* 0x06 */ 432 }; 433 434 /* RAID Accelerator Success Reply Descriptor */ 435 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 436 u8 ReplyFlags; /* 0x00 */ 437 u8 MSIxIndex; /* 0x01 */ 438 __le16 SMID; /* 0x02 */ 439 __le32 Reserved; /* 0x04 */ 440 }; 441 442 /* union of Reply Descriptors */ 443 union MPI2_REPLY_DESCRIPTORS_UNION { 444 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 445 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 446 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 447 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 448 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 449 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 450 RAIDAcceleratorSuccess; 451 __le64 Words; 452 }; 453 454 /* IOCInit Request message */ 455 struct MPI2_IOC_INIT_REQUEST { 456 u8 WhoInit; /* 0x00 */ 457 u8 Reserved1; /* 0x01 */ 458 u8 ChainOffset; /* 0x02 */ 459 u8 Function; /* 0x03 */ 460 __le16 Reserved2; /* 0x04 */ 461 u8 Reserved3; /* 0x06 */ 462 u8 MsgFlags; /* 0x07 */ 463 u8 VP_ID; /* 0x08 */ 464 u8 VF_ID; /* 0x09 */ 465 __le16 Reserved4; /* 0x0A */ 466 __le16 MsgVersion; /* 0x0C */ 467 __le16 HeaderVersion; /* 0x0E */ 468 u32 Reserved5; /* 0x10 */ 469 __le16 Reserved6; /* 0x14 */ 470 u8 Reserved7; /* 0x16 */ 471 u8 HostMSIxVectors; /* 0x17 */ 472 __le16 Reserved8; /* 0x18 */ 473 __le16 SystemRequestFrameSize; /* 0x1A */ 474 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 475 __le16 ReplyFreeQueueDepth; /* 0x1E */ 476 __le32 SenseBufferAddressHigh; /* 0x20 */ 477 __le32 SystemReplyAddressHigh; /* 0x24 */ 478 __le64 SystemRequestFrameBaseAddress; /* 0x28 */ 479 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 480 __le64 ReplyFreeQueueAddress; /* 0x38 */ 481 __le64 TimeStamp; /* 0x40 */ 482 }; 483 484 /* mrpriv defines */ 485 #define MR_PD_INVALID 0xFFFF 486 #define MAX_SPAN_DEPTH 8 487 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 488 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 489 #define MAX_ROW_SIZE 32 490 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 491 #define MAX_LOGICAL_DRIVES 64 492 #define MAX_LOGICAL_DRIVES_EXT 256 493 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 494 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 495 #define MAX_ARRAYS 128 496 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 497 #define MAX_ARRAYS_EXT 256 498 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT) 499 #define MAX_PHYSICAL_DEVICES 256 500 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 501 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 502 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 503 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ 504 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 505 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 506 507 struct MR_DEV_HANDLE_INFO { 508 __le16 curDevHdl; 509 u8 validHandles; 510 u8 reserved; 511 __le16 devHandle[2]; 512 }; 513 514 struct MR_ARRAY_INFO { 515 __le16 pd[MAX_RAIDMAP_ROW_SIZE]; 516 }; 517 518 struct MR_QUAD_ELEMENT { 519 __le64 logStart; 520 __le64 logEnd; 521 __le64 offsetInSpan; 522 __le32 diff; 523 __le32 reserved1; 524 }; 525 526 struct MR_SPAN_INFO { 527 __le32 noElements; 528 __le32 reserved1; 529 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 530 }; 531 532 struct MR_LD_SPAN { 533 __le64 startBlk; 534 __le64 numBlks; 535 __le16 arrayRef; 536 u8 spanRowSize; 537 u8 spanRowDataSize; 538 u8 reserved[4]; 539 }; 540 541 struct MR_SPAN_BLOCK_INFO { 542 __le64 num_rows; 543 struct MR_LD_SPAN span; 544 struct MR_SPAN_INFO block_span_info; 545 }; 546 547 struct MR_LD_RAID { 548 struct { 549 #if defined(__BIG_ENDIAN_BITFIELD) 550 u32 reserved4:7; 551 u32 fpNonRWCapable:1; 552 u32 fpReadAcrossStripe:1; 553 u32 fpWriteAcrossStripe:1; 554 u32 fpReadCapable:1; 555 u32 fpWriteCapable:1; 556 u32 encryptionType:8; 557 u32 pdPiMode:4; 558 u32 ldPiMode:4; 559 u32 reserved5:3; 560 u32 fpCapable:1; 561 #else 562 u32 fpCapable:1; 563 u32 reserved5:3; 564 u32 ldPiMode:4; 565 u32 pdPiMode:4; 566 u32 encryptionType:8; 567 u32 fpWriteCapable:1; 568 u32 fpReadCapable:1; 569 u32 fpWriteAcrossStripe:1; 570 u32 fpReadAcrossStripe:1; 571 u32 fpNonRWCapable:1; 572 u32 reserved4:7; 573 #endif 574 } capability; 575 __le32 reserved6; 576 __le64 size; 577 u8 spanDepth; 578 u8 level; 579 u8 stripeShift; 580 u8 rowSize; 581 u8 rowDataSize; 582 u8 writeMode; 583 u8 PRL; 584 u8 SRL; 585 __le16 targetId; 586 u8 ldState; 587 u8 regTypeReqOnWrite; 588 u8 modFactor; 589 u8 regTypeReqOnRead; 590 __le16 seqNum; 591 592 struct { 593 u32 ldSyncRequired:1; 594 u32 reserved:31; 595 } flags; 596 597 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ 598 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ 599 u8 reserved3[0x80-0x2D]; /* 0x2D */ 600 }; 601 602 struct MR_LD_SPAN_MAP { 603 struct MR_LD_RAID ldRaid; 604 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 605 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 606 }; 607 608 struct MR_FW_RAID_MAP { 609 __le32 totalSize; 610 union { 611 struct { 612 __le32 maxLd; 613 __le32 maxSpanDepth; 614 __le32 maxRowSize; 615 __le32 maxPdCount; 616 __le32 maxArrays; 617 } validationInfo; 618 __le32 version[5]; 619 }; 620 621 __le32 ldCount; 622 __le32 Reserved1; 623 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 624 MAX_RAIDMAP_VIEWS]; 625 u8 fpPdIoTimeoutSec; 626 u8 reserved2[7]; 627 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 628 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 629 struct MR_LD_SPAN_MAP ldSpanMap[1]; 630 }; 631 632 struct IO_REQUEST_INFO { 633 u64 ldStartBlock; 634 u32 numBlocks; 635 u16 ldTgtId; 636 u8 isRead; 637 __le16 devHandle; 638 u64 pdBlock; 639 u8 fpOkForIo; 640 u8 IoforUnevenSpan; 641 u8 start_span; 642 u8 reserved; 643 u64 start_row; 644 u8 span_arm; /* span[7:5], arm[4:0] */ 645 u8 pd_after_lb; 646 }; 647 648 struct MR_LD_TARGET_SYNC { 649 u8 targetId; 650 u8 reserved; 651 __le16 seqNum; 652 }; 653 654 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 655 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 656 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 657 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 658 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 659 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 660 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 661 662 struct megasas_register_set; 663 struct megasas_instance; 664 665 union desc_word { 666 u64 word; 667 struct { 668 u32 low; 669 u32 high; 670 } u; 671 }; 672 673 struct megasas_cmd_fusion { 674 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 675 dma_addr_t io_request_phys_addr; 676 677 union MPI2_SGE_IO_UNION *sg_frame; 678 dma_addr_t sg_frame_phys_addr; 679 680 u8 *sense; 681 dma_addr_t sense_phys_addr; 682 683 struct list_head list; 684 struct scsi_cmnd *scmd; 685 struct megasas_instance *instance; 686 687 u8 retry_for_fw_reset; 688 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 689 690 /* 691 * Context for a MFI frame. 692 * Used to get the mfi cmd from list when a MFI cmd is completed 693 */ 694 u32 sync_cmd_idx; 695 u32 index; 696 u8 pd_r1_lb; 697 }; 698 699 struct LD_LOAD_BALANCE_INFO { 700 u8 loadBalanceFlag; 701 u8 reserved1; 702 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 703 u64 last_accessed_block[MAX_PHYSICAL_DEVICES]; 704 }; 705 706 /* SPAN_SET is info caclulated from span info from Raid map per LD */ 707 typedef struct _LD_SPAN_SET { 708 u64 log_start_lba; 709 u64 log_end_lba; 710 u64 span_row_start; 711 u64 span_row_end; 712 u64 data_strip_start; 713 u64 data_strip_end; 714 u64 data_row_start; 715 u64 data_row_end; 716 u8 strip_offset[MAX_SPAN_DEPTH]; 717 u32 span_row_data_width; 718 u32 diff; 719 u32 reserved[2]; 720 } LD_SPAN_SET, *PLD_SPAN_SET; 721 722 typedef struct LOG_BLOCK_SPAN_INFO { 723 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 724 } LD_SPAN_INFO, *PLD_SPAN_INFO; 725 726 struct MR_FW_RAID_MAP_ALL { 727 struct MR_FW_RAID_MAP raidMap; 728 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 729 } __attribute__ ((packed)); 730 731 struct MR_DRV_RAID_MAP { 732 /* total size of this structure, including this field. 733 * This feild will be manupulated by driver for ext raid map, 734 * else pick the value from firmware raid map. 735 */ 736 __le32 totalSize; 737 738 union { 739 struct { 740 __le32 maxLd; 741 __le32 maxSpanDepth; 742 __le32 maxRowSize; 743 __le32 maxPdCount; 744 __le32 maxArrays; 745 } validationInfo; 746 __le32 version[5]; 747 }; 748 749 /* timeout value used by driver in FP IOs*/ 750 u8 fpPdIoTimeoutSec; 751 u8 reserved2[7]; 752 753 __le16 ldCount; 754 __le16 arCount; 755 __le16 spanCount; 756 __le16 reserve3; 757 758 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 759 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 760 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 761 struct MR_LD_SPAN_MAP ldSpanMap[1]; 762 763 }; 764 765 /* Driver raid map size is same as raid map ext 766 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 767 * And it is mainly for code re-use purpose. 768 */ 769 struct MR_DRV_RAID_MAP_ALL { 770 771 struct MR_DRV_RAID_MAP raidMap; 772 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 773 } __packed; 774 775 776 777 struct MR_FW_RAID_MAP_EXT { 778 /* Not usred in new map */ 779 u32 reserved; 780 781 union { 782 struct { 783 u32 maxLd; 784 u32 maxSpanDepth; 785 u32 maxRowSize; 786 u32 maxPdCount; 787 u32 maxArrays; 788 } validationInfo; 789 u32 version[5]; 790 }; 791 792 u8 fpPdIoTimeoutSec; 793 u8 reserved2[7]; 794 795 __le16 ldCount; 796 __le16 arCount; 797 __le16 spanCount; 798 __le16 reserve3; 799 800 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 801 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 802 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 803 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 804 }; 805 806 /* 807 * * define MR_PD_CFG_SEQ structure for system PDs 808 * */ 809 struct MR_PD_CFG_SEQ { 810 __le16 seqNum; 811 __le16 devHandle; 812 u8 reserved[4]; 813 } __packed; 814 815 struct MR_PD_CFG_SEQ_NUM_SYNC { 816 __le32 size; 817 __le32 count; 818 struct MR_PD_CFG_SEQ seq[1]; 819 } __packed; 820 821 struct fusion_context { 822 struct megasas_cmd_fusion **cmd_list; 823 dma_addr_t req_frames_desc_phys; 824 u8 *req_frames_desc; 825 826 struct dma_pool *io_request_frames_pool; 827 dma_addr_t io_request_frames_phys; 828 u8 *io_request_frames; 829 830 struct dma_pool *sg_dma_pool; 831 struct dma_pool *sense_dma_pool; 832 833 dma_addr_t reply_frames_desc_phys; 834 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; 835 struct dma_pool *reply_frames_desc_pool; 836 837 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; 838 839 u32 reply_q_depth; 840 u32 request_alloc_sz; 841 u32 reply_alloc_sz; 842 u32 io_frames_alloc_sz; 843 844 u16 max_sge_in_main_msg; 845 u16 max_sge_in_chain; 846 847 u8 chain_offset_io_request; 848 u8 chain_offset_mfi_pthru; 849 850 struct MR_FW_RAID_MAP_ALL *ld_map[2]; 851 dma_addr_t ld_map_phys[2]; 852 853 /*Non dma-able memory. Driver local copy.*/ 854 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 855 856 u32 max_map_sz; 857 u32 current_map_sz; 858 u32 drv_map_sz; 859 u32 drv_map_pages; 860 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT]; 861 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT]; 862 u8 fast_path_io; 863 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 864 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 865 u8 adapter_type; 866 }; 867 868 union desc_value { 869 __le64 word; 870 struct { 871 __le32 low; 872 __le32 high; 873 } u; 874 }; 875 876 877 #endif /* _MEGARAID_SAS_FUSION_H_ */ 878