1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2011 LSI Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: LSI Corporation 23 * 24 * Send feedback to: <megaraidlinux@lsi.com> 25 * 26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 27 * ATTN: Linuxraid 28 */ 29 30 #ifndef LSI_MEGARAID_SAS_H 31 #define LSI_MEGARAID_SAS_H 32 33 /* 34 * MegaRAID SAS Driver meta data 35 */ 36 #define MEGASAS_VERSION "00.00.05.29-rc1" 37 #define MEGASAS_RELDATE "Dec. 7, 2010" 38 #define MEGASAS_EXT_VERSION "Tue. Dec. 7 17:00:00 PDT 2010" 39 40 /* 41 * Device IDs 42 */ 43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 51 52 /* 53 * ===================================== 54 * MegaRAID SAS MFI firmware definitions 55 * ===================================== 56 */ 57 58 /* 59 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 60 * protocol between the software and firmware. Commands are issued using 61 * "message frames" 62 */ 63 64 /* 65 * FW posts its state in upper 4 bits of outbound_msg_0 register 66 */ 67 #define MFI_STATE_MASK 0xF0000000 68 #define MFI_STATE_UNDEFINED 0x00000000 69 #define MFI_STATE_BB_INIT 0x10000000 70 #define MFI_STATE_FW_INIT 0x40000000 71 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 72 #define MFI_STATE_FW_INIT_2 0x70000000 73 #define MFI_STATE_DEVICE_SCAN 0x80000000 74 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 75 #define MFI_STATE_FLUSH_CACHE 0xA0000000 76 #define MFI_STATE_READY 0xB0000000 77 #define MFI_STATE_OPERATIONAL 0xC0000000 78 #define MFI_STATE_FAULT 0xF0000000 79 #define MFI_RESET_REQUIRED 0x00000001 80 81 #define MEGAMFI_FRAME_SIZE 64 82 83 /* 84 * During FW init, clear pending cmds & reset state using inbound_msg_0 85 * 86 * ABORT : Abort all pending cmds 87 * READY : Move from OPERATIONAL to READY state; discard queue info 88 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 89 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 90 * HOTPLUG : Resume from Hotplug 91 * MFI_STOP_ADP : Send signal to FW to stop processing 92 */ 93 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 94 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 95 #define DIAG_WRITE_ENABLE (0x00000080) 96 #define DIAG_RESET_ADAPTER (0x00000004) 97 98 #define MFI_ADP_RESET 0x00000040 99 #define MFI_INIT_ABORT 0x00000001 100 #define MFI_INIT_READY 0x00000002 101 #define MFI_INIT_MFIMODE 0x00000004 102 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 103 #define MFI_INIT_HOTPLUG 0x00000010 104 #define MFI_STOP_ADP 0x00000020 105 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 106 MFI_INIT_MFIMODE| \ 107 MFI_INIT_ABORT 108 109 /* 110 * MFI frame flags 111 */ 112 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 113 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 114 #define MFI_FRAME_SGL32 0x0000 115 #define MFI_FRAME_SGL64 0x0002 116 #define MFI_FRAME_SENSE32 0x0000 117 #define MFI_FRAME_SENSE64 0x0004 118 #define MFI_FRAME_DIR_NONE 0x0000 119 #define MFI_FRAME_DIR_WRITE 0x0008 120 #define MFI_FRAME_DIR_READ 0x0010 121 #define MFI_FRAME_DIR_BOTH 0x0018 122 #define MFI_FRAME_IEEE 0x0020 123 124 /* 125 * Definition for cmd_status 126 */ 127 #define MFI_CMD_STATUS_POLL_MODE 0xFF 128 129 /* 130 * MFI command opcodes 131 */ 132 #define MFI_CMD_INIT 0x00 133 #define MFI_CMD_LD_READ 0x01 134 #define MFI_CMD_LD_WRITE 0x02 135 #define MFI_CMD_LD_SCSI_IO 0x03 136 #define MFI_CMD_PD_SCSI_IO 0x04 137 #define MFI_CMD_DCMD 0x05 138 #define MFI_CMD_ABORT 0x06 139 #define MFI_CMD_SMP 0x07 140 #define MFI_CMD_STP 0x08 141 142 #define MR_DCMD_CTRL_GET_INFO 0x01010000 143 #define MR_DCMD_LD_GET_LIST 0x03010000 144 145 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 146 #define MR_FLUSH_CTRL_CACHE 0x01 147 #define MR_FLUSH_DISK_CACHE 0x02 148 149 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 150 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 151 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 152 153 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 154 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 155 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 156 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 157 158 #define MR_DCMD_CLUSTER 0x08000000 159 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 160 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 161 #define MR_DCMD_PD_LIST_QUERY 0x02010100 162 163 /* 164 * MFI command completion codes 165 */ 166 enum MFI_STAT { 167 MFI_STAT_OK = 0x00, 168 MFI_STAT_INVALID_CMD = 0x01, 169 MFI_STAT_INVALID_DCMD = 0x02, 170 MFI_STAT_INVALID_PARAMETER = 0x03, 171 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 172 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 173 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 174 MFI_STAT_APP_IN_USE = 0x07, 175 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 176 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 177 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 178 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 179 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 180 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 181 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 182 MFI_STAT_FLASH_BUSY = 0x0f, 183 MFI_STAT_FLASH_ERROR = 0x10, 184 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 185 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 186 MFI_STAT_FLASH_NOT_OPEN = 0x13, 187 MFI_STAT_FLASH_NOT_STARTED = 0x14, 188 MFI_STAT_FLUSH_FAILED = 0x15, 189 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 190 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 191 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 192 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 193 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 194 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 195 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 196 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 197 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 198 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 199 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 200 MFI_STAT_MFC_HW_ERROR = 0x21, 201 MFI_STAT_NO_HW_PRESENT = 0x22, 202 MFI_STAT_NOT_FOUND = 0x23, 203 MFI_STAT_NOT_IN_ENCL = 0x24, 204 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 205 MFI_STAT_PD_TYPE_WRONG = 0x26, 206 MFI_STAT_PR_DISABLED = 0x27, 207 MFI_STAT_ROW_INDEX_INVALID = 0x28, 208 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 209 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 210 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 211 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 212 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 213 MFI_STAT_SCSI_IO_FAILED = 0x2e, 214 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 215 MFI_STAT_SHUTDOWN_FAILED = 0x30, 216 MFI_STAT_TIME_NOT_SET = 0x31, 217 MFI_STAT_WRONG_STATE = 0x32, 218 MFI_STAT_LD_OFFLINE = 0x33, 219 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 220 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 221 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 222 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 223 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 224 225 MFI_STAT_INVALID_STATUS = 0xFF 226 }; 227 228 /* 229 * Number of mailbox bytes in DCMD message frame 230 */ 231 #define MFI_MBOX_SIZE 12 232 233 enum MR_EVT_CLASS { 234 235 MR_EVT_CLASS_DEBUG = -2, 236 MR_EVT_CLASS_PROGRESS = -1, 237 MR_EVT_CLASS_INFO = 0, 238 MR_EVT_CLASS_WARNING = 1, 239 MR_EVT_CLASS_CRITICAL = 2, 240 MR_EVT_CLASS_FATAL = 3, 241 MR_EVT_CLASS_DEAD = 4, 242 243 }; 244 245 enum MR_EVT_LOCALE { 246 247 MR_EVT_LOCALE_LD = 0x0001, 248 MR_EVT_LOCALE_PD = 0x0002, 249 MR_EVT_LOCALE_ENCL = 0x0004, 250 MR_EVT_LOCALE_BBU = 0x0008, 251 MR_EVT_LOCALE_SAS = 0x0010, 252 MR_EVT_LOCALE_CTRL = 0x0020, 253 MR_EVT_LOCALE_CONFIG = 0x0040, 254 MR_EVT_LOCALE_CLUSTER = 0x0080, 255 MR_EVT_LOCALE_ALL = 0xffff, 256 257 }; 258 259 enum MR_EVT_ARGS { 260 261 MR_EVT_ARGS_NONE, 262 MR_EVT_ARGS_CDB_SENSE, 263 MR_EVT_ARGS_LD, 264 MR_EVT_ARGS_LD_COUNT, 265 MR_EVT_ARGS_LD_LBA, 266 MR_EVT_ARGS_LD_OWNER, 267 MR_EVT_ARGS_LD_LBA_PD_LBA, 268 MR_EVT_ARGS_LD_PROG, 269 MR_EVT_ARGS_LD_STATE, 270 MR_EVT_ARGS_LD_STRIP, 271 MR_EVT_ARGS_PD, 272 MR_EVT_ARGS_PD_ERR, 273 MR_EVT_ARGS_PD_LBA, 274 MR_EVT_ARGS_PD_LBA_LD, 275 MR_EVT_ARGS_PD_PROG, 276 MR_EVT_ARGS_PD_STATE, 277 MR_EVT_ARGS_PCI, 278 MR_EVT_ARGS_RATE, 279 MR_EVT_ARGS_STR, 280 MR_EVT_ARGS_TIME, 281 MR_EVT_ARGS_ECC, 282 MR_EVT_ARGS_LD_PROP, 283 MR_EVT_ARGS_PD_SPARE, 284 MR_EVT_ARGS_PD_INDEX, 285 MR_EVT_ARGS_DIAG_PASS, 286 MR_EVT_ARGS_DIAG_FAIL, 287 MR_EVT_ARGS_PD_LBA_LBA, 288 MR_EVT_ARGS_PORT_PHY, 289 MR_EVT_ARGS_PD_MISSING, 290 MR_EVT_ARGS_PD_ADDRESS, 291 MR_EVT_ARGS_BITMAP, 292 MR_EVT_ARGS_CONNECTOR, 293 MR_EVT_ARGS_PD_PD, 294 MR_EVT_ARGS_PD_FRU, 295 MR_EVT_ARGS_PD_PATHINFO, 296 MR_EVT_ARGS_PD_POWER_STATE, 297 MR_EVT_ARGS_GENERIC, 298 }; 299 300 /* 301 * define constants for device list query options 302 */ 303 enum MR_PD_QUERY_TYPE { 304 MR_PD_QUERY_TYPE_ALL = 0, 305 MR_PD_QUERY_TYPE_STATE = 1, 306 MR_PD_QUERY_TYPE_POWER_STATE = 2, 307 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 308 MR_PD_QUERY_TYPE_SPEED = 4, 309 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 310 }; 311 312 #define MR_EVT_CFG_CLEARED 0x0004 313 #define MR_EVT_LD_STATE_CHANGE 0x0051 314 #define MR_EVT_PD_INSERTED 0x005b 315 #define MR_EVT_PD_REMOVED 0x0070 316 #define MR_EVT_LD_CREATED 0x008a 317 #define MR_EVT_LD_DELETED 0x008b 318 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 319 #define MR_EVT_LD_OFFLINE 0x00fc 320 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 321 #define MAX_LOGICAL_DRIVES 64 322 323 enum MR_PD_STATE { 324 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 325 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 326 MR_PD_STATE_HOT_SPARE = 0x02, 327 MR_PD_STATE_OFFLINE = 0x10, 328 MR_PD_STATE_FAILED = 0x11, 329 MR_PD_STATE_REBUILD = 0x14, 330 MR_PD_STATE_ONLINE = 0x18, 331 MR_PD_STATE_COPYBACK = 0x20, 332 MR_PD_STATE_SYSTEM = 0x40, 333 }; 334 335 336 /* 337 * defines the physical drive address structure 338 */ 339 struct MR_PD_ADDRESS { 340 u16 deviceId; 341 u16 enclDeviceId; 342 343 union { 344 struct { 345 u8 enclIndex; 346 u8 slotNumber; 347 } mrPdAddress; 348 struct { 349 u8 enclPosition; 350 u8 enclConnectorIndex; 351 } mrEnclAddress; 352 }; 353 u8 scsiDevType; 354 union { 355 u8 connectedPortBitmap; 356 u8 connectedPortNumbers; 357 }; 358 u64 sasAddr[2]; 359 } __packed; 360 361 /* 362 * defines the physical drive list structure 363 */ 364 struct MR_PD_LIST { 365 u32 size; 366 u32 count; 367 struct MR_PD_ADDRESS addr[1]; 368 } __packed; 369 370 struct megasas_pd_list { 371 u16 tid; 372 u8 driveType; 373 u8 driveState; 374 } __packed; 375 376 /* 377 * defines the logical drive reference structure 378 */ 379 union MR_LD_REF { 380 struct { 381 u8 targetId; 382 u8 reserved; 383 u16 seqNum; 384 }; 385 u32 ref; 386 } __packed; 387 388 /* 389 * defines the logical drive list structure 390 */ 391 struct MR_LD_LIST { 392 u32 ldCount; 393 u32 reserved; 394 struct { 395 union MR_LD_REF ref; 396 u8 state; 397 u8 reserved[3]; 398 u64 size; 399 } ldList[MAX_LOGICAL_DRIVES]; 400 } __packed; 401 402 /* 403 * SAS controller properties 404 */ 405 struct megasas_ctrl_prop { 406 407 u16 seq_num; 408 u16 pred_fail_poll_interval; 409 u16 intr_throttle_count; 410 u16 intr_throttle_timeouts; 411 u8 rebuild_rate; 412 u8 patrol_read_rate; 413 u8 bgi_rate; 414 u8 cc_rate; 415 u8 recon_rate; 416 u8 cache_flush_interval; 417 u8 spinup_drv_count; 418 u8 spinup_delay; 419 u8 cluster_enable; 420 u8 coercion_mode; 421 u8 alarm_enable; 422 u8 disable_auto_rebuild; 423 u8 disable_battery_warn; 424 u8 ecc_bucket_size; 425 u16 ecc_bucket_leak_rate; 426 u8 restore_hotspare_on_insertion; 427 u8 expose_encl_devices; 428 u8 maintainPdFailHistory; 429 u8 disallowHostRequestReordering; 430 u8 abortCCOnError; 431 u8 loadBalanceMode; 432 u8 disableAutoDetectBackplane; 433 434 u8 snapVDSpace; 435 436 /* 437 * Add properties that can be controlled by 438 * a bit in the following structure. 439 */ 440 struct { 441 u32 copyBackDisabled : 1; 442 u32 SMARTerEnabled : 1; 443 u32 prCorrectUnconfiguredAreas : 1; 444 u32 useFdeOnly : 1; 445 u32 disableNCQ : 1; 446 u32 SSDSMARTerEnabled : 1; 447 u32 SSDPatrolReadEnabled : 1; 448 u32 enableSpinDownUnconfigured : 1; 449 u32 autoEnhancedImport : 1; 450 u32 enableSecretKeyControl : 1; 451 u32 disableOnlineCtrlReset : 1; 452 u32 allowBootWithPinnedCache : 1; 453 u32 disableSpinDownHS : 1; 454 u32 enableJBOD : 1; 455 u32 reserved :18; 456 } OnOffProperties; 457 u8 autoSnapVDSpace; 458 u8 viewSpace; 459 u16 spinDownTime; 460 u8 reserved[24]; 461 } __packed; 462 463 /* 464 * SAS controller information 465 */ 466 struct megasas_ctrl_info { 467 468 /* 469 * PCI device information 470 */ 471 struct { 472 473 u16 vendor_id; 474 u16 device_id; 475 u16 sub_vendor_id; 476 u16 sub_device_id; 477 u8 reserved[24]; 478 479 } __attribute__ ((packed)) pci; 480 481 /* 482 * Host interface information 483 */ 484 struct { 485 486 u8 PCIX:1; 487 u8 PCIE:1; 488 u8 iSCSI:1; 489 u8 SAS_3G:1; 490 u8 reserved_0:4; 491 u8 reserved_1[6]; 492 u8 port_count; 493 u64 port_addr[8]; 494 495 } __attribute__ ((packed)) host_interface; 496 497 /* 498 * Device (backend) interface information 499 */ 500 struct { 501 502 u8 SPI:1; 503 u8 SAS_3G:1; 504 u8 SATA_1_5G:1; 505 u8 SATA_3G:1; 506 u8 reserved_0:4; 507 u8 reserved_1[6]; 508 u8 port_count; 509 u64 port_addr[8]; 510 511 } __attribute__ ((packed)) device_interface; 512 513 /* 514 * List of components residing in flash. All str are null terminated 515 */ 516 u32 image_check_word; 517 u32 image_component_count; 518 519 struct { 520 521 char name[8]; 522 char version[32]; 523 char build_date[16]; 524 char built_time[16]; 525 526 } __attribute__ ((packed)) image_component[8]; 527 528 /* 529 * List of flash components that have been flashed on the card, but 530 * are not in use, pending reset of the adapter. This list will be 531 * empty if a flash operation has not occurred. All stings are null 532 * terminated 533 */ 534 u32 pending_image_component_count; 535 536 struct { 537 538 char name[8]; 539 char version[32]; 540 char build_date[16]; 541 char build_time[16]; 542 543 } __attribute__ ((packed)) pending_image_component[8]; 544 545 u8 max_arms; 546 u8 max_spans; 547 u8 max_arrays; 548 u8 max_lds; 549 550 char product_name[80]; 551 char serial_no[32]; 552 553 /* 554 * Other physical/controller/operation information. Indicates the 555 * presence of the hardware 556 */ 557 struct { 558 559 u32 bbu:1; 560 u32 alarm:1; 561 u32 nvram:1; 562 u32 uart:1; 563 u32 reserved:28; 564 565 } __attribute__ ((packed)) hw_present; 566 567 u32 current_fw_time; 568 569 /* 570 * Maximum data transfer sizes 571 */ 572 u16 max_concurrent_cmds; 573 u16 max_sge_count; 574 u32 max_request_size; 575 576 /* 577 * Logical and physical device counts 578 */ 579 u16 ld_present_count; 580 u16 ld_degraded_count; 581 u16 ld_offline_count; 582 583 u16 pd_present_count; 584 u16 pd_disk_present_count; 585 u16 pd_disk_pred_failure_count; 586 u16 pd_disk_failed_count; 587 588 /* 589 * Memory size information 590 */ 591 u16 nvram_size; 592 u16 memory_size; 593 u16 flash_size; 594 595 /* 596 * Error counters 597 */ 598 u16 mem_correctable_error_count; 599 u16 mem_uncorrectable_error_count; 600 601 /* 602 * Cluster information 603 */ 604 u8 cluster_permitted; 605 u8 cluster_active; 606 607 /* 608 * Additional max data transfer sizes 609 */ 610 u16 max_strips_per_io; 611 612 /* 613 * Controller capabilities structures 614 */ 615 struct { 616 617 u32 raid_level_0:1; 618 u32 raid_level_1:1; 619 u32 raid_level_5:1; 620 u32 raid_level_1E:1; 621 u32 raid_level_6:1; 622 u32 reserved:27; 623 624 } __attribute__ ((packed)) raid_levels; 625 626 struct { 627 628 u32 rbld_rate:1; 629 u32 cc_rate:1; 630 u32 bgi_rate:1; 631 u32 recon_rate:1; 632 u32 patrol_rate:1; 633 u32 alarm_control:1; 634 u32 cluster_supported:1; 635 u32 bbu:1; 636 u32 spanning_allowed:1; 637 u32 dedicated_hotspares:1; 638 u32 revertible_hotspares:1; 639 u32 foreign_config_import:1; 640 u32 self_diagnostic:1; 641 u32 mixed_redundancy_arr:1; 642 u32 global_hot_spares:1; 643 u32 reserved:17; 644 645 } __attribute__ ((packed)) adapter_operations; 646 647 struct { 648 649 u32 read_policy:1; 650 u32 write_policy:1; 651 u32 io_policy:1; 652 u32 access_policy:1; 653 u32 disk_cache_policy:1; 654 u32 reserved:27; 655 656 } __attribute__ ((packed)) ld_operations; 657 658 struct { 659 660 u8 min; 661 u8 max; 662 u8 reserved[2]; 663 664 } __attribute__ ((packed)) stripe_sz_ops; 665 666 struct { 667 668 u32 force_online:1; 669 u32 force_offline:1; 670 u32 force_rebuild:1; 671 u32 reserved:29; 672 673 } __attribute__ ((packed)) pd_operations; 674 675 struct { 676 677 u32 ctrl_supports_sas:1; 678 u32 ctrl_supports_sata:1; 679 u32 allow_mix_in_encl:1; 680 u32 allow_mix_in_ld:1; 681 u32 allow_sata_in_cluster:1; 682 u32 reserved:27; 683 684 } __attribute__ ((packed)) pd_mix_support; 685 686 /* 687 * Define ECC single-bit-error bucket information 688 */ 689 u8 ecc_bucket_count; 690 u8 reserved_2[11]; 691 692 /* 693 * Include the controller properties (changeable items) 694 */ 695 struct megasas_ctrl_prop properties; 696 697 /* 698 * Define FW pkg version (set in envt v'bles on OEM basis) 699 */ 700 char package_version[0x60]; 701 702 u8 pad[0x800 - 0x6a0]; 703 704 } __packed; 705 706 /* 707 * =============================== 708 * MegaRAID SAS driver definitions 709 * =============================== 710 */ 711 #define MEGASAS_MAX_PD_CHANNELS 2 712 #define MEGASAS_MAX_LD_CHANNELS 2 713 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 714 MEGASAS_MAX_LD_CHANNELS) 715 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 716 #define MEGASAS_DEFAULT_INIT_ID -1 717 #define MEGASAS_MAX_LUN 8 718 #define MEGASAS_MAX_LD 64 719 #define MEGASAS_DEFAULT_CMD_PER_LUN 128 720 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 721 MEGASAS_MAX_DEV_PER_CHANNEL) 722 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 723 MEGASAS_MAX_DEV_PER_CHANNEL) 724 725 #define MEGASAS_MAX_SECTORS (2*1024) 726 #define MEGASAS_DBG_LVL 1 727 728 #define MEGASAS_FW_BUSY 1 729 730 /* Frame Type */ 731 #define IO_FRAME 0 732 #define PTHRU_FRAME 1 733 734 /* 735 * When SCSI mid-layer calls driver's reset routine, driver waits for 736 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 737 * that the driver cannot _actually_ abort or reset pending commands. While 738 * it is waiting for the commands to complete, it prints a diagnostic message 739 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 740 */ 741 #define MEGASAS_RESET_WAIT_TIME 180 742 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 743 #define MEGASAS_RESET_NOTICE_INTERVAL 5 744 #define MEGASAS_IOCTL_CMD 0 745 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 746 747 /* 748 * FW reports the maximum of number of commands that it can accept (maximum 749 * commands that can be outstanding) at any time. The driver must report a 750 * lower number to the mid layer because it can issue a few internal commands 751 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 752 * is shown below 753 */ 754 #define MEGASAS_INT_CMDS 32 755 #define MEGASAS_SKINNY_INT_CMDS 5 756 757 /* 758 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 759 * SGLs based on the size of dma_addr_t 760 */ 761 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 762 763 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 764 765 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 766 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 767 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 768 769 #define MFI_OB_INTR_STATUS_MASK 0x00000002 770 #define MFI_POLL_TIMEOUT_SECS 60 771 #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10) 772 773 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 774 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 775 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 776 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 777 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 778 779 #define MFI_1068_PCSR_OFFSET 0x84 780 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 781 #define MFI_1068_FW_READY 0xDDDD0000 782 /* 783 * register set for both 1068 and 1078 controllers 784 * structure extended for 1078 registers 785 */ 786 787 struct megasas_register_set { 788 u32 doorbell; /*0000h*/ 789 u32 fusion_seq_offset; /*0004h*/ 790 u32 fusion_host_diag; /*0008h*/ 791 u32 reserved_01; /*000Ch*/ 792 793 u32 inbound_msg_0; /*0010h*/ 794 u32 inbound_msg_1; /*0014h*/ 795 u32 outbound_msg_0; /*0018h*/ 796 u32 outbound_msg_1; /*001Ch*/ 797 798 u32 inbound_doorbell; /*0020h*/ 799 u32 inbound_intr_status; /*0024h*/ 800 u32 inbound_intr_mask; /*0028h*/ 801 802 u32 outbound_doorbell; /*002Ch*/ 803 u32 outbound_intr_status; /*0030h*/ 804 u32 outbound_intr_mask; /*0034h*/ 805 806 u32 reserved_1[2]; /*0038h*/ 807 808 u32 inbound_queue_port; /*0040h*/ 809 u32 outbound_queue_port; /*0044h*/ 810 811 u32 reserved_2[9]; /*0048h*/ 812 u32 reply_post_host_index; /*006Ch*/ 813 u32 reserved_2_2[12]; /*0070h*/ 814 815 u32 outbound_doorbell_clear; /*00A0h*/ 816 817 u32 reserved_3[3]; /*00A4h*/ 818 819 u32 outbound_scratch_pad ; /*00B0h*/ 820 u32 outbound_scratch_pad_2; /*00B4h*/ 821 822 u32 reserved_4[2]; /*00B8h*/ 823 824 u32 inbound_low_queue_port ; /*00C0h*/ 825 826 u32 inbound_high_queue_port ; /*00C4h*/ 827 828 u32 reserved_5; /*00C8h*/ 829 u32 res_6[11]; /*CCh*/ 830 u32 host_diag; 831 u32 seq_offset; 832 u32 index_registers[807]; /*00CCh*/ 833 } __attribute__ ((packed)); 834 835 struct megasas_sge32 { 836 837 u32 phys_addr; 838 u32 length; 839 840 } __attribute__ ((packed)); 841 842 struct megasas_sge64 { 843 844 u64 phys_addr; 845 u32 length; 846 847 } __attribute__ ((packed)); 848 849 struct megasas_sge_skinny { 850 u64 phys_addr; 851 u32 length; 852 u32 flag; 853 } __packed; 854 855 union megasas_sgl { 856 857 struct megasas_sge32 sge32[1]; 858 struct megasas_sge64 sge64[1]; 859 struct megasas_sge_skinny sge_skinny[1]; 860 861 } __attribute__ ((packed)); 862 863 struct megasas_header { 864 865 u8 cmd; /*00h */ 866 u8 sense_len; /*01h */ 867 u8 cmd_status; /*02h */ 868 u8 scsi_status; /*03h */ 869 870 u8 target_id; /*04h */ 871 u8 lun; /*05h */ 872 u8 cdb_len; /*06h */ 873 u8 sge_count; /*07h */ 874 875 u32 context; /*08h */ 876 u32 pad_0; /*0Ch */ 877 878 u16 flags; /*10h */ 879 u16 timeout; /*12h */ 880 u32 data_xferlen; /*14h */ 881 882 } __attribute__ ((packed)); 883 884 union megasas_sgl_frame { 885 886 struct megasas_sge32 sge32[8]; 887 struct megasas_sge64 sge64[5]; 888 889 } __attribute__ ((packed)); 890 891 struct megasas_init_frame { 892 893 u8 cmd; /*00h */ 894 u8 reserved_0; /*01h */ 895 u8 cmd_status; /*02h */ 896 897 u8 reserved_1; /*03h */ 898 u32 reserved_2; /*04h */ 899 900 u32 context; /*08h */ 901 u32 pad_0; /*0Ch */ 902 903 u16 flags; /*10h */ 904 u16 reserved_3; /*12h */ 905 u32 data_xfer_len; /*14h */ 906 907 u32 queue_info_new_phys_addr_lo; /*18h */ 908 u32 queue_info_new_phys_addr_hi; /*1Ch */ 909 u32 queue_info_old_phys_addr_lo; /*20h */ 910 u32 queue_info_old_phys_addr_hi; /*24h */ 911 912 u32 reserved_4[6]; /*28h */ 913 914 } __attribute__ ((packed)); 915 916 struct megasas_init_queue_info { 917 918 u32 init_flags; /*00h */ 919 u32 reply_queue_entries; /*04h */ 920 921 u32 reply_queue_start_phys_addr_lo; /*08h */ 922 u32 reply_queue_start_phys_addr_hi; /*0Ch */ 923 u32 producer_index_phys_addr_lo; /*10h */ 924 u32 producer_index_phys_addr_hi; /*14h */ 925 u32 consumer_index_phys_addr_lo; /*18h */ 926 u32 consumer_index_phys_addr_hi; /*1Ch */ 927 928 } __attribute__ ((packed)); 929 930 struct megasas_io_frame { 931 932 u8 cmd; /*00h */ 933 u8 sense_len; /*01h */ 934 u8 cmd_status; /*02h */ 935 u8 scsi_status; /*03h */ 936 937 u8 target_id; /*04h */ 938 u8 access_byte; /*05h */ 939 u8 reserved_0; /*06h */ 940 u8 sge_count; /*07h */ 941 942 u32 context; /*08h */ 943 u32 pad_0; /*0Ch */ 944 945 u16 flags; /*10h */ 946 u16 timeout; /*12h */ 947 u32 lba_count; /*14h */ 948 949 u32 sense_buf_phys_addr_lo; /*18h */ 950 u32 sense_buf_phys_addr_hi; /*1Ch */ 951 952 u32 start_lba_lo; /*20h */ 953 u32 start_lba_hi; /*24h */ 954 955 union megasas_sgl sgl; /*28h */ 956 957 } __attribute__ ((packed)); 958 959 struct megasas_pthru_frame { 960 961 u8 cmd; /*00h */ 962 u8 sense_len; /*01h */ 963 u8 cmd_status; /*02h */ 964 u8 scsi_status; /*03h */ 965 966 u8 target_id; /*04h */ 967 u8 lun; /*05h */ 968 u8 cdb_len; /*06h */ 969 u8 sge_count; /*07h */ 970 971 u32 context; /*08h */ 972 u32 pad_0; /*0Ch */ 973 974 u16 flags; /*10h */ 975 u16 timeout; /*12h */ 976 u32 data_xfer_len; /*14h */ 977 978 u32 sense_buf_phys_addr_lo; /*18h */ 979 u32 sense_buf_phys_addr_hi; /*1Ch */ 980 981 u8 cdb[16]; /*20h */ 982 union megasas_sgl sgl; /*30h */ 983 984 } __attribute__ ((packed)); 985 986 struct megasas_dcmd_frame { 987 988 u8 cmd; /*00h */ 989 u8 reserved_0; /*01h */ 990 u8 cmd_status; /*02h */ 991 u8 reserved_1[4]; /*03h */ 992 u8 sge_count; /*07h */ 993 994 u32 context; /*08h */ 995 u32 pad_0; /*0Ch */ 996 997 u16 flags; /*10h */ 998 u16 timeout; /*12h */ 999 1000 u32 data_xfer_len; /*14h */ 1001 u32 opcode; /*18h */ 1002 1003 union { /*1Ch */ 1004 u8 b[12]; 1005 u16 s[6]; 1006 u32 w[3]; 1007 } mbox; 1008 1009 union megasas_sgl sgl; /*28h */ 1010 1011 } __attribute__ ((packed)); 1012 1013 struct megasas_abort_frame { 1014 1015 u8 cmd; /*00h */ 1016 u8 reserved_0; /*01h */ 1017 u8 cmd_status; /*02h */ 1018 1019 u8 reserved_1; /*03h */ 1020 u32 reserved_2; /*04h */ 1021 1022 u32 context; /*08h */ 1023 u32 pad_0; /*0Ch */ 1024 1025 u16 flags; /*10h */ 1026 u16 reserved_3; /*12h */ 1027 u32 reserved_4; /*14h */ 1028 1029 u32 abort_context; /*18h */ 1030 u32 pad_1; /*1Ch */ 1031 1032 u32 abort_mfi_phys_addr_lo; /*20h */ 1033 u32 abort_mfi_phys_addr_hi; /*24h */ 1034 1035 u32 reserved_5[6]; /*28h */ 1036 1037 } __attribute__ ((packed)); 1038 1039 struct megasas_smp_frame { 1040 1041 u8 cmd; /*00h */ 1042 u8 reserved_1; /*01h */ 1043 u8 cmd_status; /*02h */ 1044 u8 connection_status; /*03h */ 1045 1046 u8 reserved_2[3]; /*04h */ 1047 u8 sge_count; /*07h */ 1048 1049 u32 context; /*08h */ 1050 u32 pad_0; /*0Ch */ 1051 1052 u16 flags; /*10h */ 1053 u16 timeout; /*12h */ 1054 1055 u32 data_xfer_len; /*14h */ 1056 u64 sas_addr; /*18h */ 1057 1058 union { 1059 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1060 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1061 } sgl; 1062 1063 } __attribute__ ((packed)); 1064 1065 struct megasas_stp_frame { 1066 1067 u8 cmd; /*00h */ 1068 u8 reserved_1; /*01h */ 1069 u8 cmd_status; /*02h */ 1070 u8 reserved_2; /*03h */ 1071 1072 u8 target_id; /*04h */ 1073 u8 reserved_3[2]; /*05h */ 1074 u8 sge_count; /*07h */ 1075 1076 u32 context; /*08h */ 1077 u32 pad_0; /*0Ch */ 1078 1079 u16 flags; /*10h */ 1080 u16 timeout; /*12h */ 1081 1082 u32 data_xfer_len; /*14h */ 1083 1084 u16 fis[10]; /*18h */ 1085 u32 stp_flags; 1086 1087 union { 1088 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1089 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1090 } sgl; 1091 1092 } __attribute__ ((packed)); 1093 1094 union megasas_frame { 1095 1096 struct megasas_header hdr; 1097 struct megasas_init_frame init; 1098 struct megasas_io_frame io; 1099 struct megasas_pthru_frame pthru; 1100 struct megasas_dcmd_frame dcmd; 1101 struct megasas_abort_frame abort; 1102 struct megasas_smp_frame smp; 1103 struct megasas_stp_frame stp; 1104 1105 u8 raw_bytes[64]; 1106 }; 1107 1108 struct megasas_cmd; 1109 1110 union megasas_evt_class_locale { 1111 1112 struct { 1113 u16 locale; 1114 u8 reserved; 1115 s8 class; 1116 } __attribute__ ((packed)) members; 1117 1118 u32 word; 1119 1120 } __attribute__ ((packed)); 1121 1122 struct megasas_evt_log_info { 1123 u32 newest_seq_num; 1124 u32 oldest_seq_num; 1125 u32 clear_seq_num; 1126 u32 shutdown_seq_num; 1127 u32 boot_seq_num; 1128 1129 } __attribute__ ((packed)); 1130 1131 struct megasas_progress { 1132 1133 u16 progress; 1134 u16 elapsed_seconds; 1135 1136 } __attribute__ ((packed)); 1137 1138 struct megasas_evtarg_ld { 1139 1140 u16 target_id; 1141 u8 ld_index; 1142 u8 reserved; 1143 1144 } __attribute__ ((packed)); 1145 1146 struct megasas_evtarg_pd { 1147 u16 device_id; 1148 u8 encl_index; 1149 u8 slot_number; 1150 1151 } __attribute__ ((packed)); 1152 1153 struct megasas_evt_detail { 1154 1155 u32 seq_num; 1156 u32 time_stamp; 1157 u32 code; 1158 union megasas_evt_class_locale cl; 1159 u8 arg_type; 1160 u8 reserved1[15]; 1161 1162 union { 1163 struct { 1164 struct megasas_evtarg_pd pd; 1165 u8 cdb_length; 1166 u8 sense_length; 1167 u8 reserved[2]; 1168 u8 cdb[16]; 1169 u8 sense[64]; 1170 } __attribute__ ((packed)) cdbSense; 1171 1172 struct megasas_evtarg_ld ld; 1173 1174 struct { 1175 struct megasas_evtarg_ld ld; 1176 u64 count; 1177 } __attribute__ ((packed)) ld_count; 1178 1179 struct { 1180 u64 lba; 1181 struct megasas_evtarg_ld ld; 1182 } __attribute__ ((packed)) ld_lba; 1183 1184 struct { 1185 struct megasas_evtarg_ld ld; 1186 u32 prevOwner; 1187 u32 newOwner; 1188 } __attribute__ ((packed)) ld_owner; 1189 1190 struct { 1191 u64 ld_lba; 1192 u64 pd_lba; 1193 struct megasas_evtarg_ld ld; 1194 struct megasas_evtarg_pd pd; 1195 } __attribute__ ((packed)) ld_lba_pd_lba; 1196 1197 struct { 1198 struct megasas_evtarg_ld ld; 1199 struct megasas_progress prog; 1200 } __attribute__ ((packed)) ld_prog; 1201 1202 struct { 1203 struct megasas_evtarg_ld ld; 1204 u32 prev_state; 1205 u32 new_state; 1206 } __attribute__ ((packed)) ld_state; 1207 1208 struct { 1209 u64 strip; 1210 struct megasas_evtarg_ld ld; 1211 } __attribute__ ((packed)) ld_strip; 1212 1213 struct megasas_evtarg_pd pd; 1214 1215 struct { 1216 struct megasas_evtarg_pd pd; 1217 u32 err; 1218 } __attribute__ ((packed)) pd_err; 1219 1220 struct { 1221 u64 lba; 1222 struct megasas_evtarg_pd pd; 1223 } __attribute__ ((packed)) pd_lba; 1224 1225 struct { 1226 u64 lba; 1227 struct megasas_evtarg_pd pd; 1228 struct megasas_evtarg_ld ld; 1229 } __attribute__ ((packed)) pd_lba_ld; 1230 1231 struct { 1232 struct megasas_evtarg_pd pd; 1233 struct megasas_progress prog; 1234 } __attribute__ ((packed)) pd_prog; 1235 1236 struct { 1237 struct megasas_evtarg_pd pd; 1238 u32 prevState; 1239 u32 newState; 1240 } __attribute__ ((packed)) pd_state; 1241 1242 struct { 1243 u16 vendorId; 1244 u16 deviceId; 1245 u16 subVendorId; 1246 u16 subDeviceId; 1247 } __attribute__ ((packed)) pci; 1248 1249 u32 rate; 1250 char str[96]; 1251 1252 struct { 1253 u32 rtc; 1254 u32 elapsedSeconds; 1255 } __attribute__ ((packed)) time; 1256 1257 struct { 1258 u32 ecar; 1259 u32 elog; 1260 char str[64]; 1261 } __attribute__ ((packed)) ecc; 1262 1263 u8 b[96]; 1264 u16 s[48]; 1265 u32 w[24]; 1266 u64 d[12]; 1267 } args; 1268 1269 char description[128]; 1270 1271 } __attribute__ ((packed)); 1272 1273 struct megasas_aen_event { 1274 struct work_struct hotplug_work; 1275 struct megasas_instance *instance; 1276 }; 1277 1278 struct megasas_instance { 1279 1280 u32 *producer; 1281 dma_addr_t producer_h; 1282 u32 *consumer; 1283 dma_addr_t consumer_h; 1284 1285 u32 *reply_queue; 1286 dma_addr_t reply_queue_h; 1287 1288 unsigned long base_addr; 1289 struct megasas_register_set __iomem *reg_set; 1290 1291 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1292 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1293 s8 init_id; 1294 1295 u16 max_num_sge; 1296 u16 max_fw_cmds; 1297 /* For Fusion its num IOCTL cmds, for others MFI based its 1298 max_fw_cmds */ 1299 u16 max_mfi_cmds; 1300 u32 max_sectors_per_req; 1301 struct megasas_aen_event *ev; 1302 1303 struct megasas_cmd **cmd_list; 1304 struct list_head cmd_pool; 1305 /* used to sync fire the cmd to fw */ 1306 spinlock_t cmd_pool_lock; 1307 /* used to sync fire the cmd to fw */ 1308 spinlock_t hba_lock; 1309 /* used to synch producer, consumer ptrs in dpc */ 1310 spinlock_t completion_lock; 1311 struct dma_pool *frame_dma_pool; 1312 struct dma_pool *sense_dma_pool; 1313 1314 struct megasas_evt_detail *evt_detail; 1315 dma_addr_t evt_detail_h; 1316 struct megasas_cmd *aen_cmd; 1317 struct mutex aen_mutex; 1318 struct semaphore ioctl_sem; 1319 1320 struct Scsi_Host *host; 1321 1322 wait_queue_head_t int_cmd_wait_q; 1323 wait_queue_head_t abort_cmd_wait_q; 1324 1325 struct pci_dev *pdev; 1326 u32 unique_id; 1327 u32 fw_support_ieee; 1328 1329 atomic_t fw_outstanding; 1330 atomic_t fw_reset_no_pci_access; 1331 1332 struct megasas_instance_template *instancet; 1333 struct tasklet_struct isr_tasklet; 1334 struct work_struct work_init; 1335 1336 u8 flag; 1337 u8 unload; 1338 u8 flag_ieee; 1339 u8 issuepend_done; 1340 u8 disableOnlineCtrlReset; 1341 u8 adprecovery; 1342 unsigned long last_time; 1343 u32 mfiStatus; 1344 u32 last_seq_num; 1345 1346 struct timer_list io_completion_timer; 1347 struct list_head internal_reset_pending_q; 1348 1349 /* Ptr to hba specfic information */ 1350 void *ctrl_context; 1351 u8 msi_flag; 1352 struct msix_entry msixentry; 1353 u64 map_id; 1354 struct megasas_cmd *map_update_cmd; 1355 unsigned long bar; 1356 long reset_flags; 1357 struct mutex reset_mutex; 1358 }; 1359 1360 enum { 1361 MEGASAS_HBA_OPERATIONAL = 0, 1362 MEGASAS_ADPRESET_SM_INFAULT = 1, 1363 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1364 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 1365 MEGASAS_HW_CRITICAL_ERROR = 4, 1366 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1367 }; 1368 1369 struct megasas_instance_template { 1370 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 1371 u32, struct megasas_register_set __iomem *); 1372 1373 void (*enable_intr)(struct megasas_register_set __iomem *) ; 1374 void (*disable_intr)(struct megasas_register_set __iomem *); 1375 1376 int (*clear_intr)(struct megasas_register_set __iomem *); 1377 1378 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 1379 int (*adp_reset)(struct megasas_instance *, \ 1380 struct megasas_register_set __iomem *); 1381 int (*check_reset)(struct megasas_instance *, \ 1382 struct megasas_register_set __iomem *); 1383 irqreturn_t (*service_isr)(int irq, void *devp); 1384 void (*tasklet)(unsigned long); 1385 u32 (*init_adapter)(struct megasas_instance *); 1386 u32 (*build_and_issue_cmd) (struct megasas_instance *, 1387 struct scsi_cmnd *); 1388 void (*issue_dcmd) (struct megasas_instance *instance, 1389 struct megasas_cmd *cmd); 1390 }; 1391 1392 #define MEGASAS_IS_LOGICAL(scp) \ 1393 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1394 1395 #define MEGASAS_DEV_INDEX(inst, scp) \ 1396 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1397 scp->device->id 1398 1399 struct megasas_cmd { 1400 1401 union megasas_frame *frame; 1402 dma_addr_t frame_phys_addr; 1403 u8 *sense; 1404 dma_addr_t sense_phys_addr; 1405 1406 u32 index; 1407 u8 sync_cmd; 1408 u8 cmd_status; 1409 u8 abort_aen; 1410 u8 retry_for_fw_reset; 1411 1412 1413 struct list_head list; 1414 struct scsi_cmnd *scmd; 1415 struct megasas_instance *instance; 1416 union { 1417 struct { 1418 u16 smid; 1419 u16 resvd; 1420 } context; 1421 u32 frame_count; 1422 }; 1423 }; 1424 1425 #define MAX_MGMT_ADAPTERS 1024 1426 #define MAX_IOCTL_SGE 16 1427 1428 struct megasas_iocpacket { 1429 1430 u16 host_no; 1431 u16 __pad1; 1432 u32 sgl_off; 1433 u32 sge_count; 1434 u32 sense_off; 1435 u32 sense_len; 1436 union { 1437 u8 raw[128]; 1438 struct megasas_header hdr; 1439 } frame; 1440 1441 struct iovec sgl[MAX_IOCTL_SGE]; 1442 1443 } __attribute__ ((packed)); 1444 1445 struct megasas_aen { 1446 u16 host_no; 1447 u16 __pad1; 1448 u32 seq_num; 1449 u32 class_locale_word; 1450 } __attribute__ ((packed)); 1451 1452 #ifdef CONFIG_COMPAT 1453 struct compat_megasas_iocpacket { 1454 u16 host_no; 1455 u16 __pad1; 1456 u32 sgl_off; 1457 u32 sge_count; 1458 u32 sense_off; 1459 u32 sense_len; 1460 union { 1461 u8 raw[128]; 1462 struct megasas_header hdr; 1463 } frame; 1464 struct compat_iovec sgl[MAX_IOCTL_SGE]; 1465 } __attribute__ ((packed)); 1466 1467 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1468 #endif 1469 1470 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1471 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1472 1473 struct megasas_mgmt_info { 1474 1475 u16 count; 1476 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1477 int max_index; 1478 }; 1479 1480 #endif /*LSI_MEGARAID_SAS_H */ 1481