1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2003-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: Avago Technologies 23 * Kashyap Desai <kashyap.desai@avagotech.com> 24 * Sumit Saxena <sumit.saxena@avagotech.com> 25 * 26 * Send feedback to: megaraidlinux.pdl@avagotech.com 27 * 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29 * San Jose, California 95131 30 */ 31 32 #ifndef LSI_MEGARAID_SAS_H 33 #define LSI_MEGARAID_SAS_H 34 35 /* 36 * MegaRAID SAS Driver meta data 37 */ 38 #define MEGASAS_VERSION "07.703.05.00-rc1" 39 #define MEGASAS_RELDATE "October 5, 2017" 40 41 /* 42 * Device IDs 43 */ 44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 54 #define PCI_DEVICE_ID_LSI_FURY 0x005f 55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014 60 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015 61 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016 62 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 63 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B 64 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C 65 66 /* 67 * Intel HBA SSDIDs 68 */ 69 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 70 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 71 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 72 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 73 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 74 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 75 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 76 77 /* 78 * Intruder HBA SSDIDs 79 */ 80 #define MEGARAID_INTRUDER_SSDID1 0x9371 81 #define MEGARAID_INTRUDER_SSDID2 0x9390 82 #define MEGARAID_INTRUDER_SSDID3 0x9370 83 84 /* 85 * Intel HBA branding 86 */ 87 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 88 "Intel(R) RAID Controller RS3DC080" 89 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 90 "Intel(R) RAID Controller RS3DC040" 91 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 92 "Intel(R) RAID Controller RS3SC008" 93 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 94 "Intel(R) RAID Controller RS3MC044" 95 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 96 "Intel(R) RAID Controller RS3WC080" 97 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 98 "Intel(R) RAID Controller RS3WC040" 99 #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 100 "Intel(R) Integrated RAID Module RMS3BC160" 101 102 /* 103 * ===================================== 104 * MegaRAID SAS MFI firmware definitions 105 * ===================================== 106 */ 107 108 /* 109 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 110 * protocol between the software and firmware. Commands are issued using 111 * "message frames" 112 */ 113 114 /* 115 * FW posts its state in upper 4 bits of outbound_msg_0 register 116 */ 117 #define MFI_STATE_MASK 0xF0000000 118 #define MFI_STATE_UNDEFINED 0x00000000 119 #define MFI_STATE_BB_INIT 0x10000000 120 #define MFI_STATE_FW_INIT 0x40000000 121 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 122 #define MFI_STATE_FW_INIT_2 0x70000000 123 #define MFI_STATE_DEVICE_SCAN 0x80000000 124 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 125 #define MFI_STATE_FLUSH_CACHE 0xA0000000 126 #define MFI_STATE_READY 0xB0000000 127 #define MFI_STATE_OPERATIONAL 0xC0000000 128 #define MFI_STATE_FAULT 0xF0000000 129 #define MFI_STATE_FORCE_OCR 0x00000080 130 #define MFI_STATE_DMADONE 0x00000008 131 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 132 #define MFI_RESET_REQUIRED 0x00000001 133 #define MFI_RESET_ADAPTER 0x00000002 134 #define MEGAMFI_FRAME_SIZE 64 135 136 /* 137 * During FW init, clear pending cmds & reset state using inbound_msg_0 138 * 139 * ABORT : Abort all pending cmds 140 * READY : Move from OPERATIONAL to READY state; discard queue info 141 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 142 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 143 * HOTPLUG : Resume from Hotplug 144 * MFI_STOP_ADP : Send signal to FW to stop processing 145 */ 146 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 147 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 148 #define DIAG_WRITE_ENABLE (0x00000080) 149 #define DIAG_RESET_ADAPTER (0x00000004) 150 151 #define MFI_ADP_RESET 0x00000040 152 #define MFI_INIT_ABORT 0x00000001 153 #define MFI_INIT_READY 0x00000002 154 #define MFI_INIT_MFIMODE 0x00000004 155 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 156 #define MFI_INIT_HOTPLUG 0x00000010 157 #define MFI_STOP_ADP 0x00000020 158 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 159 MFI_INIT_MFIMODE| \ 160 MFI_INIT_ABORT 161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 162 163 /* 164 * MFI frame flags 165 */ 166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 168 #define MFI_FRAME_SGL32 0x0000 169 #define MFI_FRAME_SGL64 0x0002 170 #define MFI_FRAME_SENSE32 0x0000 171 #define MFI_FRAME_SENSE64 0x0004 172 #define MFI_FRAME_DIR_NONE 0x0000 173 #define MFI_FRAME_DIR_WRITE 0x0008 174 #define MFI_FRAME_DIR_READ 0x0010 175 #define MFI_FRAME_DIR_BOTH 0x0018 176 #define MFI_FRAME_IEEE 0x0020 177 178 /* Driver internal */ 179 #define DRV_DCMD_POLLED_MODE 0x1 180 #define DRV_DCMD_SKIP_REFIRE 0x2 181 182 /* 183 * Definition for cmd_status 184 */ 185 #define MFI_CMD_STATUS_POLL_MODE 0xFF 186 187 /* 188 * MFI command opcodes 189 */ 190 enum MFI_CMD_OP { 191 MFI_CMD_INIT = 0x0, 192 MFI_CMD_LD_READ = 0x1, 193 MFI_CMD_LD_WRITE = 0x2, 194 MFI_CMD_LD_SCSI_IO = 0x3, 195 MFI_CMD_PD_SCSI_IO = 0x4, 196 MFI_CMD_DCMD = 0x5, 197 MFI_CMD_ABORT = 0x6, 198 MFI_CMD_SMP = 0x7, 199 MFI_CMD_STP = 0x8, 200 MFI_CMD_OP_COUNT, 201 MFI_CMD_INVALID = 0xff 202 }; 203 204 #define MR_DCMD_CTRL_GET_INFO 0x01010000 205 #define MR_DCMD_LD_GET_LIST 0x03010000 206 #define MR_DCMD_LD_LIST_QUERY 0x03010100 207 208 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 209 #define MR_FLUSH_CTRL_CACHE 0x01 210 #define MR_FLUSH_DISK_CACHE 0x02 211 212 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 213 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 214 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 215 216 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 217 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 218 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 219 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 220 221 #define MR_DCMD_CLUSTER 0x08000000 222 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 223 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 224 #define MR_DCMD_PD_LIST_QUERY 0x02010100 225 226 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 227 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 228 #define MR_DCMD_PD_GET_INFO 0x02020000 229 230 /* 231 * Global functions 232 */ 233 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 234 235 236 /* 237 * MFI command completion codes 238 */ 239 enum MFI_STAT { 240 MFI_STAT_OK = 0x00, 241 MFI_STAT_INVALID_CMD = 0x01, 242 MFI_STAT_INVALID_DCMD = 0x02, 243 MFI_STAT_INVALID_PARAMETER = 0x03, 244 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 245 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 246 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 247 MFI_STAT_APP_IN_USE = 0x07, 248 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 249 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 250 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 251 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 252 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 253 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 254 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 255 MFI_STAT_FLASH_BUSY = 0x0f, 256 MFI_STAT_FLASH_ERROR = 0x10, 257 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 258 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 259 MFI_STAT_FLASH_NOT_OPEN = 0x13, 260 MFI_STAT_FLASH_NOT_STARTED = 0x14, 261 MFI_STAT_FLUSH_FAILED = 0x15, 262 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 263 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 264 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 265 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 266 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 267 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 268 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 269 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 270 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 271 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 272 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 273 MFI_STAT_MFC_HW_ERROR = 0x21, 274 MFI_STAT_NO_HW_PRESENT = 0x22, 275 MFI_STAT_NOT_FOUND = 0x23, 276 MFI_STAT_NOT_IN_ENCL = 0x24, 277 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 278 MFI_STAT_PD_TYPE_WRONG = 0x26, 279 MFI_STAT_PR_DISABLED = 0x27, 280 MFI_STAT_ROW_INDEX_INVALID = 0x28, 281 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 282 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 283 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 284 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 285 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 286 MFI_STAT_SCSI_IO_FAILED = 0x2e, 287 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 288 MFI_STAT_SHUTDOWN_FAILED = 0x30, 289 MFI_STAT_TIME_NOT_SET = 0x31, 290 MFI_STAT_WRONG_STATE = 0x32, 291 MFI_STAT_LD_OFFLINE = 0x33, 292 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 293 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 294 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 295 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 296 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 297 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 298 299 MFI_STAT_INVALID_STATUS = 0xFF 300 }; 301 302 enum mfi_evt_class { 303 MFI_EVT_CLASS_DEBUG = -2, 304 MFI_EVT_CLASS_PROGRESS = -1, 305 MFI_EVT_CLASS_INFO = 0, 306 MFI_EVT_CLASS_WARNING = 1, 307 MFI_EVT_CLASS_CRITICAL = 2, 308 MFI_EVT_CLASS_FATAL = 3, 309 MFI_EVT_CLASS_DEAD = 4 310 }; 311 312 /* 313 * Crash dump related defines 314 */ 315 #define MAX_CRASH_DUMP_SIZE 512 316 #define CRASH_DMA_BUF_SIZE (1024 * 1024) 317 318 enum MR_FW_CRASH_DUMP_STATE { 319 UNAVAILABLE = 0, 320 AVAILABLE = 1, 321 COPYING = 2, 322 COPIED = 3, 323 COPY_ERROR = 4, 324 }; 325 326 enum _MR_CRASH_BUF_STATUS { 327 MR_CRASH_BUF_TURN_OFF = 0, 328 MR_CRASH_BUF_TURN_ON = 1, 329 }; 330 331 /* 332 * Number of mailbox bytes in DCMD message frame 333 */ 334 #define MFI_MBOX_SIZE 12 335 336 enum MR_EVT_CLASS { 337 338 MR_EVT_CLASS_DEBUG = -2, 339 MR_EVT_CLASS_PROGRESS = -1, 340 MR_EVT_CLASS_INFO = 0, 341 MR_EVT_CLASS_WARNING = 1, 342 MR_EVT_CLASS_CRITICAL = 2, 343 MR_EVT_CLASS_FATAL = 3, 344 MR_EVT_CLASS_DEAD = 4, 345 346 }; 347 348 enum MR_EVT_LOCALE { 349 350 MR_EVT_LOCALE_LD = 0x0001, 351 MR_EVT_LOCALE_PD = 0x0002, 352 MR_EVT_LOCALE_ENCL = 0x0004, 353 MR_EVT_LOCALE_BBU = 0x0008, 354 MR_EVT_LOCALE_SAS = 0x0010, 355 MR_EVT_LOCALE_CTRL = 0x0020, 356 MR_EVT_LOCALE_CONFIG = 0x0040, 357 MR_EVT_LOCALE_CLUSTER = 0x0080, 358 MR_EVT_LOCALE_ALL = 0xffff, 359 360 }; 361 362 enum MR_EVT_ARGS { 363 364 MR_EVT_ARGS_NONE, 365 MR_EVT_ARGS_CDB_SENSE, 366 MR_EVT_ARGS_LD, 367 MR_EVT_ARGS_LD_COUNT, 368 MR_EVT_ARGS_LD_LBA, 369 MR_EVT_ARGS_LD_OWNER, 370 MR_EVT_ARGS_LD_LBA_PD_LBA, 371 MR_EVT_ARGS_LD_PROG, 372 MR_EVT_ARGS_LD_STATE, 373 MR_EVT_ARGS_LD_STRIP, 374 MR_EVT_ARGS_PD, 375 MR_EVT_ARGS_PD_ERR, 376 MR_EVT_ARGS_PD_LBA, 377 MR_EVT_ARGS_PD_LBA_LD, 378 MR_EVT_ARGS_PD_PROG, 379 MR_EVT_ARGS_PD_STATE, 380 MR_EVT_ARGS_PCI, 381 MR_EVT_ARGS_RATE, 382 MR_EVT_ARGS_STR, 383 MR_EVT_ARGS_TIME, 384 MR_EVT_ARGS_ECC, 385 MR_EVT_ARGS_LD_PROP, 386 MR_EVT_ARGS_PD_SPARE, 387 MR_EVT_ARGS_PD_INDEX, 388 MR_EVT_ARGS_DIAG_PASS, 389 MR_EVT_ARGS_DIAG_FAIL, 390 MR_EVT_ARGS_PD_LBA_LBA, 391 MR_EVT_ARGS_PORT_PHY, 392 MR_EVT_ARGS_PD_MISSING, 393 MR_EVT_ARGS_PD_ADDRESS, 394 MR_EVT_ARGS_BITMAP, 395 MR_EVT_ARGS_CONNECTOR, 396 MR_EVT_ARGS_PD_PD, 397 MR_EVT_ARGS_PD_FRU, 398 MR_EVT_ARGS_PD_PATHINFO, 399 MR_EVT_ARGS_PD_POWER_STATE, 400 MR_EVT_ARGS_GENERIC, 401 }; 402 403 404 #define SGE_BUFFER_SIZE 4096 405 #define MEGASAS_CLUSTER_ID_SIZE 16 406 /* 407 * define constants for device list query options 408 */ 409 enum MR_PD_QUERY_TYPE { 410 MR_PD_QUERY_TYPE_ALL = 0, 411 MR_PD_QUERY_TYPE_STATE = 1, 412 MR_PD_QUERY_TYPE_POWER_STATE = 2, 413 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 414 MR_PD_QUERY_TYPE_SPEED = 4, 415 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 416 }; 417 418 enum MR_LD_QUERY_TYPE { 419 MR_LD_QUERY_TYPE_ALL = 0, 420 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 421 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 422 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 423 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 424 }; 425 426 427 #define MR_EVT_CFG_CLEARED 0x0004 428 #define MR_EVT_LD_STATE_CHANGE 0x0051 429 #define MR_EVT_PD_INSERTED 0x005b 430 #define MR_EVT_PD_REMOVED 0x0070 431 #define MR_EVT_LD_CREATED 0x008a 432 #define MR_EVT_LD_DELETED 0x008b 433 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 434 #define MR_EVT_LD_OFFLINE 0x00fc 435 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 436 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 437 438 enum MR_PD_STATE { 439 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 440 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 441 MR_PD_STATE_HOT_SPARE = 0x02, 442 MR_PD_STATE_OFFLINE = 0x10, 443 MR_PD_STATE_FAILED = 0x11, 444 MR_PD_STATE_REBUILD = 0x14, 445 MR_PD_STATE_ONLINE = 0x18, 446 MR_PD_STATE_COPYBACK = 0x20, 447 MR_PD_STATE_SYSTEM = 0x40, 448 }; 449 450 union MR_PD_REF { 451 struct { 452 u16 deviceId; 453 u16 seqNum; 454 } mrPdRef; 455 u32 ref; 456 }; 457 458 /* 459 * define the DDF Type bit structure 460 */ 461 union MR_PD_DDF_TYPE { 462 struct { 463 union { 464 struct { 465 #ifndef __BIG_ENDIAN_BITFIELD 466 u16 forcedPDGUID:1; 467 u16 inVD:1; 468 u16 isGlobalSpare:1; 469 u16 isSpare:1; 470 u16 isForeign:1; 471 u16 reserved:7; 472 u16 intf:4; 473 #else 474 u16 intf:4; 475 u16 reserved:7; 476 u16 isForeign:1; 477 u16 isSpare:1; 478 u16 isGlobalSpare:1; 479 u16 inVD:1; 480 u16 forcedPDGUID:1; 481 #endif 482 } pdType; 483 u16 type; 484 }; 485 u16 reserved; 486 } ddf; 487 struct { 488 u32 reserved; 489 } nonDisk; 490 u32 type; 491 } __packed; 492 493 /* 494 * defines the progress structure 495 */ 496 union MR_PROGRESS { 497 struct { 498 u16 progress; 499 union { 500 u16 elapsedSecs; 501 u16 elapsedSecsForLastPercent; 502 }; 503 } mrProgress; 504 u32 w; 505 } __packed; 506 507 /* 508 * defines the physical drive progress structure 509 */ 510 struct MR_PD_PROGRESS { 511 struct { 512 #ifndef MFI_BIG_ENDIAN 513 u32 rbld:1; 514 u32 patrol:1; 515 u32 clear:1; 516 u32 copyBack:1; 517 u32 erase:1; 518 u32 locate:1; 519 u32 reserved:26; 520 #else 521 u32 reserved:26; 522 u32 locate:1; 523 u32 erase:1; 524 u32 copyBack:1; 525 u32 clear:1; 526 u32 patrol:1; 527 u32 rbld:1; 528 #endif 529 } active; 530 union MR_PROGRESS rbld; 531 union MR_PROGRESS patrol; 532 union { 533 union MR_PROGRESS clear; 534 union MR_PROGRESS erase; 535 }; 536 537 struct { 538 #ifndef MFI_BIG_ENDIAN 539 u32 rbld:1; 540 u32 patrol:1; 541 u32 clear:1; 542 u32 copyBack:1; 543 u32 erase:1; 544 u32 reserved:27; 545 #else 546 u32 reserved:27; 547 u32 erase:1; 548 u32 copyBack:1; 549 u32 clear:1; 550 u32 patrol:1; 551 u32 rbld:1; 552 #endif 553 } pause; 554 555 union MR_PROGRESS reserved[3]; 556 } __packed; 557 558 struct MR_PD_INFO { 559 union MR_PD_REF ref; 560 u8 inquiryData[96]; 561 u8 vpdPage83[64]; 562 u8 notSupported; 563 u8 scsiDevType; 564 565 union { 566 u8 connectedPortBitmap; 567 u8 connectedPortNumbers; 568 }; 569 570 u8 deviceSpeed; 571 u32 mediaErrCount; 572 u32 otherErrCount; 573 u32 predFailCount; 574 u32 lastPredFailEventSeqNum; 575 576 u16 fwState; 577 u8 disabledForRemoval; 578 u8 linkSpeed; 579 union MR_PD_DDF_TYPE state; 580 581 struct { 582 u8 count; 583 #ifndef __BIG_ENDIAN_BITFIELD 584 u8 isPathBroken:4; 585 u8 reserved3:3; 586 u8 widePortCapable:1; 587 #else 588 u8 widePortCapable:1; 589 u8 reserved3:3; 590 u8 isPathBroken:4; 591 #endif 592 593 u8 connectorIndex[2]; 594 u8 reserved[4]; 595 u64 sasAddr[2]; 596 u8 reserved2[16]; 597 } pathInfo; 598 599 u64 rawSize; 600 u64 nonCoercedSize; 601 u64 coercedSize; 602 u16 enclDeviceId; 603 u8 enclIndex; 604 605 union { 606 u8 slotNumber; 607 u8 enclConnectorIndex; 608 }; 609 610 struct MR_PD_PROGRESS progInfo; 611 u8 badBlockTableFull; 612 u8 unusableInCurrentConfig; 613 u8 vpdPage83Ext[64]; 614 u8 powerState; 615 u8 enclPosition; 616 u32 allowedOps; 617 u16 copyBackPartnerId; 618 u16 enclPartnerDeviceId; 619 struct { 620 #ifndef __BIG_ENDIAN_BITFIELD 621 u16 fdeCapable:1; 622 u16 fdeEnabled:1; 623 u16 secured:1; 624 u16 locked:1; 625 u16 foreign:1; 626 u16 needsEKM:1; 627 u16 reserved:10; 628 #else 629 u16 reserved:10; 630 u16 needsEKM:1; 631 u16 foreign:1; 632 u16 locked:1; 633 u16 secured:1; 634 u16 fdeEnabled:1; 635 u16 fdeCapable:1; 636 #endif 637 } security; 638 u8 mediaType; 639 u8 notCertified; 640 u8 bridgeVendor[8]; 641 u8 bridgeProductIdentification[16]; 642 u8 bridgeProductRevisionLevel[4]; 643 u8 satBridgeExists; 644 645 u8 interfaceType; 646 u8 temperature; 647 u8 emulatedBlockSize; 648 u16 userDataBlockSize; 649 u16 reserved2; 650 651 struct { 652 #ifndef __BIG_ENDIAN_BITFIELD 653 u32 piType:3; 654 u32 piFormatted:1; 655 u32 piEligible:1; 656 u32 NCQ:1; 657 u32 WCE:1; 658 u32 commissionedSpare:1; 659 u32 emergencySpare:1; 660 u32 ineligibleForSSCD:1; 661 u32 ineligibleForLd:1; 662 u32 useSSEraseType:1; 663 u32 wceUnchanged:1; 664 u32 supportScsiUnmap:1; 665 u32 reserved:18; 666 #else 667 u32 reserved:18; 668 u32 supportScsiUnmap:1; 669 u32 wceUnchanged:1; 670 u32 useSSEraseType:1; 671 u32 ineligibleForLd:1; 672 u32 ineligibleForSSCD:1; 673 u32 emergencySpare:1; 674 u32 commissionedSpare:1; 675 u32 WCE:1; 676 u32 NCQ:1; 677 u32 piEligible:1; 678 u32 piFormatted:1; 679 u32 piType:3; 680 #endif 681 } properties; 682 683 u64 shieldDiagCompletionTime; 684 u8 shieldCounter; 685 686 u8 linkSpeedOther; 687 u8 reserved4[2]; 688 689 struct { 690 #ifndef __BIG_ENDIAN_BITFIELD 691 u32 bbmErrCountSupported:1; 692 u32 bbmErrCount:31; 693 #else 694 u32 bbmErrCount:31; 695 u32 bbmErrCountSupported:1; 696 #endif 697 } bbmErr; 698 699 u8 reserved1[512-428]; 700 } __packed; 701 702 /* 703 * Definition of structure used to expose attributes of VD or JBOD 704 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP 705 * is fired by driver) 706 */ 707 struct MR_TARGET_PROPERTIES { 708 u32 max_io_size_kb; 709 u32 device_qdepth; 710 u32 sector_size; 711 u8 reserved[500]; 712 } __packed; 713 714 /* 715 * defines the physical drive address structure 716 */ 717 struct MR_PD_ADDRESS { 718 __le16 deviceId; 719 u16 enclDeviceId; 720 721 union { 722 struct { 723 u8 enclIndex; 724 u8 slotNumber; 725 } mrPdAddress; 726 struct { 727 u8 enclPosition; 728 u8 enclConnectorIndex; 729 } mrEnclAddress; 730 }; 731 u8 scsiDevType; 732 union { 733 u8 connectedPortBitmap; 734 u8 connectedPortNumbers; 735 }; 736 u64 sasAddr[2]; 737 } __packed; 738 739 /* 740 * defines the physical drive list structure 741 */ 742 struct MR_PD_LIST { 743 __le32 size; 744 __le32 count; 745 struct MR_PD_ADDRESS addr[1]; 746 } __packed; 747 748 struct megasas_pd_list { 749 u16 tid; 750 u8 driveType; 751 u8 driveState; 752 } __packed; 753 754 /* 755 * defines the logical drive reference structure 756 */ 757 union MR_LD_REF { 758 struct { 759 u8 targetId; 760 u8 reserved; 761 __le16 seqNum; 762 }; 763 __le32 ref; 764 } __packed; 765 766 /* 767 * defines the logical drive list structure 768 */ 769 struct MR_LD_LIST { 770 __le32 ldCount; 771 __le32 reserved; 772 struct { 773 union MR_LD_REF ref; 774 u8 state; 775 u8 reserved[3]; 776 __le64 size; 777 } ldList[MAX_LOGICAL_DRIVES_EXT]; 778 } __packed; 779 780 struct MR_LD_TARGETID_LIST { 781 __le32 size; 782 __le32 count; 783 u8 pad[3]; 784 u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 785 }; 786 787 788 /* 789 * SAS controller properties 790 */ 791 struct megasas_ctrl_prop { 792 793 u16 seq_num; 794 u16 pred_fail_poll_interval; 795 u16 intr_throttle_count; 796 u16 intr_throttle_timeouts; 797 u8 rebuild_rate; 798 u8 patrol_read_rate; 799 u8 bgi_rate; 800 u8 cc_rate; 801 u8 recon_rate; 802 u8 cache_flush_interval; 803 u8 spinup_drv_count; 804 u8 spinup_delay; 805 u8 cluster_enable; 806 u8 coercion_mode; 807 u8 alarm_enable; 808 u8 disable_auto_rebuild; 809 u8 disable_battery_warn; 810 u8 ecc_bucket_size; 811 u16 ecc_bucket_leak_rate; 812 u8 restore_hotspare_on_insertion; 813 u8 expose_encl_devices; 814 u8 maintainPdFailHistory; 815 u8 disallowHostRequestReordering; 816 u8 abortCCOnError; 817 u8 loadBalanceMode; 818 u8 disableAutoDetectBackplane; 819 820 u8 snapVDSpace; 821 822 /* 823 * Add properties that can be controlled by 824 * a bit in the following structure. 825 */ 826 struct { 827 #if defined(__BIG_ENDIAN_BITFIELD) 828 u32 reserved:18; 829 u32 enableJBOD:1; 830 u32 disableSpinDownHS:1; 831 u32 allowBootWithPinnedCache:1; 832 u32 disableOnlineCtrlReset:1; 833 u32 enableSecretKeyControl:1; 834 u32 autoEnhancedImport:1; 835 u32 enableSpinDownUnconfigured:1; 836 u32 SSDPatrolReadEnabled:1; 837 u32 SSDSMARTerEnabled:1; 838 u32 disableNCQ:1; 839 u32 useFdeOnly:1; 840 u32 prCorrectUnconfiguredAreas:1; 841 u32 SMARTerEnabled:1; 842 u32 copyBackDisabled:1; 843 #else 844 u32 copyBackDisabled:1; 845 u32 SMARTerEnabled:1; 846 u32 prCorrectUnconfiguredAreas:1; 847 u32 useFdeOnly:1; 848 u32 disableNCQ:1; 849 u32 SSDSMARTerEnabled:1; 850 u32 SSDPatrolReadEnabled:1; 851 u32 enableSpinDownUnconfigured:1; 852 u32 autoEnhancedImport:1; 853 u32 enableSecretKeyControl:1; 854 u32 disableOnlineCtrlReset:1; 855 u32 allowBootWithPinnedCache:1; 856 u32 disableSpinDownHS:1; 857 u32 enableJBOD:1; 858 u32 reserved:18; 859 #endif 860 } OnOffProperties; 861 u8 autoSnapVDSpace; 862 u8 viewSpace; 863 __le16 spinDownTime; 864 u8 reserved[24]; 865 } __packed; 866 867 /* 868 * SAS controller information 869 */ 870 struct megasas_ctrl_info { 871 872 /* 873 * PCI device information 874 */ 875 struct { 876 877 __le16 vendor_id; 878 __le16 device_id; 879 __le16 sub_vendor_id; 880 __le16 sub_device_id; 881 u8 reserved[24]; 882 883 } __attribute__ ((packed)) pci; 884 885 /* 886 * Host interface information 887 */ 888 struct { 889 890 u8 PCIX:1; 891 u8 PCIE:1; 892 u8 iSCSI:1; 893 u8 SAS_3G:1; 894 u8 SRIOV:1; 895 u8 reserved_0:3; 896 u8 reserved_1[6]; 897 u8 port_count; 898 u64 port_addr[8]; 899 900 } __attribute__ ((packed)) host_interface; 901 902 /* 903 * Device (backend) interface information 904 */ 905 struct { 906 907 u8 SPI:1; 908 u8 SAS_3G:1; 909 u8 SATA_1_5G:1; 910 u8 SATA_3G:1; 911 u8 reserved_0:4; 912 u8 reserved_1[6]; 913 u8 port_count; 914 u64 port_addr[8]; 915 916 } __attribute__ ((packed)) device_interface; 917 918 /* 919 * List of components residing in flash. All str are null terminated 920 */ 921 __le32 image_check_word; 922 __le32 image_component_count; 923 924 struct { 925 926 char name[8]; 927 char version[32]; 928 char build_date[16]; 929 char built_time[16]; 930 931 } __attribute__ ((packed)) image_component[8]; 932 933 /* 934 * List of flash components that have been flashed on the card, but 935 * are not in use, pending reset of the adapter. This list will be 936 * empty if a flash operation has not occurred. All stings are null 937 * terminated 938 */ 939 __le32 pending_image_component_count; 940 941 struct { 942 943 char name[8]; 944 char version[32]; 945 char build_date[16]; 946 char build_time[16]; 947 948 } __attribute__ ((packed)) pending_image_component[8]; 949 950 u8 max_arms; 951 u8 max_spans; 952 u8 max_arrays; 953 u8 max_lds; 954 955 char product_name[80]; 956 char serial_no[32]; 957 958 /* 959 * Other physical/controller/operation information. Indicates the 960 * presence of the hardware 961 */ 962 struct { 963 964 u32 bbu:1; 965 u32 alarm:1; 966 u32 nvram:1; 967 u32 uart:1; 968 u32 reserved:28; 969 970 } __attribute__ ((packed)) hw_present; 971 972 __le32 current_fw_time; 973 974 /* 975 * Maximum data transfer sizes 976 */ 977 __le16 max_concurrent_cmds; 978 __le16 max_sge_count; 979 __le32 max_request_size; 980 981 /* 982 * Logical and physical device counts 983 */ 984 __le16 ld_present_count; 985 __le16 ld_degraded_count; 986 __le16 ld_offline_count; 987 988 __le16 pd_present_count; 989 __le16 pd_disk_present_count; 990 __le16 pd_disk_pred_failure_count; 991 __le16 pd_disk_failed_count; 992 993 /* 994 * Memory size information 995 */ 996 __le16 nvram_size; 997 __le16 memory_size; 998 __le16 flash_size; 999 1000 /* 1001 * Error counters 1002 */ 1003 __le16 mem_correctable_error_count; 1004 __le16 mem_uncorrectable_error_count; 1005 1006 /* 1007 * Cluster information 1008 */ 1009 u8 cluster_permitted; 1010 u8 cluster_active; 1011 1012 /* 1013 * Additional max data transfer sizes 1014 */ 1015 __le16 max_strips_per_io; 1016 1017 /* 1018 * Controller capabilities structures 1019 */ 1020 struct { 1021 1022 u32 raid_level_0:1; 1023 u32 raid_level_1:1; 1024 u32 raid_level_5:1; 1025 u32 raid_level_1E:1; 1026 u32 raid_level_6:1; 1027 u32 reserved:27; 1028 1029 } __attribute__ ((packed)) raid_levels; 1030 1031 struct { 1032 1033 u32 rbld_rate:1; 1034 u32 cc_rate:1; 1035 u32 bgi_rate:1; 1036 u32 recon_rate:1; 1037 u32 patrol_rate:1; 1038 u32 alarm_control:1; 1039 u32 cluster_supported:1; 1040 u32 bbu:1; 1041 u32 spanning_allowed:1; 1042 u32 dedicated_hotspares:1; 1043 u32 revertible_hotspares:1; 1044 u32 foreign_config_import:1; 1045 u32 self_diagnostic:1; 1046 u32 mixed_redundancy_arr:1; 1047 u32 global_hot_spares:1; 1048 u32 reserved:17; 1049 1050 } __attribute__ ((packed)) adapter_operations; 1051 1052 struct { 1053 1054 u32 read_policy:1; 1055 u32 write_policy:1; 1056 u32 io_policy:1; 1057 u32 access_policy:1; 1058 u32 disk_cache_policy:1; 1059 u32 reserved:27; 1060 1061 } __attribute__ ((packed)) ld_operations; 1062 1063 struct { 1064 1065 u8 min; 1066 u8 max; 1067 u8 reserved[2]; 1068 1069 } __attribute__ ((packed)) stripe_sz_ops; 1070 1071 struct { 1072 1073 u32 force_online:1; 1074 u32 force_offline:1; 1075 u32 force_rebuild:1; 1076 u32 reserved:29; 1077 1078 } __attribute__ ((packed)) pd_operations; 1079 1080 struct { 1081 1082 u32 ctrl_supports_sas:1; 1083 u32 ctrl_supports_sata:1; 1084 u32 allow_mix_in_encl:1; 1085 u32 allow_mix_in_ld:1; 1086 u32 allow_sata_in_cluster:1; 1087 u32 reserved:27; 1088 1089 } __attribute__ ((packed)) pd_mix_support; 1090 1091 /* 1092 * Define ECC single-bit-error bucket information 1093 */ 1094 u8 ecc_bucket_count; 1095 u8 reserved_2[11]; 1096 1097 /* 1098 * Include the controller properties (changeable items) 1099 */ 1100 struct megasas_ctrl_prop properties; 1101 1102 /* 1103 * Define FW pkg version (set in envt v'bles on OEM basis) 1104 */ 1105 char package_version[0x60]; 1106 1107 1108 /* 1109 * If adapterOperations.supportMoreThan8Phys is set, 1110 * and deviceInterface.portCount is greater than 8, 1111 * SAS Addrs for first 8 ports shall be populated in 1112 * deviceInterface.portAddr, and the rest shall be 1113 * populated in deviceInterfacePortAddr2. 1114 */ 1115 __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1116 u8 reserved3[128]; /*6e0h */ 1117 1118 struct { /*760h */ 1119 u16 minPdRaidLevel_0:4; 1120 u16 maxPdRaidLevel_0:12; 1121 1122 u16 minPdRaidLevel_1:4; 1123 u16 maxPdRaidLevel_1:12; 1124 1125 u16 minPdRaidLevel_5:4; 1126 u16 maxPdRaidLevel_5:12; 1127 1128 u16 minPdRaidLevel_1E:4; 1129 u16 maxPdRaidLevel_1E:12; 1130 1131 u16 minPdRaidLevel_6:4; 1132 u16 maxPdRaidLevel_6:12; 1133 1134 u16 minPdRaidLevel_10:4; 1135 u16 maxPdRaidLevel_10:12; 1136 1137 u16 minPdRaidLevel_50:4; 1138 u16 maxPdRaidLevel_50:12; 1139 1140 u16 minPdRaidLevel_60:4; 1141 u16 maxPdRaidLevel_60:12; 1142 1143 u16 minPdRaidLevel_1E_RLQ0:4; 1144 u16 maxPdRaidLevel_1E_RLQ0:12; 1145 1146 u16 minPdRaidLevel_1E0_RLQ0:4; 1147 u16 maxPdRaidLevel_1E0_RLQ0:12; 1148 1149 u16 reserved[6]; 1150 } pdsForRaidLevels; 1151 1152 __le16 maxPds; /*780h */ 1153 __le16 maxDedHSPs; /*782h */ 1154 __le16 maxGlobalHSP; /*784h */ 1155 __le16 ddfSize; /*786h */ 1156 u8 maxLdsPerArray; /*788h */ 1157 u8 partitionsInDDF; /*789h */ 1158 u8 lockKeyBinding; /*78ah */ 1159 u8 maxPITsPerLd; /*78bh */ 1160 u8 maxViewsPerLd; /*78ch */ 1161 u8 maxTargetId; /*78dh */ 1162 __le16 maxBvlVdSize; /*78eh */ 1163 1164 __le16 maxConfigurableSSCSize; /*790h */ 1165 __le16 currentSSCsize; /*792h */ 1166 1167 char expanderFwVersion[12]; /*794h */ 1168 1169 __le16 PFKTrialTimeRemaining; /*7A0h */ 1170 1171 __le16 cacheMemorySize; /*7A2h */ 1172 1173 struct { /*7A4h */ 1174 #if defined(__BIG_ENDIAN_BITFIELD) 1175 u32 reserved:5; 1176 u32 activePassive:2; 1177 u32 supportConfigAutoBalance:1; 1178 u32 mpio:1; 1179 u32 supportDataLDonSSCArray:1; 1180 u32 supportPointInTimeProgress:1; 1181 u32 supportUnevenSpans:1; 1182 u32 dedicatedHotSparesLimited:1; 1183 u32 headlessMode:1; 1184 u32 supportEmulatedDrives:1; 1185 u32 supportResetNow:1; 1186 u32 realTimeScheduler:1; 1187 u32 supportSSDPatrolRead:1; 1188 u32 supportPerfTuning:1; 1189 u32 disableOnlinePFKChange:1; 1190 u32 supportJBOD:1; 1191 u32 supportBootTimePFKChange:1; 1192 u32 supportSetLinkSpeed:1; 1193 u32 supportEmergencySpares:1; 1194 u32 supportSuspendResumeBGops:1; 1195 u32 blockSSDWriteCacheChange:1; 1196 u32 supportShieldState:1; 1197 u32 supportLdBBMInfo:1; 1198 u32 supportLdPIType3:1; 1199 u32 supportLdPIType2:1; 1200 u32 supportLdPIType1:1; 1201 u32 supportPIcontroller:1; 1202 #else 1203 u32 supportPIcontroller:1; 1204 u32 supportLdPIType1:1; 1205 u32 supportLdPIType2:1; 1206 u32 supportLdPIType3:1; 1207 u32 supportLdBBMInfo:1; 1208 u32 supportShieldState:1; 1209 u32 blockSSDWriteCacheChange:1; 1210 u32 supportSuspendResumeBGops:1; 1211 u32 supportEmergencySpares:1; 1212 u32 supportSetLinkSpeed:1; 1213 u32 supportBootTimePFKChange:1; 1214 u32 supportJBOD:1; 1215 u32 disableOnlinePFKChange:1; 1216 u32 supportPerfTuning:1; 1217 u32 supportSSDPatrolRead:1; 1218 u32 realTimeScheduler:1; 1219 1220 u32 supportResetNow:1; 1221 u32 supportEmulatedDrives:1; 1222 u32 headlessMode:1; 1223 u32 dedicatedHotSparesLimited:1; 1224 1225 1226 u32 supportUnevenSpans:1; 1227 u32 supportPointInTimeProgress:1; 1228 u32 supportDataLDonSSCArray:1; 1229 u32 mpio:1; 1230 u32 supportConfigAutoBalance:1; 1231 u32 activePassive:2; 1232 u32 reserved:5; 1233 #endif 1234 } adapterOperations2; 1235 1236 u8 driverVersion[32]; /*7A8h */ 1237 u8 maxDAPdCountSpinup60; /*7C8h */ 1238 u8 temperatureROC; /*7C9h */ 1239 u8 temperatureCtrl; /*7CAh */ 1240 u8 reserved4; /*7CBh */ 1241 __le16 maxConfigurablePds; /*7CCh */ 1242 1243 1244 u8 reserved5[2]; /*0x7CDh */ 1245 1246 /* 1247 * HA cluster information 1248 */ 1249 struct { 1250 #if defined(__BIG_ENDIAN_BITFIELD) 1251 u32 reserved:25; 1252 u32 passive:1; 1253 u32 premiumFeatureMismatch:1; 1254 u32 ctrlPropIncompatible:1; 1255 u32 fwVersionMismatch:1; 1256 u32 hwIncompatible:1; 1257 u32 peerIsIncompatible:1; 1258 u32 peerIsPresent:1; 1259 #else 1260 u32 peerIsPresent:1; 1261 u32 peerIsIncompatible:1; 1262 u32 hwIncompatible:1; 1263 u32 fwVersionMismatch:1; 1264 u32 ctrlPropIncompatible:1; 1265 u32 premiumFeatureMismatch:1; 1266 u32 passive:1; 1267 u32 reserved:25; 1268 #endif 1269 } cluster; 1270 1271 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1272 struct { 1273 u8 maxVFsSupported; /*0x7E4*/ 1274 u8 numVFsEnabled; /*0x7E5*/ 1275 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1276 u8 reserved; /*0x7E7*/ 1277 } iov; 1278 1279 struct { 1280 #if defined(__BIG_ENDIAN_BITFIELD) 1281 u32 reserved:7; 1282 u32 useSeqNumJbodFP:1; 1283 u32 supportExtendedSSCSize:1; 1284 u32 supportDiskCacheSettingForSysPDs:1; 1285 u32 supportCPLDUpdate:1; 1286 u32 supportTTYLogCompression:1; 1287 u32 discardCacheDuringLDDelete:1; 1288 u32 supportSecurityonJBOD:1; 1289 u32 supportCacheBypassModes:1; 1290 u32 supportDisableSESMonitoring:1; 1291 u32 supportForceFlash:1; 1292 u32 supportNVDRAM:1; 1293 u32 supportDrvActivityLEDSetting:1; 1294 u32 supportAllowedOpsforDrvRemoval:1; 1295 u32 supportHOQRebuild:1; 1296 u32 supportForceTo512e:1; 1297 u32 supportNVCacheErase:1; 1298 u32 supportDebugQueue:1; 1299 u32 supportSwZone:1; 1300 u32 supportCrashDump:1; 1301 u32 supportMaxExtLDs:1; 1302 u32 supportT10RebuildAssist:1; 1303 u32 supportDisableImmediateIO:1; 1304 u32 supportThermalPollInterval:1; 1305 u32 supportPersonalityChange:2; 1306 #else 1307 u32 supportPersonalityChange:2; 1308 u32 supportThermalPollInterval:1; 1309 u32 supportDisableImmediateIO:1; 1310 u32 supportT10RebuildAssist:1; 1311 u32 supportMaxExtLDs:1; 1312 u32 supportCrashDump:1; 1313 u32 supportSwZone:1; 1314 u32 supportDebugQueue:1; 1315 u32 supportNVCacheErase:1; 1316 u32 supportForceTo512e:1; 1317 u32 supportHOQRebuild:1; 1318 u32 supportAllowedOpsforDrvRemoval:1; 1319 u32 supportDrvActivityLEDSetting:1; 1320 u32 supportNVDRAM:1; 1321 u32 supportForceFlash:1; 1322 u32 supportDisableSESMonitoring:1; 1323 u32 supportCacheBypassModes:1; 1324 u32 supportSecurityonJBOD:1; 1325 u32 discardCacheDuringLDDelete:1; 1326 u32 supportTTYLogCompression:1; 1327 u32 supportCPLDUpdate:1; 1328 u32 supportDiskCacheSettingForSysPDs:1; 1329 u32 supportExtendedSSCSize:1; 1330 u32 useSeqNumJbodFP:1; 1331 u32 reserved:7; 1332 #endif 1333 } adapterOperations3; 1334 1335 struct { 1336 #if defined(__BIG_ENDIAN_BITFIELD) 1337 u8 reserved:7; 1338 /* Indicates whether the CPLD image is part of 1339 * the package and stored in flash 1340 */ 1341 u8 cpld_in_flash:1; 1342 #else 1343 u8 cpld_in_flash:1; 1344 u8 reserved:7; 1345 #endif 1346 u8 reserved1[3]; 1347 /* Null terminated string. Has the version 1348 * information if cpld_in_flash = FALSE 1349 */ 1350 u8 userCodeDefinition[12]; 1351 } cpld; /* Valid only if upgradableCPLD is TRUE */ 1352 1353 struct { 1354 #if defined(__BIG_ENDIAN_BITFIELD) 1355 u16 reserved:8; 1356 u16 fw_swaps_bbu_vpd_info:1; 1357 u16 support_pd_map_target_id:1; 1358 u16 support_ses_ctrl_in_multipathcfg:1; 1359 u16 image_upload_supported:1; 1360 u16 support_encrypted_mfc:1; 1361 u16 supported_enc_algo:1; 1362 u16 support_ibutton_less:1; 1363 u16 ctrl_info_ext_supported:1; 1364 #else 1365 1366 u16 ctrl_info_ext_supported:1; 1367 u16 support_ibutton_less:1; 1368 u16 supported_enc_algo:1; 1369 u16 support_encrypted_mfc:1; 1370 u16 image_upload_supported:1; 1371 /* FW supports LUN based association and target port based */ 1372 u16 support_ses_ctrl_in_multipathcfg:1; 1373 /* association for the SES device connected in multipath mode */ 1374 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */ 1375 u16 support_pd_map_target_id:1; 1376 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to 1377 * provide the data in little endian order 1378 */ 1379 u16 fw_swaps_bbu_vpd_info:1; 1380 u16 reserved:8; 1381 #endif 1382 } adapter_operations4; 1383 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */ 1384 } __packed; 1385 1386 /* 1387 * =============================== 1388 * MegaRAID SAS driver definitions 1389 * =============================== 1390 */ 1391 #define MEGASAS_MAX_PD_CHANNELS 2 1392 #define MEGASAS_MAX_LD_CHANNELS 2 1393 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1394 MEGASAS_MAX_LD_CHANNELS) 1395 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1396 #define MEGASAS_DEFAULT_INIT_ID -1 1397 #define MEGASAS_MAX_LUN 8 1398 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 1399 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 1400 MEGASAS_MAX_DEV_PER_CHANNEL) 1401 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1402 MEGASAS_MAX_DEV_PER_CHANNEL) 1403 1404 #define MEGASAS_MAX_SECTORS (2*1024) 1405 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1406 #define MEGASAS_DBG_LVL 1 1407 1408 #define MEGASAS_FW_BUSY 1 1409 1410 /* Driver's internal Logging levels*/ 1411 #define OCR_LOGS (1 << 0) 1412 1413 #define SCAN_PD_CHANNEL 0x1 1414 #define SCAN_VD_CHANNEL 0x2 1415 1416 #define MEGASAS_KDUMP_QUEUE_DEPTH 100 1417 #define MR_LARGE_IO_MIN_SIZE (32 * 1024) 1418 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4 1419 1420 enum MR_SCSI_CMD_TYPE { 1421 READ_WRITE_LDIO = 0, 1422 NON_READ_WRITE_LDIO = 1, 1423 READ_WRITE_SYSPDIO = 2, 1424 NON_READ_WRITE_SYSPDIO = 3, 1425 }; 1426 1427 enum DCMD_TIMEOUT_ACTION { 1428 INITIATE_OCR = 0, 1429 KILL_ADAPTER = 1, 1430 IGNORE_TIMEOUT = 2, 1431 }; 1432 1433 enum FW_BOOT_CONTEXT { 1434 PROBE_CONTEXT = 0, 1435 OCR_CONTEXT = 1, 1436 }; 1437 1438 /* Frame Type */ 1439 #define IO_FRAME 0 1440 #define PTHRU_FRAME 1 1441 1442 /* 1443 * When SCSI mid-layer calls driver's reset routine, driver waits for 1444 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1445 * that the driver cannot _actually_ abort or reset pending commands. While 1446 * it is waiting for the commands to complete, it prints a diagnostic message 1447 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1448 */ 1449 #define MEGASAS_RESET_WAIT_TIME 180 1450 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1451 #define MEGASAS_RESET_NOTICE_INTERVAL 5 1452 #define MEGASAS_IOCTL_CMD 0 1453 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1454 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1455 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1456 /* 1457 * FW reports the maximum of number of commands that it can accept (maximum 1458 * commands that can be outstanding) at any time. The driver must report a 1459 * lower number to the mid layer because it can issue a few internal commands 1460 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1461 * is shown below 1462 */ 1463 #define MEGASAS_INT_CMDS 32 1464 #define MEGASAS_SKINNY_INT_CMDS 5 1465 #define MEGASAS_FUSION_INTERNAL_CMDS 8 1466 #define MEGASAS_FUSION_IOCTL_CMDS 3 1467 #define MEGASAS_MFI_IOCTL_CMDS 27 1468 1469 #define MEGASAS_MAX_MSIX_QUEUES 128 1470 /* 1471 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1472 * SGLs based on the size of dma_addr_t 1473 */ 1474 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1475 1476 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1477 1478 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1479 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1480 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1481 1482 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1483 #define MFI_POLL_TIMEOUT_SECS 60 1484 #define MFI_IO_TIMEOUT_SECS 180 1485 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1486 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1487 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1488 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1489 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1490 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1491 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1492 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1493 1494 #define MFI_1068_PCSR_OFFSET 0x84 1495 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1496 #define MFI_1068_FW_READY 0xDDDD0000 1497 1498 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1499 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1500 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1501 #define MR_MAX_MSIX_REG_ARRAY 16 1502 #define MR_RDPQ_MODE_OFFSET 0X00800000 1503 1504 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1505 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1506 #define MR_MIN_MAP_SIZE 0x10000 1507 /* 64k */ 1508 1509 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 1510 1511 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25) 1512 1513 enum MR_ADAPTER_TYPE { 1514 MFI_SERIES = 1, 1515 THUNDERBOLT_SERIES = 2, 1516 INVADER_SERIES = 3, 1517 VENTURA_SERIES = 4, 1518 }; 1519 1520 /* 1521 * register set for both 1068 and 1078 controllers 1522 * structure extended for 1078 registers 1523 */ 1524 1525 struct megasas_register_set { 1526 u32 doorbell; /*0000h*/ 1527 u32 fusion_seq_offset; /*0004h*/ 1528 u32 fusion_host_diag; /*0008h*/ 1529 u32 reserved_01; /*000Ch*/ 1530 1531 u32 inbound_msg_0; /*0010h*/ 1532 u32 inbound_msg_1; /*0014h*/ 1533 u32 outbound_msg_0; /*0018h*/ 1534 u32 outbound_msg_1; /*001Ch*/ 1535 1536 u32 inbound_doorbell; /*0020h*/ 1537 u32 inbound_intr_status; /*0024h*/ 1538 u32 inbound_intr_mask; /*0028h*/ 1539 1540 u32 outbound_doorbell; /*002Ch*/ 1541 u32 outbound_intr_status; /*0030h*/ 1542 u32 outbound_intr_mask; /*0034h*/ 1543 1544 u32 reserved_1[2]; /*0038h*/ 1545 1546 u32 inbound_queue_port; /*0040h*/ 1547 u32 outbound_queue_port; /*0044h*/ 1548 1549 u32 reserved_2[9]; /*0048h*/ 1550 u32 reply_post_host_index; /*006Ch*/ 1551 u32 reserved_2_2[12]; /*0070h*/ 1552 1553 u32 outbound_doorbell_clear; /*00A0h*/ 1554 1555 u32 reserved_3[3]; /*00A4h*/ 1556 1557 u32 outbound_scratch_pad ; /*00B0h*/ 1558 u32 outbound_scratch_pad_2; /*00B4h*/ 1559 u32 outbound_scratch_pad_3; /*00B8h*/ 1560 u32 outbound_scratch_pad_4; /*00BCh*/ 1561 1562 1563 u32 inbound_low_queue_port ; /*00C0h*/ 1564 1565 u32 inbound_high_queue_port ; /*00C4h*/ 1566 1567 u32 inbound_single_queue_port; /*00C8h*/ 1568 u32 res_6[11]; /*CCh*/ 1569 u32 host_diag; 1570 u32 seq_offset; 1571 u32 index_registers[807]; /*00CCh*/ 1572 } __attribute__ ((packed)); 1573 1574 struct megasas_sge32 { 1575 1576 __le32 phys_addr; 1577 __le32 length; 1578 1579 } __attribute__ ((packed)); 1580 1581 struct megasas_sge64 { 1582 1583 __le64 phys_addr; 1584 __le32 length; 1585 1586 } __attribute__ ((packed)); 1587 1588 struct megasas_sge_skinny { 1589 __le64 phys_addr; 1590 __le32 length; 1591 __le32 flag; 1592 } __packed; 1593 1594 union megasas_sgl { 1595 1596 struct megasas_sge32 sge32[1]; 1597 struct megasas_sge64 sge64[1]; 1598 struct megasas_sge_skinny sge_skinny[1]; 1599 1600 } __attribute__ ((packed)); 1601 1602 struct megasas_header { 1603 1604 u8 cmd; /*00h */ 1605 u8 sense_len; /*01h */ 1606 u8 cmd_status; /*02h */ 1607 u8 scsi_status; /*03h */ 1608 1609 u8 target_id; /*04h */ 1610 u8 lun; /*05h */ 1611 u8 cdb_len; /*06h */ 1612 u8 sge_count; /*07h */ 1613 1614 __le32 context; /*08h */ 1615 __le32 pad_0; /*0Ch */ 1616 1617 __le16 flags; /*10h */ 1618 __le16 timeout; /*12h */ 1619 __le32 data_xferlen; /*14h */ 1620 1621 } __attribute__ ((packed)); 1622 1623 union megasas_sgl_frame { 1624 1625 struct megasas_sge32 sge32[8]; 1626 struct megasas_sge64 sge64[5]; 1627 1628 } __attribute__ ((packed)); 1629 1630 typedef union _MFI_CAPABILITIES { 1631 struct { 1632 #if defined(__BIG_ENDIAN_BITFIELD) 1633 u32 reserved:18; 1634 u32 support_64bit_mode:1; 1635 u32 support_pd_map_target_id:1; 1636 u32 support_qd_throttling:1; 1637 u32 support_fp_rlbypass:1; 1638 u32 support_vfid_in_ioframe:1; 1639 u32 support_ext_io_size:1; 1640 u32 support_ext_queue_depth:1; 1641 u32 security_protocol_cmds_fw:1; 1642 u32 support_core_affinity:1; 1643 u32 support_ndrive_r1_lb:1; 1644 u32 support_max_255lds:1; 1645 u32 support_fastpath_wb:1; 1646 u32 support_additional_msix:1; 1647 u32 support_fp_remote_lun:1; 1648 #else 1649 u32 support_fp_remote_lun:1; 1650 u32 support_additional_msix:1; 1651 u32 support_fastpath_wb:1; 1652 u32 support_max_255lds:1; 1653 u32 support_ndrive_r1_lb:1; 1654 u32 support_core_affinity:1; 1655 u32 security_protocol_cmds_fw:1; 1656 u32 support_ext_queue_depth:1; 1657 u32 support_ext_io_size:1; 1658 u32 support_vfid_in_ioframe:1; 1659 u32 support_fp_rlbypass:1; 1660 u32 support_qd_throttling:1; 1661 u32 support_pd_map_target_id:1; 1662 u32 support_64bit_mode:1; 1663 u32 reserved:18; 1664 #endif 1665 } mfi_capabilities; 1666 __le32 reg; 1667 } MFI_CAPABILITIES; 1668 1669 struct megasas_init_frame { 1670 1671 u8 cmd; /*00h */ 1672 u8 reserved_0; /*01h */ 1673 u8 cmd_status; /*02h */ 1674 1675 u8 reserved_1; /*03h */ 1676 MFI_CAPABILITIES driver_operations; /*04h*/ 1677 1678 __le32 context; /*08h */ 1679 __le32 pad_0; /*0Ch */ 1680 1681 __le16 flags; /*10h */ 1682 __le16 reserved_3; /*12h */ 1683 __le32 data_xfer_len; /*14h */ 1684 1685 __le32 queue_info_new_phys_addr_lo; /*18h */ 1686 __le32 queue_info_new_phys_addr_hi; /*1Ch */ 1687 __le32 queue_info_old_phys_addr_lo; /*20h */ 1688 __le32 queue_info_old_phys_addr_hi; /*24h */ 1689 __le32 reserved_4[2]; /*28h */ 1690 __le32 system_info_lo; /*30h */ 1691 __le32 system_info_hi; /*34h */ 1692 __le32 reserved_5[2]; /*38h */ 1693 1694 } __attribute__ ((packed)); 1695 1696 struct megasas_init_queue_info { 1697 1698 __le32 init_flags; /*00h */ 1699 __le32 reply_queue_entries; /*04h */ 1700 1701 __le32 reply_queue_start_phys_addr_lo; /*08h */ 1702 __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 1703 __le32 producer_index_phys_addr_lo; /*10h */ 1704 __le32 producer_index_phys_addr_hi; /*14h */ 1705 __le32 consumer_index_phys_addr_lo; /*18h */ 1706 __le32 consumer_index_phys_addr_hi; /*1Ch */ 1707 1708 } __attribute__ ((packed)); 1709 1710 struct megasas_io_frame { 1711 1712 u8 cmd; /*00h */ 1713 u8 sense_len; /*01h */ 1714 u8 cmd_status; /*02h */ 1715 u8 scsi_status; /*03h */ 1716 1717 u8 target_id; /*04h */ 1718 u8 access_byte; /*05h */ 1719 u8 reserved_0; /*06h */ 1720 u8 sge_count; /*07h */ 1721 1722 __le32 context; /*08h */ 1723 __le32 pad_0; /*0Ch */ 1724 1725 __le16 flags; /*10h */ 1726 __le16 timeout; /*12h */ 1727 __le32 lba_count; /*14h */ 1728 1729 __le32 sense_buf_phys_addr_lo; /*18h */ 1730 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1731 1732 __le32 start_lba_lo; /*20h */ 1733 __le32 start_lba_hi; /*24h */ 1734 1735 union megasas_sgl sgl; /*28h */ 1736 1737 } __attribute__ ((packed)); 1738 1739 struct megasas_pthru_frame { 1740 1741 u8 cmd; /*00h */ 1742 u8 sense_len; /*01h */ 1743 u8 cmd_status; /*02h */ 1744 u8 scsi_status; /*03h */ 1745 1746 u8 target_id; /*04h */ 1747 u8 lun; /*05h */ 1748 u8 cdb_len; /*06h */ 1749 u8 sge_count; /*07h */ 1750 1751 __le32 context; /*08h */ 1752 __le32 pad_0; /*0Ch */ 1753 1754 __le16 flags; /*10h */ 1755 __le16 timeout; /*12h */ 1756 __le32 data_xfer_len; /*14h */ 1757 1758 __le32 sense_buf_phys_addr_lo; /*18h */ 1759 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1760 1761 u8 cdb[16]; /*20h */ 1762 union megasas_sgl sgl; /*30h */ 1763 1764 } __attribute__ ((packed)); 1765 1766 struct megasas_dcmd_frame { 1767 1768 u8 cmd; /*00h */ 1769 u8 reserved_0; /*01h */ 1770 u8 cmd_status; /*02h */ 1771 u8 reserved_1[4]; /*03h */ 1772 u8 sge_count; /*07h */ 1773 1774 __le32 context; /*08h */ 1775 __le32 pad_0; /*0Ch */ 1776 1777 __le16 flags; /*10h */ 1778 __le16 timeout; /*12h */ 1779 1780 __le32 data_xfer_len; /*14h */ 1781 __le32 opcode; /*18h */ 1782 1783 union { /*1Ch */ 1784 u8 b[12]; 1785 __le16 s[6]; 1786 __le32 w[3]; 1787 } mbox; 1788 1789 union megasas_sgl sgl; /*28h */ 1790 1791 } __attribute__ ((packed)); 1792 1793 struct megasas_abort_frame { 1794 1795 u8 cmd; /*00h */ 1796 u8 reserved_0; /*01h */ 1797 u8 cmd_status; /*02h */ 1798 1799 u8 reserved_1; /*03h */ 1800 __le32 reserved_2; /*04h */ 1801 1802 __le32 context; /*08h */ 1803 __le32 pad_0; /*0Ch */ 1804 1805 __le16 flags; /*10h */ 1806 __le16 reserved_3; /*12h */ 1807 __le32 reserved_4; /*14h */ 1808 1809 __le32 abort_context; /*18h */ 1810 __le32 pad_1; /*1Ch */ 1811 1812 __le32 abort_mfi_phys_addr_lo; /*20h */ 1813 __le32 abort_mfi_phys_addr_hi; /*24h */ 1814 1815 __le32 reserved_5[6]; /*28h */ 1816 1817 } __attribute__ ((packed)); 1818 1819 struct megasas_smp_frame { 1820 1821 u8 cmd; /*00h */ 1822 u8 reserved_1; /*01h */ 1823 u8 cmd_status; /*02h */ 1824 u8 connection_status; /*03h */ 1825 1826 u8 reserved_2[3]; /*04h */ 1827 u8 sge_count; /*07h */ 1828 1829 __le32 context; /*08h */ 1830 __le32 pad_0; /*0Ch */ 1831 1832 __le16 flags; /*10h */ 1833 __le16 timeout; /*12h */ 1834 1835 __le32 data_xfer_len; /*14h */ 1836 __le64 sas_addr; /*18h */ 1837 1838 union { 1839 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1840 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1841 } sgl; 1842 1843 } __attribute__ ((packed)); 1844 1845 struct megasas_stp_frame { 1846 1847 u8 cmd; /*00h */ 1848 u8 reserved_1; /*01h */ 1849 u8 cmd_status; /*02h */ 1850 u8 reserved_2; /*03h */ 1851 1852 u8 target_id; /*04h */ 1853 u8 reserved_3[2]; /*05h */ 1854 u8 sge_count; /*07h */ 1855 1856 __le32 context; /*08h */ 1857 __le32 pad_0; /*0Ch */ 1858 1859 __le16 flags; /*10h */ 1860 __le16 timeout; /*12h */ 1861 1862 __le32 data_xfer_len; /*14h */ 1863 1864 __le16 fis[10]; /*18h */ 1865 __le32 stp_flags; 1866 1867 union { 1868 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1869 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1870 } sgl; 1871 1872 } __attribute__ ((packed)); 1873 1874 union megasas_frame { 1875 1876 struct megasas_header hdr; 1877 struct megasas_init_frame init; 1878 struct megasas_io_frame io; 1879 struct megasas_pthru_frame pthru; 1880 struct megasas_dcmd_frame dcmd; 1881 struct megasas_abort_frame abort; 1882 struct megasas_smp_frame smp; 1883 struct megasas_stp_frame stp; 1884 1885 u8 raw_bytes[64]; 1886 }; 1887 1888 /** 1889 * struct MR_PRIV_DEVICE - sdev private hostdata 1890 * @is_tm_capable: firmware managed tm_capable flag 1891 * @tm_busy: TM request is in progress 1892 */ 1893 struct MR_PRIV_DEVICE { 1894 bool is_tm_capable; 1895 bool tm_busy; 1896 atomic_t r1_ldio_hint; 1897 u8 interface_type; 1898 }; 1899 struct megasas_cmd; 1900 1901 union megasas_evt_class_locale { 1902 1903 struct { 1904 #ifndef __BIG_ENDIAN_BITFIELD 1905 u16 locale; 1906 u8 reserved; 1907 s8 class; 1908 #else 1909 s8 class; 1910 u8 reserved; 1911 u16 locale; 1912 #endif 1913 } __attribute__ ((packed)) members; 1914 1915 u32 word; 1916 1917 } __attribute__ ((packed)); 1918 1919 struct megasas_evt_log_info { 1920 __le32 newest_seq_num; 1921 __le32 oldest_seq_num; 1922 __le32 clear_seq_num; 1923 __le32 shutdown_seq_num; 1924 __le32 boot_seq_num; 1925 1926 } __attribute__ ((packed)); 1927 1928 struct megasas_progress { 1929 1930 __le16 progress; 1931 __le16 elapsed_seconds; 1932 1933 } __attribute__ ((packed)); 1934 1935 struct megasas_evtarg_ld { 1936 1937 u16 target_id; 1938 u8 ld_index; 1939 u8 reserved; 1940 1941 } __attribute__ ((packed)); 1942 1943 struct megasas_evtarg_pd { 1944 u16 device_id; 1945 u8 encl_index; 1946 u8 slot_number; 1947 1948 } __attribute__ ((packed)); 1949 1950 struct megasas_evt_detail { 1951 1952 __le32 seq_num; 1953 __le32 time_stamp; 1954 __le32 code; 1955 union megasas_evt_class_locale cl; 1956 u8 arg_type; 1957 u8 reserved1[15]; 1958 1959 union { 1960 struct { 1961 struct megasas_evtarg_pd pd; 1962 u8 cdb_length; 1963 u8 sense_length; 1964 u8 reserved[2]; 1965 u8 cdb[16]; 1966 u8 sense[64]; 1967 } __attribute__ ((packed)) cdbSense; 1968 1969 struct megasas_evtarg_ld ld; 1970 1971 struct { 1972 struct megasas_evtarg_ld ld; 1973 __le64 count; 1974 } __attribute__ ((packed)) ld_count; 1975 1976 struct { 1977 __le64 lba; 1978 struct megasas_evtarg_ld ld; 1979 } __attribute__ ((packed)) ld_lba; 1980 1981 struct { 1982 struct megasas_evtarg_ld ld; 1983 __le32 prevOwner; 1984 __le32 newOwner; 1985 } __attribute__ ((packed)) ld_owner; 1986 1987 struct { 1988 u64 ld_lba; 1989 u64 pd_lba; 1990 struct megasas_evtarg_ld ld; 1991 struct megasas_evtarg_pd pd; 1992 } __attribute__ ((packed)) ld_lba_pd_lba; 1993 1994 struct { 1995 struct megasas_evtarg_ld ld; 1996 struct megasas_progress prog; 1997 } __attribute__ ((packed)) ld_prog; 1998 1999 struct { 2000 struct megasas_evtarg_ld ld; 2001 u32 prev_state; 2002 u32 new_state; 2003 } __attribute__ ((packed)) ld_state; 2004 2005 struct { 2006 u64 strip; 2007 struct megasas_evtarg_ld ld; 2008 } __attribute__ ((packed)) ld_strip; 2009 2010 struct megasas_evtarg_pd pd; 2011 2012 struct { 2013 struct megasas_evtarg_pd pd; 2014 u32 err; 2015 } __attribute__ ((packed)) pd_err; 2016 2017 struct { 2018 u64 lba; 2019 struct megasas_evtarg_pd pd; 2020 } __attribute__ ((packed)) pd_lba; 2021 2022 struct { 2023 u64 lba; 2024 struct megasas_evtarg_pd pd; 2025 struct megasas_evtarg_ld ld; 2026 } __attribute__ ((packed)) pd_lba_ld; 2027 2028 struct { 2029 struct megasas_evtarg_pd pd; 2030 struct megasas_progress prog; 2031 } __attribute__ ((packed)) pd_prog; 2032 2033 struct { 2034 struct megasas_evtarg_pd pd; 2035 u32 prevState; 2036 u32 newState; 2037 } __attribute__ ((packed)) pd_state; 2038 2039 struct { 2040 u16 vendorId; 2041 __le16 deviceId; 2042 u16 subVendorId; 2043 u16 subDeviceId; 2044 } __attribute__ ((packed)) pci; 2045 2046 u32 rate; 2047 char str[96]; 2048 2049 struct { 2050 u32 rtc; 2051 u32 elapsedSeconds; 2052 } __attribute__ ((packed)) time; 2053 2054 struct { 2055 u32 ecar; 2056 u32 elog; 2057 char str[64]; 2058 } __attribute__ ((packed)) ecc; 2059 2060 u8 b[96]; 2061 __le16 s[48]; 2062 __le32 w[24]; 2063 __le64 d[12]; 2064 } args; 2065 2066 char description[128]; 2067 2068 } __attribute__ ((packed)); 2069 2070 struct megasas_aen_event { 2071 struct delayed_work hotplug_work; 2072 struct megasas_instance *instance; 2073 }; 2074 2075 struct megasas_irq_context { 2076 struct megasas_instance *instance; 2077 u32 MSIxIndex; 2078 }; 2079 2080 struct MR_DRV_SYSTEM_INFO { 2081 u8 infoVersion; 2082 u8 systemIdLength; 2083 u16 reserved0; 2084 u8 systemId[64]; 2085 u8 reserved[1980]; 2086 }; 2087 2088 enum MR_PD_TYPE { 2089 UNKNOWN_DRIVE = 0, 2090 PARALLEL_SCSI = 1, 2091 SAS_PD = 2, 2092 SATA_PD = 3, 2093 FC_PD = 4, 2094 NVME_PD = 5, 2095 }; 2096 2097 /* JBOD Queue depth definitions */ 2098 #define MEGASAS_SATA_QD 32 2099 #define MEGASAS_SAS_QD 64 2100 #define MEGASAS_DEFAULT_PD_QD 64 2101 #define MEGASAS_NVME_QD 32 2102 2103 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 2104 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 2105 #define MR_DEFAULT_NVME_MDTS_KB 128 2106 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 2107 2108 struct megasas_instance { 2109 2110 __le32 *producer; 2111 dma_addr_t producer_h; 2112 __le32 *consumer; 2113 dma_addr_t consumer_h; 2114 struct MR_DRV_SYSTEM_INFO *system_info_buf; 2115 dma_addr_t system_info_h; 2116 struct MR_LD_VF_AFFILIATION *vf_affiliation; 2117 dma_addr_t vf_affiliation_h; 2118 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2119 dma_addr_t vf_affiliation_111_h; 2120 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2121 dma_addr_t hb_host_mem_h; 2122 struct MR_PD_INFO *pd_info; 2123 dma_addr_t pd_info_h; 2124 struct MR_TARGET_PROPERTIES *tgt_prop; 2125 dma_addr_t tgt_prop_h; 2126 2127 __le32 *reply_queue; 2128 dma_addr_t reply_queue_h; 2129 2130 u32 *crash_dump_buf; 2131 dma_addr_t crash_dump_h; 2132 2133 struct MR_PD_LIST *pd_list_buf; 2134 dma_addr_t pd_list_buf_h; 2135 2136 struct megasas_ctrl_info *ctrl_info_buf; 2137 dma_addr_t ctrl_info_buf_h; 2138 2139 struct MR_LD_LIST *ld_list_buf; 2140 dma_addr_t ld_list_buf_h; 2141 2142 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf; 2143 dma_addr_t ld_targetid_list_buf_h; 2144 2145 void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2146 unsigned int fw_crash_buffer_size; 2147 unsigned int fw_crash_state; 2148 unsigned int fw_crash_buffer_offset; 2149 u32 drv_buf_index; 2150 u32 drv_buf_alloc; 2151 u32 crash_dump_fw_support; 2152 u32 crash_dump_drv_support; 2153 u32 crash_dump_app_support; 2154 u32 secure_jbod_support; 2155 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ 2156 bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2157 spinlock_t crashdump_lock; 2158 2159 struct megasas_register_set __iomem *reg_set; 2160 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 2161 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2162 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2163 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2164 s8 init_id; 2165 2166 u16 max_num_sge; 2167 u16 max_fw_cmds; 2168 u16 max_mpt_cmds; 2169 u16 max_mfi_cmds; 2170 u16 max_scsi_cmds; 2171 u16 ldio_threshold; 2172 u16 cur_can_queue; 2173 u32 max_sectors_per_req; 2174 struct megasas_aen_event *ev; 2175 2176 struct megasas_cmd **cmd_list; 2177 struct list_head cmd_pool; 2178 /* used to sync fire the cmd to fw */ 2179 spinlock_t mfi_pool_lock; 2180 /* used to sync fire the cmd to fw */ 2181 spinlock_t hba_lock; 2182 /* used to synch producer, consumer ptrs in dpc */ 2183 spinlock_t stream_lock; 2184 spinlock_t completion_lock; 2185 struct dma_pool *frame_dma_pool; 2186 struct dma_pool *sense_dma_pool; 2187 2188 struct megasas_evt_detail *evt_detail; 2189 dma_addr_t evt_detail_h; 2190 struct megasas_cmd *aen_cmd; 2191 struct mutex hba_mutex; 2192 struct semaphore ioctl_sem; 2193 2194 struct Scsi_Host *host; 2195 2196 wait_queue_head_t int_cmd_wait_q; 2197 wait_queue_head_t abort_cmd_wait_q; 2198 2199 struct pci_dev *pdev; 2200 u32 unique_id; 2201 u32 fw_support_ieee; 2202 2203 atomic_t fw_outstanding; 2204 atomic_t ldio_outstanding; 2205 atomic_t fw_reset_no_pci_access; 2206 atomic_t ieee_sgl; 2207 atomic_t prp_sgl; 2208 atomic_t sge_holes_type1; 2209 atomic_t sge_holes_type2; 2210 atomic_t sge_holes_type3; 2211 2212 struct megasas_instance_template *instancet; 2213 struct tasklet_struct isr_tasklet; 2214 struct work_struct work_init; 2215 struct work_struct crash_init; 2216 2217 u8 flag; 2218 u8 unload; 2219 u8 flag_ieee; 2220 u8 issuepend_done; 2221 u8 disableOnlineCtrlReset; 2222 u8 UnevenSpanSupport; 2223 2224 u8 supportmax256vd; 2225 u8 pd_list_not_supported; 2226 u16 fw_supported_vd_count; 2227 u16 fw_supported_pd_count; 2228 2229 u16 drv_supported_vd_count; 2230 u16 drv_supported_pd_count; 2231 2232 atomic_t adprecovery; 2233 unsigned long last_time; 2234 u32 mfiStatus; 2235 u32 last_seq_num; 2236 2237 struct list_head internal_reset_pending_q; 2238 2239 /* Ptr to hba specific information */ 2240 void *ctrl_context; 2241 unsigned int msix_vectors; 2242 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 2243 u64 map_id; 2244 u64 pd_seq_map_id; 2245 struct megasas_cmd *map_update_cmd; 2246 struct megasas_cmd *jbod_seq_cmd; 2247 unsigned long bar; 2248 long reset_flags; 2249 struct mutex reset_mutex; 2250 struct timer_list sriov_heartbeat_timer; 2251 char skip_heartbeat_timer_del; 2252 u8 requestorId; 2253 char PlasmaFW111; 2254 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 2255 u8 peerIsPresent; 2256 u8 passive; 2257 u16 throttlequeuedepth; 2258 u8 mask_interrupts; 2259 u16 max_chain_frame_sz; 2260 u8 is_imr; 2261 u8 is_rdpq; 2262 bool dev_handle; 2263 bool fw_sync_cache_support; 2264 u32 mfi_frame_size; 2265 bool msix_combined; 2266 u16 max_raid_mapsize; 2267 /* preffered count to send as LDIO irrspective of FP capable.*/ 2268 u8 r1_ldio_hint_default; 2269 u32 nvme_page_size; 2270 u8 adapter_type; 2271 bool consistent_mask_64bit; 2272 }; 2273 struct MR_LD_VF_MAP { 2274 u32 size; 2275 union MR_LD_REF ref; 2276 u8 ldVfCount; 2277 u8 reserved[6]; 2278 u8 policy[1]; 2279 }; 2280 2281 struct MR_LD_VF_AFFILIATION { 2282 u32 size; 2283 u8 ldCount; 2284 u8 vfCount; 2285 u8 thisVf; 2286 u8 reserved[9]; 2287 struct MR_LD_VF_MAP map[1]; 2288 }; 2289 2290 /* Plasma 1.11 FW backward compatibility structures */ 2291 #define IOV_111_OFFSET 0x7CE 2292 #define MAX_VIRTUAL_FUNCTIONS 8 2293 #define MR_LD_ACCESS_HIDDEN 15 2294 2295 struct IOV_111 { 2296 u8 maxVFsSupported; 2297 u8 numVFsEnabled; 2298 u8 requestorId; 2299 u8 reserved[5]; 2300 }; 2301 2302 struct MR_LD_VF_MAP_111 { 2303 u8 targetId; 2304 u8 reserved[3]; 2305 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2306 }; 2307 2308 struct MR_LD_VF_AFFILIATION_111 { 2309 u8 vdCount; 2310 u8 vfCount; 2311 u8 thisVf; 2312 u8 reserved[5]; 2313 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2314 }; 2315 2316 struct MR_CTRL_HB_HOST_MEM { 2317 struct { 2318 u32 fwCounter; /* Firmware heart beat counter */ 2319 struct { 2320 u32 debugmode:1; /* 1=Firmware is in debug mode. 2321 Heart beat will not be updated. */ 2322 u32 reserved:31; 2323 } debug; 2324 u32 reserved_fw[6]; 2325 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2326 u32 reserved_driver[7]; 2327 } HB; 2328 u8 pad[0x400-0x40]; 2329 }; 2330 2331 enum { 2332 MEGASAS_HBA_OPERATIONAL = 0, 2333 MEGASAS_ADPRESET_SM_INFAULT = 1, 2334 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 2335 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 2336 MEGASAS_HW_CRITICAL_ERROR = 4, 2337 MEGASAS_ADPRESET_SM_POLLING = 5, 2338 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2339 }; 2340 2341 struct megasas_instance_template { 2342 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 2343 u32, struct megasas_register_set __iomem *); 2344 2345 void (*enable_intr)(struct megasas_instance *); 2346 void (*disable_intr)(struct megasas_instance *); 2347 2348 int (*clear_intr)(struct megasas_register_set __iomem *); 2349 2350 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 2351 int (*adp_reset)(struct megasas_instance *, \ 2352 struct megasas_register_set __iomem *); 2353 int (*check_reset)(struct megasas_instance *, \ 2354 struct megasas_register_set __iomem *); 2355 irqreturn_t (*service_isr)(int irq, void *devp); 2356 void (*tasklet)(unsigned long); 2357 u32 (*init_adapter)(struct megasas_instance *); 2358 u32 (*build_and_issue_cmd) (struct megasas_instance *, 2359 struct scsi_cmnd *); 2360 void (*issue_dcmd)(struct megasas_instance *instance, 2361 struct megasas_cmd *cmd); 2362 }; 2363 2364 #define MEGASAS_IS_LOGICAL(sdev) \ 2365 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) 2366 2367 #define MEGASAS_DEV_INDEX(scp) \ 2368 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2369 scp->device->id) 2370 2371 #define MEGASAS_PD_INDEX(scp) \ 2372 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2373 scp->device->id) 2374 2375 struct megasas_cmd { 2376 2377 union megasas_frame *frame; 2378 dma_addr_t frame_phys_addr; 2379 u8 *sense; 2380 dma_addr_t sense_phys_addr; 2381 2382 u32 index; 2383 u8 sync_cmd; 2384 u8 cmd_status_drv; 2385 u8 abort_aen; 2386 u8 retry_for_fw_reset; 2387 2388 2389 struct list_head list; 2390 struct scsi_cmnd *scmd; 2391 u8 flags; 2392 2393 struct megasas_instance *instance; 2394 union { 2395 struct { 2396 u16 smid; 2397 u16 resvd; 2398 } context; 2399 u32 frame_count; 2400 }; 2401 }; 2402 2403 #define MAX_MGMT_ADAPTERS 1024 2404 #define MAX_IOCTL_SGE 16 2405 2406 struct megasas_iocpacket { 2407 2408 u16 host_no; 2409 u16 __pad1; 2410 u32 sgl_off; 2411 u32 sge_count; 2412 u32 sense_off; 2413 u32 sense_len; 2414 union { 2415 u8 raw[128]; 2416 struct megasas_header hdr; 2417 } frame; 2418 2419 struct iovec sgl[MAX_IOCTL_SGE]; 2420 2421 } __attribute__ ((packed)); 2422 2423 struct megasas_aen { 2424 u16 host_no; 2425 u16 __pad1; 2426 u32 seq_num; 2427 u32 class_locale_word; 2428 } __attribute__ ((packed)); 2429 2430 #ifdef CONFIG_COMPAT 2431 struct compat_megasas_iocpacket { 2432 u16 host_no; 2433 u16 __pad1; 2434 u32 sgl_off; 2435 u32 sge_count; 2436 u32 sense_off; 2437 u32 sense_len; 2438 union { 2439 u8 raw[128]; 2440 struct megasas_header hdr; 2441 } frame; 2442 struct compat_iovec sgl[MAX_IOCTL_SGE]; 2443 } __attribute__ ((packed)); 2444 2445 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2446 #endif 2447 2448 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2449 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2450 2451 struct megasas_mgmt_info { 2452 2453 u16 count; 2454 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2455 int max_index; 2456 }; 2457 2458 enum MEGASAS_OCR_CAUSE { 2459 FW_FAULT_OCR = 0, 2460 SCSIIO_TIMEOUT_OCR = 1, 2461 MFI_IO_TIMEOUT_OCR = 2, 2462 }; 2463 2464 enum DCMD_RETURN_STATUS { 2465 DCMD_SUCCESS = 0, 2466 DCMD_TIMEOUT = 1, 2467 DCMD_FAILED = 2, 2468 DCMD_NOT_FIRED = 3, 2469 }; 2470 2471 u8 2472 MR_BuildRaidContext(struct megasas_instance *instance, 2473 struct IO_REQUEST_INFO *io_info, 2474 struct RAID_CONTEXT *pRAID_Context, 2475 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2476 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 2477 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2478 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 2479 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 2480 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 2481 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2482 2483 __le16 get_updated_dev_handle(struct megasas_instance *instance, 2484 struct LD_LOAD_BALANCE_INFO *lbInfo, 2485 struct IO_REQUEST_INFO *in_info, 2486 struct MR_DRV_RAID_MAP_ALL *drv_map); 2487 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 2488 struct LD_LOAD_BALANCE_INFO *lbInfo); 2489 int megasas_get_ctrl_info(struct megasas_instance *instance); 2490 /* PD sequence */ 2491 int 2492 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2493 void megasas_set_dynamic_target_properties(struct scsi_device *sdev); 2494 int megasas_set_crash_dump_params(struct megasas_instance *instance, 2495 u8 crash_buf_state); 2496 void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2497 void megasas_fusion_crash_dump_wq(struct work_struct *work); 2498 2499 void megasas_return_cmd_fusion(struct megasas_instance *instance, 2500 struct megasas_cmd_fusion *cmd); 2501 int megasas_issue_blocked_cmd(struct megasas_instance *instance, 2502 struct megasas_cmd *cmd, int timeout); 2503 void __megasas_return_cmd(struct megasas_instance *instance, 2504 struct megasas_cmd *cmd); 2505 2506 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 2507 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 2508 int megasas_cmd_type(struct scsi_cmnd *cmd); 2509 void megasas_setup_jbod_map(struct megasas_instance *instance); 2510 2511 void megasas_update_sdev_properties(struct scsi_device *sdev); 2512 int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 2513 int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 2514 int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2515 u32 mega_mod64(u64 dividend, u32 divisor); 2516 int megasas_alloc_fusion_context(struct megasas_instance *instance); 2517 void megasas_free_fusion_context(struct megasas_instance *instance); 2518 void megasas_set_dma_settings(struct megasas_instance *instance, 2519 struct megasas_dcmd_frame *dcmd, 2520 dma_addr_t dma_addr, u32 dma_len); 2521 #endif /*LSI_MEGARAID_SAS_H */ 2522