1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2003-2012 LSI Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: LSI Corporation 23 * 24 * Send feedback to: <megaraidlinux@lsi.com> 25 * 26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 27 * ATTN: Linuxraid 28 */ 29 30 #ifndef LSI_MEGARAID_SAS_H 31 #define LSI_MEGARAID_SAS_H 32 33 /* 34 * MegaRAID SAS Driver meta data 35 */ 36 #define MEGASAS_VERSION "06.803.01.00-rc1" 37 #define MEGASAS_RELDATE "Mar. 10, 2014" 38 #define MEGASAS_EXT_VERSION "Mon. Mar. 10 17:00:00 PDT 2014" 39 40 /* 41 * Device IDs 42 */ 43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 51 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 52 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 53 #define PCI_DEVICE_ID_LSI_FURY 0x005f 54 55 /* 56 * Intel HBA SSDIDs 57 */ 58 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 59 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 60 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 61 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 62 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 63 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 64 65 /* 66 * Intel HBA branding 67 */ 68 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 69 "Intel(R) RAID Controller RS3DC080" 70 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 71 "Intel(R) RAID Controller RS3DC040" 72 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 73 "Intel(R) RAID Controller RS3SC008" 74 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 75 "Intel(R) RAID Controller RS3MC044" 76 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 77 "Intel(R) RAID Controller RS3WC080" 78 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 79 "Intel(R) RAID Controller RS3WC040" 80 81 /* 82 * ===================================== 83 * MegaRAID SAS MFI firmware definitions 84 * ===================================== 85 */ 86 87 /* 88 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 89 * protocol between the software and firmware. Commands are issued using 90 * "message frames" 91 */ 92 93 /* 94 * FW posts its state in upper 4 bits of outbound_msg_0 register 95 */ 96 #define MFI_STATE_MASK 0xF0000000 97 #define MFI_STATE_UNDEFINED 0x00000000 98 #define MFI_STATE_BB_INIT 0x10000000 99 #define MFI_STATE_FW_INIT 0x40000000 100 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 101 #define MFI_STATE_FW_INIT_2 0x70000000 102 #define MFI_STATE_DEVICE_SCAN 0x80000000 103 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 104 #define MFI_STATE_FLUSH_CACHE 0xA0000000 105 #define MFI_STATE_READY 0xB0000000 106 #define MFI_STATE_OPERATIONAL 0xC0000000 107 #define MFI_STATE_FAULT 0xF0000000 108 #define MFI_RESET_REQUIRED 0x00000001 109 #define MFI_RESET_ADAPTER 0x00000002 110 #define MEGAMFI_FRAME_SIZE 64 111 112 /* 113 * During FW init, clear pending cmds & reset state using inbound_msg_0 114 * 115 * ABORT : Abort all pending cmds 116 * READY : Move from OPERATIONAL to READY state; discard queue info 117 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 118 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 119 * HOTPLUG : Resume from Hotplug 120 * MFI_STOP_ADP : Send signal to FW to stop processing 121 */ 122 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 123 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 124 #define DIAG_WRITE_ENABLE (0x00000080) 125 #define DIAG_RESET_ADAPTER (0x00000004) 126 127 #define MFI_ADP_RESET 0x00000040 128 #define MFI_INIT_ABORT 0x00000001 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_INIT_HOTPLUG 0x00000010 133 #define MFI_STOP_ADP 0x00000020 134 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 135 MFI_INIT_MFIMODE| \ 136 MFI_INIT_ABORT 137 138 /* 139 * MFI frame flags 140 */ 141 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 142 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 143 #define MFI_FRAME_SGL32 0x0000 144 #define MFI_FRAME_SGL64 0x0002 145 #define MFI_FRAME_SENSE32 0x0000 146 #define MFI_FRAME_SENSE64 0x0004 147 #define MFI_FRAME_DIR_NONE 0x0000 148 #define MFI_FRAME_DIR_WRITE 0x0008 149 #define MFI_FRAME_DIR_READ 0x0010 150 #define MFI_FRAME_DIR_BOTH 0x0018 151 #define MFI_FRAME_IEEE 0x0020 152 153 /* 154 * Definition for cmd_status 155 */ 156 #define MFI_CMD_STATUS_POLL_MODE 0xFF 157 158 /* 159 * MFI command opcodes 160 */ 161 #define MFI_CMD_INIT 0x00 162 #define MFI_CMD_LD_READ 0x01 163 #define MFI_CMD_LD_WRITE 0x02 164 #define MFI_CMD_LD_SCSI_IO 0x03 165 #define MFI_CMD_PD_SCSI_IO 0x04 166 #define MFI_CMD_DCMD 0x05 167 #define MFI_CMD_ABORT 0x06 168 #define MFI_CMD_SMP 0x07 169 #define MFI_CMD_STP 0x08 170 #define MFI_CMD_INVALID 0xff 171 172 #define MR_DCMD_CTRL_GET_INFO 0x01010000 173 #define MR_DCMD_LD_GET_LIST 0x03010000 174 #define MR_DCMD_LD_LIST_QUERY 0x03010100 175 176 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 177 #define MR_FLUSH_CTRL_CACHE 0x01 178 #define MR_FLUSH_DISK_CACHE 0x02 179 180 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 181 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 182 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 183 184 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 185 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 186 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 187 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 188 189 #define MR_DCMD_CLUSTER 0x08000000 190 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 191 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 192 #define MR_DCMD_PD_LIST_QUERY 0x02010100 193 194 /* 195 * Global functions 196 */ 197 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 198 199 200 /* 201 * MFI command completion codes 202 */ 203 enum MFI_STAT { 204 MFI_STAT_OK = 0x00, 205 MFI_STAT_INVALID_CMD = 0x01, 206 MFI_STAT_INVALID_DCMD = 0x02, 207 MFI_STAT_INVALID_PARAMETER = 0x03, 208 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 209 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 210 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 211 MFI_STAT_APP_IN_USE = 0x07, 212 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 213 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 214 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 215 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 216 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 217 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 218 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 219 MFI_STAT_FLASH_BUSY = 0x0f, 220 MFI_STAT_FLASH_ERROR = 0x10, 221 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 222 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 223 MFI_STAT_FLASH_NOT_OPEN = 0x13, 224 MFI_STAT_FLASH_NOT_STARTED = 0x14, 225 MFI_STAT_FLUSH_FAILED = 0x15, 226 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 227 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 228 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 229 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 230 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 231 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 232 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 233 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 234 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 235 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 236 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 237 MFI_STAT_MFC_HW_ERROR = 0x21, 238 MFI_STAT_NO_HW_PRESENT = 0x22, 239 MFI_STAT_NOT_FOUND = 0x23, 240 MFI_STAT_NOT_IN_ENCL = 0x24, 241 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 242 MFI_STAT_PD_TYPE_WRONG = 0x26, 243 MFI_STAT_PR_DISABLED = 0x27, 244 MFI_STAT_ROW_INDEX_INVALID = 0x28, 245 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 246 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 247 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 248 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 249 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 250 MFI_STAT_SCSI_IO_FAILED = 0x2e, 251 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 252 MFI_STAT_SHUTDOWN_FAILED = 0x30, 253 MFI_STAT_TIME_NOT_SET = 0x31, 254 MFI_STAT_WRONG_STATE = 0x32, 255 MFI_STAT_LD_OFFLINE = 0x33, 256 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 257 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 258 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 259 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 260 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 261 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 262 263 MFI_STAT_INVALID_STATUS = 0xFF 264 }; 265 266 /* 267 * Number of mailbox bytes in DCMD message frame 268 */ 269 #define MFI_MBOX_SIZE 12 270 271 enum MR_EVT_CLASS { 272 273 MR_EVT_CLASS_DEBUG = -2, 274 MR_EVT_CLASS_PROGRESS = -1, 275 MR_EVT_CLASS_INFO = 0, 276 MR_EVT_CLASS_WARNING = 1, 277 MR_EVT_CLASS_CRITICAL = 2, 278 MR_EVT_CLASS_FATAL = 3, 279 MR_EVT_CLASS_DEAD = 4, 280 281 }; 282 283 enum MR_EVT_LOCALE { 284 285 MR_EVT_LOCALE_LD = 0x0001, 286 MR_EVT_LOCALE_PD = 0x0002, 287 MR_EVT_LOCALE_ENCL = 0x0004, 288 MR_EVT_LOCALE_BBU = 0x0008, 289 MR_EVT_LOCALE_SAS = 0x0010, 290 MR_EVT_LOCALE_CTRL = 0x0020, 291 MR_EVT_LOCALE_CONFIG = 0x0040, 292 MR_EVT_LOCALE_CLUSTER = 0x0080, 293 MR_EVT_LOCALE_ALL = 0xffff, 294 295 }; 296 297 enum MR_EVT_ARGS { 298 299 MR_EVT_ARGS_NONE, 300 MR_EVT_ARGS_CDB_SENSE, 301 MR_EVT_ARGS_LD, 302 MR_EVT_ARGS_LD_COUNT, 303 MR_EVT_ARGS_LD_LBA, 304 MR_EVT_ARGS_LD_OWNER, 305 MR_EVT_ARGS_LD_LBA_PD_LBA, 306 MR_EVT_ARGS_LD_PROG, 307 MR_EVT_ARGS_LD_STATE, 308 MR_EVT_ARGS_LD_STRIP, 309 MR_EVT_ARGS_PD, 310 MR_EVT_ARGS_PD_ERR, 311 MR_EVT_ARGS_PD_LBA, 312 MR_EVT_ARGS_PD_LBA_LD, 313 MR_EVT_ARGS_PD_PROG, 314 MR_EVT_ARGS_PD_STATE, 315 MR_EVT_ARGS_PCI, 316 MR_EVT_ARGS_RATE, 317 MR_EVT_ARGS_STR, 318 MR_EVT_ARGS_TIME, 319 MR_EVT_ARGS_ECC, 320 MR_EVT_ARGS_LD_PROP, 321 MR_EVT_ARGS_PD_SPARE, 322 MR_EVT_ARGS_PD_INDEX, 323 MR_EVT_ARGS_DIAG_PASS, 324 MR_EVT_ARGS_DIAG_FAIL, 325 MR_EVT_ARGS_PD_LBA_LBA, 326 MR_EVT_ARGS_PORT_PHY, 327 MR_EVT_ARGS_PD_MISSING, 328 MR_EVT_ARGS_PD_ADDRESS, 329 MR_EVT_ARGS_BITMAP, 330 MR_EVT_ARGS_CONNECTOR, 331 MR_EVT_ARGS_PD_PD, 332 MR_EVT_ARGS_PD_FRU, 333 MR_EVT_ARGS_PD_PATHINFO, 334 MR_EVT_ARGS_PD_POWER_STATE, 335 MR_EVT_ARGS_GENERIC, 336 }; 337 338 /* 339 * define constants for device list query options 340 */ 341 enum MR_PD_QUERY_TYPE { 342 MR_PD_QUERY_TYPE_ALL = 0, 343 MR_PD_QUERY_TYPE_STATE = 1, 344 MR_PD_QUERY_TYPE_POWER_STATE = 2, 345 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 346 MR_PD_QUERY_TYPE_SPEED = 4, 347 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 348 }; 349 350 enum MR_LD_QUERY_TYPE { 351 MR_LD_QUERY_TYPE_ALL = 0, 352 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 353 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 354 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 355 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 356 }; 357 358 359 #define MR_EVT_CFG_CLEARED 0x0004 360 #define MR_EVT_LD_STATE_CHANGE 0x0051 361 #define MR_EVT_PD_INSERTED 0x005b 362 #define MR_EVT_PD_REMOVED 0x0070 363 #define MR_EVT_LD_CREATED 0x008a 364 #define MR_EVT_LD_DELETED 0x008b 365 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 366 #define MR_EVT_LD_OFFLINE 0x00fc 367 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 368 #define MAX_LOGICAL_DRIVES 64 369 370 enum MR_PD_STATE { 371 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 372 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 373 MR_PD_STATE_HOT_SPARE = 0x02, 374 MR_PD_STATE_OFFLINE = 0x10, 375 MR_PD_STATE_FAILED = 0x11, 376 MR_PD_STATE_REBUILD = 0x14, 377 MR_PD_STATE_ONLINE = 0x18, 378 MR_PD_STATE_COPYBACK = 0x20, 379 MR_PD_STATE_SYSTEM = 0x40, 380 }; 381 382 383 /* 384 * defines the physical drive address structure 385 */ 386 struct MR_PD_ADDRESS { 387 u16 deviceId; 388 u16 enclDeviceId; 389 390 union { 391 struct { 392 u8 enclIndex; 393 u8 slotNumber; 394 } mrPdAddress; 395 struct { 396 u8 enclPosition; 397 u8 enclConnectorIndex; 398 } mrEnclAddress; 399 }; 400 u8 scsiDevType; 401 union { 402 u8 connectedPortBitmap; 403 u8 connectedPortNumbers; 404 }; 405 u64 sasAddr[2]; 406 } __packed; 407 408 /* 409 * defines the physical drive list structure 410 */ 411 struct MR_PD_LIST { 412 u32 size; 413 u32 count; 414 struct MR_PD_ADDRESS addr[1]; 415 } __packed; 416 417 struct megasas_pd_list { 418 u16 tid; 419 u8 driveType; 420 u8 driveState; 421 } __packed; 422 423 /* 424 * defines the logical drive reference structure 425 */ 426 union MR_LD_REF { 427 struct { 428 u8 targetId; 429 u8 reserved; 430 u16 seqNum; 431 }; 432 u32 ref; 433 } __packed; 434 435 /* 436 * defines the logical drive list structure 437 */ 438 struct MR_LD_LIST { 439 u32 ldCount; 440 u32 reserved; 441 struct { 442 union MR_LD_REF ref; 443 u8 state; 444 u8 reserved[3]; 445 u64 size; 446 } ldList[MAX_LOGICAL_DRIVES]; 447 } __packed; 448 449 struct MR_LD_TARGETID_LIST { 450 u32 size; 451 u32 count; 452 u8 pad[3]; 453 u8 targetId[MAX_LOGICAL_DRIVES]; 454 }; 455 456 457 /* 458 * SAS controller properties 459 */ 460 struct megasas_ctrl_prop { 461 462 u16 seq_num; 463 u16 pred_fail_poll_interval; 464 u16 intr_throttle_count; 465 u16 intr_throttle_timeouts; 466 u8 rebuild_rate; 467 u8 patrol_read_rate; 468 u8 bgi_rate; 469 u8 cc_rate; 470 u8 recon_rate; 471 u8 cache_flush_interval; 472 u8 spinup_drv_count; 473 u8 spinup_delay; 474 u8 cluster_enable; 475 u8 coercion_mode; 476 u8 alarm_enable; 477 u8 disable_auto_rebuild; 478 u8 disable_battery_warn; 479 u8 ecc_bucket_size; 480 u16 ecc_bucket_leak_rate; 481 u8 restore_hotspare_on_insertion; 482 u8 expose_encl_devices; 483 u8 maintainPdFailHistory; 484 u8 disallowHostRequestReordering; 485 u8 abortCCOnError; 486 u8 loadBalanceMode; 487 u8 disableAutoDetectBackplane; 488 489 u8 snapVDSpace; 490 491 /* 492 * Add properties that can be controlled by 493 * a bit in the following structure. 494 */ 495 struct { 496 #if defined(__BIG_ENDIAN_BITFIELD) 497 u32 reserved:18; 498 u32 enableJBOD:1; 499 u32 disableSpinDownHS:1; 500 u32 allowBootWithPinnedCache:1; 501 u32 disableOnlineCtrlReset:1; 502 u32 enableSecretKeyControl:1; 503 u32 autoEnhancedImport:1; 504 u32 enableSpinDownUnconfigured:1; 505 u32 SSDPatrolReadEnabled:1; 506 u32 SSDSMARTerEnabled:1; 507 u32 disableNCQ:1; 508 u32 useFdeOnly:1; 509 u32 prCorrectUnconfiguredAreas:1; 510 u32 SMARTerEnabled:1; 511 u32 copyBackDisabled:1; 512 #else 513 u32 copyBackDisabled:1; 514 u32 SMARTerEnabled:1; 515 u32 prCorrectUnconfiguredAreas:1; 516 u32 useFdeOnly:1; 517 u32 disableNCQ:1; 518 u32 SSDSMARTerEnabled:1; 519 u32 SSDPatrolReadEnabled:1; 520 u32 enableSpinDownUnconfigured:1; 521 u32 autoEnhancedImport:1; 522 u32 enableSecretKeyControl:1; 523 u32 disableOnlineCtrlReset:1; 524 u32 allowBootWithPinnedCache:1; 525 u32 disableSpinDownHS:1; 526 u32 enableJBOD:1; 527 u32 reserved:18; 528 #endif 529 } OnOffProperties; 530 u8 autoSnapVDSpace; 531 u8 viewSpace; 532 u16 spinDownTime; 533 u8 reserved[24]; 534 } __packed; 535 536 /* 537 * SAS controller information 538 */ 539 struct megasas_ctrl_info { 540 541 /* 542 * PCI device information 543 */ 544 struct { 545 546 u16 vendor_id; 547 u16 device_id; 548 u16 sub_vendor_id; 549 u16 sub_device_id; 550 u8 reserved[24]; 551 552 } __attribute__ ((packed)) pci; 553 554 /* 555 * Host interface information 556 */ 557 struct { 558 559 u8 PCIX:1; 560 u8 PCIE:1; 561 u8 iSCSI:1; 562 u8 SAS_3G:1; 563 u8 SRIOV:1; 564 u8 reserved_0:3; 565 u8 reserved_1[6]; 566 u8 port_count; 567 u64 port_addr[8]; 568 569 } __attribute__ ((packed)) host_interface; 570 571 /* 572 * Device (backend) interface information 573 */ 574 struct { 575 576 u8 SPI:1; 577 u8 SAS_3G:1; 578 u8 SATA_1_5G:1; 579 u8 SATA_3G:1; 580 u8 reserved_0:4; 581 u8 reserved_1[6]; 582 u8 port_count; 583 u64 port_addr[8]; 584 585 } __attribute__ ((packed)) device_interface; 586 587 /* 588 * List of components residing in flash. All str are null terminated 589 */ 590 u32 image_check_word; 591 u32 image_component_count; 592 593 struct { 594 595 char name[8]; 596 char version[32]; 597 char build_date[16]; 598 char built_time[16]; 599 600 } __attribute__ ((packed)) image_component[8]; 601 602 /* 603 * List of flash components that have been flashed on the card, but 604 * are not in use, pending reset of the adapter. This list will be 605 * empty if a flash operation has not occurred. All stings are null 606 * terminated 607 */ 608 u32 pending_image_component_count; 609 610 struct { 611 612 char name[8]; 613 char version[32]; 614 char build_date[16]; 615 char build_time[16]; 616 617 } __attribute__ ((packed)) pending_image_component[8]; 618 619 u8 max_arms; 620 u8 max_spans; 621 u8 max_arrays; 622 u8 max_lds; 623 624 char product_name[80]; 625 char serial_no[32]; 626 627 /* 628 * Other physical/controller/operation information. Indicates the 629 * presence of the hardware 630 */ 631 struct { 632 633 u32 bbu:1; 634 u32 alarm:1; 635 u32 nvram:1; 636 u32 uart:1; 637 u32 reserved:28; 638 639 } __attribute__ ((packed)) hw_present; 640 641 u32 current_fw_time; 642 643 /* 644 * Maximum data transfer sizes 645 */ 646 u16 max_concurrent_cmds; 647 u16 max_sge_count; 648 u32 max_request_size; 649 650 /* 651 * Logical and physical device counts 652 */ 653 u16 ld_present_count; 654 u16 ld_degraded_count; 655 u16 ld_offline_count; 656 657 u16 pd_present_count; 658 u16 pd_disk_present_count; 659 u16 pd_disk_pred_failure_count; 660 u16 pd_disk_failed_count; 661 662 /* 663 * Memory size information 664 */ 665 u16 nvram_size; 666 u16 memory_size; 667 u16 flash_size; 668 669 /* 670 * Error counters 671 */ 672 u16 mem_correctable_error_count; 673 u16 mem_uncorrectable_error_count; 674 675 /* 676 * Cluster information 677 */ 678 u8 cluster_permitted; 679 u8 cluster_active; 680 681 /* 682 * Additional max data transfer sizes 683 */ 684 u16 max_strips_per_io; 685 686 /* 687 * Controller capabilities structures 688 */ 689 struct { 690 691 u32 raid_level_0:1; 692 u32 raid_level_1:1; 693 u32 raid_level_5:1; 694 u32 raid_level_1E:1; 695 u32 raid_level_6:1; 696 u32 reserved:27; 697 698 } __attribute__ ((packed)) raid_levels; 699 700 struct { 701 702 u32 rbld_rate:1; 703 u32 cc_rate:1; 704 u32 bgi_rate:1; 705 u32 recon_rate:1; 706 u32 patrol_rate:1; 707 u32 alarm_control:1; 708 u32 cluster_supported:1; 709 u32 bbu:1; 710 u32 spanning_allowed:1; 711 u32 dedicated_hotspares:1; 712 u32 revertible_hotspares:1; 713 u32 foreign_config_import:1; 714 u32 self_diagnostic:1; 715 u32 mixed_redundancy_arr:1; 716 u32 global_hot_spares:1; 717 u32 reserved:17; 718 719 } __attribute__ ((packed)) adapter_operations; 720 721 struct { 722 723 u32 read_policy:1; 724 u32 write_policy:1; 725 u32 io_policy:1; 726 u32 access_policy:1; 727 u32 disk_cache_policy:1; 728 u32 reserved:27; 729 730 } __attribute__ ((packed)) ld_operations; 731 732 struct { 733 734 u8 min; 735 u8 max; 736 u8 reserved[2]; 737 738 } __attribute__ ((packed)) stripe_sz_ops; 739 740 struct { 741 742 u32 force_online:1; 743 u32 force_offline:1; 744 u32 force_rebuild:1; 745 u32 reserved:29; 746 747 } __attribute__ ((packed)) pd_operations; 748 749 struct { 750 751 u32 ctrl_supports_sas:1; 752 u32 ctrl_supports_sata:1; 753 u32 allow_mix_in_encl:1; 754 u32 allow_mix_in_ld:1; 755 u32 allow_sata_in_cluster:1; 756 u32 reserved:27; 757 758 } __attribute__ ((packed)) pd_mix_support; 759 760 /* 761 * Define ECC single-bit-error bucket information 762 */ 763 u8 ecc_bucket_count; 764 u8 reserved_2[11]; 765 766 /* 767 * Include the controller properties (changeable items) 768 */ 769 struct megasas_ctrl_prop properties; 770 771 /* 772 * Define FW pkg version (set in envt v'bles on OEM basis) 773 */ 774 char package_version[0x60]; 775 776 777 /* 778 * If adapterOperations.supportMoreThan8Phys is set, 779 * and deviceInterface.portCount is greater than 8, 780 * SAS Addrs for first 8 ports shall be populated in 781 * deviceInterface.portAddr, and the rest shall be 782 * populated in deviceInterfacePortAddr2. 783 */ 784 u64 deviceInterfacePortAddr2[8]; /*6a0h */ 785 u8 reserved3[128]; /*6e0h */ 786 787 struct { /*760h */ 788 u16 minPdRaidLevel_0:4; 789 u16 maxPdRaidLevel_0:12; 790 791 u16 minPdRaidLevel_1:4; 792 u16 maxPdRaidLevel_1:12; 793 794 u16 minPdRaidLevel_5:4; 795 u16 maxPdRaidLevel_5:12; 796 797 u16 minPdRaidLevel_1E:4; 798 u16 maxPdRaidLevel_1E:12; 799 800 u16 minPdRaidLevel_6:4; 801 u16 maxPdRaidLevel_6:12; 802 803 u16 minPdRaidLevel_10:4; 804 u16 maxPdRaidLevel_10:12; 805 806 u16 minPdRaidLevel_50:4; 807 u16 maxPdRaidLevel_50:12; 808 809 u16 minPdRaidLevel_60:4; 810 u16 maxPdRaidLevel_60:12; 811 812 u16 minPdRaidLevel_1E_RLQ0:4; 813 u16 maxPdRaidLevel_1E_RLQ0:12; 814 815 u16 minPdRaidLevel_1E0_RLQ0:4; 816 u16 maxPdRaidLevel_1E0_RLQ0:12; 817 818 u16 reserved[6]; 819 } pdsForRaidLevels; 820 821 u16 maxPds; /*780h */ 822 u16 maxDedHSPs; /*782h */ 823 u16 maxGlobalHSPs; /*784h */ 824 u16 ddfSize; /*786h */ 825 u8 maxLdsPerArray; /*788h */ 826 u8 partitionsInDDF; /*789h */ 827 u8 lockKeyBinding; /*78ah */ 828 u8 maxPITsPerLd; /*78bh */ 829 u8 maxViewsPerLd; /*78ch */ 830 u8 maxTargetId; /*78dh */ 831 u16 maxBvlVdSize; /*78eh */ 832 833 u16 maxConfigurableSSCSize; /*790h */ 834 u16 currentSSCsize; /*792h */ 835 836 char expanderFwVersion[12]; /*794h */ 837 838 u16 PFKTrialTimeRemaining; /*7A0h */ 839 840 u16 cacheMemorySize; /*7A2h */ 841 842 struct { /*7A4h */ 843 #if defined(__BIG_ENDIAN_BITFIELD) 844 u32 reserved:5; 845 u32 activePassive:2; 846 u32 supportConfigAutoBalance:1; 847 u32 mpio:1; 848 u32 supportDataLDonSSCArray:1; 849 u32 supportPointInTimeProgress:1; 850 u32 supportUnevenSpans:1; 851 u32 dedicatedHotSparesLimited:1; 852 u32 headlessMode:1; 853 u32 supportEmulatedDrives:1; 854 u32 supportResetNow:1; 855 u32 realTimeScheduler:1; 856 u32 supportSSDPatrolRead:1; 857 u32 supportPerfTuning:1; 858 u32 disableOnlinePFKChange:1; 859 u32 supportJBOD:1; 860 u32 supportBootTimePFKChange:1; 861 u32 supportSetLinkSpeed:1; 862 u32 supportEmergencySpares:1; 863 u32 supportSuspendResumeBGops:1; 864 u32 blockSSDWriteCacheChange:1; 865 u32 supportShieldState:1; 866 u32 supportLdBBMInfo:1; 867 u32 supportLdPIType3:1; 868 u32 supportLdPIType2:1; 869 u32 supportLdPIType1:1; 870 u32 supportPIcontroller:1; 871 #else 872 u32 supportPIcontroller:1; 873 u32 supportLdPIType1:1; 874 u32 supportLdPIType2:1; 875 u32 supportLdPIType3:1; 876 u32 supportLdBBMInfo:1; 877 u32 supportShieldState:1; 878 u32 blockSSDWriteCacheChange:1; 879 u32 supportSuspendResumeBGops:1; 880 u32 supportEmergencySpares:1; 881 u32 supportSetLinkSpeed:1; 882 u32 supportBootTimePFKChange:1; 883 u32 supportJBOD:1; 884 u32 disableOnlinePFKChange:1; 885 u32 supportPerfTuning:1; 886 u32 supportSSDPatrolRead:1; 887 u32 realTimeScheduler:1; 888 889 u32 supportResetNow:1; 890 u32 supportEmulatedDrives:1; 891 u32 headlessMode:1; 892 u32 dedicatedHotSparesLimited:1; 893 894 895 u32 supportUnevenSpans:1; 896 u32 supportPointInTimeProgress:1; 897 u32 supportDataLDonSSCArray:1; 898 u32 mpio:1; 899 u32 supportConfigAutoBalance:1; 900 u32 activePassive:2; 901 u32 reserved:5; 902 #endif 903 } adapterOperations2; 904 905 u8 driverVersion[32]; /*7A8h */ 906 u8 maxDAPdCountSpinup60; /*7C8h */ 907 u8 temperatureROC; /*7C9h */ 908 u8 temperatureCtrl; /*7CAh */ 909 u8 reserved4; /*7CBh */ 910 u16 maxConfigurablePds; /*7CCh */ 911 912 913 u8 reserved5[2]; /*0x7CDh */ 914 915 /* 916 * HA cluster information 917 */ 918 struct { 919 u32 peerIsPresent:1; 920 u32 peerIsIncompatible:1; 921 u32 hwIncompatible:1; 922 u32 fwVersionMismatch:1; 923 u32 ctrlPropIncompatible:1; 924 u32 premiumFeatureMismatch:1; 925 u32 reserved:26; 926 } cluster; 927 928 char clusterId[16]; /*7D4h */ 929 struct { 930 u8 maxVFsSupported; /*0x7E4*/ 931 u8 numVFsEnabled; /*0x7E5*/ 932 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 933 u8 reserved; /*0x7E7*/ 934 } iov; 935 936 u8 pad[0x800-0x7E8]; /*0x7E8 pad to 2k */ 937 } __packed; 938 939 /* 940 * =============================== 941 * MegaRAID SAS driver definitions 942 * =============================== 943 */ 944 #define MEGASAS_MAX_PD_CHANNELS 2 945 #define MEGASAS_MAX_LD_CHANNELS 1 946 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 947 MEGASAS_MAX_LD_CHANNELS) 948 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 949 #define MEGASAS_DEFAULT_INIT_ID -1 950 #define MEGASAS_MAX_LUN 8 951 #define MEGASAS_MAX_LD 64 952 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 953 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 954 MEGASAS_MAX_DEV_PER_CHANNEL) 955 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 956 MEGASAS_MAX_DEV_PER_CHANNEL) 957 958 #define MEGASAS_MAX_SECTORS (2*1024) 959 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 960 #define MEGASAS_DBG_LVL 1 961 962 #define MEGASAS_FW_BUSY 1 963 964 /* Frame Type */ 965 #define IO_FRAME 0 966 #define PTHRU_FRAME 1 967 968 /* 969 * When SCSI mid-layer calls driver's reset routine, driver waits for 970 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 971 * that the driver cannot _actually_ abort or reset pending commands. While 972 * it is waiting for the commands to complete, it prints a diagnostic message 973 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 974 */ 975 #define MEGASAS_RESET_WAIT_TIME 180 976 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 977 #define MEGASAS_RESET_NOTICE_INTERVAL 5 978 #define MEGASAS_IOCTL_CMD 0 979 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 980 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 981 982 /* 983 * FW reports the maximum of number of commands that it can accept (maximum 984 * commands that can be outstanding) at any time. The driver must report a 985 * lower number to the mid layer because it can issue a few internal commands 986 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 987 * is shown below 988 */ 989 #define MEGASAS_INT_CMDS 32 990 #define MEGASAS_SKINNY_INT_CMDS 5 991 992 #define MEGASAS_MAX_MSIX_QUEUES 128 993 /* 994 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 995 * SGLs based on the size of dma_addr_t 996 */ 997 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 998 999 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1000 1001 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1002 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1003 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1004 1005 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1006 #define MFI_POLL_TIMEOUT_SECS 60 1007 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1008 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1009 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1010 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1011 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1012 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1013 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1014 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1015 1016 #define MFI_1068_PCSR_OFFSET 0x84 1017 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1018 #define MFI_1068_FW_READY 0xDDDD0000 1019 1020 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1021 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1022 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1023 #define MR_MAX_MSIX_REG_ARRAY 16 1024 /* 1025 * register set for both 1068 and 1078 controllers 1026 * structure extended for 1078 registers 1027 */ 1028 1029 struct megasas_register_set { 1030 u32 doorbell; /*0000h*/ 1031 u32 fusion_seq_offset; /*0004h*/ 1032 u32 fusion_host_diag; /*0008h*/ 1033 u32 reserved_01; /*000Ch*/ 1034 1035 u32 inbound_msg_0; /*0010h*/ 1036 u32 inbound_msg_1; /*0014h*/ 1037 u32 outbound_msg_0; /*0018h*/ 1038 u32 outbound_msg_1; /*001Ch*/ 1039 1040 u32 inbound_doorbell; /*0020h*/ 1041 u32 inbound_intr_status; /*0024h*/ 1042 u32 inbound_intr_mask; /*0028h*/ 1043 1044 u32 outbound_doorbell; /*002Ch*/ 1045 u32 outbound_intr_status; /*0030h*/ 1046 u32 outbound_intr_mask; /*0034h*/ 1047 1048 u32 reserved_1[2]; /*0038h*/ 1049 1050 u32 inbound_queue_port; /*0040h*/ 1051 u32 outbound_queue_port; /*0044h*/ 1052 1053 u32 reserved_2[9]; /*0048h*/ 1054 u32 reply_post_host_index; /*006Ch*/ 1055 u32 reserved_2_2[12]; /*0070h*/ 1056 1057 u32 outbound_doorbell_clear; /*00A0h*/ 1058 1059 u32 reserved_3[3]; /*00A4h*/ 1060 1061 u32 outbound_scratch_pad ; /*00B0h*/ 1062 u32 outbound_scratch_pad_2; /*00B4h*/ 1063 1064 u32 reserved_4[2]; /*00B8h*/ 1065 1066 u32 inbound_low_queue_port ; /*00C0h*/ 1067 1068 u32 inbound_high_queue_port ; /*00C4h*/ 1069 1070 u32 reserved_5; /*00C8h*/ 1071 u32 res_6[11]; /*CCh*/ 1072 u32 host_diag; 1073 u32 seq_offset; 1074 u32 index_registers[807]; /*00CCh*/ 1075 } __attribute__ ((packed)); 1076 1077 struct megasas_sge32 { 1078 1079 u32 phys_addr; 1080 u32 length; 1081 1082 } __attribute__ ((packed)); 1083 1084 struct megasas_sge64 { 1085 1086 u64 phys_addr; 1087 u32 length; 1088 1089 } __attribute__ ((packed)); 1090 1091 struct megasas_sge_skinny { 1092 u64 phys_addr; 1093 u32 length; 1094 u32 flag; 1095 } __packed; 1096 1097 union megasas_sgl { 1098 1099 struct megasas_sge32 sge32[1]; 1100 struct megasas_sge64 sge64[1]; 1101 struct megasas_sge_skinny sge_skinny[1]; 1102 1103 } __attribute__ ((packed)); 1104 1105 struct megasas_header { 1106 1107 u8 cmd; /*00h */ 1108 u8 sense_len; /*01h */ 1109 u8 cmd_status; /*02h */ 1110 u8 scsi_status; /*03h */ 1111 1112 u8 target_id; /*04h */ 1113 u8 lun; /*05h */ 1114 u8 cdb_len; /*06h */ 1115 u8 sge_count; /*07h */ 1116 1117 u32 context; /*08h */ 1118 u32 pad_0; /*0Ch */ 1119 1120 u16 flags; /*10h */ 1121 u16 timeout; /*12h */ 1122 u32 data_xferlen; /*14h */ 1123 1124 } __attribute__ ((packed)); 1125 1126 union megasas_sgl_frame { 1127 1128 struct megasas_sge32 sge32[8]; 1129 struct megasas_sge64 sge64[5]; 1130 1131 } __attribute__ ((packed)); 1132 1133 typedef union _MFI_CAPABILITIES { 1134 struct { 1135 #if defined(__BIG_ENDIAN_BITFIELD) 1136 u32 reserved:30; 1137 u32 support_additional_msix:1; 1138 u32 support_fp_remote_lun:1; 1139 #else 1140 u32 support_fp_remote_lun:1; 1141 u32 support_additional_msix:1; 1142 u32 reserved:30; 1143 #endif 1144 } mfi_capabilities; 1145 u32 reg; 1146 } MFI_CAPABILITIES; 1147 1148 struct megasas_init_frame { 1149 1150 u8 cmd; /*00h */ 1151 u8 reserved_0; /*01h */ 1152 u8 cmd_status; /*02h */ 1153 1154 u8 reserved_1; /*03h */ 1155 MFI_CAPABILITIES driver_operations; /*04h*/ 1156 1157 u32 context; /*08h */ 1158 u32 pad_0; /*0Ch */ 1159 1160 u16 flags; /*10h */ 1161 u16 reserved_3; /*12h */ 1162 u32 data_xfer_len; /*14h */ 1163 1164 u32 queue_info_new_phys_addr_lo; /*18h */ 1165 u32 queue_info_new_phys_addr_hi; /*1Ch */ 1166 u32 queue_info_old_phys_addr_lo; /*20h */ 1167 u32 queue_info_old_phys_addr_hi; /*24h */ 1168 1169 u32 reserved_4[6]; /*28h */ 1170 1171 } __attribute__ ((packed)); 1172 1173 struct megasas_init_queue_info { 1174 1175 u32 init_flags; /*00h */ 1176 u32 reply_queue_entries; /*04h */ 1177 1178 u32 reply_queue_start_phys_addr_lo; /*08h */ 1179 u32 reply_queue_start_phys_addr_hi; /*0Ch */ 1180 u32 producer_index_phys_addr_lo; /*10h */ 1181 u32 producer_index_phys_addr_hi; /*14h */ 1182 u32 consumer_index_phys_addr_lo; /*18h */ 1183 u32 consumer_index_phys_addr_hi; /*1Ch */ 1184 1185 } __attribute__ ((packed)); 1186 1187 struct megasas_io_frame { 1188 1189 u8 cmd; /*00h */ 1190 u8 sense_len; /*01h */ 1191 u8 cmd_status; /*02h */ 1192 u8 scsi_status; /*03h */ 1193 1194 u8 target_id; /*04h */ 1195 u8 access_byte; /*05h */ 1196 u8 reserved_0; /*06h */ 1197 u8 sge_count; /*07h */ 1198 1199 u32 context; /*08h */ 1200 u32 pad_0; /*0Ch */ 1201 1202 u16 flags; /*10h */ 1203 u16 timeout; /*12h */ 1204 u32 lba_count; /*14h */ 1205 1206 u32 sense_buf_phys_addr_lo; /*18h */ 1207 u32 sense_buf_phys_addr_hi; /*1Ch */ 1208 1209 u32 start_lba_lo; /*20h */ 1210 u32 start_lba_hi; /*24h */ 1211 1212 union megasas_sgl sgl; /*28h */ 1213 1214 } __attribute__ ((packed)); 1215 1216 struct megasas_pthru_frame { 1217 1218 u8 cmd; /*00h */ 1219 u8 sense_len; /*01h */ 1220 u8 cmd_status; /*02h */ 1221 u8 scsi_status; /*03h */ 1222 1223 u8 target_id; /*04h */ 1224 u8 lun; /*05h */ 1225 u8 cdb_len; /*06h */ 1226 u8 sge_count; /*07h */ 1227 1228 u32 context; /*08h */ 1229 u32 pad_0; /*0Ch */ 1230 1231 u16 flags; /*10h */ 1232 u16 timeout; /*12h */ 1233 u32 data_xfer_len; /*14h */ 1234 1235 u32 sense_buf_phys_addr_lo; /*18h */ 1236 u32 sense_buf_phys_addr_hi; /*1Ch */ 1237 1238 u8 cdb[16]; /*20h */ 1239 union megasas_sgl sgl; /*30h */ 1240 1241 } __attribute__ ((packed)); 1242 1243 struct megasas_dcmd_frame { 1244 1245 u8 cmd; /*00h */ 1246 u8 reserved_0; /*01h */ 1247 u8 cmd_status; /*02h */ 1248 u8 reserved_1[4]; /*03h */ 1249 u8 sge_count; /*07h */ 1250 1251 u32 context; /*08h */ 1252 u32 pad_0; /*0Ch */ 1253 1254 u16 flags; /*10h */ 1255 u16 timeout; /*12h */ 1256 1257 u32 data_xfer_len; /*14h */ 1258 u32 opcode; /*18h */ 1259 1260 union { /*1Ch */ 1261 u8 b[12]; 1262 u16 s[6]; 1263 u32 w[3]; 1264 } mbox; 1265 1266 union megasas_sgl sgl; /*28h */ 1267 1268 } __attribute__ ((packed)); 1269 1270 struct megasas_abort_frame { 1271 1272 u8 cmd; /*00h */ 1273 u8 reserved_0; /*01h */ 1274 u8 cmd_status; /*02h */ 1275 1276 u8 reserved_1; /*03h */ 1277 u32 reserved_2; /*04h */ 1278 1279 u32 context; /*08h */ 1280 u32 pad_0; /*0Ch */ 1281 1282 u16 flags; /*10h */ 1283 u16 reserved_3; /*12h */ 1284 u32 reserved_4; /*14h */ 1285 1286 u32 abort_context; /*18h */ 1287 u32 pad_1; /*1Ch */ 1288 1289 u32 abort_mfi_phys_addr_lo; /*20h */ 1290 u32 abort_mfi_phys_addr_hi; /*24h */ 1291 1292 u32 reserved_5[6]; /*28h */ 1293 1294 } __attribute__ ((packed)); 1295 1296 struct megasas_smp_frame { 1297 1298 u8 cmd; /*00h */ 1299 u8 reserved_1; /*01h */ 1300 u8 cmd_status; /*02h */ 1301 u8 connection_status; /*03h */ 1302 1303 u8 reserved_2[3]; /*04h */ 1304 u8 sge_count; /*07h */ 1305 1306 u32 context; /*08h */ 1307 u32 pad_0; /*0Ch */ 1308 1309 u16 flags; /*10h */ 1310 u16 timeout; /*12h */ 1311 1312 u32 data_xfer_len; /*14h */ 1313 u64 sas_addr; /*18h */ 1314 1315 union { 1316 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1317 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1318 } sgl; 1319 1320 } __attribute__ ((packed)); 1321 1322 struct megasas_stp_frame { 1323 1324 u8 cmd; /*00h */ 1325 u8 reserved_1; /*01h */ 1326 u8 cmd_status; /*02h */ 1327 u8 reserved_2; /*03h */ 1328 1329 u8 target_id; /*04h */ 1330 u8 reserved_3[2]; /*05h */ 1331 u8 sge_count; /*07h */ 1332 1333 u32 context; /*08h */ 1334 u32 pad_0; /*0Ch */ 1335 1336 u16 flags; /*10h */ 1337 u16 timeout; /*12h */ 1338 1339 u32 data_xfer_len; /*14h */ 1340 1341 u16 fis[10]; /*18h */ 1342 u32 stp_flags; 1343 1344 union { 1345 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1346 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1347 } sgl; 1348 1349 } __attribute__ ((packed)); 1350 1351 union megasas_frame { 1352 1353 struct megasas_header hdr; 1354 struct megasas_init_frame init; 1355 struct megasas_io_frame io; 1356 struct megasas_pthru_frame pthru; 1357 struct megasas_dcmd_frame dcmd; 1358 struct megasas_abort_frame abort; 1359 struct megasas_smp_frame smp; 1360 struct megasas_stp_frame stp; 1361 1362 u8 raw_bytes[64]; 1363 }; 1364 1365 struct megasas_cmd; 1366 1367 union megasas_evt_class_locale { 1368 1369 struct { 1370 #ifndef __BIG_ENDIAN_BITFIELD 1371 u16 locale; 1372 u8 reserved; 1373 s8 class; 1374 #else 1375 s8 class; 1376 u8 reserved; 1377 u16 locale; 1378 #endif 1379 } __attribute__ ((packed)) members; 1380 1381 u32 word; 1382 1383 } __attribute__ ((packed)); 1384 1385 struct megasas_evt_log_info { 1386 u32 newest_seq_num; 1387 u32 oldest_seq_num; 1388 u32 clear_seq_num; 1389 u32 shutdown_seq_num; 1390 u32 boot_seq_num; 1391 1392 } __attribute__ ((packed)); 1393 1394 struct megasas_progress { 1395 1396 u16 progress; 1397 u16 elapsed_seconds; 1398 1399 } __attribute__ ((packed)); 1400 1401 struct megasas_evtarg_ld { 1402 1403 u16 target_id; 1404 u8 ld_index; 1405 u8 reserved; 1406 1407 } __attribute__ ((packed)); 1408 1409 struct megasas_evtarg_pd { 1410 u16 device_id; 1411 u8 encl_index; 1412 u8 slot_number; 1413 1414 } __attribute__ ((packed)); 1415 1416 struct megasas_evt_detail { 1417 1418 u32 seq_num; 1419 u32 time_stamp; 1420 u32 code; 1421 union megasas_evt_class_locale cl; 1422 u8 arg_type; 1423 u8 reserved1[15]; 1424 1425 union { 1426 struct { 1427 struct megasas_evtarg_pd pd; 1428 u8 cdb_length; 1429 u8 sense_length; 1430 u8 reserved[2]; 1431 u8 cdb[16]; 1432 u8 sense[64]; 1433 } __attribute__ ((packed)) cdbSense; 1434 1435 struct megasas_evtarg_ld ld; 1436 1437 struct { 1438 struct megasas_evtarg_ld ld; 1439 u64 count; 1440 } __attribute__ ((packed)) ld_count; 1441 1442 struct { 1443 u64 lba; 1444 struct megasas_evtarg_ld ld; 1445 } __attribute__ ((packed)) ld_lba; 1446 1447 struct { 1448 struct megasas_evtarg_ld ld; 1449 u32 prevOwner; 1450 u32 newOwner; 1451 } __attribute__ ((packed)) ld_owner; 1452 1453 struct { 1454 u64 ld_lba; 1455 u64 pd_lba; 1456 struct megasas_evtarg_ld ld; 1457 struct megasas_evtarg_pd pd; 1458 } __attribute__ ((packed)) ld_lba_pd_lba; 1459 1460 struct { 1461 struct megasas_evtarg_ld ld; 1462 struct megasas_progress prog; 1463 } __attribute__ ((packed)) ld_prog; 1464 1465 struct { 1466 struct megasas_evtarg_ld ld; 1467 u32 prev_state; 1468 u32 new_state; 1469 } __attribute__ ((packed)) ld_state; 1470 1471 struct { 1472 u64 strip; 1473 struct megasas_evtarg_ld ld; 1474 } __attribute__ ((packed)) ld_strip; 1475 1476 struct megasas_evtarg_pd pd; 1477 1478 struct { 1479 struct megasas_evtarg_pd pd; 1480 u32 err; 1481 } __attribute__ ((packed)) pd_err; 1482 1483 struct { 1484 u64 lba; 1485 struct megasas_evtarg_pd pd; 1486 } __attribute__ ((packed)) pd_lba; 1487 1488 struct { 1489 u64 lba; 1490 struct megasas_evtarg_pd pd; 1491 struct megasas_evtarg_ld ld; 1492 } __attribute__ ((packed)) pd_lba_ld; 1493 1494 struct { 1495 struct megasas_evtarg_pd pd; 1496 struct megasas_progress prog; 1497 } __attribute__ ((packed)) pd_prog; 1498 1499 struct { 1500 struct megasas_evtarg_pd pd; 1501 u32 prevState; 1502 u32 newState; 1503 } __attribute__ ((packed)) pd_state; 1504 1505 struct { 1506 u16 vendorId; 1507 u16 deviceId; 1508 u16 subVendorId; 1509 u16 subDeviceId; 1510 } __attribute__ ((packed)) pci; 1511 1512 u32 rate; 1513 char str[96]; 1514 1515 struct { 1516 u32 rtc; 1517 u32 elapsedSeconds; 1518 } __attribute__ ((packed)) time; 1519 1520 struct { 1521 u32 ecar; 1522 u32 elog; 1523 char str[64]; 1524 } __attribute__ ((packed)) ecc; 1525 1526 u8 b[96]; 1527 u16 s[48]; 1528 u32 w[24]; 1529 u64 d[12]; 1530 } args; 1531 1532 char description[128]; 1533 1534 } __attribute__ ((packed)); 1535 1536 struct megasas_aen_event { 1537 struct delayed_work hotplug_work; 1538 struct megasas_instance *instance; 1539 }; 1540 1541 struct megasas_irq_context { 1542 struct megasas_instance *instance; 1543 u32 MSIxIndex; 1544 }; 1545 1546 struct megasas_instance { 1547 1548 u32 *producer; 1549 dma_addr_t producer_h; 1550 u32 *consumer; 1551 dma_addr_t consumer_h; 1552 struct MR_LD_VF_AFFILIATION *vf_affiliation; 1553 dma_addr_t vf_affiliation_h; 1554 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 1555 dma_addr_t vf_affiliation_111_h; 1556 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 1557 dma_addr_t hb_host_mem_h; 1558 1559 u32 *reply_queue; 1560 dma_addr_t reply_queue_h; 1561 1562 struct megasas_register_set __iomem *reg_set; 1563 u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 1564 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1565 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 1566 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1567 s8 init_id; 1568 1569 u16 max_num_sge; 1570 u16 max_fw_cmds; 1571 /* For Fusion its num IOCTL cmds, for others MFI based its 1572 max_fw_cmds */ 1573 u16 max_mfi_cmds; 1574 u32 max_sectors_per_req; 1575 struct megasas_aen_event *ev; 1576 1577 struct megasas_cmd **cmd_list; 1578 struct list_head cmd_pool; 1579 /* used to sync fire the cmd to fw */ 1580 spinlock_t cmd_pool_lock; 1581 /* used to sync fire the cmd to fw */ 1582 spinlock_t hba_lock; 1583 /* used to synch producer, consumer ptrs in dpc */ 1584 spinlock_t completion_lock; 1585 struct dma_pool *frame_dma_pool; 1586 struct dma_pool *sense_dma_pool; 1587 1588 struct megasas_evt_detail *evt_detail; 1589 dma_addr_t evt_detail_h; 1590 struct megasas_cmd *aen_cmd; 1591 struct mutex aen_mutex; 1592 struct semaphore ioctl_sem; 1593 1594 struct Scsi_Host *host; 1595 1596 wait_queue_head_t int_cmd_wait_q; 1597 wait_queue_head_t abort_cmd_wait_q; 1598 1599 struct pci_dev *pdev; 1600 u32 unique_id; 1601 u32 fw_support_ieee; 1602 1603 atomic_t fw_outstanding; 1604 atomic_t fw_reset_no_pci_access; 1605 1606 struct megasas_instance_template *instancet; 1607 struct tasklet_struct isr_tasklet; 1608 struct work_struct work_init; 1609 1610 u8 flag; 1611 u8 unload; 1612 u8 flag_ieee; 1613 u8 issuepend_done; 1614 u8 disableOnlineCtrlReset; 1615 u8 UnevenSpanSupport; 1616 u8 adprecovery; 1617 unsigned long last_time; 1618 u32 mfiStatus; 1619 u32 last_seq_num; 1620 1621 struct list_head internal_reset_pending_q; 1622 1623 /* Ptr to hba specific information */ 1624 void *ctrl_context; 1625 unsigned int msix_vectors; 1626 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 1627 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 1628 u64 map_id; 1629 struct megasas_cmd *map_update_cmd; 1630 unsigned long bar; 1631 long reset_flags; 1632 struct mutex reset_mutex; 1633 struct timer_list sriov_heartbeat_timer; 1634 char skip_heartbeat_timer_del; 1635 u8 requestorId; 1636 u64 initiator_sas_address; 1637 u64 ld_sas_address[64]; 1638 char PlasmaFW111; 1639 char mpio; 1640 int throttlequeuedepth; 1641 u8 mask_interrupts; 1642 u8 is_imr; 1643 }; 1644 struct MR_LD_VF_MAP { 1645 u32 size; 1646 union MR_LD_REF ref; 1647 u8 ldVfCount; 1648 u8 reserved[6]; 1649 u8 policy[1]; 1650 }; 1651 1652 struct MR_LD_VF_AFFILIATION { 1653 u32 size; 1654 u8 ldCount; 1655 u8 vfCount; 1656 u8 thisVf; 1657 u8 reserved[9]; 1658 struct MR_LD_VF_MAP map[1]; 1659 }; 1660 1661 /* Plasma 1.11 FW backward compatibility structures */ 1662 #define IOV_111_OFFSET 0x7CE 1663 #define MAX_VIRTUAL_FUNCTIONS 8 1664 1665 struct IOV_111 { 1666 u8 maxVFsSupported; 1667 u8 numVFsEnabled; 1668 u8 requestorId; 1669 u8 reserved[5]; 1670 }; 1671 1672 struct MR_LD_VF_MAP_111 { 1673 u8 targetId; 1674 u8 reserved[3]; 1675 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 1676 }; 1677 1678 struct MR_LD_VF_AFFILIATION_111 { 1679 u8 vdCount; 1680 u8 vfCount; 1681 u8 thisVf; 1682 u8 reserved[5]; 1683 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 1684 }; 1685 1686 struct MR_CTRL_HB_HOST_MEM { 1687 struct { 1688 u32 fwCounter; /* Firmware heart beat counter */ 1689 struct { 1690 u32 debugmode:1; /* 1=Firmware is in debug mode. 1691 Heart beat will not be updated. */ 1692 u32 reserved:31; 1693 } debug; 1694 u32 reserved_fw[6]; 1695 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 1696 u32 reserved_driver[7]; 1697 } HB; 1698 u8 pad[0x400-0x40]; 1699 }; 1700 1701 enum { 1702 MEGASAS_HBA_OPERATIONAL = 0, 1703 MEGASAS_ADPRESET_SM_INFAULT = 1, 1704 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1705 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 1706 MEGASAS_HW_CRITICAL_ERROR = 4, 1707 MEGASAS_ADPRESET_SM_POLLING = 5, 1708 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1709 }; 1710 1711 struct megasas_instance_template { 1712 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 1713 u32, struct megasas_register_set __iomem *); 1714 1715 void (*enable_intr)(struct megasas_instance *); 1716 void (*disable_intr)(struct megasas_instance *); 1717 1718 int (*clear_intr)(struct megasas_register_set __iomem *); 1719 1720 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 1721 int (*adp_reset)(struct megasas_instance *, \ 1722 struct megasas_register_set __iomem *); 1723 int (*check_reset)(struct megasas_instance *, \ 1724 struct megasas_register_set __iomem *); 1725 irqreturn_t (*service_isr)(int irq, void *devp); 1726 void (*tasklet)(unsigned long); 1727 u32 (*init_adapter)(struct megasas_instance *); 1728 u32 (*build_and_issue_cmd) (struct megasas_instance *, 1729 struct scsi_cmnd *); 1730 void (*issue_dcmd) (struct megasas_instance *instance, 1731 struct megasas_cmd *cmd); 1732 }; 1733 1734 #define MEGASAS_IS_LOGICAL(scp) \ 1735 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1736 1737 #define MEGASAS_DEV_INDEX(inst, scp) \ 1738 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1739 scp->device->id 1740 1741 struct megasas_cmd { 1742 1743 union megasas_frame *frame; 1744 dma_addr_t frame_phys_addr; 1745 u8 *sense; 1746 dma_addr_t sense_phys_addr; 1747 1748 u32 index; 1749 u8 sync_cmd; 1750 u8 cmd_status; 1751 u8 abort_aen; 1752 u8 retry_for_fw_reset; 1753 1754 1755 struct list_head list; 1756 struct scsi_cmnd *scmd; 1757 struct megasas_instance *instance; 1758 union { 1759 struct { 1760 u16 smid; 1761 u16 resvd; 1762 } context; 1763 u32 frame_count; 1764 }; 1765 }; 1766 1767 #define MAX_MGMT_ADAPTERS 1024 1768 #define MAX_IOCTL_SGE 16 1769 1770 struct megasas_iocpacket { 1771 1772 u16 host_no; 1773 u16 __pad1; 1774 u32 sgl_off; 1775 u32 sge_count; 1776 u32 sense_off; 1777 u32 sense_len; 1778 union { 1779 u8 raw[128]; 1780 struct megasas_header hdr; 1781 } frame; 1782 1783 struct iovec sgl[MAX_IOCTL_SGE]; 1784 1785 } __attribute__ ((packed)); 1786 1787 struct megasas_aen { 1788 u16 host_no; 1789 u16 __pad1; 1790 u32 seq_num; 1791 u32 class_locale_word; 1792 } __attribute__ ((packed)); 1793 1794 #ifdef CONFIG_COMPAT 1795 struct compat_megasas_iocpacket { 1796 u16 host_no; 1797 u16 __pad1; 1798 u32 sgl_off; 1799 u32 sge_count; 1800 u32 sense_off; 1801 u32 sense_len; 1802 union { 1803 u8 raw[128]; 1804 struct megasas_header hdr; 1805 } frame; 1806 struct compat_iovec sgl[MAX_IOCTL_SGE]; 1807 } __attribute__ ((packed)); 1808 1809 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1810 #endif 1811 1812 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1813 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1814 1815 struct megasas_mgmt_info { 1816 1817 u16 count; 1818 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1819 int max_index; 1820 }; 1821 1822 u8 1823 MR_BuildRaidContext(struct megasas_instance *instance, 1824 struct IO_REQUEST_INFO *io_info, 1825 struct RAID_CONTEXT *pRAID_Context, 1826 struct MR_FW_RAID_MAP_ALL *map, u8 **raidLUN); 1827 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_FW_RAID_MAP_ALL *map); 1828 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_FW_RAID_MAP_ALL *map); 1829 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_FW_RAID_MAP_ALL *map); 1830 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_FW_RAID_MAP_ALL *map); 1831 u16 MR_PdDevHandleGet(u32 pd, struct MR_FW_RAID_MAP_ALL *map); 1832 u16 MR_GetLDTgtId(u32 ld, struct MR_FW_RAID_MAP_ALL *map); 1833 1834 #endif /*LSI_MEGARAID_SAS_H */ 1835