1 /*
2  *
3  *		Linux MegaRAID driver for SAS based RAID controllers
4  *
5  * Copyright (c) 2003-2005  LSI Corporation.
6  *
7  *		This program is free software; you can redistribute it and/or
8  *		modify it under the terms of the GNU General Public License
9  *		as published by the Free Software Foundation; either version
10  *		2 of the License, or (at your option) any later version.
11  *
12  * FILE		: megaraid_sas.h
13  */
14 
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
17 
18 /*
19  * MegaRAID SAS Driver meta data
20  */
21 #define MEGASAS_VERSION				"00.00.03.16-rc1"
22 #define MEGASAS_RELDATE				"Nov. 07, 2007"
23 #define MEGASAS_EXT_VERSION			"Thu. Nov. 07 10:09:32 PDT 2007"
24 
25 /*
26  * Device IDs
27  */
28 #define	PCI_DEVICE_ID_LSI_SAS1078R		0x0060
29 #define	PCI_DEVICE_ID_LSI_VERDE_ZCR		0x0413
30 
31 /*
32  * =====================================
33  * MegaRAID SAS MFI firmware definitions
34  * =====================================
35  */
36 
37 /*
38  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
39  * protocol between the software and firmware. Commands are issued using
40  * "message frames"
41  */
42 
43 /*
44  * FW posts its state in upper 4 bits of outbound_msg_0 register
45  */
46 #define MFI_STATE_MASK				0xF0000000
47 #define MFI_STATE_UNDEFINED			0x00000000
48 #define MFI_STATE_BB_INIT			0x10000000
49 #define MFI_STATE_FW_INIT			0x40000000
50 #define MFI_STATE_WAIT_HANDSHAKE		0x60000000
51 #define MFI_STATE_FW_INIT_2			0x70000000
52 #define MFI_STATE_DEVICE_SCAN			0x80000000
53 #define MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
54 #define MFI_STATE_FLUSH_CACHE			0xA0000000
55 #define MFI_STATE_READY				0xB0000000
56 #define MFI_STATE_OPERATIONAL			0xC0000000
57 #define MFI_STATE_FAULT				0xF0000000
58 
59 #define MEGAMFI_FRAME_SIZE			64
60 
61 /*
62  * During FW init, clear pending cmds & reset state using inbound_msg_0
63  *
64  * ABORT	: Abort all pending cmds
65  * READY	: Move from OPERATIONAL to READY state; discard queue info
66  * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
67  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
68  * HOTPLUG	: Resume from Hotplug
69  * MFI_STOP_ADP	: Send signal to FW to stop processing
70  */
71 #define MFI_INIT_ABORT				0x00000001
72 #define MFI_INIT_READY				0x00000002
73 #define MFI_INIT_MFIMODE			0x00000004
74 #define MFI_INIT_CLEAR_HANDSHAKE		0x00000008
75 #define MFI_INIT_HOTPLUG			0x00000010
76 #define MFI_STOP_ADP				0x00000020
77 #define MFI_RESET_FLAGS				MFI_INIT_READY| \
78 						MFI_INIT_MFIMODE| \
79 						MFI_INIT_ABORT
80 
81 /*
82  * MFI frame flags
83  */
84 #define MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
85 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
86 #define MFI_FRAME_SGL32				0x0000
87 #define MFI_FRAME_SGL64				0x0002
88 #define MFI_FRAME_SENSE32			0x0000
89 #define MFI_FRAME_SENSE64			0x0004
90 #define MFI_FRAME_DIR_NONE			0x0000
91 #define MFI_FRAME_DIR_WRITE			0x0008
92 #define MFI_FRAME_DIR_READ			0x0010
93 #define MFI_FRAME_DIR_BOTH			0x0018
94 
95 /*
96  * Definition for cmd_status
97  */
98 #define MFI_CMD_STATUS_POLL_MODE		0xFF
99 
100 /*
101  * MFI command opcodes
102  */
103 #define MFI_CMD_INIT				0x00
104 #define MFI_CMD_LD_READ				0x01
105 #define MFI_CMD_LD_WRITE			0x02
106 #define MFI_CMD_LD_SCSI_IO			0x03
107 #define MFI_CMD_PD_SCSI_IO			0x04
108 #define MFI_CMD_DCMD				0x05
109 #define MFI_CMD_ABORT				0x06
110 #define MFI_CMD_SMP				0x07
111 #define MFI_CMD_STP				0x08
112 
113 #define MR_DCMD_CTRL_GET_INFO			0x01010000
114 
115 #define MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
116 #define MR_FLUSH_CTRL_CACHE			0x01
117 #define MR_FLUSH_DISK_CACHE			0x02
118 
119 #define MR_DCMD_CTRL_SHUTDOWN			0x01050000
120 #define MR_DCMD_HIBERNATE_SHUTDOWN		0x01060000
121 #define MR_ENABLE_DRIVE_SPINDOWN		0x01
122 
123 #define MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
124 #define MR_DCMD_CTRL_EVENT_GET			0x01040300
125 #define MR_DCMD_CTRL_EVENT_WAIT			0x01040500
126 #define MR_DCMD_LD_GET_PROPERTIES		0x03030000
127 
128 #define MR_DCMD_CLUSTER				0x08000000
129 #define MR_DCMD_CLUSTER_RESET_ALL		0x08010100
130 #define MR_DCMD_CLUSTER_RESET_LD		0x08010200
131 
132 /*
133  * MFI command completion codes
134  */
135 enum MFI_STAT {
136 	MFI_STAT_OK = 0x00,
137 	MFI_STAT_INVALID_CMD = 0x01,
138 	MFI_STAT_INVALID_DCMD = 0x02,
139 	MFI_STAT_INVALID_PARAMETER = 0x03,
140 	MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
141 	MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
142 	MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
143 	MFI_STAT_APP_IN_USE = 0x07,
144 	MFI_STAT_APP_NOT_INITIALIZED = 0x08,
145 	MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
146 	MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
147 	MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
148 	MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
149 	MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
150 	MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
151 	MFI_STAT_FLASH_BUSY = 0x0f,
152 	MFI_STAT_FLASH_ERROR = 0x10,
153 	MFI_STAT_FLASH_IMAGE_BAD = 0x11,
154 	MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
155 	MFI_STAT_FLASH_NOT_OPEN = 0x13,
156 	MFI_STAT_FLASH_NOT_STARTED = 0x14,
157 	MFI_STAT_FLUSH_FAILED = 0x15,
158 	MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
159 	MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
160 	MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
161 	MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
162 	MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
163 	MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
164 	MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
165 	MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
166 	MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
167 	MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
168 	MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
169 	MFI_STAT_MFC_HW_ERROR = 0x21,
170 	MFI_STAT_NO_HW_PRESENT = 0x22,
171 	MFI_STAT_NOT_FOUND = 0x23,
172 	MFI_STAT_NOT_IN_ENCL = 0x24,
173 	MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
174 	MFI_STAT_PD_TYPE_WRONG = 0x26,
175 	MFI_STAT_PR_DISABLED = 0x27,
176 	MFI_STAT_ROW_INDEX_INVALID = 0x28,
177 	MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
178 	MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
179 	MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
180 	MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
181 	MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
182 	MFI_STAT_SCSI_IO_FAILED = 0x2e,
183 	MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
184 	MFI_STAT_SHUTDOWN_FAILED = 0x30,
185 	MFI_STAT_TIME_NOT_SET = 0x31,
186 	MFI_STAT_WRONG_STATE = 0x32,
187 	MFI_STAT_LD_OFFLINE = 0x33,
188 	MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
189 	MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
190 	MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
191 	MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
192 	MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
193 
194 	MFI_STAT_INVALID_STATUS = 0xFF
195 };
196 
197 /*
198  * Number of mailbox bytes in DCMD message frame
199  */
200 #define MFI_MBOX_SIZE				12
201 
202 enum MR_EVT_CLASS {
203 
204 	MR_EVT_CLASS_DEBUG = -2,
205 	MR_EVT_CLASS_PROGRESS = -1,
206 	MR_EVT_CLASS_INFO = 0,
207 	MR_EVT_CLASS_WARNING = 1,
208 	MR_EVT_CLASS_CRITICAL = 2,
209 	MR_EVT_CLASS_FATAL = 3,
210 	MR_EVT_CLASS_DEAD = 4,
211 
212 };
213 
214 enum MR_EVT_LOCALE {
215 
216 	MR_EVT_LOCALE_LD = 0x0001,
217 	MR_EVT_LOCALE_PD = 0x0002,
218 	MR_EVT_LOCALE_ENCL = 0x0004,
219 	MR_EVT_LOCALE_BBU = 0x0008,
220 	MR_EVT_LOCALE_SAS = 0x0010,
221 	MR_EVT_LOCALE_CTRL = 0x0020,
222 	MR_EVT_LOCALE_CONFIG = 0x0040,
223 	MR_EVT_LOCALE_CLUSTER = 0x0080,
224 	MR_EVT_LOCALE_ALL = 0xffff,
225 
226 };
227 
228 enum MR_EVT_ARGS {
229 
230 	MR_EVT_ARGS_NONE,
231 	MR_EVT_ARGS_CDB_SENSE,
232 	MR_EVT_ARGS_LD,
233 	MR_EVT_ARGS_LD_COUNT,
234 	MR_EVT_ARGS_LD_LBA,
235 	MR_EVT_ARGS_LD_OWNER,
236 	MR_EVT_ARGS_LD_LBA_PD_LBA,
237 	MR_EVT_ARGS_LD_PROG,
238 	MR_EVT_ARGS_LD_STATE,
239 	MR_EVT_ARGS_LD_STRIP,
240 	MR_EVT_ARGS_PD,
241 	MR_EVT_ARGS_PD_ERR,
242 	MR_EVT_ARGS_PD_LBA,
243 	MR_EVT_ARGS_PD_LBA_LD,
244 	MR_EVT_ARGS_PD_PROG,
245 	MR_EVT_ARGS_PD_STATE,
246 	MR_EVT_ARGS_PCI,
247 	MR_EVT_ARGS_RATE,
248 	MR_EVT_ARGS_STR,
249 	MR_EVT_ARGS_TIME,
250 	MR_EVT_ARGS_ECC,
251 
252 };
253 
254 /*
255  * SAS controller properties
256  */
257 struct megasas_ctrl_prop {
258 
259 	u16 seq_num;
260 	u16 pred_fail_poll_interval;
261 	u16 intr_throttle_count;
262 	u16 intr_throttle_timeouts;
263 	u8 rebuild_rate;
264 	u8 patrol_read_rate;
265 	u8 bgi_rate;
266 	u8 cc_rate;
267 	u8 recon_rate;
268 	u8 cache_flush_interval;
269 	u8 spinup_drv_count;
270 	u8 spinup_delay;
271 	u8 cluster_enable;
272 	u8 coercion_mode;
273 	u8 alarm_enable;
274 	u8 disable_auto_rebuild;
275 	u8 disable_battery_warn;
276 	u8 ecc_bucket_size;
277 	u16 ecc_bucket_leak_rate;
278 	u8 restore_hotspare_on_insertion;
279 	u8 expose_encl_devices;
280 	u8 reserved[38];
281 
282 } __attribute__ ((packed));
283 
284 /*
285  * SAS controller information
286  */
287 struct megasas_ctrl_info {
288 
289 	/*
290 	 * PCI device information
291 	 */
292 	struct {
293 
294 		u16 vendor_id;
295 		u16 device_id;
296 		u16 sub_vendor_id;
297 		u16 sub_device_id;
298 		u8 reserved[24];
299 
300 	} __attribute__ ((packed)) pci;
301 
302 	/*
303 	 * Host interface information
304 	 */
305 	struct {
306 
307 		u8 PCIX:1;
308 		u8 PCIE:1;
309 		u8 iSCSI:1;
310 		u8 SAS_3G:1;
311 		u8 reserved_0:4;
312 		u8 reserved_1[6];
313 		u8 port_count;
314 		u64 port_addr[8];
315 
316 	} __attribute__ ((packed)) host_interface;
317 
318 	/*
319 	 * Device (backend) interface information
320 	 */
321 	struct {
322 
323 		u8 SPI:1;
324 		u8 SAS_3G:1;
325 		u8 SATA_1_5G:1;
326 		u8 SATA_3G:1;
327 		u8 reserved_0:4;
328 		u8 reserved_1[6];
329 		u8 port_count;
330 		u64 port_addr[8];
331 
332 	} __attribute__ ((packed)) device_interface;
333 
334 	/*
335 	 * List of components residing in flash. All str are null terminated
336 	 */
337 	u32 image_check_word;
338 	u32 image_component_count;
339 
340 	struct {
341 
342 		char name[8];
343 		char version[32];
344 		char build_date[16];
345 		char built_time[16];
346 
347 	} __attribute__ ((packed)) image_component[8];
348 
349 	/*
350 	 * List of flash components that have been flashed on the card, but
351 	 * are not in use, pending reset of the adapter. This list will be
352 	 * empty if a flash operation has not occurred. All stings are null
353 	 * terminated
354 	 */
355 	u32 pending_image_component_count;
356 
357 	struct {
358 
359 		char name[8];
360 		char version[32];
361 		char build_date[16];
362 		char build_time[16];
363 
364 	} __attribute__ ((packed)) pending_image_component[8];
365 
366 	u8 max_arms;
367 	u8 max_spans;
368 	u8 max_arrays;
369 	u8 max_lds;
370 
371 	char product_name[80];
372 	char serial_no[32];
373 
374 	/*
375 	 * Other physical/controller/operation information. Indicates the
376 	 * presence of the hardware
377 	 */
378 	struct {
379 
380 		u32 bbu:1;
381 		u32 alarm:1;
382 		u32 nvram:1;
383 		u32 uart:1;
384 		u32 reserved:28;
385 
386 	} __attribute__ ((packed)) hw_present;
387 
388 	u32 current_fw_time;
389 
390 	/*
391 	 * Maximum data transfer sizes
392 	 */
393 	u16 max_concurrent_cmds;
394 	u16 max_sge_count;
395 	u32 max_request_size;
396 
397 	/*
398 	 * Logical and physical device counts
399 	 */
400 	u16 ld_present_count;
401 	u16 ld_degraded_count;
402 	u16 ld_offline_count;
403 
404 	u16 pd_present_count;
405 	u16 pd_disk_present_count;
406 	u16 pd_disk_pred_failure_count;
407 	u16 pd_disk_failed_count;
408 
409 	/*
410 	 * Memory size information
411 	 */
412 	u16 nvram_size;
413 	u16 memory_size;
414 	u16 flash_size;
415 
416 	/*
417 	 * Error counters
418 	 */
419 	u16 mem_correctable_error_count;
420 	u16 mem_uncorrectable_error_count;
421 
422 	/*
423 	 * Cluster information
424 	 */
425 	u8 cluster_permitted;
426 	u8 cluster_active;
427 
428 	/*
429 	 * Additional max data transfer sizes
430 	 */
431 	u16 max_strips_per_io;
432 
433 	/*
434 	 * Controller capabilities structures
435 	 */
436 	struct {
437 
438 		u32 raid_level_0:1;
439 		u32 raid_level_1:1;
440 		u32 raid_level_5:1;
441 		u32 raid_level_1E:1;
442 		u32 raid_level_6:1;
443 		u32 reserved:27;
444 
445 	} __attribute__ ((packed)) raid_levels;
446 
447 	struct {
448 
449 		u32 rbld_rate:1;
450 		u32 cc_rate:1;
451 		u32 bgi_rate:1;
452 		u32 recon_rate:1;
453 		u32 patrol_rate:1;
454 		u32 alarm_control:1;
455 		u32 cluster_supported:1;
456 		u32 bbu:1;
457 		u32 spanning_allowed:1;
458 		u32 dedicated_hotspares:1;
459 		u32 revertible_hotspares:1;
460 		u32 foreign_config_import:1;
461 		u32 self_diagnostic:1;
462 		u32 mixed_redundancy_arr:1;
463 		u32 global_hot_spares:1;
464 		u32 reserved:17;
465 
466 	} __attribute__ ((packed)) adapter_operations;
467 
468 	struct {
469 
470 		u32 read_policy:1;
471 		u32 write_policy:1;
472 		u32 io_policy:1;
473 		u32 access_policy:1;
474 		u32 disk_cache_policy:1;
475 		u32 reserved:27;
476 
477 	} __attribute__ ((packed)) ld_operations;
478 
479 	struct {
480 
481 		u8 min;
482 		u8 max;
483 		u8 reserved[2];
484 
485 	} __attribute__ ((packed)) stripe_sz_ops;
486 
487 	struct {
488 
489 		u32 force_online:1;
490 		u32 force_offline:1;
491 		u32 force_rebuild:1;
492 		u32 reserved:29;
493 
494 	} __attribute__ ((packed)) pd_operations;
495 
496 	struct {
497 
498 		u32 ctrl_supports_sas:1;
499 		u32 ctrl_supports_sata:1;
500 		u32 allow_mix_in_encl:1;
501 		u32 allow_mix_in_ld:1;
502 		u32 allow_sata_in_cluster:1;
503 		u32 reserved:27;
504 
505 	} __attribute__ ((packed)) pd_mix_support;
506 
507 	/*
508 	 * Define ECC single-bit-error bucket information
509 	 */
510 	u8 ecc_bucket_count;
511 	u8 reserved_2[11];
512 
513 	/*
514 	 * Include the controller properties (changeable items)
515 	 */
516 	struct megasas_ctrl_prop properties;
517 
518 	/*
519 	 * Define FW pkg version (set in envt v'bles on OEM basis)
520 	 */
521 	char package_version[0x60];
522 
523 	u8 pad[0x800 - 0x6a0];
524 
525 } __attribute__ ((packed));
526 
527 /*
528  * ===============================
529  * MegaRAID SAS driver definitions
530  * ===============================
531  */
532 #define MEGASAS_MAX_PD_CHANNELS			2
533 #define MEGASAS_MAX_LD_CHANNELS			2
534 #define MEGASAS_MAX_CHANNELS			(MEGASAS_MAX_PD_CHANNELS + \
535 						MEGASAS_MAX_LD_CHANNELS)
536 #define MEGASAS_MAX_DEV_PER_CHANNEL		128
537 #define MEGASAS_DEFAULT_INIT_ID			-1
538 #define MEGASAS_MAX_LUN				8
539 #define MEGASAS_MAX_LD				64
540 
541 #define MEGASAS_DBG_LVL				1
542 
543 #define MEGASAS_FW_BUSY				1
544 
545 /*
546  * When SCSI mid-layer calls driver's reset routine, driver waits for
547  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
548  * that the driver cannot _actually_ abort or reset pending commands. While
549  * it is waiting for the commands to complete, it prints a diagnostic message
550  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
551  */
552 #define MEGASAS_RESET_WAIT_TIME			180
553 #define MEGASAS_INTERNAL_CMD_WAIT_TIME		180
554 #define	MEGASAS_RESET_NOTICE_INTERVAL		5
555 #define MEGASAS_IOCTL_CMD			0
556 #define MEGASAS_DEFAULT_CMD_TIMEOUT		90
557 
558 /*
559  * FW reports the maximum of number of commands that it can accept (maximum
560  * commands that can be outstanding) at any time. The driver must report a
561  * lower number to the mid layer because it can issue a few internal commands
562  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
563  * is shown below
564  */
565 #define MEGASAS_INT_CMDS			32
566 
567 /*
568  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
569  * SGLs based on the size of dma_addr_t
570  */
571 #define IS_DMA64				(sizeof(dma_addr_t) == 8)
572 
573 #define MFI_OB_INTR_STATUS_MASK			0x00000002
574 #define MFI_POLL_TIMEOUT_SECS			60
575 #define MEGASAS_COMPLETION_TIMER_INTERVAL      (HZ/10)
576 
577 #define MFI_REPLY_1078_MESSAGE_INTERRUPT	0x80000000
578 
579 /*
580 * register set for both 1068 and 1078 controllers
581 * structure extended for 1078 registers
582 */
583 
584 struct megasas_register_set {
585 	u32 	reserved_0[4];			/*0000h*/
586 
587 	u32 	inbound_msg_0;			/*0010h*/
588 	u32 	inbound_msg_1;			/*0014h*/
589 	u32 	outbound_msg_0;			/*0018h*/
590 	u32 	outbound_msg_1;			/*001Ch*/
591 
592 	u32 	inbound_doorbell;		/*0020h*/
593 	u32 	inbound_intr_status;		/*0024h*/
594 	u32 	inbound_intr_mask;		/*0028h*/
595 
596 	u32 	outbound_doorbell;		/*002Ch*/
597 	u32 	outbound_intr_status;		/*0030h*/
598 	u32 	outbound_intr_mask;		/*0034h*/
599 
600 	u32 	reserved_1[2];			/*0038h*/
601 
602 	u32 	inbound_queue_port;		/*0040h*/
603 	u32 	outbound_queue_port;		/*0044h*/
604 
605 	u32 	reserved_2[22];			/*0048h*/
606 
607 	u32 	outbound_doorbell_clear;	/*00A0h*/
608 
609 	u32 	reserved_3[3];			/*00A4h*/
610 
611 	u32 	outbound_scratch_pad ;		/*00B0h*/
612 
613 	u32 	reserved_4[3];			/*00B4h*/
614 
615 	u32 	inbound_low_queue_port ;	/*00C0h*/
616 
617 	u32 	inbound_high_queue_port ;	/*00C4h*/
618 
619 	u32 	reserved_5;			/*00C8h*/
620 	u32 	index_registers[820];		/*00CCh*/
621 
622 } __attribute__ ((packed));
623 
624 struct megasas_sge32 {
625 
626 	u32 phys_addr;
627 	u32 length;
628 
629 } __attribute__ ((packed));
630 
631 struct megasas_sge64 {
632 
633 	u64 phys_addr;
634 	u32 length;
635 
636 } __attribute__ ((packed));
637 
638 union megasas_sgl {
639 
640 	struct megasas_sge32 sge32[1];
641 	struct megasas_sge64 sge64[1];
642 
643 } __attribute__ ((packed));
644 
645 struct megasas_header {
646 
647 	u8 cmd;			/*00h */
648 	u8 sense_len;		/*01h */
649 	u8 cmd_status;		/*02h */
650 	u8 scsi_status;		/*03h */
651 
652 	u8 target_id;		/*04h */
653 	u8 lun;			/*05h */
654 	u8 cdb_len;		/*06h */
655 	u8 sge_count;		/*07h */
656 
657 	u32 context;		/*08h */
658 	u32 pad_0;		/*0Ch */
659 
660 	u16 flags;		/*10h */
661 	u16 timeout;		/*12h */
662 	u32 data_xferlen;	/*14h */
663 
664 } __attribute__ ((packed));
665 
666 union megasas_sgl_frame {
667 
668 	struct megasas_sge32 sge32[8];
669 	struct megasas_sge64 sge64[5];
670 
671 } __attribute__ ((packed));
672 
673 struct megasas_init_frame {
674 
675 	u8 cmd;			/*00h */
676 	u8 reserved_0;		/*01h */
677 	u8 cmd_status;		/*02h */
678 
679 	u8 reserved_1;		/*03h */
680 	u32 reserved_2;		/*04h */
681 
682 	u32 context;		/*08h */
683 	u32 pad_0;		/*0Ch */
684 
685 	u16 flags;		/*10h */
686 	u16 reserved_3;		/*12h */
687 	u32 data_xfer_len;	/*14h */
688 
689 	u32 queue_info_new_phys_addr_lo;	/*18h */
690 	u32 queue_info_new_phys_addr_hi;	/*1Ch */
691 	u32 queue_info_old_phys_addr_lo;	/*20h */
692 	u32 queue_info_old_phys_addr_hi;	/*24h */
693 
694 	u32 reserved_4[6];	/*28h */
695 
696 } __attribute__ ((packed));
697 
698 struct megasas_init_queue_info {
699 
700 	u32 init_flags;		/*00h */
701 	u32 reply_queue_entries;	/*04h */
702 
703 	u32 reply_queue_start_phys_addr_lo;	/*08h */
704 	u32 reply_queue_start_phys_addr_hi;	/*0Ch */
705 	u32 producer_index_phys_addr_lo;	/*10h */
706 	u32 producer_index_phys_addr_hi;	/*14h */
707 	u32 consumer_index_phys_addr_lo;	/*18h */
708 	u32 consumer_index_phys_addr_hi;	/*1Ch */
709 
710 } __attribute__ ((packed));
711 
712 struct megasas_io_frame {
713 
714 	u8 cmd;			/*00h */
715 	u8 sense_len;		/*01h */
716 	u8 cmd_status;		/*02h */
717 	u8 scsi_status;		/*03h */
718 
719 	u8 target_id;		/*04h */
720 	u8 access_byte;		/*05h */
721 	u8 reserved_0;		/*06h */
722 	u8 sge_count;		/*07h */
723 
724 	u32 context;		/*08h */
725 	u32 pad_0;		/*0Ch */
726 
727 	u16 flags;		/*10h */
728 	u16 timeout;		/*12h */
729 	u32 lba_count;		/*14h */
730 
731 	u32 sense_buf_phys_addr_lo;	/*18h */
732 	u32 sense_buf_phys_addr_hi;	/*1Ch */
733 
734 	u32 start_lba_lo;	/*20h */
735 	u32 start_lba_hi;	/*24h */
736 
737 	union megasas_sgl sgl;	/*28h */
738 
739 } __attribute__ ((packed));
740 
741 struct megasas_pthru_frame {
742 
743 	u8 cmd;			/*00h */
744 	u8 sense_len;		/*01h */
745 	u8 cmd_status;		/*02h */
746 	u8 scsi_status;		/*03h */
747 
748 	u8 target_id;		/*04h */
749 	u8 lun;			/*05h */
750 	u8 cdb_len;		/*06h */
751 	u8 sge_count;		/*07h */
752 
753 	u32 context;		/*08h */
754 	u32 pad_0;		/*0Ch */
755 
756 	u16 flags;		/*10h */
757 	u16 timeout;		/*12h */
758 	u32 data_xfer_len;	/*14h */
759 
760 	u32 sense_buf_phys_addr_lo;	/*18h */
761 	u32 sense_buf_phys_addr_hi;	/*1Ch */
762 
763 	u8 cdb[16];		/*20h */
764 	union megasas_sgl sgl;	/*30h */
765 
766 } __attribute__ ((packed));
767 
768 struct megasas_dcmd_frame {
769 
770 	u8 cmd;			/*00h */
771 	u8 reserved_0;		/*01h */
772 	u8 cmd_status;		/*02h */
773 	u8 reserved_1[4];	/*03h */
774 	u8 sge_count;		/*07h */
775 
776 	u32 context;		/*08h */
777 	u32 pad_0;		/*0Ch */
778 
779 	u16 flags;		/*10h */
780 	u16 timeout;		/*12h */
781 
782 	u32 data_xfer_len;	/*14h */
783 	u32 opcode;		/*18h */
784 
785 	union {			/*1Ch */
786 		u8 b[12];
787 		u16 s[6];
788 		u32 w[3];
789 	} mbox;
790 
791 	union megasas_sgl sgl;	/*28h */
792 
793 } __attribute__ ((packed));
794 
795 struct megasas_abort_frame {
796 
797 	u8 cmd;			/*00h */
798 	u8 reserved_0;		/*01h */
799 	u8 cmd_status;		/*02h */
800 
801 	u8 reserved_1;		/*03h */
802 	u32 reserved_2;		/*04h */
803 
804 	u32 context;		/*08h */
805 	u32 pad_0;		/*0Ch */
806 
807 	u16 flags;		/*10h */
808 	u16 reserved_3;		/*12h */
809 	u32 reserved_4;		/*14h */
810 
811 	u32 abort_context;	/*18h */
812 	u32 pad_1;		/*1Ch */
813 
814 	u32 abort_mfi_phys_addr_lo;	/*20h */
815 	u32 abort_mfi_phys_addr_hi;	/*24h */
816 
817 	u32 reserved_5[6];	/*28h */
818 
819 } __attribute__ ((packed));
820 
821 struct megasas_smp_frame {
822 
823 	u8 cmd;			/*00h */
824 	u8 reserved_1;		/*01h */
825 	u8 cmd_status;		/*02h */
826 	u8 connection_status;	/*03h */
827 
828 	u8 reserved_2[3];	/*04h */
829 	u8 sge_count;		/*07h */
830 
831 	u32 context;		/*08h */
832 	u32 pad_0;		/*0Ch */
833 
834 	u16 flags;		/*10h */
835 	u16 timeout;		/*12h */
836 
837 	u32 data_xfer_len;	/*14h */
838 	u64 sas_addr;		/*18h */
839 
840 	union {
841 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: req */
842 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: req */
843 	} sgl;
844 
845 } __attribute__ ((packed));
846 
847 struct megasas_stp_frame {
848 
849 	u8 cmd;			/*00h */
850 	u8 reserved_1;		/*01h */
851 	u8 cmd_status;		/*02h */
852 	u8 reserved_2;		/*03h */
853 
854 	u8 target_id;		/*04h */
855 	u8 reserved_3[2];	/*05h */
856 	u8 sge_count;		/*07h */
857 
858 	u32 context;		/*08h */
859 	u32 pad_0;		/*0Ch */
860 
861 	u16 flags;		/*10h */
862 	u16 timeout;		/*12h */
863 
864 	u32 data_xfer_len;	/*14h */
865 
866 	u16 fis[10];		/*18h */
867 	u32 stp_flags;
868 
869 	union {
870 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: data */
871 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: data */
872 	} sgl;
873 
874 } __attribute__ ((packed));
875 
876 union megasas_frame {
877 
878 	struct megasas_header hdr;
879 	struct megasas_init_frame init;
880 	struct megasas_io_frame io;
881 	struct megasas_pthru_frame pthru;
882 	struct megasas_dcmd_frame dcmd;
883 	struct megasas_abort_frame abort;
884 	struct megasas_smp_frame smp;
885 	struct megasas_stp_frame stp;
886 
887 	u8 raw_bytes[64];
888 };
889 
890 struct megasas_cmd;
891 
892 union megasas_evt_class_locale {
893 
894 	struct {
895 		u16 locale;
896 		u8 reserved;
897 		s8 class;
898 	} __attribute__ ((packed)) members;
899 
900 	u32 word;
901 
902 } __attribute__ ((packed));
903 
904 struct megasas_evt_log_info {
905 	u32 newest_seq_num;
906 	u32 oldest_seq_num;
907 	u32 clear_seq_num;
908 	u32 shutdown_seq_num;
909 	u32 boot_seq_num;
910 
911 } __attribute__ ((packed));
912 
913 struct megasas_progress {
914 
915 	u16 progress;
916 	u16 elapsed_seconds;
917 
918 } __attribute__ ((packed));
919 
920 struct megasas_evtarg_ld {
921 
922 	u16 target_id;
923 	u8 ld_index;
924 	u8 reserved;
925 
926 } __attribute__ ((packed));
927 
928 struct megasas_evtarg_pd {
929 	u16 device_id;
930 	u8 encl_index;
931 	u8 slot_number;
932 
933 } __attribute__ ((packed));
934 
935 struct megasas_evt_detail {
936 
937 	u32 seq_num;
938 	u32 time_stamp;
939 	u32 code;
940 	union megasas_evt_class_locale cl;
941 	u8 arg_type;
942 	u8 reserved1[15];
943 
944 	union {
945 		struct {
946 			struct megasas_evtarg_pd pd;
947 			u8 cdb_length;
948 			u8 sense_length;
949 			u8 reserved[2];
950 			u8 cdb[16];
951 			u8 sense[64];
952 		} __attribute__ ((packed)) cdbSense;
953 
954 		struct megasas_evtarg_ld ld;
955 
956 		struct {
957 			struct megasas_evtarg_ld ld;
958 			u64 count;
959 		} __attribute__ ((packed)) ld_count;
960 
961 		struct {
962 			u64 lba;
963 			struct megasas_evtarg_ld ld;
964 		} __attribute__ ((packed)) ld_lba;
965 
966 		struct {
967 			struct megasas_evtarg_ld ld;
968 			u32 prevOwner;
969 			u32 newOwner;
970 		} __attribute__ ((packed)) ld_owner;
971 
972 		struct {
973 			u64 ld_lba;
974 			u64 pd_lba;
975 			struct megasas_evtarg_ld ld;
976 			struct megasas_evtarg_pd pd;
977 		} __attribute__ ((packed)) ld_lba_pd_lba;
978 
979 		struct {
980 			struct megasas_evtarg_ld ld;
981 			struct megasas_progress prog;
982 		} __attribute__ ((packed)) ld_prog;
983 
984 		struct {
985 			struct megasas_evtarg_ld ld;
986 			u32 prev_state;
987 			u32 new_state;
988 		} __attribute__ ((packed)) ld_state;
989 
990 		struct {
991 			u64 strip;
992 			struct megasas_evtarg_ld ld;
993 		} __attribute__ ((packed)) ld_strip;
994 
995 		struct megasas_evtarg_pd pd;
996 
997 		struct {
998 			struct megasas_evtarg_pd pd;
999 			u32 err;
1000 		} __attribute__ ((packed)) pd_err;
1001 
1002 		struct {
1003 			u64 lba;
1004 			struct megasas_evtarg_pd pd;
1005 		} __attribute__ ((packed)) pd_lba;
1006 
1007 		struct {
1008 			u64 lba;
1009 			struct megasas_evtarg_pd pd;
1010 			struct megasas_evtarg_ld ld;
1011 		} __attribute__ ((packed)) pd_lba_ld;
1012 
1013 		struct {
1014 			struct megasas_evtarg_pd pd;
1015 			struct megasas_progress prog;
1016 		} __attribute__ ((packed)) pd_prog;
1017 
1018 		struct {
1019 			struct megasas_evtarg_pd pd;
1020 			u32 prevState;
1021 			u32 newState;
1022 		} __attribute__ ((packed)) pd_state;
1023 
1024 		struct {
1025 			u16 vendorId;
1026 			u16 deviceId;
1027 			u16 subVendorId;
1028 			u16 subDeviceId;
1029 		} __attribute__ ((packed)) pci;
1030 
1031 		u32 rate;
1032 		char str[96];
1033 
1034 		struct {
1035 			u32 rtc;
1036 			u32 elapsedSeconds;
1037 		} __attribute__ ((packed)) time;
1038 
1039 		struct {
1040 			u32 ecar;
1041 			u32 elog;
1042 			char str[64];
1043 		} __attribute__ ((packed)) ecc;
1044 
1045 		u8 b[96];
1046 		u16 s[48];
1047 		u32 w[24];
1048 		u64 d[12];
1049 	} args;
1050 
1051 	char description[128];
1052 
1053 } __attribute__ ((packed));
1054 
1055  struct megasas_instance_template {
1056 	void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1057 
1058 	void (*enable_intr)(struct megasas_register_set __iomem *) ;
1059 	void (*disable_intr)(struct megasas_register_set __iomem *);
1060 
1061 	int (*clear_intr)(struct megasas_register_set __iomem *);
1062 
1063 	u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1064  };
1065 
1066 struct megasas_instance {
1067 
1068 	u32 *producer;
1069 	dma_addr_t producer_h;
1070 	u32 *consumer;
1071 	dma_addr_t consumer_h;
1072 
1073 	u32 *reply_queue;
1074 	dma_addr_t reply_queue_h;
1075 
1076 	unsigned long base_addr;
1077 	struct megasas_register_set __iomem *reg_set;
1078 
1079 	s8 init_id;
1080 
1081 	u16 max_num_sge;
1082 	u16 max_fw_cmds;
1083 	u32 max_sectors_per_req;
1084 
1085 	struct megasas_cmd **cmd_list;
1086 	struct list_head cmd_pool;
1087 	spinlock_t cmd_pool_lock;
1088 	/* used to synch producer, consumer ptrs in dpc */
1089 	spinlock_t completion_lock;
1090 	struct dma_pool *frame_dma_pool;
1091 	struct dma_pool *sense_dma_pool;
1092 
1093 	struct megasas_evt_detail *evt_detail;
1094 	dma_addr_t evt_detail_h;
1095 	struct megasas_cmd *aen_cmd;
1096 	struct mutex aen_mutex;
1097 	struct semaphore ioctl_sem;
1098 
1099 	struct Scsi_Host *host;
1100 
1101 	wait_queue_head_t int_cmd_wait_q;
1102 	wait_queue_head_t abort_cmd_wait_q;
1103 
1104 	struct pci_dev *pdev;
1105 	u32 unique_id;
1106 
1107 	atomic_t fw_outstanding;
1108 	u32 hw_crit_error;
1109 
1110 	struct megasas_instance_template *instancet;
1111 	struct tasklet_struct isr_tasklet;
1112 
1113 	u8 flag;
1114 	unsigned long last_time;
1115 
1116 	struct timer_list io_completion_timer;
1117 };
1118 
1119 #define MEGASAS_IS_LOGICAL(scp)						\
1120 	(scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1121 
1122 #define MEGASAS_DEV_INDEX(inst, scp)					\
1123 	((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + 	\
1124 	scp->device->id
1125 
1126 struct megasas_cmd {
1127 
1128 	union megasas_frame *frame;
1129 	dma_addr_t frame_phys_addr;
1130 	u8 *sense;
1131 	dma_addr_t sense_phys_addr;
1132 
1133 	u32 index;
1134 	u8 sync_cmd;
1135 	u8 cmd_status;
1136 	u16 abort_aen;
1137 
1138 	struct list_head list;
1139 	struct scsi_cmnd *scmd;
1140 	struct megasas_instance *instance;
1141 	u32 frame_count;
1142 };
1143 
1144 #define MAX_MGMT_ADAPTERS		1024
1145 #define MAX_IOCTL_SGE			16
1146 
1147 struct megasas_iocpacket {
1148 
1149 	u16 host_no;
1150 	u16 __pad1;
1151 	u32 sgl_off;
1152 	u32 sge_count;
1153 	u32 sense_off;
1154 	u32 sense_len;
1155 	union {
1156 		u8 raw[128];
1157 		struct megasas_header hdr;
1158 	} frame;
1159 
1160 	struct iovec sgl[MAX_IOCTL_SGE];
1161 
1162 } __attribute__ ((packed));
1163 
1164 struct megasas_aen {
1165 	u16 host_no;
1166 	u16 __pad1;
1167 	u32 seq_num;
1168 	u32 class_locale_word;
1169 } __attribute__ ((packed));
1170 
1171 #ifdef CONFIG_COMPAT
1172 struct compat_megasas_iocpacket {
1173 	u16 host_no;
1174 	u16 __pad1;
1175 	u32 sgl_off;
1176 	u32 sge_count;
1177 	u32 sense_off;
1178 	u32 sense_len;
1179 	union {
1180 		u8 raw[128];
1181 		struct megasas_header hdr;
1182 	} frame;
1183 	struct compat_iovec sgl[MAX_IOCTL_SGE];
1184 } __attribute__ ((packed));
1185 
1186 #define MEGASAS_IOC_FIRMWARE32	_IOWR('M', 1, struct compat_megasas_iocpacket)
1187 #endif
1188 
1189 #define MEGASAS_IOC_FIRMWARE	_IOWR('M', 1, struct megasas_iocpacket)
1190 #define MEGASAS_IOC_GET_AEN	_IOW('M', 3, struct megasas_aen)
1191 
1192 struct megasas_mgmt_info {
1193 
1194 	u16 count;
1195 	struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1196 	int max_index;
1197 };
1198 
1199 #endif				/*LSI_MEGARAID_SAS_H */
1200