1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2003-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: Avago Technologies 23 * Kashyap Desai <kashyap.desai@avagotech.com> 24 * Sumit Saxena <sumit.saxena@avagotech.com> 25 * 26 * Send feedback to: megaraidlinux.pdl@avagotech.com 27 * 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29 * San Jose, California 95131 30 */ 31 32 #ifndef LSI_MEGARAID_SAS_H 33 #define LSI_MEGARAID_SAS_H 34 35 /* 36 * MegaRAID SAS Driver meta data 37 */ 38 #define MEGASAS_VERSION "07.704.04.00-rc1" 39 #define MEGASAS_RELDATE "December 7, 2017" 40 41 /* 42 * Device IDs 43 */ 44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 54 #define PCI_DEVICE_ID_LSI_FURY 0x005f 55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014 60 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015 61 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016 62 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 63 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B 64 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C 65 66 /* 67 * Intel HBA SSDIDs 68 */ 69 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 70 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 71 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 72 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 73 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 74 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 75 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 76 77 /* 78 * Intruder HBA SSDIDs 79 */ 80 #define MEGARAID_INTRUDER_SSDID1 0x9371 81 #define MEGARAID_INTRUDER_SSDID2 0x9390 82 #define MEGARAID_INTRUDER_SSDID3 0x9370 83 84 /* 85 * Intel HBA branding 86 */ 87 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 88 "Intel(R) RAID Controller RS3DC080" 89 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 90 "Intel(R) RAID Controller RS3DC040" 91 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 92 "Intel(R) RAID Controller RS3SC008" 93 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 94 "Intel(R) RAID Controller RS3MC044" 95 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 96 "Intel(R) RAID Controller RS3WC080" 97 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 98 "Intel(R) RAID Controller RS3WC040" 99 #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 100 "Intel(R) Integrated RAID Module RMS3BC160" 101 102 /* 103 * ===================================== 104 * MegaRAID SAS MFI firmware definitions 105 * ===================================== 106 */ 107 108 /* 109 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 110 * protocol between the software and firmware. Commands are issued using 111 * "message frames" 112 */ 113 114 /* 115 * FW posts its state in upper 4 bits of outbound_msg_0 register 116 */ 117 #define MFI_STATE_MASK 0xF0000000 118 #define MFI_STATE_UNDEFINED 0x00000000 119 #define MFI_STATE_BB_INIT 0x10000000 120 #define MFI_STATE_FW_INIT 0x40000000 121 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 122 #define MFI_STATE_FW_INIT_2 0x70000000 123 #define MFI_STATE_DEVICE_SCAN 0x80000000 124 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 125 #define MFI_STATE_FLUSH_CACHE 0xA0000000 126 #define MFI_STATE_READY 0xB0000000 127 #define MFI_STATE_OPERATIONAL 0xC0000000 128 #define MFI_STATE_FAULT 0xF0000000 129 #define MFI_STATE_FORCE_OCR 0x00000080 130 #define MFI_STATE_DMADONE 0x00000008 131 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 132 #define MFI_RESET_REQUIRED 0x00000001 133 #define MFI_RESET_ADAPTER 0x00000002 134 #define MEGAMFI_FRAME_SIZE 64 135 136 /* 137 * During FW init, clear pending cmds & reset state using inbound_msg_0 138 * 139 * ABORT : Abort all pending cmds 140 * READY : Move from OPERATIONAL to READY state; discard queue info 141 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 142 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 143 * HOTPLUG : Resume from Hotplug 144 * MFI_STOP_ADP : Send signal to FW to stop processing 145 */ 146 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 147 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 148 #define DIAG_WRITE_ENABLE (0x00000080) 149 #define DIAG_RESET_ADAPTER (0x00000004) 150 151 #define MFI_ADP_RESET 0x00000040 152 #define MFI_INIT_ABORT 0x00000001 153 #define MFI_INIT_READY 0x00000002 154 #define MFI_INIT_MFIMODE 0x00000004 155 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 156 #define MFI_INIT_HOTPLUG 0x00000010 157 #define MFI_STOP_ADP 0x00000020 158 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 159 MFI_INIT_MFIMODE| \ 160 MFI_INIT_ABORT 161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 162 163 /* 164 * MFI frame flags 165 */ 166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 168 #define MFI_FRAME_SGL32 0x0000 169 #define MFI_FRAME_SGL64 0x0002 170 #define MFI_FRAME_SENSE32 0x0000 171 #define MFI_FRAME_SENSE64 0x0004 172 #define MFI_FRAME_DIR_NONE 0x0000 173 #define MFI_FRAME_DIR_WRITE 0x0008 174 #define MFI_FRAME_DIR_READ 0x0010 175 #define MFI_FRAME_DIR_BOTH 0x0018 176 #define MFI_FRAME_IEEE 0x0020 177 178 /* Driver internal */ 179 #define DRV_DCMD_POLLED_MODE 0x1 180 #define DRV_DCMD_SKIP_REFIRE 0x2 181 182 /* 183 * Definition for cmd_status 184 */ 185 #define MFI_CMD_STATUS_POLL_MODE 0xFF 186 187 /* 188 * MFI command opcodes 189 */ 190 enum MFI_CMD_OP { 191 MFI_CMD_INIT = 0x0, 192 MFI_CMD_LD_READ = 0x1, 193 MFI_CMD_LD_WRITE = 0x2, 194 MFI_CMD_LD_SCSI_IO = 0x3, 195 MFI_CMD_PD_SCSI_IO = 0x4, 196 MFI_CMD_DCMD = 0x5, 197 MFI_CMD_ABORT = 0x6, 198 MFI_CMD_SMP = 0x7, 199 MFI_CMD_STP = 0x8, 200 MFI_CMD_NVME = 0x9, 201 MFI_CMD_OP_COUNT, 202 MFI_CMD_INVALID = 0xff 203 }; 204 205 #define MR_DCMD_CTRL_GET_INFO 0x01010000 206 #define MR_DCMD_LD_GET_LIST 0x03010000 207 #define MR_DCMD_LD_LIST_QUERY 0x03010100 208 209 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 210 #define MR_FLUSH_CTRL_CACHE 0x01 211 #define MR_FLUSH_DISK_CACHE 0x02 212 213 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 214 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 215 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 216 217 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 218 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 219 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 220 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 221 222 #define MR_DCMD_CLUSTER 0x08000000 223 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 224 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 225 #define MR_DCMD_PD_LIST_QUERY 0x02010100 226 227 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 228 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 229 #define MR_DCMD_PD_GET_INFO 0x02020000 230 231 /* 232 * Global functions 233 */ 234 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id); 235 236 237 /* 238 * MFI command completion codes 239 */ 240 enum MFI_STAT { 241 MFI_STAT_OK = 0x00, 242 MFI_STAT_INVALID_CMD = 0x01, 243 MFI_STAT_INVALID_DCMD = 0x02, 244 MFI_STAT_INVALID_PARAMETER = 0x03, 245 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 246 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 247 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 248 MFI_STAT_APP_IN_USE = 0x07, 249 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 250 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 251 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 252 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 253 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 254 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 255 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 256 MFI_STAT_FLASH_BUSY = 0x0f, 257 MFI_STAT_FLASH_ERROR = 0x10, 258 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 259 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 260 MFI_STAT_FLASH_NOT_OPEN = 0x13, 261 MFI_STAT_FLASH_NOT_STARTED = 0x14, 262 MFI_STAT_FLUSH_FAILED = 0x15, 263 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 264 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 265 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 266 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 267 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 268 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 269 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 270 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 271 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 272 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 273 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 274 MFI_STAT_MFC_HW_ERROR = 0x21, 275 MFI_STAT_NO_HW_PRESENT = 0x22, 276 MFI_STAT_NOT_FOUND = 0x23, 277 MFI_STAT_NOT_IN_ENCL = 0x24, 278 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 279 MFI_STAT_PD_TYPE_WRONG = 0x26, 280 MFI_STAT_PR_DISABLED = 0x27, 281 MFI_STAT_ROW_INDEX_INVALID = 0x28, 282 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 283 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 284 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 285 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 286 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 287 MFI_STAT_SCSI_IO_FAILED = 0x2e, 288 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 289 MFI_STAT_SHUTDOWN_FAILED = 0x30, 290 MFI_STAT_TIME_NOT_SET = 0x31, 291 MFI_STAT_WRONG_STATE = 0x32, 292 MFI_STAT_LD_OFFLINE = 0x33, 293 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 294 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 295 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 296 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 297 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 298 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 299 300 MFI_STAT_INVALID_STATUS = 0xFF 301 }; 302 303 enum mfi_evt_class { 304 MFI_EVT_CLASS_DEBUG = -2, 305 MFI_EVT_CLASS_PROGRESS = -1, 306 MFI_EVT_CLASS_INFO = 0, 307 MFI_EVT_CLASS_WARNING = 1, 308 MFI_EVT_CLASS_CRITICAL = 2, 309 MFI_EVT_CLASS_FATAL = 3, 310 MFI_EVT_CLASS_DEAD = 4 311 }; 312 313 /* 314 * Crash dump related defines 315 */ 316 #define MAX_CRASH_DUMP_SIZE 512 317 #define CRASH_DMA_BUF_SIZE (1024 * 1024) 318 319 enum MR_FW_CRASH_DUMP_STATE { 320 UNAVAILABLE = 0, 321 AVAILABLE = 1, 322 COPYING = 2, 323 COPIED = 3, 324 COPY_ERROR = 4, 325 }; 326 327 enum _MR_CRASH_BUF_STATUS { 328 MR_CRASH_BUF_TURN_OFF = 0, 329 MR_CRASH_BUF_TURN_ON = 1, 330 }; 331 332 /* 333 * Number of mailbox bytes in DCMD message frame 334 */ 335 #define MFI_MBOX_SIZE 12 336 337 enum MR_EVT_CLASS { 338 339 MR_EVT_CLASS_DEBUG = -2, 340 MR_EVT_CLASS_PROGRESS = -1, 341 MR_EVT_CLASS_INFO = 0, 342 MR_EVT_CLASS_WARNING = 1, 343 MR_EVT_CLASS_CRITICAL = 2, 344 MR_EVT_CLASS_FATAL = 3, 345 MR_EVT_CLASS_DEAD = 4, 346 347 }; 348 349 enum MR_EVT_LOCALE { 350 351 MR_EVT_LOCALE_LD = 0x0001, 352 MR_EVT_LOCALE_PD = 0x0002, 353 MR_EVT_LOCALE_ENCL = 0x0004, 354 MR_EVT_LOCALE_BBU = 0x0008, 355 MR_EVT_LOCALE_SAS = 0x0010, 356 MR_EVT_LOCALE_CTRL = 0x0020, 357 MR_EVT_LOCALE_CONFIG = 0x0040, 358 MR_EVT_LOCALE_CLUSTER = 0x0080, 359 MR_EVT_LOCALE_ALL = 0xffff, 360 361 }; 362 363 enum MR_EVT_ARGS { 364 365 MR_EVT_ARGS_NONE, 366 MR_EVT_ARGS_CDB_SENSE, 367 MR_EVT_ARGS_LD, 368 MR_EVT_ARGS_LD_COUNT, 369 MR_EVT_ARGS_LD_LBA, 370 MR_EVT_ARGS_LD_OWNER, 371 MR_EVT_ARGS_LD_LBA_PD_LBA, 372 MR_EVT_ARGS_LD_PROG, 373 MR_EVT_ARGS_LD_STATE, 374 MR_EVT_ARGS_LD_STRIP, 375 MR_EVT_ARGS_PD, 376 MR_EVT_ARGS_PD_ERR, 377 MR_EVT_ARGS_PD_LBA, 378 MR_EVT_ARGS_PD_LBA_LD, 379 MR_EVT_ARGS_PD_PROG, 380 MR_EVT_ARGS_PD_STATE, 381 MR_EVT_ARGS_PCI, 382 MR_EVT_ARGS_RATE, 383 MR_EVT_ARGS_STR, 384 MR_EVT_ARGS_TIME, 385 MR_EVT_ARGS_ECC, 386 MR_EVT_ARGS_LD_PROP, 387 MR_EVT_ARGS_PD_SPARE, 388 MR_EVT_ARGS_PD_INDEX, 389 MR_EVT_ARGS_DIAG_PASS, 390 MR_EVT_ARGS_DIAG_FAIL, 391 MR_EVT_ARGS_PD_LBA_LBA, 392 MR_EVT_ARGS_PORT_PHY, 393 MR_EVT_ARGS_PD_MISSING, 394 MR_EVT_ARGS_PD_ADDRESS, 395 MR_EVT_ARGS_BITMAP, 396 MR_EVT_ARGS_CONNECTOR, 397 MR_EVT_ARGS_PD_PD, 398 MR_EVT_ARGS_PD_FRU, 399 MR_EVT_ARGS_PD_PATHINFO, 400 MR_EVT_ARGS_PD_POWER_STATE, 401 MR_EVT_ARGS_GENERIC, 402 }; 403 404 405 #define SGE_BUFFER_SIZE 4096 406 #define MEGASAS_CLUSTER_ID_SIZE 16 407 /* 408 * define constants for device list query options 409 */ 410 enum MR_PD_QUERY_TYPE { 411 MR_PD_QUERY_TYPE_ALL = 0, 412 MR_PD_QUERY_TYPE_STATE = 1, 413 MR_PD_QUERY_TYPE_POWER_STATE = 2, 414 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 415 MR_PD_QUERY_TYPE_SPEED = 4, 416 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 417 }; 418 419 enum MR_LD_QUERY_TYPE { 420 MR_LD_QUERY_TYPE_ALL = 0, 421 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 422 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 423 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 424 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 425 }; 426 427 428 #define MR_EVT_CFG_CLEARED 0x0004 429 #define MR_EVT_LD_STATE_CHANGE 0x0051 430 #define MR_EVT_PD_INSERTED 0x005b 431 #define MR_EVT_PD_REMOVED 0x0070 432 #define MR_EVT_LD_CREATED 0x008a 433 #define MR_EVT_LD_DELETED 0x008b 434 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 435 #define MR_EVT_LD_OFFLINE 0x00fc 436 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 437 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 438 439 enum MR_PD_STATE { 440 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 441 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 442 MR_PD_STATE_HOT_SPARE = 0x02, 443 MR_PD_STATE_OFFLINE = 0x10, 444 MR_PD_STATE_FAILED = 0x11, 445 MR_PD_STATE_REBUILD = 0x14, 446 MR_PD_STATE_ONLINE = 0x18, 447 MR_PD_STATE_COPYBACK = 0x20, 448 MR_PD_STATE_SYSTEM = 0x40, 449 }; 450 451 union MR_PD_REF { 452 struct { 453 u16 deviceId; 454 u16 seqNum; 455 } mrPdRef; 456 u32 ref; 457 }; 458 459 /* 460 * define the DDF Type bit structure 461 */ 462 union MR_PD_DDF_TYPE { 463 struct { 464 union { 465 struct { 466 #ifndef __BIG_ENDIAN_BITFIELD 467 u16 forcedPDGUID:1; 468 u16 inVD:1; 469 u16 isGlobalSpare:1; 470 u16 isSpare:1; 471 u16 isForeign:1; 472 u16 reserved:7; 473 u16 intf:4; 474 #else 475 u16 intf:4; 476 u16 reserved:7; 477 u16 isForeign:1; 478 u16 isSpare:1; 479 u16 isGlobalSpare:1; 480 u16 inVD:1; 481 u16 forcedPDGUID:1; 482 #endif 483 } pdType; 484 u16 type; 485 }; 486 u16 reserved; 487 } ddf; 488 struct { 489 u32 reserved; 490 } nonDisk; 491 u32 type; 492 } __packed; 493 494 /* 495 * defines the progress structure 496 */ 497 union MR_PROGRESS { 498 struct { 499 u16 progress; 500 union { 501 u16 elapsedSecs; 502 u16 elapsedSecsForLastPercent; 503 }; 504 } mrProgress; 505 u32 w; 506 } __packed; 507 508 /* 509 * defines the physical drive progress structure 510 */ 511 struct MR_PD_PROGRESS { 512 struct { 513 #ifndef MFI_BIG_ENDIAN 514 u32 rbld:1; 515 u32 patrol:1; 516 u32 clear:1; 517 u32 copyBack:1; 518 u32 erase:1; 519 u32 locate:1; 520 u32 reserved:26; 521 #else 522 u32 reserved:26; 523 u32 locate:1; 524 u32 erase:1; 525 u32 copyBack:1; 526 u32 clear:1; 527 u32 patrol:1; 528 u32 rbld:1; 529 #endif 530 } active; 531 union MR_PROGRESS rbld; 532 union MR_PROGRESS patrol; 533 union { 534 union MR_PROGRESS clear; 535 union MR_PROGRESS erase; 536 }; 537 538 struct { 539 #ifndef MFI_BIG_ENDIAN 540 u32 rbld:1; 541 u32 patrol:1; 542 u32 clear:1; 543 u32 copyBack:1; 544 u32 erase:1; 545 u32 reserved:27; 546 #else 547 u32 reserved:27; 548 u32 erase:1; 549 u32 copyBack:1; 550 u32 clear:1; 551 u32 patrol:1; 552 u32 rbld:1; 553 #endif 554 } pause; 555 556 union MR_PROGRESS reserved[3]; 557 } __packed; 558 559 struct MR_PD_INFO { 560 union MR_PD_REF ref; 561 u8 inquiryData[96]; 562 u8 vpdPage83[64]; 563 u8 notSupported; 564 u8 scsiDevType; 565 566 union { 567 u8 connectedPortBitmap; 568 u8 connectedPortNumbers; 569 }; 570 571 u8 deviceSpeed; 572 u32 mediaErrCount; 573 u32 otherErrCount; 574 u32 predFailCount; 575 u32 lastPredFailEventSeqNum; 576 577 u16 fwState; 578 u8 disabledForRemoval; 579 u8 linkSpeed; 580 union MR_PD_DDF_TYPE state; 581 582 struct { 583 u8 count; 584 #ifndef __BIG_ENDIAN_BITFIELD 585 u8 isPathBroken:4; 586 u8 reserved3:3; 587 u8 widePortCapable:1; 588 #else 589 u8 widePortCapable:1; 590 u8 reserved3:3; 591 u8 isPathBroken:4; 592 #endif 593 594 u8 connectorIndex[2]; 595 u8 reserved[4]; 596 u64 sasAddr[2]; 597 u8 reserved2[16]; 598 } pathInfo; 599 600 u64 rawSize; 601 u64 nonCoercedSize; 602 u64 coercedSize; 603 u16 enclDeviceId; 604 u8 enclIndex; 605 606 union { 607 u8 slotNumber; 608 u8 enclConnectorIndex; 609 }; 610 611 struct MR_PD_PROGRESS progInfo; 612 u8 badBlockTableFull; 613 u8 unusableInCurrentConfig; 614 u8 vpdPage83Ext[64]; 615 u8 powerState; 616 u8 enclPosition; 617 u32 allowedOps; 618 u16 copyBackPartnerId; 619 u16 enclPartnerDeviceId; 620 struct { 621 #ifndef __BIG_ENDIAN_BITFIELD 622 u16 fdeCapable:1; 623 u16 fdeEnabled:1; 624 u16 secured:1; 625 u16 locked:1; 626 u16 foreign:1; 627 u16 needsEKM:1; 628 u16 reserved:10; 629 #else 630 u16 reserved:10; 631 u16 needsEKM:1; 632 u16 foreign:1; 633 u16 locked:1; 634 u16 secured:1; 635 u16 fdeEnabled:1; 636 u16 fdeCapable:1; 637 #endif 638 } security; 639 u8 mediaType; 640 u8 notCertified; 641 u8 bridgeVendor[8]; 642 u8 bridgeProductIdentification[16]; 643 u8 bridgeProductRevisionLevel[4]; 644 u8 satBridgeExists; 645 646 u8 interfaceType; 647 u8 temperature; 648 u8 emulatedBlockSize; 649 u16 userDataBlockSize; 650 u16 reserved2; 651 652 struct { 653 #ifndef __BIG_ENDIAN_BITFIELD 654 u32 piType:3; 655 u32 piFormatted:1; 656 u32 piEligible:1; 657 u32 NCQ:1; 658 u32 WCE:1; 659 u32 commissionedSpare:1; 660 u32 emergencySpare:1; 661 u32 ineligibleForSSCD:1; 662 u32 ineligibleForLd:1; 663 u32 useSSEraseType:1; 664 u32 wceUnchanged:1; 665 u32 supportScsiUnmap:1; 666 u32 reserved:18; 667 #else 668 u32 reserved:18; 669 u32 supportScsiUnmap:1; 670 u32 wceUnchanged:1; 671 u32 useSSEraseType:1; 672 u32 ineligibleForLd:1; 673 u32 ineligibleForSSCD:1; 674 u32 emergencySpare:1; 675 u32 commissionedSpare:1; 676 u32 WCE:1; 677 u32 NCQ:1; 678 u32 piEligible:1; 679 u32 piFormatted:1; 680 u32 piType:3; 681 #endif 682 } properties; 683 684 u64 shieldDiagCompletionTime; 685 u8 shieldCounter; 686 687 u8 linkSpeedOther; 688 u8 reserved4[2]; 689 690 struct { 691 #ifndef __BIG_ENDIAN_BITFIELD 692 u32 bbmErrCountSupported:1; 693 u32 bbmErrCount:31; 694 #else 695 u32 bbmErrCount:31; 696 u32 bbmErrCountSupported:1; 697 #endif 698 } bbmErr; 699 700 u8 reserved1[512-428]; 701 } __packed; 702 703 /* 704 * Definition of structure used to expose attributes of VD or JBOD 705 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP 706 * is fired by driver) 707 */ 708 struct MR_TARGET_PROPERTIES { 709 u32 max_io_size_kb; 710 u32 device_qdepth; 711 u32 sector_size; 712 u8 reserved[500]; 713 } __packed; 714 715 /* 716 * defines the physical drive address structure 717 */ 718 struct MR_PD_ADDRESS { 719 __le16 deviceId; 720 u16 enclDeviceId; 721 722 union { 723 struct { 724 u8 enclIndex; 725 u8 slotNumber; 726 } mrPdAddress; 727 struct { 728 u8 enclPosition; 729 u8 enclConnectorIndex; 730 } mrEnclAddress; 731 }; 732 u8 scsiDevType; 733 union { 734 u8 connectedPortBitmap; 735 u8 connectedPortNumbers; 736 }; 737 u64 sasAddr[2]; 738 } __packed; 739 740 /* 741 * defines the physical drive list structure 742 */ 743 struct MR_PD_LIST { 744 __le32 size; 745 __le32 count; 746 struct MR_PD_ADDRESS addr[1]; 747 } __packed; 748 749 struct megasas_pd_list { 750 u16 tid; 751 u8 driveType; 752 u8 driveState; 753 } __packed; 754 755 /* 756 * defines the logical drive reference structure 757 */ 758 union MR_LD_REF { 759 struct { 760 u8 targetId; 761 u8 reserved; 762 __le16 seqNum; 763 }; 764 __le32 ref; 765 } __packed; 766 767 /* 768 * defines the logical drive list structure 769 */ 770 struct MR_LD_LIST { 771 __le32 ldCount; 772 __le32 reserved; 773 struct { 774 union MR_LD_REF ref; 775 u8 state; 776 u8 reserved[3]; 777 __le64 size; 778 } ldList[MAX_LOGICAL_DRIVES_EXT]; 779 } __packed; 780 781 struct MR_LD_TARGETID_LIST { 782 __le32 size; 783 __le32 count; 784 u8 pad[3]; 785 u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 786 }; 787 788 789 /* 790 * SAS controller properties 791 */ 792 struct megasas_ctrl_prop { 793 794 u16 seq_num; 795 u16 pred_fail_poll_interval; 796 u16 intr_throttle_count; 797 u16 intr_throttle_timeouts; 798 u8 rebuild_rate; 799 u8 patrol_read_rate; 800 u8 bgi_rate; 801 u8 cc_rate; 802 u8 recon_rate; 803 u8 cache_flush_interval; 804 u8 spinup_drv_count; 805 u8 spinup_delay; 806 u8 cluster_enable; 807 u8 coercion_mode; 808 u8 alarm_enable; 809 u8 disable_auto_rebuild; 810 u8 disable_battery_warn; 811 u8 ecc_bucket_size; 812 u16 ecc_bucket_leak_rate; 813 u8 restore_hotspare_on_insertion; 814 u8 expose_encl_devices; 815 u8 maintainPdFailHistory; 816 u8 disallowHostRequestReordering; 817 u8 abortCCOnError; 818 u8 loadBalanceMode; 819 u8 disableAutoDetectBackplane; 820 821 u8 snapVDSpace; 822 823 /* 824 * Add properties that can be controlled by 825 * a bit in the following structure. 826 */ 827 struct { 828 #if defined(__BIG_ENDIAN_BITFIELD) 829 u32 reserved:18; 830 u32 enableJBOD:1; 831 u32 disableSpinDownHS:1; 832 u32 allowBootWithPinnedCache:1; 833 u32 disableOnlineCtrlReset:1; 834 u32 enableSecretKeyControl:1; 835 u32 autoEnhancedImport:1; 836 u32 enableSpinDownUnconfigured:1; 837 u32 SSDPatrolReadEnabled:1; 838 u32 SSDSMARTerEnabled:1; 839 u32 disableNCQ:1; 840 u32 useFdeOnly:1; 841 u32 prCorrectUnconfiguredAreas:1; 842 u32 SMARTerEnabled:1; 843 u32 copyBackDisabled:1; 844 #else 845 u32 copyBackDisabled:1; 846 u32 SMARTerEnabled:1; 847 u32 prCorrectUnconfiguredAreas:1; 848 u32 useFdeOnly:1; 849 u32 disableNCQ:1; 850 u32 SSDSMARTerEnabled:1; 851 u32 SSDPatrolReadEnabled:1; 852 u32 enableSpinDownUnconfigured:1; 853 u32 autoEnhancedImport:1; 854 u32 enableSecretKeyControl:1; 855 u32 disableOnlineCtrlReset:1; 856 u32 allowBootWithPinnedCache:1; 857 u32 disableSpinDownHS:1; 858 u32 enableJBOD:1; 859 u32 reserved:18; 860 #endif 861 } OnOffProperties; 862 u8 autoSnapVDSpace; 863 u8 viewSpace; 864 __le16 spinDownTime; 865 u8 reserved[24]; 866 } __packed; 867 868 /* 869 * SAS controller information 870 */ 871 struct megasas_ctrl_info { 872 873 /* 874 * PCI device information 875 */ 876 struct { 877 878 __le16 vendor_id; 879 __le16 device_id; 880 __le16 sub_vendor_id; 881 __le16 sub_device_id; 882 u8 reserved[24]; 883 884 } __attribute__ ((packed)) pci; 885 886 /* 887 * Host interface information 888 */ 889 struct { 890 891 u8 PCIX:1; 892 u8 PCIE:1; 893 u8 iSCSI:1; 894 u8 SAS_3G:1; 895 u8 SRIOV:1; 896 u8 reserved_0:3; 897 u8 reserved_1[6]; 898 u8 port_count; 899 u64 port_addr[8]; 900 901 } __attribute__ ((packed)) host_interface; 902 903 /* 904 * Device (backend) interface information 905 */ 906 struct { 907 908 u8 SPI:1; 909 u8 SAS_3G:1; 910 u8 SATA_1_5G:1; 911 u8 SATA_3G:1; 912 u8 reserved_0:4; 913 u8 reserved_1[6]; 914 u8 port_count; 915 u64 port_addr[8]; 916 917 } __attribute__ ((packed)) device_interface; 918 919 /* 920 * List of components residing in flash. All str are null terminated 921 */ 922 __le32 image_check_word; 923 __le32 image_component_count; 924 925 struct { 926 927 char name[8]; 928 char version[32]; 929 char build_date[16]; 930 char built_time[16]; 931 932 } __attribute__ ((packed)) image_component[8]; 933 934 /* 935 * List of flash components that have been flashed on the card, but 936 * are not in use, pending reset of the adapter. This list will be 937 * empty if a flash operation has not occurred. All stings are null 938 * terminated 939 */ 940 __le32 pending_image_component_count; 941 942 struct { 943 944 char name[8]; 945 char version[32]; 946 char build_date[16]; 947 char build_time[16]; 948 949 } __attribute__ ((packed)) pending_image_component[8]; 950 951 u8 max_arms; 952 u8 max_spans; 953 u8 max_arrays; 954 u8 max_lds; 955 956 char product_name[80]; 957 char serial_no[32]; 958 959 /* 960 * Other physical/controller/operation information. Indicates the 961 * presence of the hardware 962 */ 963 struct { 964 965 u32 bbu:1; 966 u32 alarm:1; 967 u32 nvram:1; 968 u32 uart:1; 969 u32 reserved:28; 970 971 } __attribute__ ((packed)) hw_present; 972 973 __le32 current_fw_time; 974 975 /* 976 * Maximum data transfer sizes 977 */ 978 __le16 max_concurrent_cmds; 979 __le16 max_sge_count; 980 __le32 max_request_size; 981 982 /* 983 * Logical and physical device counts 984 */ 985 __le16 ld_present_count; 986 __le16 ld_degraded_count; 987 __le16 ld_offline_count; 988 989 __le16 pd_present_count; 990 __le16 pd_disk_present_count; 991 __le16 pd_disk_pred_failure_count; 992 __le16 pd_disk_failed_count; 993 994 /* 995 * Memory size information 996 */ 997 __le16 nvram_size; 998 __le16 memory_size; 999 __le16 flash_size; 1000 1001 /* 1002 * Error counters 1003 */ 1004 __le16 mem_correctable_error_count; 1005 __le16 mem_uncorrectable_error_count; 1006 1007 /* 1008 * Cluster information 1009 */ 1010 u8 cluster_permitted; 1011 u8 cluster_active; 1012 1013 /* 1014 * Additional max data transfer sizes 1015 */ 1016 __le16 max_strips_per_io; 1017 1018 /* 1019 * Controller capabilities structures 1020 */ 1021 struct { 1022 1023 u32 raid_level_0:1; 1024 u32 raid_level_1:1; 1025 u32 raid_level_5:1; 1026 u32 raid_level_1E:1; 1027 u32 raid_level_6:1; 1028 u32 reserved:27; 1029 1030 } __attribute__ ((packed)) raid_levels; 1031 1032 struct { 1033 1034 u32 rbld_rate:1; 1035 u32 cc_rate:1; 1036 u32 bgi_rate:1; 1037 u32 recon_rate:1; 1038 u32 patrol_rate:1; 1039 u32 alarm_control:1; 1040 u32 cluster_supported:1; 1041 u32 bbu:1; 1042 u32 spanning_allowed:1; 1043 u32 dedicated_hotspares:1; 1044 u32 revertible_hotspares:1; 1045 u32 foreign_config_import:1; 1046 u32 self_diagnostic:1; 1047 u32 mixed_redundancy_arr:1; 1048 u32 global_hot_spares:1; 1049 u32 reserved:17; 1050 1051 } __attribute__ ((packed)) adapter_operations; 1052 1053 struct { 1054 1055 u32 read_policy:1; 1056 u32 write_policy:1; 1057 u32 io_policy:1; 1058 u32 access_policy:1; 1059 u32 disk_cache_policy:1; 1060 u32 reserved:27; 1061 1062 } __attribute__ ((packed)) ld_operations; 1063 1064 struct { 1065 1066 u8 min; 1067 u8 max; 1068 u8 reserved[2]; 1069 1070 } __attribute__ ((packed)) stripe_sz_ops; 1071 1072 struct { 1073 1074 u32 force_online:1; 1075 u32 force_offline:1; 1076 u32 force_rebuild:1; 1077 u32 reserved:29; 1078 1079 } __attribute__ ((packed)) pd_operations; 1080 1081 struct { 1082 1083 u32 ctrl_supports_sas:1; 1084 u32 ctrl_supports_sata:1; 1085 u32 allow_mix_in_encl:1; 1086 u32 allow_mix_in_ld:1; 1087 u32 allow_sata_in_cluster:1; 1088 u32 reserved:27; 1089 1090 } __attribute__ ((packed)) pd_mix_support; 1091 1092 /* 1093 * Define ECC single-bit-error bucket information 1094 */ 1095 u8 ecc_bucket_count; 1096 u8 reserved_2[11]; 1097 1098 /* 1099 * Include the controller properties (changeable items) 1100 */ 1101 struct megasas_ctrl_prop properties; 1102 1103 /* 1104 * Define FW pkg version (set in envt v'bles on OEM basis) 1105 */ 1106 char package_version[0x60]; 1107 1108 1109 /* 1110 * If adapterOperations.supportMoreThan8Phys is set, 1111 * and deviceInterface.portCount is greater than 8, 1112 * SAS Addrs for first 8 ports shall be populated in 1113 * deviceInterface.portAddr, and the rest shall be 1114 * populated in deviceInterfacePortAddr2. 1115 */ 1116 __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1117 u8 reserved3[128]; /*6e0h */ 1118 1119 struct { /*760h */ 1120 u16 minPdRaidLevel_0:4; 1121 u16 maxPdRaidLevel_0:12; 1122 1123 u16 minPdRaidLevel_1:4; 1124 u16 maxPdRaidLevel_1:12; 1125 1126 u16 minPdRaidLevel_5:4; 1127 u16 maxPdRaidLevel_5:12; 1128 1129 u16 minPdRaidLevel_1E:4; 1130 u16 maxPdRaidLevel_1E:12; 1131 1132 u16 minPdRaidLevel_6:4; 1133 u16 maxPdRaidLevel_6:12; 1134 1135 u16 minPdRaidLevel_10:4; 1136 u16 maxPdRaidLevel_10:12; 1137 1138 u16 minPdRaidLevel_50:4; 1139 u16 maxPdRaidLevel_50:12; 1140 1141 u16 minPdRaidLevel_60:4; 1142 u16 maxPdRaidLevel_60:12; 1143 1144 u16 minPdRaidLevel_1E_RLQ0:4; 1145 u16 maxPdRaidLevel_1E_RLQ0:12; 1146 1147 u16 minPdRaidLevel_1E0_RLQ0:4; 1148 u16 maxPdRaidLevel_1E0_RLQ0:12; 1149 1150 u16 reserved[6]; 1151 } pdsForRaidLevels; 1152 1153 __le16 maxPds; /*780h */ 1154 __le16 maxDedHSPs; /*782h */ 1155 __le16 maxGlobalHSP; /*784h */ 1156 __le16 ddfSize; /*786h */ 1157 u8 maxLdsPerArray; /*788h */ 1158 u8 partitionsInDDF; /*789h */ 1159 u8 lockKeyBinding; /*78ah */ 1160 u8 maxPITsPerLd; /*78bh */ 1161 u8 maxViewsPerLd; /*78ch */ 1162 u8 maxTargetId; /*78dh */ 1163 __le16 maxBvlVdSize; /*78eh */ 1164 1165 __le16 maxConfigurableSSCSize; /*790h */ 1166 __le16 currentSSCsize; /*792h */ 1167 1168 char expanderFwVersion[12]; /*794h */ 1169 1170 __le16 PFKTrialTimeRemaining; /*7A0h */ 1171 1172 __le16 cacheMemorySize; /*7A2h */ 1173 1174 struct { /*7A4h */ 1175 #if defined(__BIG_ENDIAN_BITFIELD) 1176 u32 reserved:5; 1177 u32 activePassive:2; 1178 u32 supportConfigAutoBalance:1; 1179 u32 mpio:1; 1180 u32 supportDataLDonSSCArray:1; 1181 u32 supportPointInTimeProgress:1; 1182 u32 supportUnevenSpans:1; 1183 u32 dedicatedHotSparesLimited:1; 1184 u32 headlessMode:1; 1185 u32 supportEmulatedDrives:1; 1186 u32 supportResetNow:1; 1187 u32 realTimeScheduler:1; 1188 u32 supportSSDPatrolRead:1; 1189 u32 supportPerfTuning:1; 1190 u32 disableOnlinePFKChange:1; 1191 u32 supportJBOD:1; 1192 u32 supportBootTimePFKChange:1; 1193 u32 supportSetLinkSpeed:1; 1194 u32 supportEmergencySpares:1; 1195 u32 supportSuspendResumeBGops:1; 1196 u32 blockSSDWriteCacheChange:1; 1197 u32 supportShieldState:1; 1198 u32 supportLdBBMInfo:1; 1199 u32 supportLdPIType3:1; 1200 u32 supportLdPIType2:1; 1201 u32 supportLdPIType1:1; 1202 u32 supportPIcontroller:1; 1203 #else 1204 u32 supportPIcontroller:1; 1205 u32 supportLdPIType1:1; 1206 u32 supportLdPIType2:1; 1207 u32 supportLdPIType3:1; 1208 u32 supportLdBBMInfo:1; 1209 u32 supportShieldState:1; 1210 u32 blockSSDWriteCacheChange:1; 1211 u32 supportSuspendResumeBGops:1; 1212 u32 supportEmergencySpares:1; 1213 u32 supportSetLinkSpeed:1; 1214 u32 supportBootTimePFKChange:1; 1215 u32 supportJBOD:1; 1216 u32 disableOnlinePFKChange:1; 1217 u32 supportPerfTuning:1; 1218 u32 supportSSDPatrolRead:1; 1219 u32 realTimeScheduler:1; 1220 1221 u32 supportResetNow:1; 1222 u32 supportEmulatedDrives:1; 1223 u32 headlessMode:1; 1224 u32 dedicatedHotSparesLimited:1; 1225 1226 1227 u32 supportUnevenSpans:1; 1228 u32 supportPointInTimeProgress:1; 1229 u32 supportDataLDonSSCArray:1; 1230 u32 mpio:1; 1231 u32 supportConfigAutoBalance:1; 1232 u32 activePassive:2; 1233 u32 reserved:5; 1234 #endif 1235 } adapterOperations2; 1236 1237 u8 driverVersion[32]; /*7A8h */ 1238 u8 maxDAPdCountSpinup60; /*7C8h */ 1239 u8 temperatureROC; /*7C9h */ 1240 u8 temperatureCtrl; /*7CAh */ 1241 u8 reserved4; /*7CBh */ 1242 __le16 maxConfigurablePds; /*7CCh */ 1243 1244 1245 u8 reserved5[2]; /*0x7CDh */ 1246 1247 /* 1248 * HA cluster information 1249 */ 1250 struct { 1251 #if defined(__BIG_ENDIAN_BITFIELD) 1252 u32 reserved:25; 1253 u32 passive:1; 1254 u32 premiumFeatureMismatch:1; 1255 u32 ctrlPropIncompatible:1; 1256 u32 fwVersionMismatch:1; 1257 u32 hwIncompatible:1; 1258 u32 peerIsIncompatible:1; 1259 u32 peerIsPresent:1; 1260 #else 1261 u32 peerIsPresent:1; 1262 u32 peerIsIncompatible:1; 1263 u32 hwIncompatible:1; 1264 u32 fwVersionMismatch:1; 1265 u32 ctrlPropIncompatible:1; 1266 u32 premiumFeatureMismatch:1; 1267 u32 passive:1; 1268 u32 reserved:25; 1269 #endif 1270 } cluster; 1271 1272 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1273 struct { 1274 u8 maxVFsSupported; /*0x7E4*/ 1275 u8 numVFsEnabled; /*0x7E5*/ 1276 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1277 u8 reserved; /*0x7E7*/ 1278 } iov; 1279 1280 struct { 1281 #if defined(__BIG_ENDIAN_BITFIELD) 1282 u32 reserved:7; 1283 u32 useSeqNumJbodFP:1; 1284 u32 supportExtendedSSCSize:1; 1285 u32 supportDiskCacheSettingForSysPDs:1; 1286 u32 supportCPLDUpdate:1; 1287 u32 supportTTYLogCompression:1; 1288 u32 discardCacheDuringLDDelete:1; 1289 u32 supportSecurityonJBOD:1; 1290 u32 supportCacheBypassModes:1; 1291 u32 supportDisableSESMonitoring:1; 1292 u32 supportForceFlash:1; 1293 u32 supportNVDRAM:1; 1294 u32 supportDrvActivityLEDSetting:1; 1295 u32 supportAllowedOpsforDrvRemoval:1; 1296 u32 supportHOQRebuild:1; 1297 u32 supportForceTo512e:1; 1298 u32 supportNVCacheErase:1; 1299 u32 supportDebugQueue:1; 1300 u32 supportSwZone:1; 1301 u32 supportCrashDump:1; 1302 u32 supportMaxExtLDs:1; 1303 u32 supportT10RebuildAssist:1; 1304 u32 supportDisableImmediateIO:1; 1305 u32 supportThermalPollInterval:1; 1306 u32 supportPersonalityChange:2; 1307 #else 1308 u32 supportPersonalityChange:2; 1309 u32 supportThermalPollInterval:1; 1310 u32 supportDisableImmediateIO:1; 1311 u32 supportT10RebuildAssist:1; 1312 u32 supportMaxExtLDs:1; 1313 u32 supportCrashDump:1; 1314 u32 supportSwZone:1; 1315 u32 supportDebugQueue:1; 1316 u32 supportNVCacheErase:1; 1317 u32 supportForceTo512e:1; 1318 u32 supportHOQRebuild:1; 1319 u32 supportAllowedOpsforDrvRemoval:1; 1320 u32 supportDrvActivityLEDSetting:1; 1321 u32 supportNVDRAM:1; 1322 u32 supportForceFlash:1; 1323 u32 supportDisableSESMonitoring:1; 1324 u32 supportCacheBypassModes:1; 1325 u32 supportSecurityonJBOD:1; 1326 u32 discardCacheDuringLDDelete:1; 1327 u32 supportTTYLogCompression:1; 1328 u32 supportCPLDUpdate:1; 1329 u32 supportDiskCacheSettingForSysPDs:1; 1330 u32 supportExtendedSSCSize:1; 1331 u32 useSeqNumJbodFP:1; 1332 u32 reserved:7; 1333 #endif 1334 } adapterOperations3; 1335 1336 struct { 1337 #if defined(__BIG_ENDIAN_BITFIELD) 1338 u8 reserved:7; 1339 /* Indicates whether the CPLD image is part of 1340 * the package and stored in flash 1341 */ 1342 u8 cpld_in_flash:1; 1343 #else 1344 u8 cpld_in_flash:1; 1345 u8 reserved:7; 1346 #endif 1347 u8 reserved1[3]; 1348 /* Null terminated string. Has the version 1349 * information if cpld_in_flash = FALSE 1350 */ 1351 u8 userCodeDefinition[12]; 1352 } cpld; /* Valid only if upgradableCPLD is TRUE */ 1353 1354 struct { 1355 #if defined(__BIG_ENDIAN_BITFIELD) 1356 u16 reserved:2; 1357 u16 support_nvme_passthru:1; 1358 u16 support_pl_debug_info:1; 1359 u16 support_flash_comp_info:1; 1360 u16 support_host_info:1; 1361 u16 support_dual_fw_update:1; 1362 u16 support_ssc_rev3:1; 1363 u16 fw_swaps_bbu_vpd_info:1; 1364 u16 support_pd_map_target_id:1; 1365 u16 support_ses_ctrl_in_multipathcfg:1; 1366 u16 image_upload_supported:1; 1367 u16 support_encrypted_mfc:1; 1368 u16 supported_enc_algo:1; 1369 u16 support_ibutton_less:1; 1370 u16 ctrl_info_ext_supported:1; 1371 #else 1372 1373 u16 ctrl_info_ext_supported:1; 1374 u16 support_ibutton_less:1; 1375 u16 supported_enc_algo:1; 1376 u16 support_encrypted_mfc:1; 1377 u16 image_upload_supported:1; 1378 /* FW supports LUN based association and target port based */ 1379 u16 support_ses_ctrl_in_multipathcfg:1; 1380 /* association for the SES device connected in multipath mode */ 1381 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */ 1382 u16 support_pd_map_target_id:1; 1383 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to 1384 * provide the data in little endian order 1385 */ 1386 u16 fw_swaps_bbu_vpd_info:1; 1387 u16 support_ssc_rev3:1; 1388 /* FW supports CacheCade 3.0, only one SSCD creation allowed */ 1389 u16 support_dual_fw_update:1; 1390 /* FW supports dual firmware update feature */ 1391 u16 support_host_info:1; 1392 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */ 1393 u16 support_flash_comp_info:1; 1394 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */ 1395 u16 support_pl_debug_info:1; 1396 /* FW supports retrieval of PL debug information through apps */ 1397 u16 support_nvme_passthru:1; 1398 /* FW supports NVMe passthru commands */ 1399 u16 reserved:2; 1400 #endif 1401 } adapter_operations4; 1402 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */ 1403 } __packed; 1404 1405 /* 1406 * =============================== 1407 * MegaRAID SAS driver definitions 1408 * =============================== 1409 */ 1410 #define MEGASAS_MAX_PD_CHANNELS 2 1411 #define MEGASAS_MAX_LD_CHANNELS 2 1412 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1413 MEGASAS_MAX_LD_CHANNELS) 1414 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1415 #define MEGASAS_DEFAULT_INIT_ID -1 1416 #define MEGASAS_MAX_LUN 8 1417 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 1418 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 1419 MEGASAS_MAX_DEV_PER_CHANNEL) 1420 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1421 MEGASAS_MAX_DEV_PER_CHANNEL) 1422 1423 #define MEGASAS_MAX_SECTORS (2*1024) 1424 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1425 #define MEGASAS_DBG_LVL 1 1426 1427 #define MEGASAS_FW_BUSY 1 1428 1429 /* Driver's internal Logging levels*/ 1430 #define OCR_LOGS (1 << 0) 1431 1432 #define SCAN_PD_CHANNEL 0x1 1433 #define SCAN_VD_CHANNEL 0x2 1434 1435 #define MEGASAS_KDUMP_QUEUE_DEPTH 100 1436 #define MR_LARGE_IO_MIN_SIZE (32 * 1024) 1437 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4 1438 1439 enum MR_SCSI_CMD_TYPE { 1440 READ_WRITE_LDIO = 0, 1441 NON_READ_WRITE_LDIO = 1, 1442 READ_WRITE_SYSPDIO = 2, 1443 NON_READ_WRITE_SYSPDIO = 3, 1444 }; 1445 1446 enum DCMD_TIMEOUT_ACTION { 1447 INITIATE_OCR = 0, 1448 KILL_ADAPTER = 1, 1449 IGNORE_TIMEOUT = 2, 1450 }; 1451 1452 enum FW_BOOT_CONTEXT { 1453 PROBE_CONTEXT = 0, 1454 OCR_CONTEXT = 1, 1455 }; 1456 1457 /* Frame Type */ 1458 #define IO_FRAME 0 1459 #define PTHRU_FRAME 1 1460 1461 /* 1462 * When SCSI mid-layer calls driver's reset routine, driver waits for 1463 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1464 * that the driver cannot _actually_ abort or reset pending commands. While 1465 * it is waiting for the commands to complete, it prints a diagnostic message 1466 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1467 */ 1468 #define MEGASAS_RESET_WAIT_TIME 180 1469 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1470 #define MEGASAS_RESET_NOTICE_INTERVAL 5 1471 #define MEGASAS_IOCTL_CMD 0 1472 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1473 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1474 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1475 /* 1476 * FW reports the maximum of number of commands that it can accept (maximum 1477 * commands that can be outstanding) at any time. The driver must report a 1478 * lower number to the mid layer because it can issue a few internal commands 1479 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1480 * is shown below 1481 */ 1482 #define MEGASAS_INT_CMDS 32 1483 #define MEGASAS_SKINNY_INT_CMDS 5 1484 #define MEGASAS_FUSION_INTERNAL_CMDS 8 1485 #define MEGASAS_FUSION_IOCTL_CMDS 3 1486 #define MEGASAS_MFI_IOCTL_CMDS 27 1487 1488 #define MEGASAS_MAX_MSIX_QUEUES 128 1489 /* 1490 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1491 * SGLs based on the size of dma_addr_t 1492 */ 1493 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1494 1495 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1496 1497 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1498 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1499 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1500 1501 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1502 #define MFI_POLL_TIMEOUT_SECS 60 1503 #define MFI_IO_TIMEOUT_SECS 180 1504 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1505 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1506 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1507 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1508 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1509 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1510 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1511 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1512 1513 #define MFI_1068_PCSR_OFFSET 0x84 1514 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1515 #define MFI_1068_FW_READY 0xDDDD0000 1516 1517 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1518 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1519 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1520 #define MR_MAX_MSIX_REG_ARRAY 16 1521 #define MR_RDPQ_MODE_OFFSET 0X00800000 1522 1523 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1524 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1525 #define MR_MIN_MAP_SIZE 0x10000 1526 /* 64k */ 1527 1528 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 1529 1530 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25) 1531 1532 enum MR_ADAPTER_TYPE { 1533 MFI_SERIES = 1, 1534 THUNDERBOLT_SERIES = 2, 1535 INVADER_SERIES = 3, 1536 VENTURA_SERIES = 4, 1537 }; 1538 1539 /* 1540 * register set for both 1068 and 1078 controllers 1541 * structure extended for 1078 registers 1542 */ 1543 1544 struct megasas_register_set { 1545 u32 doorbell; /*0000h*/ 1546 u32 fusion_seq_offset; /*0004h*/ 1547 u32 fusion_host_diag; /*0008h*/ 1548 u32 reserved_01; /*000Ch*/ 1549 1550 u32 inbound_msg_0; /*0010h*/ 1551 u32 inbound_msg_1; /*0014h*/ 1552 u32 outbound_msg_0; /*0018h*/ 1553 u32 outbound_msg_1; /*001Ch*/ 1554 1555 u32 inbound_doorbell; /*0020h*/ 1556 u32 inbound_intr_status; /*0024h*/ 1557 u32 inbound_intr_mask; /*0028h*/ 1558 1559 u32 outbound_doorbell; /*002Ch*/ 1560 u32 outbound_intr_status; /*0030h*/ 1561 u32 outbound_intr_mask; /*0034h*/ 1562 1563 u32 reserved_1[2]; /*0038h*/ 1564 1565 u32 inbound_queue_port; /*0040h*/ 1566 u32 outbound_queue_port; /*0044h*/ 1567 1568 u32 reserved_2[9]; /*0048h*/ 1569 u32 reply_post_host_index; /*006Ch*/ 1570 u32 reserved_2_2[12]; /*0070h*/ 1571 1572 u32 outbound_doorbell_clear; /*00A0h*/ 1573 1574 u32 reserved_3[3]; /*00A4h*/ 1575 1576 u32 outbound_scratch_pad ; /*00B0h*/ 1577 u32 outbound_scratch_pad_2; /*00B4h*/ 1578 u32 outbound_scratch_pad_3; /*00B8h*/ 1579 u32 outbound_scratch_pad_4; /*00BCh*/ 1580 1581 1582 u32 inbound_low_queue_port ; /*00C0h*/ 1583 1584 u32 inbound_high_queue_port ; /*00C4h*/ 1585 1586 u32 inbound_single_queue_port; /*00C8h*/ 1587 u32 res_6[11]; /*CCh*/ 1588 u32 host_diag; 1589 u32 seq_offset; 1590 u32 index_registers[807]; /*00CCh*/ 1591 } __attribute__ ((packed)); 1592 1593 struct megasas_sge32 { 1594 1595 __le32 phys_addr; 1596 __le32 length; 1597 1598 } __attribute__ ((packed)); 1599 1600 struct megasas_sge64 { 1601 1602 __le64 phys_addr; 1603 __le32 length; 1604 1605 } __attribute__ ((packed)); 1606 1607 struct megasas_sge_skinny { 1608 __le64 phys_addr; 1609 __le32 length; 1610 __le32 flag; 1611 } __packed; 1612 1613 union megasas_sgl { 1614 1615 struct megasas_sge32 sge32[1]; 1616 struct megasas_sge64 sge64[1]; 1617 struct megasas_sge_skinny sge_skinny[1]; 1618 1619 } __attribute__ ((packed)); 1620 1621 struct megasas_header { 1622 1623 u8 cmd; /*00h */ 1624 u8 sense_len; /*01h */ 1625 u8 cmd_status; /*02h */ 1626 u8 scsi_status; /*03h */ 1627 1628 u8 target_id; /*04h */ 1629 u8 lun; /*05h */ 1630 u8 cdb_len; /*06h */ 1631 u8 sge_count; /*07h */ 1632 1633 __le32 context; /*08h */ 1634 __le32 pad_0; /*0Ch */ 1635 1636 __le16 flags; /*10h */ 1637 __le16 timeout; /*12h */ 1638 __le32 data_xferlen; /*14h */ 1639 1640 } __attribute__ ((packed)); 1641 1642 union megasas_sgl_frame { 1643 1644 struct megasas_sge32 sge32[8]; 1645 struct megasas_sge64 sge64[5]; 1646 1647 } __attribute__ ((packed)); 1648 1649 typedef union _MFI_CAPABILITIES { 1650 struct { 1651 #if defined(__BIG_ENDIAN_BITFIELD) 1652 u32 reserved:17; 1653 u32 support_nvme_passthru:1; 1654 u32 support_64bit_mode:1; 1655 u32 support_pd_map_target_id:1; 1656 u32 support_qd_throttling:1; 1657 u32 support_fp_rlbypass:1; 1658 u32 support_vfid_in_ioframe:1; 1659 u32 support_ext_io_size:1; 1660 u32 support_ext_queue_depth:1; 1661 u32 security_protocol_cmds_fw:1; 1662 u32 support_core_affinity:1; 1663 u32 support_ndrive_r1_lb:1; 1664 u32 support_max_255lds:1; 1665 u32 support_fastpath_wb:1; 1666 u32 support_additional_msix:1; 1667 u32 support_fp_remote_lun:1; 1668 #else 1669 u32 support_fp_remote_lun:1; 1670 u32 support_additional_msix:1; 1671 u32 support_fastpath_wb:1; 1672 u32 support_max_255lds:1; 1673 u32 support_ndrive_r1_lb:1; 1674 u32 support_core_affinity:1; 1675 u32 security_protocol_cmds_fw:1; 1676 u32 support_ext_queue_depth:1; 1677 u32 support_ext_io_size:1; 1678 u32 support_vfid_in_ioframe:1; 1679 u32 support_fp_rlbypass:1; 1680 u32 support_qd_throttling:1; 1681 u32 support_pd_map_target_id:1; 1682 u32 support_64bit_mode:1; 1683 u32 support_nvme_passthru:1; 1684 u32 reserved:17; 1685 #endif 1686 } mfi_capabilities; 1687 __le32 reg; 1688 } MFI_CAPABILITIES; 1689 1690 struct megasas_init_frame { 1691 1692 u8 cmd; /*00h */ 1693 u8 reserved_0; /*01h */ 1694 u8 cmd_status; /*02h */ 1695 1696 u8 reserved_1; /*03h */ 1697 MFI_CAPABILITIES driver_operations; /*04h*/ 1698 1699 __le32 context; /*08h */ 1700 __le32 pad_0; /*0Ch */ 1701 1702 __le16 flags; /*10h */ 1703 __le16 reserved_3; /*12h */ 1704 __le32 data_xfer_len; /*14h */ 1705 1706 __le32 queue_info_new_phys_addr_lo; /*18h */ 1707 __le32 queue_info_new_phys_addr_hi; /*1Ch */ 1708 __le32 queue_info_old_phys_addr_lo; /*20h */ 1709 __le32 queue_info_old_phys_addr_hi; /*24h */ 1710 __le32 reserved_4[2]; /*28h */ 1711 __le32 system_info_lo; /*30h */ 1712 __le32 system_info_hi; /*34h */ 1713 __le32 reserved_5[2]; /*38h */ 1714 1715 } __attribute__ ((packed)); 1716 1717 struct megasas_init_queue_info { 1718 1719 __le32 init_flags; /*00h */ 1720 __le32 reply_queue_entries; /*04h */ 1721 1722 __le32 reply_queue_start_phys_addr_lo; /*08h */ 1723 __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 1724 __le32 producer_index_phys_addr_lo; /*10h */ 1725 __le32 producer_index_phys_addr_hi; /*14h */ 1726 __le32 consumer_index_phys_addr_lo; /*18h */ 1727 __le32 consumer_index_phys_addr_hi; /*1Ch */ 1728 1729 } __attribute__ ((packed)); 1730 1731 struct megasas_io_frame { 1732 1733 u8 cmd; /*00h */ 1734 u8 sense_len; /*01h */ 1735 u8 cmd_status; /*02h */ 1736 u8 scsi_status; /*03h */ 1737 1738 u8 target_id; /*04h */ 1739 u8 access_byte; /*05h */ 1740 u8 reserved_0; /*06h */ 1741 u8 sge_count; /*07h */ 1742 1743 __le32 context; /*08h */ 1744 __le32 pad_0; /*0Ch */ 1745 1746 __le16 flags; /*10h */ 1747 __le16 timeout; /*12h */ 1748 __le32 lba_count; /*14h */ 1749 1750 __le32 sense_buf_phys_addr_lo; /*18h */ 1751 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1752 1753 __le32 start_lba_lo; /*20h */ 1754 __le32 start_lba_hi; /*24h */ 1755 1756 union megasas_sgl sgl; /*28h */ 1757 1758 } __attribute__ ((packed)); 1759 1760 struct megasas_pthru_frame { 1761 1762 u8 cmd; /*00h */ 1763 u8 sense_len; /*01h */ 1764 u8 cmd_status; /*02h */ 1765 u8 scsi_status; /*03h */ 1766 1767 u8 target_id; /*04h */ 1768 u8 lun; /*05h */ 1769 u8 cdb_len; /*06h */ 1770 u8 sge_count; /*07h */ 1771 1772 __le32 context; /*08h */ 1773 __le32 pad_0; /*0Ch */ 1774 1775 __le16 flags; /*10h */ 1776 __le16 timeout; /*12h */ 1777 __le32 data_xfer_len; /*14h */ 1778 1779 __le32 sense_buf_phys_addr_lo; /*18h */ 1780 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1781 1782 u8 cdb[16]; /*20h */ 1783 union megasas_sgl sgl; /*30h */ 1784 1785 } __attribute__ ((packed)); 1786 1787 struct megasas_dcmd_frame { 1788 1789 u8 cmd; /*00h */ 1790 u8 reserved_0; /*01h */ 1791 u8 cmd_status; /*02h */ 1792 u8 reserved_1[4]; /*03h */ 1793 u8 sge_count; /*07h */ 1794 1795 __le32 context; /*08h */ 1796 __le32 pad_0; /*0Ch */ 1797 1798 __le16 flags; /*10h */ 1799 __le16 timeout; /*12h */ 1800 1801 __le32 data_xfer_len; /*14h */ 1802 __le32 opcode; /*18h */ 1803 1804 union { /*1Ch */ 1805 u8 b[12]; 1806 __le16 s[6]; 1807 __le32 w[3]; 1808 } mbox; 1809 1810 union megasas_sgl sgl; /*28h */ 1811 1812 } __attribute__ ((packed)); 1813 1814 struct megasas_abort_frame { 1815 1816 u8 cmd; /*00h */ 1817 u8 reserved_0; /*01h */ 1818 u8 cmd_status; /*02h */ 1819 1820 u8 reserved_1; /*03h */ 1821 __le32 reserved_2; /*04h */ 1822 1823 __le32 context; /*08h */ 1824 __le32 pad_0; /*0Ch */ 1825 1826 __le16 flags; /*10h */ 1827 __le16 reserved_3; /*12h */ 1828 __le32 reserved_4; /*14h */ 1829 1830 __le32 abort_context; /*18h */ 1831 __le32 pad_1; /*1Ch */ 1832 1833 __le32 abort_mfi_phys_addr_lo; /*20h */ 1834 __le32 abort_mfi_phys_addr_hi; /*24h */ 1835 1836 __le32 reserved_5[6]; /*28h */ 1837 1838 } __attribute__ ((packed)); 1839 1840 struct megasas_smp_frame { 1841 1842 u8 cmd; /*00h */ 1843 u8 reserved_1; /*01h */ 1844 u8 cmd_status; /*02h */ 1845 u8 connection_status; /*03h */ 1846 1847 u8 reserved_2[3]; /*04h */ 1848 u8 sge_count; /*07h */ 1849 1850 __le32 context; /*08h */ 1851 __le32 pad_0; /*0Ch */ 1852 1853 __le16 flags; /*10h */ 1854 __le16 timeout; /*12h */ 1855 1856 __le32 data_xfer_len; /*14h */ 1857 __le64 sas_addr; /*18h */ 1858 1859 union { 1860 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1861 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1862 } sgl; 1863 1864 } __attribute__ ((packed)); 1865 1866 struct megasas_stp_frame { 1867 1868 u8 cmd; /*00h */ 1869 u8 reserved_1; /*01h */ 1870 u8 cmd_status; /*02h */ 1871 u8 reserved_2; /*03h */ 1872 1873 u8 target_id; /*04h */ 1874 u8 reserved_3[2]; /*05h */ 1875 u8 sge_count; /*07h */ 1876 1877 __le32 context; /*08h */ 1878 __le32 pad_0; /*0Ch */ 1879 1880 __le16 flags; /*10h */ 1881 __le16 timeout; /*12h */ 1882 1883 __le32 data_xfer_len; /*14h */ 1884 1885 __le16 fis[10]; /*18h */ 1886 __le32 stp_flags; 1887 1888 union { 1889 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1890 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1891 } sgl; 1892 1893 } __attribute__ ((packed)); 1894 1895 union megasas_frame { 1896 1897 struct megasas_header hdr; 1898 struct megasas_init_frame init; 1899 struct megasas_io_frame io; 1900 struct megasas_pthru_frame pthru; 1901 struct megasas_dcmd_frame dcmd; 1902 struct megasas_abort_frame abort; 1903 struct megasas_smp_frame smp; 1904 struct megasas_stp_frame stp; 1905 1906 u8 raw_bytes[64]; 1907 }; 1908 1909 /** 1910 * struct MR_PRIV_DEVICE - sdev private hostdata 1911 * @is_tm_capable: firmware managed tm_capable flag 1912 * @tm_busy: TM request is in progress 1913 */ 1914 struct MR_PRIV_DEVICE { 1915 bool is_tm_capable; 1916 bool tm_busy; 1917 atomic_t r1_ldio_hint; 1918 u8 interface_type; 1919 }; 1920 struct megasas_cmd; 1921 1922 union megasas_evt_class_locale { 1923 1924 struct { 1925 #ifndef __BIG_ENDIAN_BITFIELD 1926 u16 locale; 1927 u8 reserved; 1928 s8 class; 1929 #else 1930 s8 class; 1931 u8 reserved; 1932 u16 locale; 1933 #endif 1934 } __attribute__ ((packed)) members; 1935 1936 u32 word; 1937 1938 } __attribute__ ((packed)); 1939 1940 struct megasas_evt_log_info { 1941 __le32 newest_seq_num; 1942 __le32 oldest_seq_num; 1943 __le32 clear_seq_num; 1944 __le32 shutdown_seq_num; 1945 __le32 boot_seq_num; 1946 1947 } __attribute__ ((packed)); 1948 1949 struct megasas_progress { 1950 1951 __le16 progress; 1952 __le16 elapsed_seconds; 1953 1954 } __attribute__ ((packed)); 1955 1956 struct megasas_evtarg_ld { 1957 1958 u16 target_id; 1959 u8 ld_index; 1960 u8 reserved; 1961 1962 } __attribute__ ((packed)); 1963 1964 struct megasas_evtarg_pd { 1965 u16 device_id; 1966 u8 encl_index; 1967 u8 slot_number; 1968 1969 } __attribute__ ((packed)); 1970 1971 struct megasas_evt_detail { 1972 1973 __le32 seq_num; 1974 __le32 time_stamp; 1975 __le32 code; 1976 union megasas_evt_class_locale cl; 1977 u8 arg_type; 1978 u8 reserved1[15]; 1979 1980 union { 1981 struct { 1982 struct megasas_evtarg_pd pd; 1983 u8 cdb_length; 1984 u8 sense_length; 1985 u8 reserved[2]; 1986 u8 cdb[16]; 1987 u8 sense[64]; 1988 } __attribute__ ((packed)) cdbSense; 1989 1990 struct megasas_evtarg_ld ld; 1991 1992 struct { 1993 struct megasas_evtarg_ld ld; 1994 __le64 count; 1995 } __attribute__ ((packed)) ld_count; 1996 1997 struct { 1998 __le64 lba; 1999 struct megasas_evtarg_ld ld; 2000 } __attribute__ ((packed)) ld_lba; 2001 2002 struct { 2003 struct megasas_evtarg_ld ld; 2004 __le32 prevOwner; 2005 __le32 newOwner; 2006 } __attribute__ ((packed)) ld_owner; 2007 2008 struct { 2009 u64 ld_lba; 2010 u64 pd_lba; 2011 struct megasas_evtarg_ld ld; 2012 struct megasas_evtarg_pd pd; 2013 } __attribute__ ((packed)) ld_lba_pd_lba; 2014 2015 struct { 2016 struct megasas_evtarg_ld ld; 2017 struct megasas_progress prog; 2018 } __attribute__ ((packed)) ld_prog; 2019 2020 struct { 2021 struct megasas_evtarg_ld ld; 2022 u32 prev_state; 2023 u32 new_state; 2024 } __attribute__ ((packed)) ld_state; 2025 2026 struct { 2027 u64 strip; 2028 struct megasas_evtarg_ld ld; 2029 } __attribute__ ((packed)) ld_strip; 2030 2031 struct megasas_evtarg_pd pd; 2032 2033 struct { 2034 struct megasas_evtarg_pd pd; 2035 u32 err; 2036 } __attribute__ ((packed)) pd_err; 2037 2038 struct { 2039 u64 lba; 2040 struct megasas_evtarg_pd pd; 2041 } __attribute__ ((packed)) pd_lba; 2042 2043 struct { 2044 u64 lba; 2045 struct megasas_evtarg_pd pd; 2046 struct megasas_evtarg_ld ld; 2047 } __attribute__ ((packed)) pd_lba_ld; 2048 2049 struct { 2050 struct megasas_evtarg_pd pd; 2051 struct megasas_progress prog; 2052 } __attribute__ ((packed)) pd_prog; 2053 2054 struct { 2055 struct megasas_evtarg_pd pd; 2056 u32 prevState; 2057 u32 newState; 2058 } __attribute__ ((packed)) pd_state; 2059 2060 struct { 2061 u16 vendorId; 2062 __le16 deviceId; 2063 u16 subVendorId; 2064 u16 subDeviceId; 2065 } __attribute__ ((packed)) pci; 2066 2067 u32 rate; 2068 char str[96]; 2069 2070 struct { 2071 u32 rtc; 2072 u32 elapsedSeconds; 2073 } __attribute__ ((packed)) time; 2074 2075 struct { 2076 u32 ecar; 2077 u32 elog; 2078 char str[64]; 2079 } __attribute__ ((packed)) ecc; 2080 2081 u8 b[96]; 2082 __le16 s[48]; 2083 __le32 w[24]; 2084 __le64 d[12]; 2085 } args; 2086 2087 char description[128]; 2088 2089 } __attribute__ ((packed)); 2090 2091 struct megasas_aen_event { 2092 struct delayed_work hotplug_work; 2093 struct megasas_instance *instance; 2094 }; 2095 2096 struct megasas_irq_context { 2097 struct megasas_instance *instance; 2098 u32 MSIxIndex; 2099 }; 2100 2101 struct MR_DRV_SYSTEM_INFO { 2102 u8 infoVersion; 2103 u8 systemIdLength; 2104 u16 reserved0; 2105 u8 systemId[64]; 2106 u8 reserved[1980]; 2107 }; 2108 2109 enum MR_PD_TYPE { 2110 UNKNOWN_DRIVE = 0, 2111 PARALLEL_SCSI = 1, 2112 SAS_PD = 2, 2113 SATA_PD = 3, 2114 FC_PD = 4, 2115 NVME_PD = 5, 2116 }; 2117 2118 /* JBOD Queue depth definitions */ 2119 #define MEGASAS_SATA_QD 32 2120 #define MEGASAS_SAS_QD 64 2121 #define MEGASAS_DEFAULT_PD_QD 64 2122 #define MEGASAS_NVME_QD 32 2123 2124 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 2125 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 2126 #define MR_DEFAULT_NVME_MDTS_KB 128 2127 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 2128 2129 struct megasas_instance { 2130 2131 __le32 *producer; 2132 dma_addr_t producer_h; 2133 __le32 *consumer; 2134 dma_addr_t consumer_h; 2135 struct MR_DRV_SYSTEM_INFO *system_info_buf; 2136 dma_addr_t system_info_h; 2137 struct MR_LD_VF_AFFILIATION *vf_affiliation; 2138 dma_addr_t vf_affiliation_h; 2139 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2140 dma_addr_t vf_affiliation_111_h; 2141 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2142 dma_addr_t hb_host_mem_h; 2143 struct MR_PD_INFO *pd_info; 2144 dma_addr_t pd_info_h; 2145 struct MR_TARGET_PROPERTIES *tgt_prop; 2146 dma_addr_t tgt_prop_h; 2147 2148 __le32 *reply_queue; 2149 dma_addr_t reply_queue_h; 2150 2151 u32 *crash_dump_buf; 2152 dma_addr_t crash_dump_h; 2153 2154 struct MR_PD_LIST *pd_list_buf; 2155 dma_addr_t pd_list_buf_h; 2156 2157 struct megasas_ctrl_info *ctrl_info_buf; 2158 dma_addr_t ctrl_info_buf_h; 2159 2160 struct MR_LD_LIST *ld_list_buf; 2161 dma_addr_t ld_list_buf_h; 2162 2163 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf; 2164 dma_addr_t ld_targetid_list_buf_h; 2165 2166 void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2167 unsigned int fw_crash_buffer_size; 2168 unsigned int fw_crash_state; 2169 unsigned int fw_crash_buffer_offset; 2170 u32 drv_buf_index; 2171 u32 drv_buf_alloc; 2172 u32 crash_dump_fw_support; 2173 u32 crash_dump_drv_support; 2174 u32 crash_dump_app_support; 2175 u32 secure_jbod_support; 2176 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ 2177 bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2178 spinlock_t crashdump_lock; 2179 2180 struct megasas_register_set __iomem *reg_set; 2181 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 2182 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2183 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2184 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2185 s8 init_id; 2186 2187 u16 max_num_sge; 2188 u16 max_fw_cmds; 2189 u16 max_mpt_cmds; 2190 u16 max_mfi_cmds; 2191 u16 max_scsi_cmds; 2192 u16 ldio_threshold; 2193 u16 cur_can_queue; 2194 u32 max_sectors_per_req; 2195 struct megasas_aen_event *ev; 2196 2197 struct megasas_cmd **cmd_list; 2198 struct list_head cmd_pool; 2199 /* used to sync fire the cmd to fw */ 2200 spinlock_t mfi_pool_lock; 2201 /* used to sync fire the cmd to fw */ 2202 spinlock_t hba_lock; 2203 /* used to synch producer, consumer ptrs in dpc */ 2204 spinlock_t stream_lock; 2205 spinlock_t completion_lock; 2206 struct dma_pool *frame_dma_pool; 2207 struct dma_pool *sense_dma_pool; 2208 2209 struct megasas_evt_detail *evt_detail; 2210 dma_addr_t evt_detail_h; 2211 struct megasas_cmd *aen_cmd; 2212 struct semaphore ioctl_sem; 2213 2214 struct Scsi_Host *host; 2215 2216 wait_queue_head_t int_cmd_wait_q; 2217 wait_queue_head_t abort_cmd_wait_q; 2218 2219 struct pci_dev *pdev; 2220 u32 unique_id; 2221 u32 fw_support_ieee; 2222 2223 atomic_t fw_outstanding; 2224 atomic_t ldio_outstanding; 2225 atomic_t fw_reset_no_pci_access; 2226 atomic_t ieee_sgl; 2227 atomic_t prp_sgl; 2228 atomic_t sge_holes_type1; 2229 atomic_t sge_holes_type2; 2230 atomic_t sge_holes_type3; 2231 2232 struct megasas_instance_template *instancet; 2233 struct tasklet_struct isr_tasklet; 2234 struct work_struct work_init; 2235 struct work_struct crash_init; 2236 2237 u8 flag; 2238 u8 unload; 2239 u8 flag_ieee; 2240 u8 issuepend_done; 2241 u8 disableOnlineCtrlReset; 2242 u8 UnevenSpanSupport; 2243 2244 u8 supportmax256vd; 2245 u8 pd_list_not_supported; 2246 u16 fw_supported_vd_count; 2247 u16 fw_supported_pd_count; 2248 2249 u16 drv_supported_vd_count; 2250 u16 drv_supported_pd_count; 2251 2252 atomic_t adprecovery; 2253 unsigned long last_time; 2254 u32 mfiStatus; 2255 u32 last_seq_num; 2256 2257 struct list_head internal_reset_pending_q; 2258 2259 /* Ptr to hba specific information */ 2260 void *ctrl_context; 2261 unsigned int msix_vectors; 2262 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 2263 u64 map_id; 2264 u64 pd_seq_map_id; 2265 struct megasas_cmd *map_update_cmd; 2266 struct megasas_cmd *jbod_seq_cmd; 2267 unsigned long bar; 2268 long reset_flags; 2269 struct mutex reset_mutex; 2270 struct timer_list sriov_heartbeat_timer; 2271 char skip_heartbeat_timer_del; 2272 u8 requestorId; 2273 char PlasmaFW111; 2274 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 2275 u8 peerIsPresent; 2276 u8 passive; 2277 u16 throttlequeuedepth; 2278 u8 mask_interrupts; 2279 u16 max_chain_frame_sz; 2280 u8 is_imr; 2281 u8 is_rdpq; 2282 bool dev_handle; 2283 bool fw_sync_cache_support; 2284 u32 mfi_frame_size; 2285 bool msix_combined; 2286 u16 max_raid_mapsize; 2287 /* preffered count to send as LDIO irrspective of FP capable.*/ 2288 u8 r1_ldio_hint_default; 2289 u32 nvme_page_size; 2290 u8 adapter_type; 2291 bool consistent_mask_64bit; 2292 bool support_nvme_passthru; 2293 }; 2294 struct MR_LD_VF_MAP { 2295 u32 size; 2296 union MR_LD_REF ref; 2297 u8 ldVfCount; 2298 u8 reserved[6]; 2299 u8 policy[1]; 2300 }; 2301 2302 struct MR_LD_VF_AFFILIATION { 2303 u32 size; 2304 u8 ldCount; 2305 u8 vfCount; 2306 u8 thisVf; 2307 u8 reserved[9]; 2308 struct MR_LD_VF_MAP map[1]; 2309 }; 2310 2311 /* Plasma 1.11 FW backward compatibility structures */ 2312 #define IOV_111_OFFSET 0x7CE 2313 #define MAX_VIRTUAL_FUNCTIONS 8 2314 #define MR_LD_ACCESS_HIDDEN 15 2315 2316 struct IOV_111 { 2317 u8 maxVFsSupported; 2318 u8 numVFsEnabled; 2319 u8 requestorId; 2320 u8 reserved[5]; 2321 }; 2322 2323 struct MR_LD_VF_MAP_111 { 2324 u8 targetId; 2325 u8 reserved[3]; 2326 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2327 }; 2328 2329 struct MR_LD_VF_AFFILIATION_111 { 2330 u8 vdCount; 2331 u8 vfCount; 2332 u8 thisVf; 2333 u8 reserved[5]; 2334 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2335 }; 2336 2337 struct MR_CTRL_HB_HOST_MEM { 2338 struct { 2339 u32 fwCounter; /* Firmware heart beat counter */ 2340 struct { 2341 u32 debugmode:1; /* 1=Firmware is in debug mode. 2342 Heart beat will not be updated. */ 2343 u32 reserved:31; 2344 } debug; 2345 u32 reserved_fw[6]; 2346 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2347 u32 reserved_driver[7]; 2348 } HB; 2349 u8 pad[0x400-0x40]; 2350 }; 2351 2352 enum { 2353 MEGASAS_HBA_OPERATIONAL = 0, 2354 MEGASAS_ADPRESET_SM_INFAULT = 1, 2355 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 2356 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 2357 MEGASAS_HW_CRITICAL_ERROR = 4, 2358 MEGASAS_ADPRESET_SM_POLLING = 5, 2359 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2360 }; 2361 2362 struct megasas_instance_template { 2363 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 2364 u32, struct megasas_register_set __iomem *); 2365 2366 void (*enable_intr)(struct megasas_instance *); 2367 void (*disable_intr)(struct megasas_instance *); 2368 2369 int (*clear_intr)(struct megasas_register_set __iomem *); 2370 2371 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 2372 int (*adp_reset)(struct megasas_instance *, \ 2373 struct megasas_register_set __iomem *); 2374 int (*check_reset)(struct megasas_instance *, \ 2375 struct megasas_register_set __iomem *); 2376 irqreturn_t (*service_isr)(int irq, void *devp); 2377 void (*tasklet)(unsigned long); 2378 u32 (*init_adapter)(struct megasas_instance *); 2379 u32 (*build_and_issue_cmd) (struct megasas_instance *, 2380 struct scsi_cmnd *); 2381 void (*issue_dcmd)(struct megasas_instance *instance, 2382 struct megasas_cmd *cmd); 2383 }; 2384 2385 #define MEGASAS_IS_LOGICAL(sdev) \ 2386 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) 2387 2388 #define MEGASAS_DEV_INDEX(scp) \ 2389 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2390 scp->device->id) 2391 2392 #define MEGASAS_PD_INDEX(scp) \ 2393 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2394 scp->device->id) 2395 2396 struct megasas_cmd { 2397 2398 union megasas_frame *frame; 2399 dma_addr_t frame_phys_addr; 2400 u8 *sense; 2401 dma_addr_t sense_phys_addr; 2402 2403 u32 index; 2404 u8 sync_cmd; 2405 u8 cmd_status_drv; 2406 u8 abort_aen; 2407 u8 retry_for_fw_reset; 2408 2409 2410 struct list_head list; 2411 struct scsi_cmnd *scmd; 2412 u8 flags; 2413 2414 struct megasas_instance *instance; 2415 union { 2416 struct { 2417 u16 smid; 2418 u16 resvd; 2419 } context; 2420 u32 frame_count; 2421 }; 2422 }; 2423 2424 #define MAX_MGMT_ADAPTERS 1024 2425 #define MAX_IOCTL_SGE 16 2426 2427 struct megasas_iocpacket { 2428 2429 u16 host_no; 2430 u16 __pad1; 2431 u32 sgl_off; 2432 u32 sge_count; 2433 u32 sense_off; 2434 u32 sense_len; 2435 union { 2436 u8 raw[128]; 2437 struct megasas_header hdr; 2438 } frame; 2439 2440 struct iovec sgl[MAX_IOCTL_SGE]; 2441 2442 } __attribute__ ((packed)); 2443 2444 struct megasas_aen { 2445 u16 host_no; 2446 u16 __pad1; 2447 u32 seq_num; 2448 u32 class_locale_word; 2449 } __attribute__ ((packed)); 2450 2451 #ifdef CONFIG_COMPAT 2452 struct compat_megasas_iocpacket { 2453 u16 host_no; 2454 u16 __pad1; 2455 u32 sgl_off; 2456 u32 sge_count; 2457 u32 sense_off; 2458 u32 sense_len; 2459 union { 2460 u8 raw[128]; 2461 struct megasas_header hdr; 2462 } frame; 2463 struct compat_iovec sgl[MAX_IOCTL_SGE]; 2464 } __attribute__ ((packed)); 2465 2466 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2467 #endif 2468 2469 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2470 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2471 2472 struct megasas_mgmt_info { 2473 2474 u16 count; 2475 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2476 int max_index; 2477 }; 2478 2479 enum MEGASAS_OCR_CAUSE { 2480 FW_FAULT_OCR = 0, 2481 SCSIIO_TIMEOUT_OCR = 1, 2482 MFI_IO_TIMEOUT_OCR = 2, 2483 }; 2484 2485 enum DCMD_RETURN_STATUS { 2486 DCMD_SUCCESS = 0, 2487 DCMD_TIMEOUT = 1, 2488 DCMD_FAILED = 2, 2489 DCMD_NOT_FIRED = 3, 2490 }; 2491 2492 u8 2493 MR_BuildRaidContext(struct megasas_instance *instance, 2494 struct IO_REQUEST_INFO *io_info, 2495 struct RAID_CONTEXT *pRAID_Context, 2496 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2497 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 2498 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2499 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 2500 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 2501 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 2502 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2503 2504 __le16 get_updated_dev_handle(struct megasas_instance *instance, 2505 struct LD_LOAD_BALANCE_INFO *lbInfo, 2506 struct IO_REQUEST_INFO *in_info, 2507 struct MR_DRV_RAID_MAP_ALL *drv_map); 2508 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 2509 struct LD_LOAD_BALANCE_INFO *lbInfo); 2510 int megasas_get_ctrl_info(struct megasas_instance *instance); 2511 /* PD sequence */ 2512 int 2513 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2514 void megasas_set_dynamic_target_properties(struct scsi_device *sdev); 2515 int megasas_set_crash_dump_params(struct megasas_instance *instance, 2516 u8 crash_buf_state); 2517 void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2518 void megasas_fusion_crash_dump_wq(struct work_struct *work); 2519 2520 void megasas_return_cmd_fusion(struct megasas_instance *instance, 2521 struct megasas_cmd_fusion *cmd); 2522 int megasas_issue_blocked_cmd(struct megasas_instance *instance, 2523 struct megasas_cmd *cmd, int timeout); 2524 void __megasas_return_cmd(struct megasas_instance *instance, 2525 struct megasas_cmd *cmd); 2526 2527 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 2528 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 2529 int megasas_cmd_type(struct scsi_cmnd *cmd); 2530 void megasas_setup_jbod_map(struct megasas_instance *instance); 2531 2532 void megasas_update_sdev_properties(struct scsi_device *sdev); 2533 int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 2534 int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 2535 int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2536 u32 mega_mod64(u64 dividend, u32 divisor); 2537 int megasas_alloc_fusion_context(struct megasas_instance *instance); 2538 void megasas_free_fusion_context(struct megasas_instance *instance); 2539 void megasas_set_dma_settings(struct megasas_instance *instance, 2540 struct megasas_dcmd_frame *dcmd, 2541 dma_addr_t dma_addr, u32 dma_len); 2542 #endif /*LSI_MEGARAID_SAS_H */ 2543