1 /*
2  *
3  *		Linux MegaRAID driver for SAS based RAID controllers
4  *
5  * Copyright (c) 2003-2005  LSI Corporation.
6  *
7  *		This program is free software; you can redistribute it and/or
8  *		modify it under the terms of the GNU General Public License
9  *		as published by the Free Software Foundation; either version
10  *		2 of the License, or (at your option) any later version.
11  *
12  * FILE		: megaraid_sas.h
13  */
14 
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
17 
18 /*
19  * MegaRAID SAS Driver meta data
20  */
21 #define MEGASAS_VERSION				"00.00.04.12-rc1"
22 #define MEGASAS_RELDATE				"Sep. 17, 2009"
23 #define MEGASAS_EXT_VERSION			"Thu Sep. 17 11:41:51 PST 2009"
24 
25 /*
26  * Device IDs
27  */
28 #define	PCI_DEVICE_ID_LSI_SAS1078R		0x0060
29 #define	PCI_DEVICE_ID_LSI_SAS1078DE		0x007C
30 #define	PCI_DEVICE_ID_LSI_VERDE_ZCR		0x0413
31 #define	PCI_DEVICE_ID_LSI_SAS1078GEN2		0x0078
32 #define	PCI_DEVICE_ID_LSI_SAS0079GEN2		0x0079
33 #define	PCI_DEVICE_ID_LSI_SAS0073SKINNY		0x0073
34 #define	PCI_DEVICE_ID_LSI_SAS0071SKINNY		0x0071
35 
36 /*
37  * =====================================
38  * MegaRAID SAS MFI firmware definitions
39  * =====================================
40  */
41 
42 /*
43  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
44  * protocol between the software and firmware. Commands are issued using
45  * "message frames"
46  */
47 
48 /*
49  * FW posts its state in upper 4 bits of outbound_msg_0 register
50  */
51 #define MFI_STATE_MASK				0xF0000000
52 #define MFI_STATE_UNDEFINED			0x00000000
53 #define MFI_STATE_BB_INIT			0x10000000
54 #define MFI_STATE_FW_INIT			0x40000000
55 #define MFI_STATE_WAIT_HANDSHAKE		0x60000000
56 #define MFI_STATE_FW_INIT_2			0x70000000
57 #define MFI_STATE_DEVICE_SCAN			0x80000000
58 #define MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
59 #define MFI_STATE_FLUSH_CACHE			0xA0000000
60 #define MFI_STATE_READY				0xB0000000
61 #define MFI_STATE_OPERATIONAL			0xC0000000
62 #define MFI_STATE_FAULT				0xF0000000
63 
64 #define MEGAMFI_FRAME_SIZE			64
65 
66 /*
67  * During FW init, clear pending cmds & reset state using inbound_msg_0
68  *
69  * ABORT	: Abort all pending cmds
70  * READY	: Move from OPERATIONAL to READY state; discard queue info
71  * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
72  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
73  * HOTPLUG	: Resume from Hotplug
74  * MFI_STOP_ADP	: Send signal to FW to stop processing
75  */
76 #define MFI_INIT_ABORT				0x00000001
77 #define MFI_INIT_READY				0x00000002
78 #define MFI_INIT_MFIMODE			0x00000004
79 #define MFI_INIT_CLEAR_HANDSHAKE		0x00000008
80 #define MFI_INIT_HOTPLUG			0x00000010
81 #define MFI_STOP_ADP				0x00000020
82 #define MFI_RESET_FLAGS				MFI_INIT_READY| \
83 						MFI_INIT_MFIMODE| \
84 						MFI_INIT_ABORT
85 
86 /*
87  * MFI frame flags
88  */
89 #define MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
90 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
91 #define MFI_FRAME_SGL32				0x0000
92 #define MFI_FRAME_SGL64				0x0002
93 #define MFI_FRAME_SENSE32			0x0000
94 #define MFI_FRAME_SENSE64			0x0004
95 #define MFI_FRAME_DIR_NONE			0x0000
96 #define MFI_FRAME_DIR_WRITE			0x0008
97 #define MFI_FRAME_DIR_READ			0x0010
98 #define MFI_FRAME_DIR_BOTH			0x0018
99 #define MFI_FRAME_IEEE                          0x0020
100 
101 /*
102  * Definition for cmd_status
103  */
104 #define MFI_CMD_STATUS_POLL_MODE		0xFF
105 
106 /*
107  * MFI command opcodes
108  */
109 #define MFI_CMD_INIT				0x00
110 #define MFI_CMD_LD_READ				0x01
111 #define MFI_CMD_LD_WRITE			0x02
112 #define MFI_CMD_LD_SCSI_IO			0x03
113 #define MFI_CMD_PD_SCSI_IO			0x04
114 #define MFI_CMD_DCMD				0x05
115 #define MFI_CMD_ABORT				0x06
116 #define MFI_CMD_SMP				0x07
117 #define MFI_CMD_STP				0x08
118 
119 #define MR_DCMD_CTRL_GET_INFO			0x01010000
120 
121 #define MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
122 #define MR_FLUSH_CTRL_CACHE			0x01
123 #define MR_FLUSH_DISK_CACHE			0x02
124 
125 #define MR_DCMD_CTRL_SHUTDOWN			0x01050000
126 #define MR_DCMD_HIBERNATE_SHUTDOWN		0x01060000
127 #define MR_ENABLE_DRIVE_SPINDOWN		0x01
128 
129 #define MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
130 #define MR_DCMD_CTRL_EVENT_GET			0x01040300
131 #define MR_DCMD_CTRL_EVENT_WAIT			0x01040500
132 #define MR_DCMD_LD_GET_PROPERTIES		0x03030000
133 
134 #define MR_DCMD_CLUSTER				0x08000000
135 #define MR_DCMD_CLUSTER_RESET_ALL		0x08010100
136 #define MR_DCMD_CLUSTER_RESET_LD		0x08010200
137 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
138 
139 /*
140  * MFI command completion codes
141  */
142 enum MFI_STAT {
143 	MFI_STAT_OK = 0x00,
144 	MFI_STAT_INVALID_CMD = 0x01,
145 	MFI_STAT_INVALID_DCMD = 0x02,
146 	MFI_STAT_INVALID_PARAMETER = 0x03,
147 	MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
148 	MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
149 	MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
150 	MFI_STAT_APP_IN_USE = 0x07,
151 	MFI_STAT_APP_NOT_INITIALIZED = 0x08,
152 	MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
153 	MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
154 	MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
155 	MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
156 	MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
157 	MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
158 	MFI_STAT_FLASH_BUSY = 0x0f,
159 	MFI_STAT_FLASH_ERROR = 0x10,
160 	MFI_STAT_FLASH_IMAGE_BAD = 0x11,
161 	MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
162 	MFI_STAT_FLASH_NOT_OPEN = 0x13,
163 	MFI_STAT_FLASH_NOT_STARTED = 0x14,
164 	MFI_STAT_FLUSH_FAILED = 0x15,
165 	MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
166 	MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
167 	MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
168 	MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
169 	MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
170 	MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
171 	MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
172 	MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
173 	MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
174 	MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
175 	MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
176 	MFI_STAT_MFC_HW_ERROR = 0x21,
177 	MFI_STAT_NO_HW_PRESENT = 0x22,
178 	MFI_STAT_NOT_FOUND = 0x23,
179 	MFI_STAT_NOT_IN_ENCL = 0x24,
180 	MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
181 	MFI_STAT_PD_TYPE_WRONG = 0x26,
182 	MFI_STAT_PR_DISABLED = 0x27,
183 	MFI_STAT_ROW_INDEX_INVALID = 0x28,
184 	MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
185 	MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
186 	MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
187 	MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
188 	MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
189 	MFI_STAT_SCSI_IO_FAILED = 0x2e,
190 	MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
191 	MFI_STAT_SHUTDOWN_FAILED = 0x30,
192 	MFI_STAT_TIME_NOT_SET = 0x31,
193 	MFI_STAT_WRONG_STATE = 0x32,
194 	MFI_STAT_LD_OFFLINE = 0x33,
195 	MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
196 	MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
197 	MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
198 	MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
199 	MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
200 
201 	MFI_STAT_INVALID_STATUS = 0xFF
202 };
203 
204 /*
205  * Number of mailbox bytes in DCMD message frame
206  */
207 #define MFI_MBOX_SIZE				12
208 
209 enum MR_EVT_CLASS {
210 
211 	MR_EVT_CLASS_DEBUG = -2,
212 	MR_EVT_CLASS_PROGRESS = -1,
213 	MR_EVT_CLASS_INFO = 0,
214 	MR_EVT_CLASS_WARNING = 1,
215 	MR_EVT_CLASS_CRITICAL = 2,
216 	MR_EVT_CLASS_FATAL = 3,
217 	MR_EVT_CLASS_DEAD = 4,
218 
219 };
220 
221 enum MR_EVT_LOCALE {
222 
223 	MR_EVT_LOCALE_LD = 0x0001,
224 	MR_EVT_LOCALE_PD = 0x0002,
225 	MR_EVT_LOCALE_ENCL = 0x0004,
226 	MR_EVT_LOCALE_BBU = 0x0008,
227 	MR_EVT_LOCALE_SAS = 0x0010,
228 	MR_EVT_LOCALE_CTRL = 0x0020,
229 	MR_EVT_LOCALE_CONFIG = 0x0040,
230 	MR_EVT_LOCALE_CLUSTER = 0x0080,
231 	MR_EVT_LOCALE_ALL = 0xffff,
232 
233 };
234 
235 enum MR_EVT_ARGS {
236 
237 	MR_EVT_ARGS_NONE,
238 	MR_EVT_ARGS_CDB_SENSE,
239 	MR_EVT_ARGS_LD,
240 	MR_EVT_ARGS_LD_COUNT,
241 	MR_EVT_ARGS_LD_LBA,
242 	MR_EVT_ARGS_LD_OWNER,
243 	MR_EVT_ARGS_LD_LBA_PD_LBA,
244 	MR_EVT_ARGS_LD_PROG,
245 	MR_EVT_ARGS_LD_STATE,
246 	MR_EVT_ARGS_LD_STRIP,
247 	MR_EVT_ARGS_PD,
248 	MR_EVT_ARGS_PD_ERR,
249 	MR_EVT_ARGS_PD_LBA,
250 	MR_EVT_ARGS_PD_LBA_LD,
251 	MR_EVT_ARGS_PD_PROG,
252 	MR_EVT_ARGS_PD_STATE,
253 	MR_EVT_ARGS_PCI,
254 	MR_EVT_ARGS_RATE,
255 	MR_EVT_ARGS_STR,
256 	MR_EVT_ARGS_TIME,
257 	MR_EVT_ARGS_ECC,
258 	MR_EVT_ARGS_LD_PROP,
259 	MR_EVT_ARGS_PD_SPARE,
260 	MR_EVT_ARGS_PD_INDEX,
261 	MR_EVT_ARGS_DIAG_PASS,
262 	MR_EVT_ARGS_DIAG_FAIL,
263 	MR_EVT_ARGS_PD_LBA_LBA,
264 	MR_EVT_ARGS_PORT_PHY,
265 	MR_EVT_ARGS_PD_MISSING,
266 	MR_EVT_ARGS_PD_ADDRESS,
267 	MR_EVT_ARGS_BITMAP,
268 	MR_EVT_ARGS_CONNECTOR,
269 	MR_EVT_ARGS_PD_PD,
270 	MR_EVT_ARGS_PD_FRU,
271 	MR_EVT_ARGS_PD_PATHINFO,
272 	MR_EVT_ARGS_PD_POWER_STATE,
273 	MR_EVT_ARGS_GENERIC,
274 };
275 
276 /*
277  * define constants for device list query options
278  */
279 enum MR_PD_QUERY_TYPE {
280 	MR_PD_QUERY_TYPE_ALL                = 0,
281 	MR_PD_QUERY_TYPE_STATE              = 1,
282 	MR_PD_QUERY_TYPE_POWER_STATE        = 2,
283 	MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
284 	MR_PD_QUERY_TYPE_SPEED              = 4,
285 	MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
286 };
287 
288 #define MR_EVT_CFG_CLEARED                              0x0004
289 #define MR_EVT_LD_STATE_CHANGE                          0x0051
290 #define MR_EVT_PD_INSERTED                              0x005b
291 #define MR_EVT_PD_REMOVED                               0x0070
292 #define MR_EVT_LD_CREATED                               0x008a
293 #define MR_EVT_LD_DELETED                               0x008b
294 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
295 #define MR_EVT_LD_OFFLINE                               0x00fc
296 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
297 #define MAX_LOGICAL_DRIVES				64
298 
299 enum MR_PD_STATE {
300 	MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
301 	MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
302 	MR_PD_STATE_HOT_SPARE           = 0x02,
303 	MR_PD_STATE_OFFLINE             = 0x10,
304 	MR_PD_STATE_FAILED              = 0x11,
305 	MR_PD_STATE_REBUILD             = 0x14,
306 	MR_PD_STATE_ONLINE              = 0x18,
307 	MR_PD_STATE_COPYBACK            = 0x20,
308 	MR_PD_STATE_SYSTEM              = 0x40,
309  };
310 
311 
312  /*
313  * defines the physical drive address structure
314  */
315 struct MR_PD_ADDRESS {
316 	u16     deviceId;
317 	u16     enclDeviceId;
318 
319 	union {
320 		struct {
321 			u8  enclIndex;
322 			u8  slotNumber;
323 		} mrPdAddress;
324 		struct {
325 			u8  enclPosition;
326 			u8  enclConnectorIndex;
327 		} mrEnclAddress;
328 	};
329 	u8      scsiDevType;
330 	union {
331 		u8      connectedPortBitmap;
332 		u8      connectedPortNumbers;
333 	};
334 	u64     sasAddr[2];
335 } __packed;
336 
337 /*
338  * defines the physical drive list structure
339  */
340 struct MR_PD_LIST {
341 	u32             size;
342 	u32             count;
343 	struct MR_PD_ADDRESS   addr[1];
344 } __packed;
345 
346 struct megasas_pd_list {
347 	u16             tid;
348 	u8             driveType;
349 	u8             driveState;
350 } __packed;
351 
352 /*
353  * SAS controller properties
354  */
355 struct megasas_ctrl_prop {
356 
357 	u16 seq_num;
358 	u16 pred_fail_poll_interval;
359 	u16 intr_throttle_count;
360 	u16 intr_throttle_timeouts;
361 	u8 rebuild_rate;
362 	u8 patrol_read_rate;
363 	u8 bgi_rate;
364 	u8 cc_rate;
365 	u8 recon_rate;
366 	u8 cache_flush_interval;
367 	u8 spinup_drv_count;
368 	u8 spinup_delay;
369 	u8 cluster_enable;
370 	u8 coercion_mode;
371 	u8 alarm_enable;
372 	u8 disable_auto_rebuild;
373 	u8 disable_battery_warn;
374 	u8 ecc_bucket_size;
375 	u16 ecc_bucket_leak_rate;
376 	u8 restore_hotspare_on_insertion;
377 	u8 expose_encl_devices;
378 	u8 reserved[38];
379 
380 } __packed;
381 
382 /*
383  * SAS controller information
384  */
385 struct megasas_ctrl_info {
386 
387 	/*
388 	 * PCI device information
389 	 */
390 	struct {
391 
392 		u16 vendor_id;
393 		u16 device_id;
394 		u16 sub_vendor_id;
395 		u16 sub_device_id;
396 		u8 reserved[24];
397 
398 	} __attribute__ ((packed)) pci;
399 
400 	/*
401 	 * Host interface information
402 	 */
403 	struct {
404 
405 		u8 PCIX:1;
406 		u8 PCIE:1;
407 		u8 iSCSI:1;
408 		u8 SAS_3G:1;
409 		u8 reserved_0:4;
410 		u8 reserved_1[6];
411 		u8 port_count;
412 		u64 port_addr[8];
413 
414 	} __attribute__ ((packed)) host_interface;
415 
416 	/*
417 	 * Device (backend) interface information
418 	 */
419 	struct {
420 
421 		u8 SPI:1;
422 		u8 SAS_3G:1;
423 		u8 SATA_1_5G:1;
424 		u8 SATA_3G:1;
425 		u8 reserved_0:4;
426 		u8 reserved_1[6];
427 		u8 port_count;
428 		u64 port_addr[8];
429 
430 	} __attribute__ ((packed)) device_interface;
431 
432 	/*
433 	 * List of components residing in flash. All str are null terminated
434 	 */
435 	u32 image_check_word;
436 	u32 image_component_count;
437 
438 	struct {
439 
440 		char name[8];
441 		char version[32];
442 		char build_date[16];
443 		char built_time[16];
444 
445 	} __attribute__ ((packed)) image_component[8];
446 
447 	/*
448 	 * List of flash components that have been flashed on the card, but
449 	 * are not in use, pending reset of the adapter. This list will be
450 	 * empty if a flash operation has not occurred. All stings are null
451 	 * terminated
452 	 */
453 	u32 pending_image_component_count;
454 
455 	struct {
456 
457 		char name[8];
458 		char version[32];
459 		char build_date[16];
460 		char build_time[16];
461 
462 	} __attribute__ ((packed)) pending_image_component[8];
463 
464 	u8 max_arms;
465 	u8 max_spans;
466 	u8 max_arrays;
467 	u8 max_lds;
468 
469 	char product_name[80];
470 	char serial_no[32];
471 
472 	/*
473 	 * Other physical/controller/operation information. Indicates the
474 	 * presence of the hardware
475 	 */
476 	struct {
477 
478 		u32 bbu:1;
479 		u32 alarm:1;
480 		u32 nvram:1;
481 		u32 uart:1;
482 		u32 reserved:28;
483 
484 	} __attribute__ ((packed)) hw_present;
485 
486 	u32 current_fw_time;
487 
488 	/*
489 	 * Maximum data transfer sizes
490 	 */
491 	u16 max_concurrent_cmds;
492 	u16 max_sge_count;
493 	u32 max_request_size;
494 
495 	/*
496 	 * Logical and physical device counts
497 	 */
498 	u16 ld_present_count;
499 	u16 ld_degraded_count;
500 	u16 ld_offline_count;
501 
502 	u16 pd_present_count;
503 	u16 pd_disk_present_count;
504 	u16 pd_disk_pred_failure_count;
505 	u16 pd_disk_failed_count;
506 
507 	/*
508 	 * Memory size information
509 	 */
510 	u16 nvram_size;
511 	u16 memory_size;
512 	u16 flash_size;
513 
514 	/*
515 	 * Error counters
516 	 */
517 	u16 mem_correctable_error_count;
518 	u16 mem_uncorrectable_error_count;
519 
520 	/*
521 	 * Cluster information
522 	 */
523 	u8 cluster_permitted;
524 	u8 cluster_active;
525 
526 	/*
527 	 * Additional max data transfer sizes
528 	 */
529 	u16 max_strips_per_io;
530 
531 	/*
532 	 * Controller capabilities structures
533 	 */
534 	struct {
535 
536 		u32 raid_level_0:1;
537 		u32 raid_level_1:1;
538 		u32 raid_level_5:1;
539 		u32 raid_level_1E:1;
540 		u32 raid_level_6:1;
541 		u32 reserved:27;
542 
543 	} __attribute__ ((packed)) raid_levels;
544 
545 	struct {
546 
547 		u32 rbld_rate:1;
548 		u32 cc_rate:1;
549 		u32 bgi_rate:1;
550 		u32 recon_rate:1;
551 		u32 patrol_rate:1;
552 		u32 alarm_control:1;
553 		u32 cluster_supported:1;
554 		u32 bbu:1;
555 		u32 spanning_allowed:1;
556 		u32 dedicated_hotspares:1;
557 		u32 revertible_hotspares:1;
558 		u32 foreign_config_import:1;
559 		u32 self_diagnostic:1;
560 		u32 mixed_redundancy_arr:1;
561 		u32 global_hot_spares:1;
562 		u32 reserved:17;
563 
564 	} __attribute__ ((packed)) adapter_operations;
565 
566 	struct {
567 
568 		u32 read_policy:1;
569 		u32 write_policy:1;
570 		u32 io_policy:1;
571 		u32 access_policy:1;
572 		u32 disk_cache_policy:1;
573 		u32 reserved:27;
574 
575 	} __attribute__ ((packed)) ld_operations;
576 
577 	struct {
578 
579 		u8 min;
580 		u8 max;
581 		u8 reserved[2];
582 
583 	} __attribute__ ((packed)) stripe_sz_ops;
584 
585 	struct {
586 
587 		u32 force_online:1;
588 		u32 force_offline:1;
589 		u32 force_rebuild:1;
590 		u32 reserved:29;
591 
592 	} __attribute__ ((packed)) pd_operations;
593 
594 	struct {
595 
596 		u32 ctrl_supports_sas:1;
597 		u32 ctrl_supports_sata:1;
598 		u32 allow_mix_in_encl:1;
599 		u32 allow_mix_in_ld:1;
600 		u32 allow_sata_in_cluster:1;
601 		u32 reserved:27;
602 
603 	} __attribute__ ((packed)) pd_mix_support;
604 
605 	/*
606 	 * Define ECC single-bit-error bucket information
607 	 */
608 	u8 ecc_bucket_count;
609 	u8 reserved_2[11];
610 
611 	/*
612 	 * Include the controller properties (changeable items)
613 	 */
614 	struct megasas_ctrl_prop properties;
615 
616 	/*
617 	 * Define FW pkg version (set in envt v'bles on OEM basis)
618 	 */
619 	char package_version[0x60];
620 
621 	u8 pad[0x800 - 0x6a0];
622 
623 } __packed;
624 
625 /*
626  * ===============================
627  * MegaRAID SAS driver definitions
628  * ===============================
629  */
630 #define MEGASAS_MAX_PD_CHANNELS			2
631 #define MEGASAS_MAX_LD_CHANNELS			2
632 #define MEGASAS_MAX_CHANNELS			(MEGASAS_MAX_PD_CHANNELS + \
633 						MEGASAS_MAX_LD_CHANNELS)
634 #define MEGASAS_MAX_DEV_PER_CHANNEL		128
635 #define MEGASAS_DEFAULT_INIT_ID			-1
636 #define MEGASAS_MAX_LUN				8
637 #define MEGASAS_MAX_LD				64
638 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
639 						MEGASAS_MAX_DEV_PER_CHANNEL)
640 
641 #define MEGASAS_DBG_LVL				1
642 
643 #define MEGASAS_FW_BUSY				1
644 
645 /* Frame Type */
646 #define IO_FRAME				0
647 #define PTHRU_FRAME				1
648 
649 /*
650  * When SCSI mid-layer calls driver's reset routine, driver waits for
651  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
652  * that the driver cannot _actually_ abort or reset pending commands. While
653  * it is waiting for the commands to complete, it prints a diagnostic message
654  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
655  */
656 #define MEGASAS_RESET_WAIT_TIME			180
657 #define MEGASAS_INTERNAL_CMD_WAIT_TIME		180
658 #define	MEGASAS_RESET_NOTICE_INTERVAL		5
659 #define MEGASAS_IOCTL_CMD			0
660 #define MEGASAS_DEFAULT_CMD_TIMEOUT		90
661 
662 /*
663  * FW reports the maximum of number of commands that it can accept (maximum
664  * commands that can be outstanding) at any time. The driver must report a
665  * lower number to the mid layer because it can issue a few internal commands
666  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
667  * is shown below
668  */
669 #define MEGASAS_INT_CMDS			32
670 #define MEGASAS_SKINNY_INT_CMDS			5
671 
672 /*
673  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
674  * SGLs based on the size of dma_addr_t
675  */
676 #define IS_DMA64				(sizeof(dma_addr_t) == 8)
677 
678 #define MFI_OB_INTR_STATUS_MASK			0x00000002
679 #define MFI_POLL_TIMEOUT_SECS			60
680 #define MEGASAS_COMPLETION_TIMER_INTERVAL      (HZ/10)
681 
682 #define MFI_REPLY_1078_MESSAGE_INTERRUPT	0x80000000
683 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT	0x00000001
684 #define MFI_GEN2_ENABLE_INTERRUPT_MASK		(0x00000001 | 0x00000004)
685 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT	0x40000000
686 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK	(0x00000001)
687 
688 /*
689 * register set for both 1068 and 1078 controllers
690 * structure extended for 1078 registers
691 */
692 
693 struct megasas_register_set {
694 	u32 	reserved_0[4];			/*0000h*/
695 
696 	u32 	inbound_msg_0;			/*0010h*/
697 	u32 	inbound_msg_1;			/*0014h*/
698 	u32 	outbound_msg_0;			/*0018h*/
699 	u32 	outbound_msg_1;			/*001Ch*/
700 
701 	u32 	inbound_doorbell;		/*0020h*/
702 	u32 	inbound_intr_status;		/*0024h*/
703 	u32 	inbound_intr_mask;		/*0028h*/
704 
705 	u32 	outbound_doorbell;		/*002Ch*/
706 	u32 	outbound_intr_status;		/*0030h*/
707 	u32 	outbound_intr_mask;		/*0034h*/
708 
709 	u32 	reserved_1[2];			/*0038h*/
710 
711 	u32 	inbound_queue_port;		/*0040h*/
712 	u32 	outbound_queue_port;		/*0044h*/
713 
714 	u32 	reserved_2[22];			/*0048h*/
715 
716 	u32 	outbound_doorbell_clear;	/*00A0h*/
717 
718 	u32 	reserved_3[3];			/*00A4h*/
719 
720 	u32 	outbound_scratch_pad ;		/*00B0h*/
721 
722 	u32 	reserved_4[3];			/*00B4h*/
723 
724 	u32 	inbound_low_queue_port ;	/*00C0h*/
725 
726 	u32 	inbound_high_queue_port ;	/*00C4h*/
727 
728 	u32 	reserved_5;			/*00C8h*/
729 	u32 	index_registers[820];		/*00CCh*/
730 
731 } __attribute__ ((packed));
732 
733 struct megasas_sge32 {
734 
735 	u32 phys_addr;
736 	u32 length;
737 
738 } __attribute__ ((packed));
739 
740 struct megasas_sge64 {
741 
742 	u64 phys_addr;
743 	u32 length;
744 
745 } __attribute__ ((packed));
746 
747 struct megasas_sge_skinny {
748 	u64 phys_addr;
749 	u32 length;
750 	u32 flag;
751 } __packed;
752 
753 union megasas_sgl {
754 
755 	struct megasas_sge32 sge32[1];
756 	struct megasas_sge64 sge64[1];
757 	struct megasas_sge_skinny sge_skinny[1];
758 
759 } __attribute__ ((packed));
760 
761 struct megasas_header {
762 
763 	u8 cmd;			/*00h */
764 	u8 sense_len;		/*01h */
765 	u8 cmd_status;		/*02h */
766 	u8 scsi_status;		/*03h */
767 
768 	u8 target_id;		/*04h */
769 	u8 lun;			/*05h */
770 	u8 cdb_len;		/*06h */
771 	u8 sge_count;		/*07h */
772 
773 	u32 context;		/*08h */
774 	u32 pad_0;		/*0Ch */
775 
776 	u16 flags;		/*10h */
777 	u16 timeout;		/*12h */
778 	u32 data_xferlen;	/*14h */
779 
780 } __attribute__ ((packed));
781 
782 union megasas_sgl_frame {
783 
784 	struct megasas_sge32 sge32[8];
785 	struct megasas_sge64 sge64[5];
786 
787 } __attribute__ ((packed));
788 
789 struct megasas_init_frame {
790 
791 	u8 cmd;			/*00h */
792 	u8 reserved_0;		/*01h */
793 	u8 cmd_status;		/*02h */
794 
795 	u8 reserved_1;		/*03h */
796 	u32 reserved_2;		/*04h */
797 
798 	u32 context;		/*08h */
799 	u32 pad_0;		/*0Ch */
800 
801 	u16 flags;		/*10h */
802 	u16 reserved_3;		/*12h */
803 	u32 data_xfer_len;	/*14h */
804 
805 	u32 queue_info_new_phys_addr_lo;	/*18h */
806 	u32 queue_info_new_phys_addr_hi;	/*1Ch */
807 	u32 queue_info_old_phys_addr_lo;	/*20h */
808 	u32 queue_info_old_phys_addr_hi;	/*24h */
809 
810 	u32 reserved_4[6];	/*28h */
811 
812 } __attribute__ ((packed));
813 
814 struct megasas_init_queue_info {
815 
816 	u32 init_flags;		/*00h */
817 	u32 reply_queue_entries;	/*04h */
818 
819 	u32 reply_queue_start_phys_addr_lo;	/*08h */
820 	u32 reply_queue_start_phys_addr_hi;	/*0Ch */
821 	u32 producer_index_phys_addr_lo;	/*10h */
822 	u32 producer_index_phys_addr_hi;	/*14h */
823 	u32 consumer_index_phys_addr_lo;	/*18h */
824 	u32 consumer_index_phys_addr_hi;	/*1Ch */
825 
826 } __attribute__ ((packed));
827 
828 struct megasas_io_frame {
829 
830 	u8 cmd;			/*00h */
831 	u8 sense_len;		/*01h */
832 	u8 cmd_status;		/*02h */
833 	u8 scsi_status;		/*03h */
834 
835 	u8 target_id;		/*04h */
836 	u8 access_byte;		/*05h */
837 	u8 reserved_0;		/*06h */
838 	u8 sge_count;		/*07h */
839 
840 	u32 context;		/*08h */
841 	u32 pad_0;		/*0Ch */
842 
843 	u16 flags;		/*10h */
844 	u16 timeout;		/*12h */
845 	u32 lba_count;		/*14h */
846 
847 	u32 sense_buf_phys_addr_lo;	/*18h */
848 	u32 sense_buf_phys_addr_hi;	/*1Ch */
849 
850 	u32 start_lba_lo;	/*20h */
851 	u32 start_lba_hi;	/*24h */
852 
853 	union megasas_sgl sgl;	/*28h */
854 
855 } __attribute__ ((packed));
856 
857 struct megasas_pthru_frame {
858 
859 	u8 cmd;			/*00h */
860 	u8 sense_len;		/*01h */
861 	u8 cmd_status;		/*02h */
862 	u8 scsi_status;		/*03h */
863 
864 	u8 target_id;		/*04h */
865 	u8 lun;			/*05h */
866 	u8 cdb_len;		/*06h */
867 	u8 sge_count;		/*07h */
868 
869 	u32 context;		/*08h */
870 	u32 pad_0;		/*0Ch */
871 
872 	u16 flags;		/*10h */
873 	u16 timeout;		/*12h */
874 	u32 data_xfer_len;	/*14h */
875 
876 	u32 sense_buf_phys_addr_lo;	/*18h */
877 	u32 sense_buf_phys_addr_hi;	/*1Ch */
878 
879 	u8 cdb[16];		/*20h */
880 	union megasas_sgl sgl;	/*30h */
881 
882 } __attribute__ ((packed));
883 
884 struct megasas_dcmd_frame {
885 
886 	u8 cmd;			/*00h */
887 	u8 reserved_0;		/*01h */
888 	u8 cmd_status;		/*02h */
889 	u8 reserved_1[4];	/*03h */
890 	u8 sge_count;		/*07h */
891 
892 	u32 context;		/*08h */
893 	u32 pad_0;		/*0Ch */
894 
895 	u16 flags;		/*10h */
896 	u16 timeout;		/*12h */
897 
898 	u32 data_xfer_len;	/*14h */
899 	u32 opcode;		/*18h */
900 
901 	union {			/*1Ch */
902 		u8 b[12];
903 		u16 s[6];
904 		u32 w[3];
905 	} mbox;
906 
907 	union megasas_sgl sgl;	/*28h */
908 
909 } __attribute__ ((packed));
910 
911 struct megasas_abort_frame {
912 
913 	u8 cmd;			/*00h */
914 	u8 reserved_0;		/*01h */
915 	u8 cmd_status;		/*02h */
916 
917 	u8 reserved_1;		/*03h */
918 	u32 reserved_2;		/*04h */
919 
920 	u32 context;		/*08h */
921 	u32 pad_0;		/*0Ch */
922 
923 	u16 flags;		/*10h */
924 	u16 reserved_3;		/*12h */
925 	u32 reserved_4;		/*14h */
926 
927 	u32 abort_context;	/*18h */
928 	u32 pad_1;		/*1Ch */
929 
930 	u32 abort_mfi_phys_addr_lo;	/*20h */
931 	u32 abort_mfi_phys_addr_hi;	/*24h */
932 
933 	u32 reserved_5[6];	/*28h */
934 
935 } __attribute__ ((packed));
936 
937 struct megasas_smp_frame {
938 
939 	u8 cmd;			/*00h */
940 	u8 reserved_1;		/*01h */
941 	u8 cmd_status;		/*02h */
942 	u8 connection_status;	/*03h */
943 
944 	u8 reserved_2[3];	/*04h */
945 	u8 sge_count;		/*07h */
946 
947 	u32 context;		/*08h */
948 	u32 pad_0;		/*0Ch */
949 
950 	u16 flags;		/*10h */
951 	u16 timeout;		/*12h */
952 
953 	u32 data_xfer_len;	/*14h */
954 	u64 sas_addr;		/*18h */
955 
956 	union {
957 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: req */
958 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: req */
959 	} sgl;
960 
961 } __attribute__ ((packed));
962 
963 struct megasas_stp_frame {
964 
965 	u8 cmd;			/*00h */
966 	u8 reserved_1;		/*01h */
967 	u8 cmd_status;		/*02h */
968 	u8 reserved_2;		/*03h */
969 
970 	u8 target_id;		/*04h */
971 	u8 reserved_3[2];	/*05h */
972 	u8 sge_count;		/*07h */
973 
974 	u32 context;		/*08h */
975 	u32 pad_0;		/*0Ch */
976 
977 	u16 flags;		/*10h */
978 	u16 timeout;		/*12h */
979 
980 	u32 data_xfer_len;	/*14h */
981 
982 	u16 fis[10];		/*18h */
983 	u32 stp_flags;
984 
985 	union {
986 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: data */
987 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: data */
988 	} sgl;
989 
990 } __attribute__ ((packed));
991 
992 union megasas_frame {
993 
994 	struct megasas_header hdr;
995 	struct megasas_init_frame init;
996 	struct megasas_io_frame io;
997 	struct megasas_pthru_frame pthru;
998 	struct megasas_dcmd_frame dcmd;
999 	struct megasas_abort_frame abort;
1000 	struct megasas_smp_frame smp;
1001 	struct megasas_stp_frame stp;
1002 
1003 	u8 raw_bytes[64];
1004 };
1005 
1006 struct megasas_cmd;
1007 
1008 union megasas_evt_class_locale {
1009 
1010 	struct {
1011 		u16 locale;
1012 		u8 reserved;
1013 		s8 class;
1014 	} __attribute__ ((packed)) members;
1015 
1016 	u32 word;
1017 
1018 } __attribute__ ((packed));
1019 
1020 struct megasas_evt_log_info {
1021 	u32 newest_seq_num;
1022 	u32 oldest_seq_num;
1023 	u32 clear_seq_num;
1024 	u32 shutdown_seq_num;
1025 	u32 boot_seq_num;
1026 
1027 } __attribute__ ((packed));
1028 
1029 struct megasas_progress {
1030 
1031 	u16 progress;
1032 	u16 elapsed_seconds;
1033 
1034 } __attribute__ ((packed));
1035 
1036 struct megasas_evtarg_ld {
1037 
1038 	u16 target_id;
1039 	u8 ld_index;
1040 	u8 reserved;
1041 
1042 } __attribute__ ((packed));
1043 
1044 struct megasas_evtarg_pd {
1045 	u16 device_id;
1046 	u8 encl_index;
1047 	u8 slot_number;
1048 
1049 } __attribute__ ((packed));
1050 
1051 struct megasas_evt_detail {
1052 
1053 	u32 seq_num;
1054 	u32 time_stamp;
1055 	u32 code;
1056 	union megasas_evt_class_locale cl;
1057 	u8 arg_type;
1058 	u8 reserved1[15];
1059 
1060 	union {
1061 		struct {
1062 			struct megasas_evtarg_pd pd;
1063 			u8 cdb_length;
1064 			u8 sense_length;
1065 			u8 reserved[2];
1066 			u8 cdb[16];
1067 			u8 sense[64];
1068 		} __attribute__ ((packed)) cdbSense;
1069 
1070 		struct megasas_evtarg_ld ld;
1071 
1072 		struct {
1073 			struct megasas_evtarg_ld ld;
1074 			u64 count;
1075 		} __attribute__ ((packed)) ld_count;
1076 
1077 		struct {
1078 			u64 lba;
1079 			struct megasas_evtarg_ld ld;
1080 		} __attribute__ ((packed)) ld_lba;
1081 
1082 		struct {
1083 			struct megasas_evtarg_ld ld;
1084 			u32 prevOwner;
1085 			u32 newOwner;
1086 		} __attribute__ ((packed)) ld_owner;
1087 
1088 		struct {
1089 			u64 ld_lba;
1090 			u64 pd_lba;
1091 			struct megasas_evtarg_ld ld;
1092 			struct megasas_evtarg_pd pd;
1093 		} __attribute__ ((packed)) ld_lba_pd_lba;
1094 
1095 		struct {
1096 			struct megasas_evtarg_ld ld;
1097 			struct megasas_progress prog;
1098 		} __attribute__ ((packed)) ld_prog;
1099 
1100 		struct {
1101 			struct megasas_evtarg_ld ld;
1102 			u32 prev_state;
1103 			u32 new_state;
1104 		} __attribute__ ((packed)) ld_state;
1105 
1106 		struct {
1107 			u64 strip;
1108 			struct megasas_evtarg_ld ld;
1109 		} __attribute__ ((packed)) ld_strip;
1110 
1111 		struct megasas_evtarg_pd pd;
1112 
1113 		struct {
1114 			struct megasas_evtarg_pd pd;
1115 			u32 err;
1116 		} __attribute__ ((packed)) pd_err;
1117 
1118 		struct {
1119 			u64 lba;
1120 			struct megasas_evtarg_pd pd;
1121 		} __attribute__ ((packed)) pd_lba;
1122 
1123 		struct {
1124 			u64 lba;
1125 			struct megasas_evtarg_pd pd;
1126 			struct megasas_evtarg_ld ld;
1127 		} __attribute__ ((packed)) pd_lba_ld;
1128 
1129 		struct {
1130 			struct megasas_evtarg_pd pd;
1131 			struct megasas_progress prog;
1132 		} __attribute__ ((packed)) pd_prog;
1133 
1134 		struct {
1135 			struct megasas_evtarg_pd pd;
1136 			u32 prevState;
1137 			u32 newState;
1138 		} __attribute__ ((packed)) pd_state;
1139 
1140 		struct {
1141 			u16 vendorId;
1142 			u16 deviceId;
1143 			u16 subVendorId;
1144 			u16 subDeviceId;
1145 		} __attribute__ ((packed)) pci;
1146 
1147 		u32 rate;
1148 		char str[96];
1149 
1150 		struct {
1151 			u32 rtc;
1152 			u32 elapsedSeconds;
1153 		} __attribute__ ((packed)) time;
1154 
1155 		struct {
1156 			u32 ecar;
1157 			u32 elog;
1158 			char str[64];
1159 		} __attribute__ ((packed)) ecc;
1160 
1161 		u8 b[96];
1162 		u16 s[48];
1163 		u32 w[24];
1164 		u64 d[12];
1165 	} args;
1166 
1167 	char description[128];
1168 
1169 } __attribute__ ((packed));
1170 
1171 struct megasas_aen_event {
1172 	struct work_struct hotplug_work;
1173 	struct megasas_instance *instance;
1174 };
1175 
1176 struct megasas_instance {
1177 
1178 	u32 *producer;
1179 	dma_addr_t producer_h;
1180 	u32 *consumer;
1181 	dma_addr_t consumer_h;
1182 
1183 	u32 *reply_queue;
1184 	dma_addr_t reply_queue_h;
1185 
1186 	unsigned long base_addr;
1187 	struct megasas_register_set __iomem *reg_set;
1188 
1189 	struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
1190 	s8 init_id;
1191 
1192 	u16 max_num_sge;
1193 	u16 max_fw_cmds;
1194 	u32 max_sectors_per_req;
1195 	struct megasas_aen_event *ev;
1196 
1197 	struct megasas_cmd **cmd_list;
1198 	struct list_head cmd_pool;
1199 	spinlock_t cmd_pool_lock;
1200 	/* used to synch producer, consumer ptrs in dpc */
1201 	spinlock_t completion_lock;
1202 	/* used to sync fire the cmd to fw */
1203 	spinlock_t fire_lock;
1204 	struct dma_pool *frame_dma_pool;
1205 	struct dma_pool *sense_dma_pool;
1206 
1207 	struct megasas_evt_detail *evt_detail;
1208 	dma_addr_t evt_detail_h;
1209 	struct megasas_cmd *aen_cmd;
1210 	struct mutex aen_mutex;
1211 	struct semaphore ioctl_sem;
1212 
1213 	struct Scsi_Host *host;
1214 
1215 	wait_queue_head_t int_cmd_wait_q;
1216 	wait_queue_head_t abort_cmd_wait_q;
1217 
1218 	struct pci_dev *pdev;
1219 	u32 unique_id;
1220 
1221 	atomic_t fw_outstanding;
1222 	u32 hw_crit_error;
1223 
1224 	struct megasas_instance_template *instancet;
1225 	struct tasklet_struct isr_tasklet;
1226 
1227 	u8 flag;
1228 	u8 unload;
1229 	u8 flag_ieee;
1230 	unsigned long last_time;
1231 
1232 	struct timer_list io_completion_timer;
1233 };
1234 
1235 struct megasas_instance_template {
1236 	void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1237 		u32, struct megasas_register_set __iomem *);
1238 
1239 	void (*enable_intr)(struct megasas_register_set __iomem *) ;
1240 	void (*disable_intr)(struct megasas_register_set __iomem *);
1241 
1242 	int (*clear_intr)(struct megasas_register_set __iomem *);
1243 
1244 	u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1245 };
1246 
1247 #define MEGASAS_IS_LOGICAL(scp)						\
1248 	(scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1249 
1250 #define MEGASAS_DEV_INDEX(inst, scp)					\
1251 	((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + 	\
1252 	scp->device->id
1253 
1254 struct megasas_cmd {
1255 
1256 	union megasas_frame *frame;
1257 	dma_addr_t frame_phys_addr;
1258 	u8 *sense;
1259 	dma_addr_t sense_phys_addr;
1260 
1261 	u32 index;
1262 	u8 sync_cmd;
1263 	u8 cmd_status;
1264 	u16 abort_aen;
1265 
1266 	struct list_head list;
1267 	struct scsi_cmnd *scmd;
1268 	struct megasas_instance *instance;
1269 	u32 frame_count;
1270 };
1271 
1272 #define MAX_MGMT_ADAPTERS		1024
1273 #define MAX_IOCTL_SGE			16
1274 
1275 struct megasas_iocpacket {
1276 
1277 	u16 host_no;
1278 	u16 __pad1;
1279 	u32 sgl_off;
1280 	u32 sge_count;
1281 	u32 sense_off;
1282 	u32 sense_len;
1283 	union {
1284 		u8 raw[128];
1285 		struct megasas_header hdr;
1286 	} frame;
1287 
1288 	struct iovec sgl[MAX_IOCTL_SGE];
1289 
1290 } __attribute__ ((packed));
1291 
1292 struct megasas_aen {
1293 	u16 host_no;
1294 	u16 __pad1;
1295 	u32 seq_num;
1296 	u32 class_locale_word;
1297 } __attribute__ ((packed));
1298 
1299 #ifdef CONFIG_COMPAT
1300 struct compat_megasas_iocpacket {
1301 	u16 host_no;
1302 	u16 __pad1;
1303 	u32 sgl_off;
1304 	u32 sge_count;
1305 	u32 sense_off;
1306 	u32 sense_len;
1307 	union {
1308 		u8 raw[128];
1309 		struct megasas_header hdr;
1310 	} frame;
1311 	struct compat_iovec sgl[MAX_IOCTL_SGE];
1312 } __attribute__ ((packed));
1313 
1314 #define MEGASAS_IOC_FIRMWARE32	_IOWR('M', 1, struct compat_megasas_iocpacket)
1315 #endif
1316 
1317 #define MEGASAS_IOC_FIRMWARE	_IOWR('M', 1, struct megasas_iocpacket)
1318 #define MEGASAS_IOC_GET_AEN	_IOW('M', 3, struct megasas_aen)
1319 
1320 struct megasas_mgmt_info {
1321 
1322 	u16 count;
1323 	struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1324 	int max_index;
1325 };
1326 
1327 #endif				/*LSI_MEGARAID_SAS_H */
1328