1 /*
2  *
3  *		Linux MegaRAID driver for SAS based RAID controllers
4  *
5  * Copyright (c) 2003-2005  LSI Corporation.
6  *
7  *		This program is free software; you can redistribute it and/or
8  *		modify it under the terms of the GNU General Public License
9  *		as published by the Free Software Foundation; either version
10  *		2 of the License, or (at your option) any later version.
11  *
12  * FILE		: megaraid_sas.h
13  */
14 
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
17 
18 /*
19  * MegaRAID SAS Driver meta data
20  */
21 #define MEGASAS_VERSION			"00.00.03.20-rc1"
22 #define MEGASAS_RELDATE			"March 10, 2008"
23 #define MEGASAS_EXT_VERSION		"Mon. March 10 11:02:31 PDT 2008"
24 
25 /*
26  * Device IDs
27  */
28 #define	PCI_DEVICE_ID_LSI_SAS1078R		0x0060
29 #define	PCI_DEVICE_ID_LSI_SAS1078DE		0x007C
30 #define	PCI_DEVICE_ID_LSI_VERDE_ZCR		0x0413
31 
32 /*
33  * =====================================
34  * MegaRAID SAS MFI firmware definitions
35  * =====================================
36  */
37 
38 /*
39  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
40  * protocol between the software and firmware. Commands are issued using
41  * "message frames"
42  */
43 
44 /*
45  * FW posts its state in upper 4 bits of outbound_msg_0 register
46  */
47 #define MFI_STATE_MASK				0xF0000000
48 #define MFI_STATE_UNDEFINED			0x00000000
49 #define MFI_STATE_BB_INIT			0x10000000
50 #define MFI_STATE_FW_INIT			0x40000000
51 #define MFI_STATE_WAIT_HANDSHAKE		0x60000000
52 #define MFI_STATE_FW_INIT_2			0x70000000
53 #define MFI_STATE_DEVICE_SCAN			0x80000000
54 #define MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
55 #define MFI_STATE_FLUSH_CACHE			0xA0000000
56 #define MFI_STATE_READY				0xB0000000
57 #define MFI_STATE_OPERATIONAL			0xC0000000
58 #define MFI_STATE_FAULT				0xF0000000
59 
60 #define MEGAMFI_FRAME_SIZE			64
61 
62 /*
63  * During FW init, clear pending cmds & reset state using inbound_msg_0
64  *
65  * ABORT	: Abort all pending cmds
66  * READY	: Move from OPERATIONAL to READY state; discard queue info
67  * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
68  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
69  * HOTPLUG	: Resume from Hotplug
70  * MFI_STOP_ADP	: Send signal to FW to stop processing
71  */
72 #define MFI_INIT_ABORT				0x00000001
73 #define MFI_INIT_READY				0x00000002
74 #define MFI_INIT_MFIMODE			0x00000004
75 #define MFI_INIT_CLEAR_HANDSHAKE		0x00000008
76 #define MFI_INIT_HOTPLUG			0x00000010
77 #define MFI_STOP_ADP				0x00000020
78 #define MFI_RESET_FLAGS				MFI_INIT_READY| \
79 						MFI_INIT_MFIMODE| \
80 						MFI_INIT_ABORT
81 
82 /*
83  * MFI frame flags
84  */
85 #define MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
86 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
87 #define MFI_FRAME_SGL32				0x0000
88 #define MFI_FRAME_SGL64				0x0002
89 #define MFI_FRAME_SENSE32			0x0000
90 #define MFI_FRAME_SENSE64			0x0004
91 #define MFI_FRAME_DIR_NONE			0x0000
92 #define MFI_FRAME_DIR_WRITE			0x0008
93 #define MFI_FRAME_DIR_READ			0x0010
94 #define MFI_FRAME_DIR_BOTH			0x0018
95 
96 /*
97  * Definition for cmd_status
98  */
99 #define MFI_CMD_STATUS_POLL_MODE		0xFF
100 
101 /*
102  * MFI command opcodes
103  */
104 #define MFI_CMD_INIT				0x00
105 #define MFI_CMD_LD_READ				0x01
106 #define MFI_CMD_LD_WRITE			0x02
107 #define MFI_CMD_LD_SCSI_IO			0x03
108 #define MFI_CMD_PD_SCSI_IO			0x04
109 #define MFI_CMD_DCMD				0x05
110 #define MFI_CMD_ABORT				0x06
111 #define MFI_CMD_SMP				0x07
112 #define MFI_CMD_STP				0x08
113 
114 #define MR_DCMD_CTRL_GET_INFO			0x01010000
115 
116 #define MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
117 #define MR_FLUSH_CTRL_CACHE			0x01
118 #define MR_FLUSH_DISK_CACHE			0x02
119 
120 #define MR_DCMD_CTRL_SHUTDOWN			0x01050000
121 #define MR_DCMD_HIBERNATE_SHUTDOWN		0x01060000
122 #define MR_ENABLE_DRIVE_SPINDOWN		0x01
123 
124 #define MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
125 #define MR_DCMD_CTRL_EVENT_GET			0x01040300
126 #define MR_DCMD_CTRL_EVENT_WAIT			0x01040500
127 #define MR_DCMD_LD_GET_PROPERTIES		0x03030000
128 
129 #define MR_DCMD_CLUSTER				0x08000000
130 #define MR_DCMD_CLUSTER_RESET_ALL		0x08010100
131 #define MR_DCMD_CLUSTER_RESET_LD		0x08010200
132 
133 /*
134  * MFI command completion codes
135  */
136 enum MFI_STAT {
137 	MFI_STAT_OK = 0x00,
138 	MFI_STAT_INVALID_CMD = 0x01,
139 	MFI_STAT_INVALID_DCMD = 0x02,
140 	MFI_STAT_INVALID_PARAMETER = 0x03,
141 	MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
142 	MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
143 	MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
144 	MFI_STAT_APP_IN_USE = 0x07,
145 	MFI_STAT_APP_NOT_INITIALIZED = 0x08,
146 	MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
147 	MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
148 	MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
149 	MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
150 	MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
151 	MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
152 	MFI_STAT_FLASH_BUSY = 0x0f,
153 	MFI_STAT_FLASH_ERROR = 0x10,
154 	MFI_STAT_FLASH_IMAGE_BAD = 0x11,
155 	MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
156 	MFI_STAT_FLASH_NOT_OPEN = 0x13,
157 	MFI_STAT_FLASH_NOT_STARTED = 0x14,
158 	MFI_STAT_FLUSH_FAILED = 0x15,
159 	MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
160 	MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
161 	MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
162 	MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
163 	MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
164 	MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
165 	MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
166 	MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
167 	MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
168 	MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
169 	MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
170 	MFI_STAT_MFC_HW_ERROR = 0x21,
171 	MFI_STAT_NO_HW_PRESENT = 0x22,
172 	MFI_STAT_NOT_FOUND = 0x23,
173 	MFI_STAT_NOT_IN_ENCL = 0x24,
174 	MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
175 	MFI_STAT_PD_TYPE_WRONG = 0x26,
176 	MFI_STAT_PR_DISABLED = 0x27,
177 	MFI_STAT_ROW_INDEX_INVALID = 0x28,
178 	MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
179 	MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
180 	MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
181 	MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
182 	MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
183 	MFI_STAT_SCSI_IO_FAILED = 0x2e,
184 	MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
185 	MFI_STAT_SHUTDOWN_FAILED = 0x30,
186 	MFI_STAT_TIME_NOT_SET = 0x31,
187 	MFI_STAT_WRONG_STATE = 0x32,
188 	MFI_STAT_LD_OFFLINE = 0x33,
189 	MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
190 	MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
191 	MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
192 	MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
193 	MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
194 
195 	MFI_STAT_INVALID_STATUS = 0xFF
196 };
197 
198 /*
199  * Number of mailbox bytes in DCMD message frame
200  */
201 #define MFI_MBOX_SIZE				12
202 
203 enum MR_EVT_CLASS {
204 
205 	MR_EVT_CLASS_DEBUG = -2,
206 	MR_EVT_CLASS_PROGRESS = -1,
207 	MR_EVT_CLASS_INFO = 0,
208 	MR_EVT_CLASS_WARNING = 1,
209 	MR_EVT_CLASS_CRITICAL = 2,
210 	MR_EVT_CLASS_FATAL = 3,
211 	MR_EVT_CLASS_DEAD = 4,
212 
213 };
214 
215 enum MR_EVT_LOCALE {
216 
217 	MR_EVT_LOCALE_LD = 0x0001,
218 	MR_EVT_LOCALE_PD = 0x0002,
219 	MR_EVT_LOCALE_ENCL = 0x0004,
220 	MR_EVT_LOCALE_BBU = 0x0008,
221 	MR_EVT_LOCALE_SAS = 0x0010,
222 	MR_EVT_LOCALE_CTRL = 0x0020,
223 	MR_EVT_LOCALE_CONFIG = 0x0040,
224 	MR_EVT_LOCALE_CLUSTER = 0x0080,
225 	MR_EVT_LOCALE_ALL = 0xffff,
226 
227 };
228 
229 enum MR_EVT_ARGS {
230 
231 	MR_EVT_ARGS_NONE,
232 	MR_EVT_ARGS_CDB_SENSE,
233 	MR_EVT_ARGS_LD,
234 	MR_EVT_ARGS_LD_COUNT,
235 	MR_EVT_ARGS_LD_LBA,
236 	MR_EVT_ARGS_LD_OWNER,
237 	MR_EVT_ARGS_LD_LBA_PD_LBA,
238 	MR_EVT_ARGS_LD_PROG,
239 	MR_EVT_ARGS_LD_STATE,
240 	MR_EVT_ARGS_LD_STRIP,
241 	MR_EVT_ARGS_PD,
242 	MR_EVT_ARGS_PD_ERR,
243 	MR_EVT_ARGS_PD_LBA,
244 	MR_EVT_ARGS_PD_LBA_LD,
245 	MR_EVT_ARGS_PD_PROG,
246 	MR_EVT_ARGS_PD_STATE,
247 	MR_EVT_ARGS_PCI,
248 	MR_EVT_ARGS_RATE,
249 	MR_EVT_ARGS_STR,
250 	MR_EVT_ARGS_TIME,
251 	MR_EVT_ARGS_ECC,
252 
253 };
254 
255 /*
256  * SAS controller properties
257  */
258 struct megasas_ctrl_prop {
259 
260 	u16 seq_num;
261 	u16 pred_fail_poll_interval;
262 	u16 intr_throttle_count;
263 	u16 intr_throttle_timeouts;
264 	u8 rebuild_rate;
265 	u8 patrol_read_rate;
266 	u8 bgi_rate;
267 	u8 cc_rate;
268 	u8 recon_rate;
269 	u8 cache_flush_interval;
270 	u8 spinup_drv_count;
271 	u8 spinup_delay;
272 	u8 cluster_enable;
273 	u8 coercion_mode;
274 	u8 alarm_enable;
275 	u8 disable_auto_rebuild;
276 	u8 disable_battery_warn;
277 	u8 ecc_bucket_size;
278 	u16 ecc_bucket_leak_rate;
279 	u8 restore_hotspare_on_insertion;
280 	u8 expose_encl_devices;
281 	u8 reserved[38];
282 
283 } __attribute__ ((packed));
284 
285 /*
286  * SAS controller information
287  */
288 struct megasas_ctrl_info {
289 
290 	/*
291 	 * PCI device information
292 	 */
293 	struct {
294 
295 		u16 vendor_id;
296 		u16 device_id;
297 		u16 sub_vendor_id;
298 		u16 sub_device_id;
299 		u8 reserved[24];
300 
301 	} __attribute__ ((packed)) pci;
302 
303 	/*
304 	 * Host interface information
305 	 */
306 	struct {
307 
308 		u8 PCIX:1;
309 		u8 PCIE:1;
310 		u8 iSCSI:1;
311 		u8 SAS_3G:1;
312 		u8 reserved_0:4;
313 		u8 reserved_1[6];
314 		u8 port_count;
315 		u64 port_addr[8];
316 
317 	} __attribute__ ((packed)) host_interface;
318 
319 	/*
320 	 * Device (backend) interface information
321 	 */
322 	struct {
323 
324 		u8 SPI:1;
325 		u8 SAS_3G:1;
326 		u8 SATA_1_5G:1;
327 		u8 SATA_3G:1;
328 		u8 reserved_0:4;
329 		u8 reserved_1[6];
330 		u8 port_count;
331 		u64 port_addr[8];
332 
333 	} __attribute__ ((packed)) device_interface;
334 
335 	/*
336 	 * List of components residing in flash. All str are null terminated
337 	 */
338 	u32 image_check_word;
339 	u32 image_component_count;
340 
341 	struct {
342 
343 		char name[8];
344 		char version[32];
345 		char build_date[16];
346 		char built_time[16];
347 
348 	} __attribute__ ((packed)) image_component[8];
349 
350 	/*
351 	 * List of flash components that have been flashed on the card, but
352 	 * are not in use, pending reset of the adapter. This list will be
353 	 * empty if a flash operation has not occurred. All stings are null
354 	 * terminated
355 	 */
356 	u32 pending_image_component_count;
357 
358 	struct {
359 
360 		char name[8];
361 		char version[32];
362 		char build_date[16];
363 		char build_time[16];
364 
365 	} __attribute__ ((packed)) pending_image_component[8];
366 
367 	u8 max_arms;
368 	u8 max_spans;
369 	u8 max_arrays;
370 	u8 max_lds;
371 
372 	char product_name[80];
373 	char serial_no[32];
374 
375 	/*
376 	 * Other physical/controller/operation information. Indicates the
377 	 * presence of the hardware
378 	 */
379 	struct {
380 
381 		u32 bbu:1;
382 		u32 alarm:1;
383 		u32 nvram:1;
384 		u32 uart:1;
385 		u32 reserved:28;
386 
387 	} __attribute__ ((packed)) hw_present;
388 
389 	u32 current_fw_time;
390 
391 	/*
392 	 * Maximum data transfer sizes
393 	 */
394 	u16 max_concurrent_cmds;
395 	u16 max_sge_count;
396 	u32 max_request_size;
397 
398 	/*
399 	 * Logical and physical device counts
400 	 */
401 	u16 ld_present_count;
402 	u16 ld_degraded_count;
403 	u16 ld_offline_count;
404 
405 	u16 pd_present_count;
406 	u16 pd_disk_present_count;
407 	u16 pd_disk_pred_failure_count;
408 	u16 pd_disk_failed_count;
409 
410 	/*
411 	 * Memory size information
412 	 */
413 	u16 nvram_size;
414 	u16 memory_size;
415 	u16 flash_size;
416 
417 	/*
418 	 * Error counters
419 	 */
420 	u16 mem_correctable_error_count;
421 	u16 mem_uncorrectable_error_count;
422 
423 	/*
424 	 * Cluster information
425 	 */
426 	u8 cluster_permitted;
427 	u8 cluster_active;
428 
429 	/*
430 	 * Additional max data transfer sizes
431 	 */
432 	u16 max_strips_per_io;
433 
434 	/*
435 	 * Controller capabilities structures
436 	 */
437 	struct {
438 
439 		u32 raid_level_0:1;
440 		u32 raid_level_1:1;
441 		u32 raid_level_5:1;
442 		u32 raid_level_1E:1;
443 		u32 raid_level_6:1;
444 		u32 reserved:27;
445 
446 	} __attribute__ ((packed)) raid_levels;
447 
448 	struct {
449 
450 		u32 rbld_rate:1;
451 		u32 cc_rate:1;
452 		u32 bgi_rate:1;
453 		u32 recon_rate:1;
454 		u32 patrol_rate:1;
455 		u32 alarm_control:1;
456 		u32 cluster_supported:1;
457 		u32 bbu:1;
458 		u32 spanning_allowed:1;
459 		u32 dedicated_hotspares:1;
460 		u32 revertible_hotspares:1;
461 		u32 foreign_config_import:1;
462 		u32 self_diagnostic:1;
463 		u32 mixed_redundancy_arr:1;
464 		u32 global_hot_spares:1;
465 		u32 reserved:17;
466 
467 	} __attribute__ ((packed)) adapter_operations;
468 
469 	struct {
470 
471 		u32 read_policy:1;
472 		u32 write_policy:1;
473 		u32 io_policy:1;
474 		u32 access_policy:1;
475 		u32 disk_cache_policy:1;
476 		u32 reserved:27;
477 
478 	} __attribute__ ((packed)) ld_operations;
479 
480 	struct {
481 
482 		u8 min;
483 		u8 max;
484 		u8 reserved[2];
485 
486 	} __attribute__ ((packed)) stripe_sz_ops;
487 
488 	struct {
489 
490 		u32 force_online:1;
491 		u32 force_offline:1;
492 		u32 force_rebuild:1;
493 		u32 reserved:29;
494 
495 	} __attribute__ ((packed)) pd_operations;
496 
497 	struct {
498 
499 		u32 ctrl_supports_sas:1;
500 		u32 ctrl_supports_sata:1;
501 		u32 allow_mix_in_encl:1;
502 		u32 allow_mix_in_ld:1;
503 		u32 allow_sata_in_cluster:1;
504 		u32 reserved:27;
505 
506 	} __attribute__ ((packed)) pd_mix_support;
507 
508 	/*
509 	 * Define ECC single-bit-error bucket information
510 	 */
511 	u8 ecc_bucket_count;
512 	u8 reserved_2[11];
513 
514 	/*
515 	 * Include the controller properties (changeable items)
516 	 */
517 	struct megasas_ctrl_prop properties;
518 
519 	/*
520 	 * Define FW pkg version (set in envt v'bles on OEM basis)
521 	 */
522 	char package_version[0x60];
523 
524 	u8 pad[0x800 - 0x6a0];
525 
526 } __attribute__ ((packed));
527 
528 /*
529  * ===============================
530  * MegaRAID SAS driver definitions
531  * ===============================
532  */
533 #define MEGASAS_MAX_PD_CHANNELS			2
534 #define MEGASAS_MAX_LD_CHANNELS			2
535 #define MEGASAS_MAX_CHANNELS			(MEGASAS_MAX_PD_CHANNELS + \
536 						MEGASAS_MAX_LD_CHANNELS)
537 #define MEGASAS_MAX_DEV_PER_CHANNEL		128
538 #define MEGASAS_DEFAULT_INIT_ID			-1
539 #define MEGASAS_MAX_LUN				8
540 #define MEGASAS_MAX_LD				64
541 
542 #define MEGASAS_DBG_LVL				1
543 
544 #define MEGASAS_FW_BUSY				1
545 
546 /* Frame Type */
547 #define IO_FRAME				0
548 #define PTHRU_FRAME				1
549 
550 /*
551  * When SCSI mid-layer calls driver's reset routine, driver waits for
552  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
553  * that the driver cannot _actually_ abort or reset pending commands. While
554  * it is waiting for the commands to complete, it prints a diagnostic message
555  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
556  */
557 #define MEGASAS_RESET_WAIT_TIME			180
558 #define MEGASAS_INTERNAL_CMD_WAIT_TIME		180
559 #define	MEGASAS_RESET_NOTICE_INTERVAL		5
560 #define MEGASAS_IOCTL_CMD			0
561 #define MEGASAS_DEFAULT_CMD_TIMEOUT		90
562 
563 /*
564  * FW reports the maximum of number of commands that it can accept (maximum
565  * commands that can be outstanding) at any time. The driver must report a
566  * lower number to the mid layer because it can issue a few internal commands
567  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
568  * is shown below
569  */
570 #define MEGASAS_INT_CMDS			32
571 
572 /*
573  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
574  * SGLs based on the size of dma_addr_t
575  */
576 #define IS_DMA64				(sizeof(dma_addr_t) == 8)
577 
578 #define MFI_OB_INTR_STATUS_MASK			0x00000002
579 #define MFI_POLL_TIMEOUT_SECS			60
580 #define MEGASAS_COMPLETION_TIMER_INTERVAL      (HZ/10)
581 
582 #define MFI_REPLY_1078_MESSAGE_INTERRUPT	0x80000000
583 
584 /*
585 * register set for both 1068 and 1078 controllers
586 * structure extended for 1078 registers
587 */
588 
589 struct megasas_register_set {
590 	u32 	reserved_0[4];			/*0000h*/
591 
592 	u32 	inbound_msg_0;			/*0010h*/
593 	u32 	inbound_msg_1;			/*0014h*/
594 	u32 	outbound_msg_0;			/*0018h*/
595 	u32 	outbound_msg_1;			/*001Ch*/
596 
597 	u32 	inbound_doorbell;		/*0020h*/
598 	u32 	inbound_intr_status;		/*0024h*/
599 	u32 	inbound_intr_mask;		/*0028h*/
600 
601 	u32 	outbound_doorbell;		/*002Ch*/
602 	u32 	outbound_intr_status;		/*0030h*/
603 	u32 	outbound_intr_mask;		/*0034h*/
604 
605 	u32 	reserved_1[2];			/*0038h*/
606 
607 	u32 	inbound_queue_port;		/*0040h*/
608 	u32 	outbound_queue_port;		/*0044h*/
609 
610 	u32 	reserved_2[22];			/*0048h*/
611 
612 	u32 	outbound_doorbell_clear;	/*00A0h*/
613 
614 	u32 	reserved_3[3];			/*00A4h*/
615 
616 	u32 	outbound_scratch_pad ;		/*00B0h*/
617 
618 	u32 	reserved_4[3];			/*00B4h*/
619 
620 	u32 	inbound_low_queue_port ;	/*00C0h*/
621 
622 	u32 	inbound_high_queue_port ;	/*00C4h*/
623 
624 	u32 	reserved_5;			/*00C8h*/
625 	u32 	index_registers[820];		/*00CCh*/
626 
627 } __attribute__ ((packed));
628 
629 struct megasas_sge32 {
630 
631 	u32 phys_addr;
632 	u32 length;
633 
634 } __attribute__ ((packed));
635 
636 struct megasas_sge64 {
637 
638 	u64 phys_addr;
639 	u32 length;
640 
641 } __attribute__ ((packed));
642 
643 union megasas_sgl {
644 
645 	struct megasas_sge32 sge32[1];
646 	struct megasas_sge64 sge64[1];
647 
648 } __attribute__ ((packed));
649 
650 struct megasas_header {
651 
652 	u8 cmd;			/*00h */
653 	u8 sense_len;		/*01h */
654 	u8 cmd_status;		/*02h */
655 	u8 scsi_status;		/*03h */
656 
657 	u8 target_id;		/*04h */
658 	u8 lun;			/*05h */
659 	u8 cdb_len;		/*06h */
660 	u8 sge_count;		/*07h */
661 
662 	u32 context;		/*08h */
663 	u32 pad_0;		/*0Ch */
664 
665 	u16 flags;		/*10h */
666 	u16 timeout;		/*12h */
667 	u32 data_xferlen;	/*14h */
668 
669 } __attribute__ ((packed));
670 
671 union megasas_sgl_frame {
672 
673 	struct megasas_sge32 sge32[8];
674 	struct megasas_sge64 sge64[5];
675 
676 } __attribute__ ((packed));
677 
678 struct megasas_init_frame {
679 
680 	u8 cmd;			/*00h */
681 	u8 reserved_0;		/*01h */
682 	u8 cmd_status;		/*02h */
683 
684 	u8 reserved_1;		/*03h */
685 	u32 reserved_2;		/*04h */
686 
687 	u32 context;		/*08h */
688 	u32 pad_0;		/*0Ch */
689 
690 	u16 flags;		/*10h */
691 	u16 reserved_3;		/*12h */
692 	u32 data_xfer_len;	/*14h */
693 
694 	u32 queue_info_new_phys_addr_lo;	/*18h */
695 	u32 queue_info_new_phys_addr_hi;	/*1Ch */
696 	u32 queue_info_old_phys_addr_lo;	/*20h */
697 	u32 queue_info_old_phys_addr_hi;	/*24h */
698 
699 	u32 reserved_4[6];	/*28h */
700 
701 } __attribute__ ((packed));
702 
703 struct megasas_init_queue_info {
704 
705 	u32 init_flags;		/*00h */
706 	u32 reply_queue_entries;	/*04h */
707 
708 	u32 reply_queue_start_phys_addr_lo;	/*08h */
709 	u32 reply_queue_start_phys_addr_hi;	/*0Ch */
710 	u32 producer_index_phys_addr_lo;	/*10h */
711 	u32 producer_index_phys_addr_hi;	/*14h */
712 	u32 consumer_index_phys_addr_lo;	/*18h */
713 	u32 consumer_index_phys_addr_hi;	/*1Ch */
714 
715 } __attribute__ ((packed));
716 
717 struct megasas_io_frame {
718 
719 	u8 cmd;			/*00h */
720 	u8 sense_len;		/*01h */
721 	u8 cmd_status;		/*02h */
722 	u8 scsi_status;		/*03h */
723 
724 	u8 target_id;		/*04h */
725 	u8 access_byte;		/*05h */
726 	u8 reserved_0;		/*06h */
727 	u8 sge_count;		/*07h */
728 
729 	u32 context;		/*08h */
730 	u32 pad_0;		/*0Ch */
731 
732 	u16 flags;		/*10h */
733 	u16 timeout;		/*12h */
734 	u32 lba_count;		/*14h */
735 
736 	u32 sense_buf_phys_addr_lo;	/*18h */
737 	u32 sense_buf_phys_addr_hi;	/*1Ch */
738 
739 	u32 start_lba_lo;	/*20h */
740 	u32 start_lba_hi;	/*24h */
741 
742 	union megasas_sgl sgl;	/*28h */
743 
744 } __attribute__ ((packed));
745 
746 struct megasas_pthru_frame {
747 
748 	u8 cmd;			/*00h */
749 	u8 sense_len;		/*01h */
750 	u8 cmd_status;		/*02h */
751 	u8 scsi_status;		/*03h */
752 
753 	u8 target_id;		/*04h */
754 	u8 lun;			/*05h */
755 	u8 cdb_len;		/*06h */
756 	u8 sge_count;		/*07h */
757 
758 	u32 context;		/*08h */
759 	u32 pad_0;		/*0Ch */
760 
761 	u16 flags;		/*10h */
762 	u16 timeout;		/*12h */
763 	u32 data_xfer_len;	/*14h */
764 
765 	u32 sense_buf_phys_addr_lo;	/*18h */
766 	u32 sense_buf_phys_addr_hi;	/*1Ch */
767 
768 	u8 cdb[16];		/*20h */
769 	union megasas_sgl sgl;	/*30h */
770 
771 } __attribute__ ((packed));
772 
773 struct megasas_dcmd_frame {
774 
775 	u8 cmd;			/*00h */
776 	u8 reserved_0;		/*01h */
777 	u8 cmd_status;		/*02h */
778 	u8 reserved_1[4];	/*03h */
779 	u8 sge_count;		/*07h */
780 
781 	u32 context;		/*08h */
782 	u32 pad_0;		/*0Ch */
783 
784 	u16 flags;		/*10h */
785 	u16 timeout;		/*12h */
786 
787 	u32 data_xfer_len;	/*14h */
788 	u32 opcode;		/*18h */
789 
790 	union {			/*1Ch */
791 		u8 b[12];
792 		u16 s[6];
793 		u32 w[3];
794 	} mbox;
795 
796 	union megasas_sgl sgl;	/*28h */
797 
798 } __attribute__ ((packed));
799 
800 struct megasas_abort_frame {
801 
802 	u8 cmd;			/*00h */
803 	u8 reserved_0;		/*01h */
804 	u8 cmd_status;		/*02h */
805 
806 	u8 reserved_1;		/*03h */
807 	u32 reserved_2;		/*04h */
808 
809 	u32 context;		/*08h */
810 	u32 pad_0;		/*0Ch */
811 
812 	u16 flags;		/*10h */
813 	u16 reserved_3;		/*12h */
814 	u32 reserved_4;		/*14h */
815 
816 	u32 abort_context;	/*18h */
817 	u32 pad_1;		/*1Ch */
818 
819 	u32 abort_mfi_phys_addr_lo;	/*20h */
820 	u32 abort_mfi_phys_addr_hi;	/*24h */
821 
822 	u32 reserved_5[6];	/*28h */
823 
824 } __attribute__ ((packed));
825 
826 struct megasas_smp_frame {
827 
828 	u8 cmd;			/*00h */
829 	u8 reserved_1;		/*01h */
830 	u8 cmd_status;		/*02h */
831 	u8 connection_status;	/*03h */
832 
833 	u8 reserved_2[3];	/*04h */
834 	u8 sge_count;		/*07h */
835 
836 	u32 context;		/*08h */
837 	u32 pad_0;		/*0Ch */
838 
839 	u16 flags;		/*10h */
840 	u16 timeout;		/*12h */
841 
842 	u32 data_xfer_len;	/*14h */
843 	u64 sas_addr;		/*18h */
844 
845 	union {
846 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: req */
847 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: req */
848 	} sgl;
849 
850 } __attribute__ ((packed));
851 
852 struct megasas_stp_frame {
853 
854 	u8 cmd;			/*00h */
855 	u8 reserved_1;		/*01h */
856 	u8 cmd_status;		/*02h */
857 	u8 reserved_2;		/*03h */
858 
859 	u8 target_id;		/*04h */
860 	u8 reserved_3[2];	/*05h */
861 	u8 sge_count;		/*07h */
862 
863 	u32 context;		/*08h */
864 	u32 pad_0;		/*0Ch */
865 
866 	u16 flags;		/*10h */
867 	u16 timeout;		/*12h */
868 
869 	u32 data_xfer_len;	/*14h */
870 
871 	u16 fis[10];		/*18h */
872 	u32 stp_flags;
873 
874 	union {
875 		struct megasas_sge32 sge32[2];	/* [0]: resp [1]: data */
876 		struct megasas_sge64 sge64[2];	/* [0]: resp [1]: data */
877 	} sgl;
878 
879 } __attribute__ ((packed));
880 
881 union megasas_frame {
882 
883 	struct megasas_header hdr;
884 	struct megasas_init_frame init;
885 	struct megasas_io_frame io;
886 	struct megasas_pthru_frame pthru;
887 	struct megasas_dcmd_frame dcmd;
888 	struct megasas_abort_frame abort;
889 	struct megasas_smp_frame smp;
890 	struct megasas_stp_frame stp;
891 
892 	u8 raw_bytes[64];
893 };
894 
895 struct megasas_cmd;
896 
897 union megasas_evt_class_locale {
898 
899 	struct {
900 		u16 locale;
901 		u8 reserved;
902 		s8 class;
903 	} __attribute__ ((packed)) members;
904 
905 	u32 word;
906 
907 } __attribute__ ((packed));
908 
909 struct megasas_evt_log_info {
910 	u32 newest_seq_num;
911 	u32 oldest_seq_num;
912 	u32 clear_seq_num;
913 	u32 shutdown_seq_num;
914 	u32 boot_seq_num;
915 
916 } __attribute__ ((packed));
917 
918 struct megasas_progress {
919 
920 	u16 progress;
921 	u16 elapsed_seconds;
922 
923 } __attribute__ ((packed));
924 
925 struct megasas_evtarg_ld {
926 
927 	u16 target_id;
928 	u8 ld_index;
929 	u8 reserved;
930 
931 } __attribute__ ((packed));
932 
933 struct megasas_evtarg_pd {
934 	u16 device_id;
935 	u8 encl_index;
936 	u8 slot_number;
937 
938 } __attribute__ ((packed));
939 
940 struct megasas_evt_detail {
941 
942 	u32 seq_num;
943 	u32 time_stamp;
944 	u32 code;
945 	union megasas_evt_class_locale cl;
946 	u8 arg_type;
947 	u8 reserved1[15];
948 
949 	union {
950 		struct {
951 			struct megasas_evtarg_pd pd;
952 			u8 cdb_length;
953 			u8 sense_length;
954 			u8 reserved[2];
955 			u8 cdb[16];
956 			u8 sense[64];
957 		} __attribute__ ((packed)) cdbSense;
958 
959 		struct megasas_evtarg_ld ld;
960 
961 		struct {
962 			struct megasas_evtarg_ld ld;
963 			u64 count;
964 		} __attribute__ ((packed)) ld_count;
965 
966 		struct {
967 			u64 lba;
968 			struct megasas_evtarg_ld ld;
969 		} __attribute__ ((packed)) ld_lba;
970 
971 		struct {
972 			struct megasas_evtarg_ld ld;
973 			u32 prevOwner;
974 			u32 newOwner;
975 		} __attribute__ ((packed)) ld_owner;
976 
977 		struct {
978 			u64 ld_lba;
979 			u64 pd_lba;
980 			struct megasas_evtarg_ld ld;
981 			struct megasas_evtarg_pd pd;
982 		} __attribute__ ((packed)) ld_lba_pd_lba;
983 
984 		struct {
985 			struct megasas_evtarg_ld ld;
986 			struct megasas_progress prog;
987 		} __attribute__ ((packed)) ld_prog;
988 
989 		struct {
990 			struct megasas_evtarg_ld ld;
991 			u32 prev_state;
992 			u32 new_state;
993 		} __attribute__ ((packed)) ld_state;
994 
995 		struct {
996 			u64 strip;
997 			struct megasas_evtarg_ld ld;
998 		} __attribute__ ((packed)) ld_strip;
999 
1000 		struct megasas_evtarg_pd pd;
1001 
1002 		struct {
1003 			struct megasas_evtarg_pd pd;
1004 			u32 err;
1005 		} __attribute__ ((packed)) pd_err;
1006 
1007 		struct {
1008 			u64 lba;
1009 			struct megasas_evtarg_pd pd;
1010 		} __attribute__ ((packed)) pd_lba;
1011 
1012 		struct {
1013 			u64 lba;
1014 			struct megasas_evtarg_pd pd;
1015 			struct megasas_evtarg_ld ld;
1016 		} __attribute__ ((packed)) pd_lba_ld;
1017 
1018 		struct {
1019 			struct megasas_evtarg_pd pd;
1020 			struct megasas_progress prog;
1021 		} __attribute__ ((packed)) pd_prog;
1022 
1023 		struct {
1024 			struct megasas_evtarg_pd pd;
1025 			u32 prevState;
1026 			u32 newState;
1027 		} __attribute__ ((packed)) pd_state;
1028 
1029 		struct {
1030 			u16 vendorId;
1031 			u16 deviceId;
1032 			u16 subVendorId;
1033 			u16 subDeviceId;
1034 		} __attribute__ ((packed)) pci;
1035 
1036 		u32 rate;
1037 		char str[96];
1038 
1039 		struct {
1040 			u32 rtc;
1041 			u32 elapsedSeconds;
1042 		} __attribute__ ((packed)) time;
1043 
1044 		struct {
1045 			u32 ecar;
1046 			u32 elog;
1047 			char str[64];
1048 		} __attribute__ ((packed)) ecc;
1049 
1050 		u8 b[96];
1051 		u16 s[48];
1052 		u32 w[24];
1053 		u64 d[12];
1054 	} args;
1055 
1056 	char description[128];
1057 
1058 } __attribute__ ((packed));
1059 
1060  struct megasas_instance_template {
1061 	void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1062 
1063 	void (*enable_intr)(struct megasas_register_set __iomem *) ;
1064 	void (*disable_intr)(struct megasas_register_set __iomem *);
1065 
1066 	int (*clear_intr)(struct megasas_register_set __iomem *);
1067 
1068 	u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1069  };
1070 
1071 struct megasas_instance {
1072 
1073 	u32 *producer;
1074 	dma_addr_t producer_h;
1075 	u32 *consumer;
1076 	dma_addr_t consumer_h;
1077 
1078 	u32 *reply_queue;
1079 	dma_addr_t reply_queue_h;
1080 
1081 	unsigned long base_addr;
1082 	struct megasas_register_set __iomem *reg_set;
1083 
1084 	s8 init_id;
1085 
1086 	u16 max_num_sge;
1087 	u16 max_fw_cmds;
1088 	u32 max_sectors_per_req;
1089 
1090 	struct megasas_cmd **cmd_list;
1091 	struct list_head cmd_pool;
1092 	spinlock_t cmd_pool_lock;
1093 	/* used to synch producer, consumer ptrs in dpc */
1094 	spinlock_t completion_lock;
1095 	struct dma_pool *frame_dma_pool;
1096 	struct dma_pool *sense_dma_pool;
1097 
1098 	struct megasas_evt_detail *evt_detail;
1099 	dma_addr_t evt_detail_h;
1100 	struct megasas_cmd *aen_cmd;
1101 	struct mutex aen_mutex;
1102 	struct semaphore ioctl_sem;
1103 
1104 	struct Scsi_Host *host;
1105 
1106 	wait_queue_head_t int_cmd_wait_q;
1107 	wait_queue_head_t abort_cmd_wait_q;
1108 
1109 	struct pci_dev *pdev;
1110 	u32 unique_id;
1111 
1112 	atomic_t fw_outstanding;
1113 	u32 hw_crit_error;
1114 
1115 	struct megasas_instance_template *instancet;
1116 	struct tasklet_struct isr_tasklet;
1117 
1118 	u8 flag;
1119 	unsigned long last_time;
1120 
1121 	struct timer_list io_completion_timer;
1122 };
1123 
1124 #define MEGASAS_IS_LOGICAL(scp)						\
1125 	(scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1126 
1127 #define MEGASAS_DEV_INDEX(inst, scp)					\
1128 	((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + 	\
1129 	scp->device->id
1130 
1131 struct megasas_cmd {
1132 
1133 	union megasas_frame *frame;
1134 	dma_addr_t frame_phys_addr;
1135 	u8 *sense;
1136 	dma_addr_t sense_phys_addr;
1137 
1138 	u32 index;
1139 	u8 sync_cmd;
1140 	u8 cmd_status;
1141 	u16 abort_aen;
1142 
1143 	struct list_head list;
1144 	struct scsi_cmnd *scmd;
1145 	struct megasas_instance *instance;
1146 	u32 frame_count;
1147 };
1148 
1149 #define MAX_MGMT_ADAPTERS		1024
1150 #define MAX_IOCTL_SGE			16
1151 
1152 struct megasas_iocpacket {
1153 
1154 	u16 host_no;
1155 	u16 __pad1;
1156 	u32 sgl_off;
1157 	u32 sge_count;
1158 	u32 sense_off;
1159 	u32 sense_len;
1160 	union {
1161 		u8 raw[128];
1162 		struct megasas_header hdr;
1163 	} frame;
1164 
1165 	struct iovec sgl[MAX_IOCTL_SGE];
1166 
1167 } __attribute__ ((packed));
1168 
1169 struct megasas_aen {
1170 	u16 host_no;
1171 	u16 __pad1;
1172 	u32 seq_num;
1173 	u32 class_locale_word;
1174 } __attribute__ ((packed));
1175 
1176 #ifdef CONFIG_COMPAT
1177 struct compat_megasas_iocpacket {
1178 	u16 host_no;
1179 	u16 __pad1;
1180 	u32 sgl_off;
1181 	u32 sge_count;
1182 	u32 sense_off;
1183 	u32 sense_len;
1184 	union {
1185 		u8 raw[128];
1186 		struct megasas_header hdr;
1187 	} frame;
1188 	struct compat_iovec sgl[MAX_IOCTL_SGE];
1189 } __attribute__ ((packed));
1190 
1191 #define MEGASAS_IOC_FIRMWARE32	_IOWR('M', 1, struct compat_megasas_iocpacket)
1192 #endif
1193 
1194 #define MEGASAS_IOC_FIRMWARE	_IOWR('M', 1, struct megasas_iocpacket)
1195 #define MEGASAS_IOC_GET_AEN	_IOW('M', 3, struct megasas_aen)
1196 
1197 struct megasas_mgmt_info {
1198 
1199 	u16 count;
1200 	struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1201 	int max_index;
1202 };
1203 
1204 #endif				/*LSI_MEGARAID_SAS_H */
1205