1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 3c4a3e0a5SBagalkote, Sreenivas * 4ae59057bSadam radford * Copyright (c) 2003-2012 LSI Corporation. 5c4a3e0a5SBagalkote, Sreenivas * 6c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 7c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 83f1530c1Sadam radford * as published by the Free Software Foundation; either version 2 93f1530c1Sadam radford * of the License, or (at your option) any later version. 103f1530c1Sadam radford * 113f1530c1Sadam radford * This program is distributed in the hope that it will be useful, 123f1530c1Sadam radford * but WITHOUT ANY WARRANTY; without even the implied warranty of 133f1530c1Sadam radford * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 143f1530c1Sadam radford * GNU General Public License for more details. 153f1530c1Sadam radford * 163f1530c1Sadam radford * You should have received a copy of the GNU General Public License 173f1530c1Sadam radford * along with this program; if not, write to the Free Software 183f1530c1Sadam radford * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19c4a3e0a5SBagalkote, Sreenivas * 20c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h 213f1530c1Sadam radford * 223f1530c1Sadam radford * Authors: LSI Corporation 233f1530c1Sadam radford * 243f1530c1Sadam radford * Send feedback to: <megaraidlinux@lsi.com> 253f1530c1Sadam radford * 263f1530c1Sadam radford * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 273f1530c1Sadam radford * ATTN: Linuxraid 28c4a3e0a5SBagalkote, Sreenivas */ 29c4a3e0a5SBagalkote, Sreenivas 30c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 31c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 32c4a3e0a5SBagalkote, Sreenivas 33a69b74d3SRandy Dunlap /* 34c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 35c4a3e0a5SBagalkote, Sreenivas */ 365eca4a67Sadam radford #define MEGASAS_VERSION "06.506.00.00-rc1" 375eca4a67Sadam radford #define MEGASAS_RELDATE "Feb. 9, 2013" 385eca4a67Sadam radford #define MEGASAS_EXT_VERSION "Sat. Feb. 9 17:00:00 PDT 2013" 390e98936cSSumant Patro 400e98936cSSumant Patro /* 410e98936cSSumant Patro * Device IDs 420e98936cSSumant Patro */ 430e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 44af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 450e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 466610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 476610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 4887911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 4987911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 509c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b 5136807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d 5221d3c710SSumit.Saxena@lsi.com #define PCI_DEVICE_ID_LSI_FURY 0x005f 530e98936cSSumant Patro 54c4a3e0a5SBagalkote, Sreenivas /* 5539b72c3cSSumit.Saxena@lsi.com * Intel HBA SSDIDs 5639b72c3cSSumit.Saxena@lsi.com */ 5739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 5839b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 5939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 6039b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 6139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 6239b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 6339b72c3cSSumit.Saxena@lsi.com 6439b72c3cSSumit.Saxena@lsi.com /* 6539b72c3cSSumit.Saxena@lsi.com * Intel HBA branding 6639b72c3cSSumit.Saxena@lsi.com */ 6739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_BRANDING \ 6839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC080" 6939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_BRANDING \ 7039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC040" 7139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_BRANDING \ 7239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3SC008" 7339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_BRANDING \ 7439b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3MC044" 7539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_BRANDING \ 7639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC080" 7739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_BRANDING \ 7839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC040" 7939b72c3cSSumit.Saxena@lsi.com 8039b72c3cSSumit.Saxena@lsi.com /* 81c4a3e0a5SBagalkote, Sreenivas * ===================================== 82c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 83c4a3e0a5SBagalkote, Sreenivas * ===================================== 84c4a3e0a5SBagalkote, Sreenivas */ 85c4a3e0a5SBagalkote, Sreenivas 86c4a3e0a5SBagalkote, Sreenivas /* 87c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 88c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 89c4a3e0a5SBagalkote, Sreenivas * "message frames" 90c4a3e0a5SBagalkote, Sreenivas */ 91c4a3e0a5SBagalkote, Sreenivas 92a69b74d3SRandy Dunlap /* 93c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 94c4a3e0a5SBagalkote, Sreenivas */ 95c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 96c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 97c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 98c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 99c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 100c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 101c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 102e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 103c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 104c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 105c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 106c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 10739a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 1087e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002 109c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 110c4a3e0a5SBagalkote, Sreenivas 111a69b74d3SRandy Dunlap /* 112c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 113c4a3e0a5SBagalkote, Sreenivas * 114c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 115c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 116c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 117c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 118e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 119e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 120c4a3e0a5SBagalkote, Sreenivas */ 12139a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 12239a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 12339a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 12439a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 12539a98554Sbo yang 12639a98554Sbo yang #define MFI_ADP_RESET 0x00000040 127e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 128c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 129c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 130c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 131e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 132e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 133e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 134e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 135e3bbff9fSSumant Patro MFI_INIT_ABORT 136c4a3e0a5SBagalkote, Sreenivas 137a69b74d3SRandy Dunlap /* 138c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 139c4a3e0a5SBagalkote, Sreenivas */ 140c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 141c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 142c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 143c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 144c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 145c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 146c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 147c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 148c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 149c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 150f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 151c4a3e0a5SBagalkote, Sreenivas 152a69b74d3SRandy Dunlap /* 153c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 154c4a3e0a5SBagalkote, Sreenivas */ 155c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 156c4a3e0a5SBagalkote, Sreenivas 157a69b74d3SRandy Dunlap /* 158c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 159c4a3e0a5SBagalkote, Sreenivas */ 160c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 161c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 162c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 163c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 164c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 165c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 166c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 167c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 168c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 169e5f93a36Sadam radford #define MFI_CMD_INVALID 0xff 170c4a3e0a5SBagalkote, Sreenivas 171c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 172bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 173c4a3e0a5SBagalkote, Sreenivas 174c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 175c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 176c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 177c4a3e0a5SBagalkote, Sreenivas 178c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 17931ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 180c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 181c4a3e0a5SBagalkote, Sreenivas 182c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 183c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 184c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 185c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 186c4a3e0a5SBagalkote, Sreenivas 187c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 188c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 189c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 19081e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 191c4a3e0a5SBagalkote, Sreenivas 192a69b74d3SRandy Dunlap /* 193c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 194c4a3e0a5SBagalkote, Sreenivas */ 195c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 196c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 197c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 198c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 199c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 200c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 201c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 202c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 203c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 204c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 205c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 206c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 207c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 208c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 209c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 210c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 211c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 212c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 213c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 214c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 215c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 216c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 217c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 218c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 219c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 220c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 221c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 222c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 223c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 224c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 225c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 226c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 227c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 228c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 229c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 230c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 231c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 232c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 233c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 234c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 235c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 236c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 237c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 238c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 239c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 240c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 241c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 242c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 243c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 244c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 245c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 246c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 247c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 248c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 249c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 250c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 251c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 252c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 25336807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 254c4a3e0a5SBagalkote, Sreenivas 255c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 256c4a3e0a5SBagalkote, Sreenivas }; 257c4a3e0a5SBagalkote, Sreenivas 258c4a3e0a5SBagalkote, Sreenivas /* 259c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 260c4a3e0a5SBagalkote, Sreenivas */ 261c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 262c4a3e0a5SBagalkote, Sreenivas 263c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 264c4a3e0a5SBagalkote, Sreenivas 265c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 266c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 267c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 268c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 269c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 270c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 271c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 272c4a3e0a5SBagalkote, Sreenivas 273c4a3e0a5SBagalkote, Sreenivas }; 274c4a3e0a5SBagalkote, Sreenivas 275c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 276c4a3e0a5SBagalkote, Sreenivas 277c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 278c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 279c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 280c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 281c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 282c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 283c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 284c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 285c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 286c4a3e0a5SBagalkote, Sreenivas 287c4a3e0a5SBagalkote, Sreenivas }; 288c4a3e0a5SBagalkote, Sreenivas 289c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 290c4a3e0a5SBagalkote, Sreenivas 291c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 292c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 293c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 294c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 295c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 296c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 297c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 298c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 299c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 300c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 301c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 302c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 303c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 304c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 305c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 306c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 307c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 308c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 309c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 310c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 311c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 31281e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 31381e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 31481e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 31581e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 31681e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 31781e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 31881e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 31981e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 32081e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 32181e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 32281e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 32381e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 32481e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 32581e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 32681e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 32781e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 328c4a3e0a5SBagalkote, Sreenivas }; 329c4a3e0a5SBagalkote, Sreenivas 330c4a3e0a5SBagalkote, Sreenivas /* 33181e403ceSYang, Bo * define constants for device list query options 33281e403ceSYang, Bo */ 33381e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 33481e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 33581e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 33681e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 33781e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 33881e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 33981e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 34081e403ceSYang, Bo }; 34181e403ceSYang, Bo 3427e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 3437e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 3447e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 3457e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 3467e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 3477e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 3487e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 3497e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 3507e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 3517e8a75f4SYang, Bo #define MAX_LOGICAL_DRIVES 64 3527e8a75f4SYang, Bo 35381e403ceSYang, Bo enum MR_PD_STATE { 35481e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 35581e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 35681e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 35781e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 35881e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 35981e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 36081e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 36181e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 36281e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 36381e403ceSYang, Bo }; 36481e403ceSYang, Bo 36581e403ceSYang, Bo 36681e403ceSYang, Bo /* 36781e403ceSYang, Bo * defines the physical drive address structure 36881e403ceSYang, Bo */ 36981e403ceSYang, Bo struct MR_PD_ADDRESS { 37081e403ceSYang, Bo u16 deviceId; 37181e403ceSYang, Bo u16 enclDeviceId; 37281e403ceSYang, Bo 37381e403ceSYang, Bo union { 37481e403ceSYang, Bo struct { 37581e403ceSYang, Bo u8 enclIndex; 37681e403ceSYang, Bo u8 slotNumber; 37781e403ceSYang, Bo } mrPdAddress; 37881e403ceSYang, Bo struct { 37981e403ceSYang, Bo u8 enclPosition; 38081e403ceSYang, Bo u8 enclConnectorIndex; 38181e403ceSYang, Bo } mrEnclAddress; 38281e403ceSYang, Bo }; 38381e403ceSYang, Bo u8 scsiDevType; 38481e403ceSYang, Bo union { 38581e403ceSYang, Bo u8 connectedPortBitmap; 38681e403ceSYang, Bo u8 connectedPortNumbers; 38781e403ceSYang, Bo }; 38881e403ceSYang, Bo u64 sasAddr[2]; 38981e403ceSYang, Bo } __packed; 39081e403ceSYang, Bo 39181e403ceSYang, Bo /* 39281e403ceSYang, Bo * defines the physical drive list structure 39381e403ceSYang, Bo */ 39481e403ceSYang, Bo struct MR_PD_LIST { 39581e403ceSYang, Bo u32 size; 39681e403ceSYang, Bo u32 count; 39781e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 39881e403ceSYang, Bo } __packed; 39981e403ceSYang, Bo 40081e403ceSYang, Bo struct megasas_pd_list { 40181e403ceSYang, Bo u16 tid; 40281e403ceSYang, Bo u8 driveType; 40381e403ceSYang, Bo u8 driveState; 40481e403ceSYang, Bo } __packed; 40581e403ceSYang, Bo 40681e403ceSYang, Bo /* 407bdc6fb8dSYang, Bo * defines the logical drive reference structure 408bdc6fb8dSYang, Bo */ 409bdc6fb8dSYang, Bo union MR_LD_REF { 410bdc6fb8dSYang, Bo struct { 411bdc6fb8dSYang, Bo u8 targetId; 412bdc6fb8dSYang, Bo u8 reserved; 413bdc6fb8dSYang, Bo u16 seqNum; 414bdc6fb8dSYang, Bo }; 415bdc6fb8dSYang, Bo u32 ref; 416bdc6fb8dSYang, Bo } __packed; 417bdc6fb8dSYang, Bo 418bdc6fb8dSYang, Bo /* 419bdc6fb8dSYang, Bo * defines the logical drive list structure 420bdc6fb8dSYang, Bo */ 421bdc6fb8dSYang, Bo struct MR_LD_LIST { 422bdc6fb8dSYang, Bo u32 ldCount; 423bdc6fb8dSYang, Bo u32 reserved; 424bdc6fb8dSYang, Bo struct { 425bdc6fb8dSYang, Bo union MR_LD_REF ref; 426bdc6fb8dSYang, Bo u8 state; 427bdc6fb8dSYang, Bo u8 reserved[3]; 428bdc6fb8dSYang, Bo u64 size; 429bdc6fb8dSYang, Bo } ldList[MAX_LOGICAL_DRIVES]; 430bdc6fb8dSYang, Bo } __packed; 431bdc6fb8dSYang, Bo 432bdc6fb8dSYang, Bo /* 433c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 434c4a3e0a5SBagalkote, Sreenivas */ 435c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 436c4a3e0a5SBagalkote, Sreenivas 437c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 438c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 439c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 440c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 441c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 442c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 443c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 444c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 445c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 446c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 447c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 448c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 449c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 450c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 451c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 452c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 453c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 454c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 455c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 456c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 457c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 45839a98554Sbo yang u8 maintainPdFailHistory; 45939a98554Sbo yang u8 disallowHostRequestReordering; 46039a98554Sbo yang u8 abortCCOnError; 46139a98554Sbo yang u8 loadBalanceMode; 46239a98554Sbo yang u8 disableAutoDetectBackplane; 463c4a3e0a5SBagalkote, Sreenivas 46439a98554Sbo yang u8 snapVDSpace; 46539a98554Sbo yang 46639a98554Sbo yang /* 46739a98554Sbo yang * Add properties that can be controlled by 46839a98554Sbo yang * a bit in the following structure. 46939a98554Sbo yang */ 47039a98554Sbo yang struct { 47139a98554Sbo yang u32 copyBackDisabled : 1; 47239a98554Sbo yang u32 SMARTerEnabled : 1; 47339a98554Sbo yang u32 prCorrectUnconfiguredAreas : 1; 47439a98554Sbo yang u32 useFdeOnly : 1; 47539a98554Sbo yang u32 disableNCQ : 1; 47639a98554Sbo yang u32 SSDSMARTerEnabled : 1; 47739a98554Sbo yang u32 SSDPatrolReadEnabled : 1; 47839a98554Sbo yang u32 enableSpinDownUnconfigured : 1; 47939a98554Sbo yang u32 autoEnhancedImport : 1; 48039a98554Sbo yang u32 enableSecretKeyControl : 1; 48139a98554Sbo yang u32 disableOnlineCtrlReset : 1; 48239a98554Sbo yang u32 allowBootWithPinnedCache : 1; 48339a98554Sbo yang u32 disableSpinDownHS : 1; 48439a98554Sbo yang u32 enableJBOD : 1; 48539a98554Sbo yang u32 reserved :18; 48639a98554Sbo yang } OnOffProperties; 48739a98554Sbo yang u8 autoSnapVDSpace; 48839a98554Sbo yang u8 viewSpace; 48939a98554Sbo yang u16 spinDownTime; 49039a98554Sbo yang u8 reserved[24]; 49181e403ceSYang, Bo } __packed; 492c4a3e0a5SBagalkote, Sreenivas 493c4a3e0a5SBagalkote, Sreenivas /* 494c4a3e0a5SBagalkote, Sreenivas * SAS controller information 495c4a3e0a5SBagalkote, Sreenivas */ 496c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 497c4a3e0a5SBagalkote, Sreenivas 498c4a3e0a5SBagalkote, Sreenivas /* 499c4a3e0a5SBagalkote, Sreenivas * PCI device information 500c4a3e0a5SBagalkote, Sreenivas */ 501c4a3e0a5SBagalkote, Sreenivas struct { 502c4a3e0a5SBagalkote, Sreenivas 503c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 504c4a3e0a5SBagalkote, Sreenivas u16 device_id; 505c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 506c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 507c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 508c4a3e0a5SBagalkote, Sreenivas 509c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 510c4a3e0a5SBagalkote, Sreenivas 511c4a3e0a5SBagalkote, Sreenivas /* 512c4a3e0a5SBagalkote, Sreenivas * Host interface information 513c4a3e0a5SBagalkote, Sreenivas */ 514c4a3e0a5SBagalkote, Sreenivas struct { 515c4a3e0a5SBagalkote, Sreenivas 516c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 517c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 518c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 519c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 520c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 521c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 522c4a3e0a5SBagalkote, Sreenivas u8 port_count; 523c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 524c4a3e0a5SBagalkote, Sreenivas 525c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 526c4a3e0a5SBagalkote, Sreenivas 527c4a3e0a5SBagalkote, Sreenivas /* 528c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 529c4a3e0a5SBagalkote, Sreenivas */ 530c4a3e0a5SBagalkote, Sreenivas struct { 531c4a3e0a5SBagalkote, Sreenivas 532c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 533c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 534c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 535c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 536c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 537c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 538c4a3e0a5SBagalkote, Sreenivas u8 port_count; 539c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 540c4a3e0a5SBagalkote, Sreenivas 541c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 542c4a3e0a5SBagalkote, Sreenivas 543c4a3e0a5SBagalkote, Sreenivas /* 544c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 545c4a3e0a5SBagalkote, Sreenivas */ 546c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 547c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 548c4a3e0a5SBagalkote, Sreenivas 549c4a3e0a5SBagalkote, Sreenivas struct { 550c4a3e0a5SBagalkote, Sreenivas 551c4a3e0a5SBagalkote, Sreenivas char name[8]; 552c4a3e0a5SBagalkote, Sreenivas char version[32]; 553c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 554c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 555c4a3e0a5SBagalkote, Sreenivas 556c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 557c4a3e0a5SBagalkote, Sreenivas 558c4a3e0a5SBagalkote, Sreenivas /* 559c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 560c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 561c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 562c4a3e0a5SBagalkote, Sreenivas * terminated 563c4a3e0a5SBagalkote, Sreenivas */ 564c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 565c4a3e0a5SBagalkote, Sreenivas 566c4a3e0a5SBagalkote, Sreenivas struct { 567c4a3e0a5SBagalkote, Sreenivas 568c4a3e0a5SBagalkote, Sreenivas char name[8]; 569c4a3e0a5SBagalkote, Sreenivas char version[32]; 570c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 571c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 572c4a3e0a5SBagalkote, Sreenivas 573c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 574c4a3e0a5SBagalkote, Sreenivas 575c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 576c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 577c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 578c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 579c4a3e0a5SBagalkote, Sreenivas 580c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 581c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 582c4a3e0a5SBagalkote, Sreenivas 583c4a3e0a5SBagalkote, Sreenivas /* 584c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 585c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 586c4a3e0a5SBagalkote, Sreenivas */ 587c4a3e0a5SBagalkote, Sreenivas struct { 588c4a3e0a5SBagalkote, Sreenivas 589c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 590c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 591c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 592c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 593c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 594c4a3e0a5SBagalkote, Sreenivas 595c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 596c4a3e0a5SBagalkote, Sreenivas 597c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 598c4a3e0a5SBagalkote, Sreenivas 599c4a3e0a5SBagalkote, Sreenivas /* 600c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 601c4a3e0a5SBagalkote, Sreenivas */ 602c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 603c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 604c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 605c4a3e0a5SBagalkote, Sreenivas 606c4a3e0a5SBagalkote, Sreenivas /* 607c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 608c4a3e0a5SBagalkote, Sreenivas */ 609c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 610c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 611c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 612c4a3e0a5SBagalkote, Sreenivas 613c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 614c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 615c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 616c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 617c4a3e0a5SBagalkote, Sreenivas 618c4a3e0a5SBagalkote, Sreenivas /* 619c4a3e0a5SBagalkote, Sreenivas * Memory size information 620c4a3e0a5SBagalkote, Sreenivas */ 621c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 622c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 623c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 624c4a3e0a5SBagalkote, Sreenivas 625c4a3e0a5SBagalkote, Sreenivas /* 626c4a3e0a5SBagalkote, Sreenivas * Error counters 627c4a3e0a5SBagalkote, Sreenivas */ 628c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 629c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 630c4a3e0a5SBagalkote, Sreenivas 631c4a3e0a5SBagalkote, Sreenivas /* 632c4a3e0a5SBagalkote, Sreenivas * Cluster information 633c4a3e0a5SBagalkote, Sreenivas */ 634c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 635c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 636c4a3e0a5SBagalkote, Sreenivas 637c4a3e0a5SBagalkote, Sreenivas /* 638c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 639c4a3e0a5SBagalkote, Sreenivas */ 640c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 641c4a3e0a5SBagalkote, Sreenivas 642c4a3e0a5SBagalkote, Sreenivas /* 643c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 644c4a3e0a5SBagalkote, Sreenivas */ 645c4a3e0a5SBagalkote, Sreenivas struct { 646c4a3e0a5SBagalkote, Sreenivas 647c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 648c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 649c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 650c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 651c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 652c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 653c4a3e0a5SBagalkote, Sreenivas 654c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 655c4a3e0a5SBagalkote, Sreenivas 656c4a3e0a5SBagalkote, Sreenivas struct { 657c4a3e0a5SBagalkote, Sreenivas 658c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 659c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 660c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 661c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 662c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 663c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 664c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 665c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 666c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 667c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 668c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 669c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 670c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 671c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 672c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 673c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 674c4a3e0a5SBagalkote, Sreenivas 675c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 676c4a3e0a5SBagalkote, Sreenivas 677c4a3e0a5SBagalkote, Sreenivas struct { 678c4a3e0a5SBagalkote, Sreenivas 679c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 680c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 681c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 682c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 683c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 684c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 685c4a3e0a5SBagalkote, Sreenivas 686c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 687c4a3e0a5SBagalkote, Sreenivas 688c4a3e0a5SBagalkote, Sreenivas struct { 689c4a3e0a5SBagalkote, Sreenivas 690c4a3e0a5SBagalkote, Sreenivas u8 min; 691c4a3e0a5SBagalkote, Sreenivas u8 max; 692c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 693c4a3e0a5SBagalkote, Sreenivas 694c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 695c4a3e0a5SBagalkote, Sreenivas 696c4a3e0a5SBagalkote, Sreenivas struct { 697c4a3e0a5SBagalkote, Sreenivas 698c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 699c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 700c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 701c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 702c4a3e0a5SBagalkote, Sreenivas 703c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 704c4a3e0a5SBagalkote, Sreenivas 705c4a3e0a5SBagalkote, Sreenivas struct { 706c4a3e0a5SBagalkote, Sreenivas 707c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 708c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 709c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 710c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 711c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 712c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 713c4a3e0a5SBagalkote, Sreenivas 714c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 715c4a3e0a5SBagalkote, Sreenivas 716c4a3e0a5SBagalkote, Sreenivas /* 717c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 718c4a3e0a5SBagalkote, Sreenivas */ 719c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 720c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 721c4a3e0a5SBagalkote, Sreenivas 722c4a3e0a5SBagalkote, Sreenivas /* 723c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 724c4a3e0a5SBagalkote, Sreenivas */ 725c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 726c4a3e0a5SBagalkote, Sreenivas 727c4a3e0a5SBagalkote, Sreenivas /* 728c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 729c4a3e0a5SBagalkote, Sreenivas */ 730c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 731c4a3e0a5SBagalkote, Sreenivas 732c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 733c4a3e0a5SBagalkote, Sreenivas 73481e403ceSYang, Bo } __packed; 735c4a3e0a5SBagalkote, Sreenivas 736c4a3e0a5SBagalkote, Sreenivas /* 737c4a3e0a5SBagalkote, Sreenivas * =============================== 738c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 739c4a3e0a5SBagalkote, Sreenivas * =============================== 740c4a3e0a5SBagalkote, Sreenivas */ 741c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 742c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 743c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 744c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 745c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 746c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 747c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 748c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 7496bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256 75081e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 75181e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 752bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 753bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 754c4a3e0a5SBagalkote, Sreenivas 7551fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024) 75642a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128) 757658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 758658dcedbSSumant Patro 75905e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 76005e9ebbeSSumant Patro 761d532dbe2Sbo yang /* Frame Type */ 762d532dbe2Sbo yang #define IO_FRAME 0 763d532dbe2Sbo yang #define PTHRU_FRAME 1 764d532dbe2Sbo yang 765c4a3e0a5SBagalkote, Sreenivas /* 766c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 767c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 768c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 769c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 770c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 771c4a3e0a5SBagalkote, Sreenivas */ 772c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 7732a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 774c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 775c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 77605e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 777c5daa6a9Sadam radford #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 778c4a3e0a5SBagalkote, Sreenivas 779c4a3e0a5SBagalkote, Sreenivas /* 780c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 781c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 782c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 783c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 784c4a3e0a5SBagalkote, Sreenivas * is shown below 785c4a3e0a5SBagalkote, Sreenivas */ 786c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 7877bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 788c4a3e0a5SBagalkote, Sreenivas 789d46a3ad6SSumit.Saxena@lsi.com #define MEGASAS_MAX_MSIX_QUEUES 128 790c4a3e0a5SBagalkote, Sreenivas /* 791c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 792c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 793c4a3e0a5SBagalkote, Sreenivas */ 794c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 795c4a3e0a5SBagalkote, Sreenivas 79639a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 79739a98554Sbo yang 79839a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 79939a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 80039a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 80139a98554Sbo yang 802c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 80314faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 804c4a3e0a5SBagalkote, Sreenivas 805f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 8066610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 8076610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 80887911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 80987911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 8100e98936cSSumant Patro 81139a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 81239a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 81339a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 814d46a3ad6SSumit.Saxena@lsi.com 815d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 816d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 817d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 818d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_MSIX_REG_ARRAY 16 8190e98936cSSumant Patro /* 8200e98936cSSumant Patro * register set for both 1068 and 1078 controllers 8210e98936cSSumant Patro * structure extended for 1078 registers 8220e98936cSSumant Patro */ 823c4a3e0a5SBagalkote, Sreenivas 824f9876f0bSSumant Patro struct megasas_register_set { 8259c915a8cSadam radford u32 doorbell; /*0000h*/ 8269c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/ 8279c915a8cSadam radford u32 fusion_host_diag; /*0008h*/ 8289c915a8cSadam radford u32 reserved_01; /*000Ch*/ 829c4a3e0a5SBagalkote, Sreenivas 830c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 831c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 832c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 833c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 834c4a3e0a5SBagalkote, Sreenivas 835c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 836c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 837c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 838c4a3e0a5SBagalkote, Sreenivas 839c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 840c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 841c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 842c4a3e0a5SBagalkote, Sreenivas 843c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 844c4a3e0a5SBagalkote, Sreenivas 845c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 846c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 847c4a3e0a5SBagalkote, Sreenivas 8489c915a8cSadam radford u32 reserved_2[9]; /*0048h*/ 8499c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/ 8509c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/ 851c4a3e0a5SBagalkote, Sreenivas 852f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 853f9876f0bSSumant Patro 854f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 855f9876f0bSSumant Patro 856f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 8579c915a8cSadam radford u32 outbound_scratch_pad_2; /*00B4h*/ 858f9876f0bSSumant Patro 8599c915a8cSadam radford u32 reserved_4[2]; /*00B8h*/ 860f9876f0bSSumant Patro 861f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 862f9876f0bSSumant Patro 863f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 864f9876f0bSSumant Patro 865f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 86639a98554Sbo yang u32 res_6[11]; /*CCh*/ 86739a98554Sbo yang u32 host_diag; 86839a98554Sbo yang u32 seq_offset; 86939a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 870c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 871c4a3e0a5SBagalkote, Sreenivas 872c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 873c4a3e0a5SBagalkote, Sreenivas 874c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 875c4a3e0a5SBagalkote, Sreenivas u32 length; 876c4a3e0a5SBagalkote, Sreenivas 877c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 878c4a3e0a5SBagalkote, Sreenivas 879c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 880c4a3e0a5SBagalkote, Sreenivas 881c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 882c4a3e0a5SBagalkote, Sreenivas u32 length; 883c4a3e0a5SBagalkote, Sreenivas 884c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 885c4a3e0a5SBagalkote, Sreenivas 886f4c9a131SYang, Bo struct megasas_sge_skinny { 887f4c9a131SYang, Bo u64 phys_addr; 888f4c9a131SYang, Bo u32 length; 889f4c9a131SYang, Bo u32 flag; 890f4c9a131SYang, Bo } __packed; 891f4c9a131SYang, Bo 892c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 893c4a3e0a5SBagalkote, Sreenivas 894c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 895c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 896f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 897c4a3e0a5SBagalkote, Sreenivas 898c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 899c4a3e0a5SBagalkote, Sreenivas 900c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 901c4a3e0a5SBagalkote, Sreenivas 902c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 903c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 904c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 905c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 906c4a3e0a5SBagalkote, Sreenivas 907c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 908c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 909c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 910c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 911c4a3e0a5SBagalkote, Sreenivas 912c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 913c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 914c4a3e0a5SBagalkote, Sreenivas 915c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 916c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 917c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 918c4a3e0a5SBagalkote, Sreenivas 919c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 920c4a3e0a5SBagalkote, Sreenivas 921c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 922c4a3e0a5SBagalkote, Sreenivas 923c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 924c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 925c4a3e0a5SBagalkote, Sreenivas 926c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 927c4a3e0a5SBagalkote, Sreenivas 928d46a3ad6SSumit.Saxena@lsi.com typedef union _MFI_CAPABILITIES { 929d46a3ad6SSumit.Saxena@lsi.com struct { 930d46a3ad6SSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 931d46a3ad6SSumit.Saxena@lsi.com u32 support_additional_msix:1; 932d46a3ad6SSumit.Saxena@lsi.com u32 reserved:30; 933d46a3ad6SSumit.Saxena@lsi.com } mfi_capabilities; 934d46a3ad6SSumit.Saxena@lsi.com u32 reg; 935d46a3ad6SSumit.Saxena@lsi.com } MFI_CAPABILITIES; 936d46a3ad6SSumit.Saxena@lsi.com 937c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 938c4a3e0a5SBagalkote, Sreenivas 939c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 940c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 941c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 942c4a3e0a5SBagalkote, Sreenivas 943c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 944d46a3ad6SSumit.Saxena@lsi.com MFI_CAPABILITIES driver_operations; /*04h*/ 945c4a3e0a5SBagalkote, Sreenivas 946c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 947c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 948c4a3e0a5SBagalkote, Sreenivas 949c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 950c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 951c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 952c4a3e0a5SBagalkote, Sreenivas 953c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 954c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 955c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 956c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 957c4a3e0a5SBagalkote, Sreenivas 958c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 959c4a3e0a5SBagalkote, Sreenivas 960c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 961c4a3e0a5SBagalkote, Sreenivas 962c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 963c4a3e0a5SBagalkote, Sreenivas 964c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 965c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 966c4a3e0a5SBagalkote, Sreenivas 967c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 968c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 969c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 970c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 971c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 972c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 973c4a3e0a5SBagalkote, Sreenivas 974c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 975c4a3e0a5SBagalkote, Sreenivas 976c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 977c4a3e0a5SBagalkote, Sreenivas 978c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 979c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 980c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 981c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 982c4a3e0a5SBagalkote, Sreenivas 983c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 984c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 985c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 986c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 987c4a3e0a5SBagalkote, Sreenivas 988c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 989c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 990c4a3e0a5SBagalkote, Sreenivas 991c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 992c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 993c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 994c4a3e0a5SBagalkote, Sreenivas 995c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 996c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 997c4a3e0a5SBagalkote, Sreenivas 998c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 999c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 1000c4a3e0a5SBagalkote, Sreenivas 1001c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1002c4a3e0a5SBagalkote, Sreenivas 1003c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1004c4a3e0a5SBagalkote, Sreenivas 1005c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 1006c4a3e0a5SBagalkote, Sreenivas 1007c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1008c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1009c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1010c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1011c4a3e0a5SBagalkote, Sreenivas 1012c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1013c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1014c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1015c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1016c4a3e0a5SBagalkote, Sreenivas 1017c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1018c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1019c4a3e0a5SBagalkote, Sreenivas 1020c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1021c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1022c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1023c4a3e0a5SBagalkote, Sreenivas 1024c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 1025c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 1026c4a3e0a5SBagalkote, Sreenivas 1027c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 1028c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 1029c4a3e0a5SBagalkote, Sreenivas 1030c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1031c4a3e0a5SBagalkote, Sreenivas 1032c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 1033c4a3e0a5SBagalkote, Sreenivas 1034c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1035c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1036c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1037c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 1038c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1039c4a3e0a5SBagalkote, Sreenivas 1040c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1041c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1042c4a3e0a5SBagalkote, Sreenivas 1043c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1044c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1045c4a3e0a5SBagalkote, Sreenivas 1046c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1047c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 1048c4a3e0a5SBagalkote, Sreenivas 1049c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 1050c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 1051c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 1052c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 1053c4a3e0a5SBagalkote, Sreenivas } mbox; 1054c4a3e0a5SBagalkote, Sreenivas 1055c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1056c4a3e0a5SBagalkote, Sreenivas 1057c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1058c4a3e0a5SBagalkote, Sreenivas 1059c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 1060c4a3e0a5SBagalkote, Sreenivas 1061c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1062c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1063c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1064c4a3e0a5SBagalkote, Sreenivas 1065c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 1066c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 1067c4a3e0a5SBagalkote, Sreenivas 1068c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1069c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1070c4a3e0a5SBagalkote, Sreenivas 1071c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1072c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 1073c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 1074c4a3e0a5SBagalkote, Sreenivas 1075c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 1076c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 1077c4a3e0a5SBagalkote, Sreenivas 1078c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 1079c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 1080c4a3e0a5SBagalkote, Sreenivas 1081c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 1082c4a3e0a5SBagalkote, Sreenivas 1083c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1084c4a3e0a5SBagalkote, Sreenivas 1085c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1086c4a3e0a5SBagalkote, Sreenivas 1087c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1088c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1089c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1090c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1091c4a3e0a5SBagalkote, Sreenivas 1092c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1093c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1094c4a3e0a5SBagalkote, Sreenivas 1095c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1096c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1097c4a3e0a5SBagalkote, Sreenivas 1098c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1099c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1100c4a3e0a5SBagalkote, Sreenivas 1101c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1102c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 1103c4a3e0a5SBagalkote, Sreenivas 1104c4a3e0a5SBagalkote, Sreenivas union { 1105c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1106c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1107c4a3e0a5SBagalkote, Sreenivas } sgl; 1108c4a3e0a5SBagalkote, Sreenivas 1109c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1110c4a3e0a5SBagalkote, Sreenivas 1111c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1112c4a3e0a5SBagalkote, Sreenivas 1113c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1114c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1115c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1116c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1117c4a3e0a5SBagalkote, Sreenivas 1118c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1119c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1120c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1121c4a3e0a5SBagalkote, Sreenivas 1122c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1123c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1124c4a3e0a5SBagalkote, Sreenivas 1125c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1126c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1127c4a3e0a5SBagalkote, Sreenivas 1128c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1129c4a3e0a5SBagalkote, Sreenivas 1130c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 1131c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 1132c4a3e0a5SBagalkote, Sreenivas 1133c4a3e0a5SBagalkote, Sreenivas union { 1134c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1135c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1136c4a3e0a5SBagalkote, Sreenivas } sgl; 1137c4a3e0a5SBagalkote, Sreenivas 1138c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1139c4a3e0a5SBagalkote, Sreenivas 1140c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1141c4a3e0a5SBagalkote, Sreenivas 1142c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1143c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1144c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1145c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1146c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1147c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1148c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1149c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1150c4a3e0a5SBagalkote, Sreenivas 1151c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1152c4a3e0a5SBagalkote, Sreenivas }; 1153c4a3e0a5SBagalkote, Sreenivas 1154c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1155c4a3e0a5SBagalkote, Sreenivas 1156c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 1157c4a3e0a5SBagalkote, Sreenivas 1158c4a3e0a5SBagalkote, Sreenivas struct { 1159c4a3e0a5SBagalkote, Sreenivas u16 locale; 1160c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1161c4a3e0a5SBagalkote, Sreenivas s8 class; 1162c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 1163c4a3e0a5SBagalkote, Sreenivas 1164c4a3e0a5SBagalkote, Sreenivas u32 word; 1165c4a3e0a5SBagalkote, Sreenivas 1166c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1167c4a3e0a5SBagalkote, Sreenivas 1168c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 1169c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 1170c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 1171c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 1172c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 1173c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 1174c4a3e0a5SBagalkote, Sreenivas 1175c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1176c4a3e0a5SBagalkote, Sreenivas 1177c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1178c4a3e0a5SBagalkote, Sreenivas 1179c4a3e0a5SBagalkote, Sreenivas u16 progress; 1180c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 1181c4a3e0a5SBagalkote, Sreenivas 1182c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1183c4a3e0a5SBagalkote, Sreenivas 1184c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1185c4a3e0a5SBagalkote, Sreenivas 1186c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1187c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1188c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1189c4a3e0a5SBagalkote, Sreenivas 1190c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1191c4a3e0a5SBagalkote, Sreenivas 1192c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1193c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1194c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1195c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1196c4a3e0a5SBagalkote, Sreenivas 1197c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1198c4a3e0a5SBagalkote, Sreenivas 1199c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1200c4a3e0a5SBagalkote, Sreenivas 1201c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1202c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 1203c4a3e0a5SBagalkote, Sreenivas u32 code; 1204c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1205c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1206c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1207c4a3e0a5SBagalkote, Sreenivas 1208c4a3e0a5SBagalkote, Sreenivas union { 1209c4a3e0a5SBagalkote, Sreenivas struct { 1210c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1211c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1212c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1213c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1214c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1215c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1216c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1217c4a3e0a5SBagalkote, Sreenivas 1218c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1219c4a3e0a5SBagalkote, Sreenivas 1220c4a3e0a5SBagalkote, Sreenivas struct { 1221c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1222c4a3e0a5SBagalkote, Sreenivas u64 count; 1223c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1224c4a3e0a5SBagalkote, Sreenivas 1225c4a3e0a5SBagalkote, Sreenivas struct { 1226c4a3e0a5SBagalkote, Sreenivas u64 lba; 1227c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1228c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1229c4a3e0a5SBagalkote, Sreenivas 1230c4a3e0a5SBagalkote, Sreenivas struct { 1231c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1232c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 1233c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 1234c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1235c4a3e0a5SBagalkote, Sreenivas 1236c4a3e0a5SBagalkote, Sreenivas struct { 1237c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1238c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1239c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1240c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1241c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1242c4a3e0a5SBagalkote, Sreenivas 1243c4a3e0a5SBagalkote, Sreenivas struct { 1244c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1245c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1246c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1247c4a3e0a5SBagalkote, Sreenivas 1248c4a3e0a5SBagalkote, Sreenivas struct { 1249c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1250c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1251c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1252c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1253c4a3e0a5SBagalkote, Sreenivas 1254c4a3e0a5SBagalkote, Sreenivas struct { 1255c4a3e0a5SBagalkote, Sreenivas u64 strip; 1256c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1257c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1258c4a3e0a5SBagalkote, Sreenivas 1259c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1260c4a3e0a5SBagalkote, Sreenivas 1261c4a3e0a5SBagalkote, Sreenivas struct { 1262c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1263c4a3e0a5SBagalkote, Sreenivas u32 err; 1264c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1265c4a3e0a5SBagalkote, Sreenivas 1266c4a3e0a5SBagalkote, Sreenivas struct { 1267c4a3e0a5SBagalkote, Sreenivas u64 lba; 1268c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1269c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1270c4a3e0a5SBagalkote, Sreenivas 1271c4a3e0a5SBagalkote, Sreenivas struct { 1272c4a3e0a5SBagalkote, Sreenivas u64 lba; 1273c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1274c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1275c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1276c4a3e0a5SBagalkote, Sreenivas 1277c4a3e0a5SBagalkote, Sreenivas struct { 1278c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1279c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1280c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1281c4a3e0a5SBagalkote, Sreenivas 1282c4a3e0a5SBagalkote, Sreenivas struct { 1283c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1284c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1285c4a3e0a5SBagalkote, Sreenivas u32 newState; 1286c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1287c4a3e0a5SBagalkote, Sreenivas 1288c4a3e0a5SBagalkote, Sreenivas struct { 1289c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1290c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1291c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1292c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1293c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1294c4a3e0a5SBagalkote, Sreenivas 1295c4a3e0a5SBagalkote, Sreenivas u32 rate; 1296c4a3e0a5SBagalkote, Sreenivas char str[96]; 1297c4a3e0a5SBagalkote, Sreenivas 1298c4a3e0a5SBagalkote, Sreenivas struct { 1299c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1300c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1301c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1302c4a3e0a5SBagalkote, Sreenivas 1303c4a3e0a5SBagalkote, Sreenivas struct { 1304c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1305c4a3e0a5SBagalkote, Sreenivas u32 elog; 1306c4a3e0a5SBagalkote, Sreenivas char str[64]; 1307c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1308c4a3e0a5SBagalkote, Sreenivas 1309c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1310c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1311c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1312c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1313c4a3e0a5SBagalkote, Sreenivas } args; 1314c4a3e0a5SBagalkote, Sreenivas 1315c4a3e0a5SBagalkote, Sreenivas char description[128]; 1316c4a3e0a5SBagalkote, Sreenivas 1317c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1318c4a3e0a5SBagalkote, Sreenivas 13197e8a75f4SYang, Bo struct megasas_aen_event { 1320c1d390d8SXiaotian Feng struct delayed_work hotplug_work; 13217e8a75f4SYang, Bo struct megasas_instance *instance; 13227e8a75f4SYang, Bo }; 13237e8a75f4SYang, Bo 1324c8e858feSadam radford struct megasas_irq_context { 1325c8e858feSadam radford struct megasas_instance *instance; 1326c8e858feSadam radford u32 MSIxIndex; 1327c8e858feSadam radford }; 1328c8e858feSadam radford 1329c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1330c4a3e0a5SBagalkote, Sreenivas 1331c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1332c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1333c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1334c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1335c4a3e0a5SBagalkote, Sreenivas 1336c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1337c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1338c4a3e0a5SBagalkote, Sreenivas 1339c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1340c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1341d46a3ad6SSumit.Saxena@lsi.com u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 134281e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1343bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1344c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1345c4a3e0a5SBagalkote, Sreenivas 1346c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1347c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 13489c915a8cSadam radford /* For Fusion its num IOCTL cmds, for others MFI based its 13499c915a8cSadam radford max_fw_cmds */ 13509c915a8cSadam radford u16 max_mfi_cmds; 1351c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 13527e8a75f4SYang, Bo struct megasas_aen_event *ev; 1353c4a3e0a5SBagalkote, Sreenivas 1354c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1355c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 135639a98554Sbo yang /* used to sync fire the cmd to fw */ 1357c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 135839a98554Sbo yang /* used to sync fire the cmd to fw */ 135939a98554Sbo yang spinlock_t hba_lock; 13607343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 13617343eb65Sbo yang spinlock_t completion_lock; 1362c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1363c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1364c4a3e0a5SBagalkote, Sreenivas 1365c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1366c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1367c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1368e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1369c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1370c4a3e0a5SBagalkote, Sreenivas 1371c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1372c4a3e0a5SBagalkote, Sreenivas 1373c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1374c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1375c4a3e0a5SBagalkote, Sreenivas 1376c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1377c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 137839a98554Sbo yang u32 fw_support_ieee; 1379c4a3e0a5SBagalkote, Sreenivas 1380e4a082c7SSumant Patro atomic_t fw_outstanding; 138139a98554Sbo yang atomic_t fw_reset_no_pci_access; 13821341c939SSumant Patro 13831341c939SSumant Patro struct megasas_instance_template *instancet; 13845d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 138539a98554Sbo yang struct work_struct work_init; 138605e9ebbeSSumant Patro 138705e9ebbeSSumant Patro u8 flag; 1388c3518837SYang, Bo u8 unload; 1389f4c9a131SYang, Bo u8 flag_ieee; 139039a98554Sbo yang u8 issuepend_done; 139139a98554Sbo yang u8 disableOnlineCtrlReset; 139239a98554Sbo yang u8 adprecovery; 139305e9ebbeSSumant Patro unsigned long last_time; 139439a98554Sbo yang u32 mfiStatus; 139539a98554Sbo yang u32 last_seq_num; 1396ad84db2eSbo yang 139739a98554Sbo yang struct list_head internal_reset_pending_q; 139880d9da98Sadam radford 139925985edcSLucas De Marchi /* Ptr to hba specific information */ 14009c915a8cSadam radford void *ctrl_context; 1401c8e858feSadam radford unsigned int msix_vectors; 1402c8e858feSadam radford struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 1403c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 14049c915a8cSadam radford u64 map_id; 14059c915a8cSadam radford struct megasas_cmd *map_update_cmd; 1406b6d5d880Sadam radford unsigned long bar; 14079c915a8cSadam radford long reset_flags; 14089c915a8cSadam radford struct mutex reset_mutex; 1409c5daa6a9Sadam radford int throttlequeuedepth; 1410d46a3ad6SSumit.Saxena@lsi.com u8 mask_interrupts; 141139a98554Sbo yang }; 141239a98554Sbo yang 141339a98554Sbo yang enum { 141439a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 141539a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 141639a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 141739a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 141839a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 141939a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1420c4a3e0a5SBagalkote, Sreenivas }; 1421c4a3e0a5SBagalkote, Sreenivas 14220c79e681SYang, Bo struct megasas_instance_template { 14230c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 14240c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 14250c79e681SYang, Bo 1426d46a3ad6SSumit.Saxena@lsi.com void (*enable_intr)(struct megasas_instance *); 1427d46a3ad6SSumit.Saxena@lsi.com void (*disable_intr)(struct megasas_instance *); 14280c79e681SYang, Bo 14290c79e681SYang, Bo int (*clear_intr)(struct megasas_register_set __iomem *); 14300c79e681SYang, Bo 14310c79e681SYang, Bo u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 143239a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 143339a98554Sbo yang struct megasas_register_set __iomem *); 143439a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 143539a98554Sbo yang struct megasas_register_set __iomem *); 1436cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp); 1437cd50ba8eSadam radford void (*tasklet)(unsigned long); 1438cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *); 1439cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *, 1440cd50ba8eSadam radford struct scsi_cmnd *); 1441cd50ba8eSadam radford void (*issue_dcmd) (struct megasas_instance *instance, 1442cd50ba8eSadam radford struct megasas_cmd *cmd); 14430c79e681SYang, Bo }; 14440c79e681SYang, Bo 1445c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1446c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1447c4a3e0a5SBagalkote, Sreenivas 1448c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1449c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1450c4a3e0a5SBagalkote, Sreenivas scp->device->id 1451c4a3e0a5SBagalkote, Sreenivas 1452c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1453c4a3e0a5SBagalkote, Sreenivas 1454c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1455c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1456c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1457c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1458c4a3e0a5SBagalkote, Sreenivas 1459c4a3e0a5SBagalkote, Sreenivas u32 index; 1460c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1461c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 146239a98554Sbo yang u8 abort_aen; 146339a98554Sbo yang u8 retry_for_fw_reset; 146439a98554Sbo yang 1465c4a3e0a5SBagalkote, Sreenivas 1466c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1467c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1468c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 14699c915a8cSadam radford union { 14709c915a8cSadam radford struct { 14719c915a8cSadam radford u16 smid; 14729c915a8cSadam radford u16 resvd; 14739c915a8cSadam radford } context; 1474c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1475c4a3e0a5SBagalkote, Sreenivas }; 14769c915a8cSadam radford }; 1477c4a3e0a5SBagalkote, Sreenivas 1478c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1479c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1480c4a3e0a5SBagalkote, Sreenivas 1481c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1482c4a3e0a5SBagalkote, Sreenivas 1483c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1484c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1485c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1486c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1487c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1488c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1489c4a3e0a5SBagalkote, Sreenivas union { 1490c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1491c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1492c4a3e0a5SBagalkote, Sreenivas } frame; 1493c4a3e0a5SBagalkote, Sreenivas 1494c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1495c4a3e0a5SBagalkote, Sreenivas 1496c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1497c4a3e0a5SBagalkote, Sreenivas 1498c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1499c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1500c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1501c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1502c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1503c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1504c4a3e0a5SBagalkote, Sreenivas 1505c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1506c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1507c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1508c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1509c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1510c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1511c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1512c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1513c4a3e0a5SBagalkote, Sreenivas union { 1514c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1515c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1516c4a3e0a5SBagalkote, Sreenivas } frame; 1517c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1518c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1519c4a3e0a5SBagalkote, Sreenivas 15200e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1521c4a3e0a5SBagalkote, Sreenivas #endif 1522c4a3e0a5SBagalkote, Sreenivas 1523cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1524c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1525c4a3e0a5SBagalkote, Sreenivas 1526c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1527c4a3e0a5SBagalkote, Sreenivas 1528c4a3e0a5SBagalkote, Sreenivas u16 count; 1529c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1530c4a3e0a5SBagalkote, Sreenivas int max_index; 1531c4a3e0a5SBagalkote, Sreenivas }; 1532c4a3e0a5SBagalkote, Sreenivas 1533c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1534