1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 3c4a3e0a5SBagalkote, Sreenivas * 43f1530c1Sadam radford * Copyright (c) 2009-2011 LSI Corporation. 5c4a3e0a5SBagalkote, Sreenivas * 6c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 7c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 83f1530c1Sadam radford * as published by the Free Software Foundation; either version 2 93f1530c1Sadam radford * of the License, or (at your option) any later version. 103f1530c1Sadam radford * 113f1530c1Sadam radford * This program is distributed in the hope that it will be useful, 123f1530c1Sadam radford * but WITHOUT ANY WARRANTY; without even the implied warranty of 133f1530c1Sadam radford * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 143f1530c1Sadam radford * GNU General Public License for more details. 153f1530c1Sadam radford * 163f1530c1Sadam radford * You should have received a copy of the GNU General Public License 173f1530c1Sadam radford * along with this program; if not, write to the Free Software 183f1530c1Sadam radford * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19c4a3e0a5SBagalkote, Sreenivas * 20c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h 213f1530c1Sadam radford * 223f1530c1Sadam radford * Authors: LSI Corporation 233f1530c1Sadam radford * 243f1530c1Sadam radford * Send feedback to: <megaraidlinux@lsi.com> 253f1530c1Sadam radford * 263f1530c1Sadam radford * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 273f1530c1Sadam radford * ATTN: Linuxraid 28c4a3e0a5SBagalkote, Sreenivas */ 29c4a3e0a5SBagalkote, Sreenivas 30c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 31c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 32c4a3e0a5SBagalkote, Sreenivas 33a69b74d3SRandy Dunlap /* 34c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 35c4a3e0a5SBagalkote, Sreenivas */ 36e1703585Sadam radford #define MEGASAS_VERSION "00.00.05.40-rc1" 37e1703585Sadam radford #define MEGASAS_RELDATE "Jul. 26, 2011" 38e1703585Sadam radford #define MEGASAS_EXT_VERSION "Tue. Jul. 26 17:00:00 PDT 2011" 390e98936cSSumant Patro 400e98936cSSumant Patro /* 410e98936cSSumant Patro * Device IDs 420e98936cSSumant Patro */ 430e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 44af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 450e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 466610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 476610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 4887911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 4987911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 509c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b 5136807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d 520e98936cSSumant Patro 53c4a3e0a5SBagalkote, Sreenivas /* 54c4a3e0a5SBagalkote, Sreenivas * ===================================== 55c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 56c4a3e0a5SBagalkote, Sreenivas * ===================================== 57c4a3e0a5SBagalkote, Sreenivas */ 58c4a3e0a5SBagalkote, Sreenivas 59c4a3e0a5SBagalkote, Sreenivas /* 60c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 61c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 62c4a3e0a5SBagalkote, Sreenivas * "message frames" 63c4a3e0a5SBagalkote, Sreenivas */ 64c4a3e0a5SBagalkote, Sreenivas 65a69b74d3SRandy Dunlap /* 66c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 67c4a3e0a5SBagalkote, Sreenivas */ 68c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 69c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 70c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 71c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 72c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 73c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 74c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 75e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 76c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 77c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 78c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 79c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 8039a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 817e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002 82c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 83c4a3e0a5SBagalkote, Sreenivas 84a69b74d3SRandy Dunlap /* 85c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 86c4a3e0a5SBagalkote, Sreenivas * 87c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 88c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 89c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 90c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 91e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 92e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 93c4a3e0a5SBagalkote, Sreenivas */ 9439a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 9539a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 9639a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 9739a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 9839a98554Sbo yang 9939a98554Sbo yang #define MFI_ADP_RESET 0x00000040 100e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 101c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 102c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 103c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 104e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 105e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 106e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 107e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 108e3bbff9fSSumant Patro MFI_INIT_ABORT 109c4a3e0a5SBagalkote, Sreenivas 110a69b74d3SRandy Dunlap /* 111c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 112c4a3e0a5SBagalkote, Sreenivas */ 113c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 114c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 115c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 116c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 117c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 118c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 119c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 120c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 121c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 122c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 123f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 124c4a3e0a5SBagalkote, Sreenivas 125a69b74d3SRandy Dunlap /* 126c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 127c4a3e0a5SBagalkote, Sreenivas */ 128c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 129c4a3e0a5SBagalkote, Sreenivas 130a69b74d3SRandy Dunlap /* 131c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 132c4a3e0a5SBagalkote, Sreenivas */ 133c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 134c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 135c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 136c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 137c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 138c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 139c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 140c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 141c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 142c4a3e0a5SBagalkote, Sreenivas 143c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 144bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 145c4a3e0a5SBagalkote, Sreenivas 146c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 147c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 148c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 149c4a3e0a5SBagalkote, Sreenivas 150c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 15131ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 152c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 153c4a3e0a5SBagalkote, Sreenivas 154c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 155c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 156c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 157c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 158c4a3e0a5SBagalkote, Sreenivas 159c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 160c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 161c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 16281e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 163c4a3e0a5SBagalkote, Sreenivas 164a69b74d3SRandy Dunlap /* 165c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 166c4a3e0a5SBagalkote, Sreenivas */ 167c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 168c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 169c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 170c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 171c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 172c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 173c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 174c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 175c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 176c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 177c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 178c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 179c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 180c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 181c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 182c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 183c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 184c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 185c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 186c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 187c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 188c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 189c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 190c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 191c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 192c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 193c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 194c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 195c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 196c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 197c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 198c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 199c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 200c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 201c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 202c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 203c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 204c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 205c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 206c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 207c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 208c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 209c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 210c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 211c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 212c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 213c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 214c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 215c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 216c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 217c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 218c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 219c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 220c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 221c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 222c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 223c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 224c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 22536807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 226c4a3e0a5SBagalkote, Sreenivas 227c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 228c4a3e0a5SBagalkote, Sreenivas }; 229c4a3e0a5SBagalkote, Sreenivas 230c4a3e0a5SBagalkote, Sreenivas /* 231c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 232c4a3e0a5SBagalkote, Sreenivas */ 233c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 234c4a3e0a5SBagalkote, Sreenivas 235c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 236c4a3e0a5SBagalkote, Sreenivas 237c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 238c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 239c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 240c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 241c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 242c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 243c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 244c4a3e0a5SBagalkote, Sreenivas 245c4a3e0a5SBagalkote, Sreenivas }; 246c4a3e0a5SBagalkote, Sreenivas 247c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 248c4a3e0a5SBagalkote, Sreenivas 249c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 250c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 251c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 252c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 253c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 254c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 255c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 256c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 257c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 258c4a3e0a5SBagalkote, Sreenivas 259c4a3e0a5SBagalkote, Sreenivas }; 260c4a3e0a5SBagalkote, Sreenivas 261c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 262c4a3e0a5SBagalkote, Sreenivas 263c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 264c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 265c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 266c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 267c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 268c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 269c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 270c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 271c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 272c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 273c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 274c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 275c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 276c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 277c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 278c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 279c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 280c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 281c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 282c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 283c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 28481e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 28581e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 28681e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 28781e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 28881e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 28981e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 29081e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 29181e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 29281e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 29381e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 29481e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 29581e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 29681e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 29781e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 29881e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 29981e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 300c4a3e0a5SBagalkote, Sreenivas }; 301c4a3e0a5SBagalkote, Sreenivas 302c4a3e0a5SBagalkote, Sreenivas /* 30381e403ceSYang, Bo * define constants for device list query options 30481e403ceSYang, Bo */ 30581e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 30681e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 30781e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 30881e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 30981e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 31081e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 31181e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 31281e403ceSYang, Bo }; 31381e403ceSYang, Bo 3147e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 3157e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 3167e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 3177e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 3187e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 3197e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 3207e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 3217e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 3227e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 3237e8a75f4SYang, Bo #define MAX_LOGICAL_DRIVES 64 3247e8a75f4SYang, Bo 32581e403ceSYang, Bo enum MR_PD_STATE { 32681e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 32781e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 32881e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 32981e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 33081e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 33181e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 33281e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 33381e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 33481e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 33581e403ceSYang, Bo }; 33681e403ceSYang, Bo 33781e403ceSYang, Bo 33881e403ceSYang, Bo /* 33981e403ceSYang, Bo * defines the physical drive address structure 34081e403ceSYang, Bo */ 34181e403ceSYang, Bo struct MR_PD_ADDRESS { 34281e403ceSYang, Bo u16 deviceId; 34381e403ceSYang, Bo u16 enclDeviceId; 34481e403ceSYang, Bo 34581e403ceSYang, Bo union { 34681e403ceSYang, Bo struct { 34781e403ceSYang, Bo u8 enclIndex; 34881e403ceSYang, Bo u8 slotNumber; 34981e403ceSYang, Bo } mrPdAddress; 35081e403ceSYang, Bo struct { 35181e403ceSYang, Bo u8 enclPosition; 35281e403ceSYang, Bo u8 enclConnectorIndex; 35381e403ceSYang, Bo } mrEnclAddress; 35481e403ceSYang, Bo }; 35581e403ceSYang, Bo u8 scsiDevType; 35681e403ceSYang, Bo union { 35781e403ceSYang, Bo u8 connectedPortBitmap; 35881e403ceSYang, Bo u8 connectedPortNumbers; 35981e403ceSYang, Bo }; 36081e403ceSYang, Bo u64 sasAddr[2]; 36181e403ceSYang, Bo } __packed; 36281e403ceSYang, Bo 36381e403ceSYang, Bo /* 36481e403ceSYang, Bo * defines the physical drive list structure 36581e403ceSYang, Bo */ 36681e403ceSYang, Bo struct MR_PD_LIST { 36781e403ceSYang, Bo u32 size; 36881e403ceSYang, Bo u32 count; 36981e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 37081e403ceSYang, Bo } __packed; 37181e403ceSYang, Bo 37281e403ceSYang, Bo struct megasas_pd_list { 37381e403ceSYang, Bo u16 tid; 37481e403ceSYang, Bo u8 driveType; 37581e403ceSYang, Bo u8 driveState; 37681e403ceSYang, Bo } __packed; 37781e403ceSYang, Bo 37881e403ceSYang, Bo /* 379bdc6fb8dSYang, Bo * defines the logical drive reference structure 380bdc6fb8dSYang, Bo */ 381bdc6fb8dSYang, Bo union MR_LD_REF { 382bdc6fb8dSYang, Bo struct { 383bdc6fb8dSYang, Bo u8 targetId; 384bdc6fb8dSYang, Bo u8 reserved; 385bdc6fb8dSYang, Bo u16 seqNum; 386bdc6fb8dSYang, Bo }; 387bdc6fb8dSYang, Bo u32 ref; 388bdc6fb8dSYang, Bo } __packed; 389bdc6fb8dSYang, Bo 390bdc6fb8dSYang, Bo /* 391bdc6fb8dSYang, Bo * defines the logical drive list structure 392bdc6fb8dSYang, Bo */ 393bdc6fb8dSYang, Bo struct MR_LD_LIST { 394bdc6fb8dSYang, Bo u32 ldCount; 395bdc6fb8dSYang, Bo u32 reserved; 396bdc6fb8dSYang, Bo struct { 397bdc6fb8dSYang, Bo union MR_LD_REF ref; 398bdc6fb8dSYang, Bo u8 state; 399bdc6fb8dSYang, Bo u8 reserved[3]; 400bdc6fb8dSYang, Bo u64 size; 401bdc6fb8dSYang, Bo } ldList[MAX_LOGICAL_DRIVES]; 402bdc6fb8dSYang, Bo } __packed; 403bdc6fb8dSYang, Bo 404bdc6fb8dSYang, Bo /* 405c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 406c4a3e0a5SBagalkote, Sreenivas */ 407c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 408c4a3e0a5SBagalkote, Sreenivas 409c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 410c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 411c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 412c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 413c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 414c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 415c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 416c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 417c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 418c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 419c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 420c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 421c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 422c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 423c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 424c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 425c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 426c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 427c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 428c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 429c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 43039a98554Sbo yang u8 maintainPdFailHistory; 43139a98554Sbo yang u8 disallowHostRequestReordering; 43239a98554Sbo yang u8 abortCCOnError; 43339a98554Sbo yang u8 loadBalanceMode; 43439a98554Sbo yang u8 disableAutoDetectBackplane; 435c4a3e0a5SBagalkote, Sreenivas 43639a98554Sbo yang u8 snapVDSpace; 43739a98554Sbo yang 43839a98554Sbo yang /* 43939a98554Sbo yang * Add properties that can be controlled by 44039a98554Sbo yang * a bit in the following structure. 44139a98554Sbo yang */ 44239a98554Sbo yang struct { 44339a98554Sbo yang u32 copyBackDisabled : 1; 44439a98554Sbo yang u32 SMARTerEnabled : 1; 44539a98554Sbo yang u32 prCorrectUnconfiguredAreas : 1; 44639a98554Sbo yang u32 useFdeOnly : 1; 44739a98554Sbo yang u32 disableNCQ : 1; 44839a98554Sbo yang u32 SSDSMARTerEnabled : 1; 44939a98554Sbo yang u32 SSDPatrolReadEnabled : 1; 45039a98554Sbo yang u32 enableSpinDownUnconfigured : 1; 45139a98554Sbo yang u32 autoEnhancedImport : 1; 45239a98554Sbo yang u32 enableSecretKeyControl : 1; 45339a98554Sbo yang u32 disableOnlineCtrlReset : 1; 45439a98554Sbo yang u32 allowBootWithPinnedCache : 1; 45539a98554Sbo yang u32 disableSpinDownHS : 1; 45639a98554Sbo yang u32 enableJBOD : 1; 45739a98554Sbo yang u32 reserved :18; 45839a98554Sbo yang } OnOffProperties; 45939a98554Sbo yang u8 autoSnapVDSpace; 46039a98554Sbo yang u8 viewSpace; 46139a98554Sbo yang u16 spinDownTime; 46239a98554Sbo yang u8 reserved[24]; 46381e403ceSYang, Bo } __packed; 464c4a3e0a5SBagalkote, Sreenivas 465c4a3e0a5SBagalkote, Sreenivas /* 466c4a3e0a5SBagalkote, Sreenivas * SAS controller information 467c4a3e0a5SBagalkote, Sreenivas */ 468c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 469c4a3e0a5SBagalkote, Sreenivas 470c4a3e0a5SBagalkote, Sreenivas /* 471c4a3e0a5SBagalkote, Sreenivas * PCI device information 472c4a3e0a5SBagalkote, Sreenivas */ 473c4a3e0a5SBagalkote, Sreenivas struct { 474c4a3e0a5SBagalkote, Sreenivas 475c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 476c4a3e0a5SBagalkote, Sreenivas u16 device_id; 477c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 478c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 479c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 480c4a3e0a5SBagalkote, Sreenivas 481c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 482c4a3e0a5SBagalkote, Sreenivas 483c4a3e0a5SBagalkote, Sreenivas /* 484c4a3e0a5SBagalkote, Sreenivas * Host interface information 485c4a3e0a5SBagalkote, Sreenivas */ 486c4a3e0a5SBagalkote, Sreenivas struct { 487c4a3e0a5SBagalkote, Sreenivas 488c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 489c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 490c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 491c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 492c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 493c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 494c4a3e0a5SBagalkote, Sreenivas u8 port_count; 495c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 496c4a3e0a5SBagalkote, Sreenivas 497c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 498c4a3e0a5SBagalkote, Sreenivas 499c4a3e0a5SBagalkote, Sreenivas /* 500c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 501c4a3e0a5SBagalkote, Sreenivas */ 502c4a3e0a5SBagalkote, Sreenivas struct { 503c4a3e0a5SBagalkote, Sreenivas 504c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 505c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 506c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 507c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 508c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 509c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 510c4a3e0a5SBagalkote, Sreenivas u8 port_count; 511c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 512c4a3e0a5SBagalkote, Sreenivas 513c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 514c4a3e0a5SBagalkote, Sreenivas 515c4a3e0a5SBagalkote, Sreenivas /* 516c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 517c4a3e0a5SBagalkote, Sreenivas */ 518c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 519c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 520c4a3e0a5SBagalkote, Sreenivas 521c4a3e0a5SBagalkote, Sreenivas struct { 522c4a3e0a5SBagalkote, Sreenivas 523c4a3e0a5SBagalkote, Sreenivas char name[8]; 524c4a3e0a5SBagalkote, Sreenivas char version[32]; 525c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 526c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 527c4a3e0a5SBagalkote, Sreenivas 528c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 529c4a3e0a5SBagalkote, Sreenivas 530c4a3e0a5SBagalkote, Sreenivas /* 531c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 532c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 533c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 534c4a3e0a5SBagalkote, Sreenivas * terminated 535c4a3e0a5SBagalkote, Sreenivas */ 536c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 537c4a3e0a5SBagalkote, Sreenivas 538c4a3e0a5SBagalkote, Sreenivas struct { 539c4a3e0a5SBagalkote, Sreenivas 540c4a3e0a5SBagalkote, Sreenivas char name[8]; 541c4a3e0a5SBagalkote, Sreenivas char version[32]; 542c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 543c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 544c4a3e0a5SBagalkote, Sreenivas 545c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 546c4a3e0a5SBagalkote, Sreenivas 547c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 548c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 549c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 550c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 551c4a3e0a5SBagalkote, Sreenivas 552c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 553c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 554c4a3e0a5SBagalkote, Sreenivas 555c4a3e0a5SBagalkote, Sreenivas /* 556c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 557c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 558c4a3e0a5SBagalkote, Sreenivas */ 559c4a3e0a5SBagalkote, Sreenivas struct { 560c4a3e0a5SBagalkote, Sreenivas 561c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 562c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 563c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 564c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 565c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 566c4a3e0a5SBagalkote, Sreenivas 567c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 568c4a3e0a5SBagalkote, Sreenivas 569c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 570c4a3e0a5SBagalkote, Sreenivas 571c4a3e0a5SBagalkote, Sreenivas /* 572c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 573c4a3e0a5SBagalkote, Sreenivas */ 574c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 575c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 576c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 577c4a3e0a5SBagalkote, Sreenivas 578c4a3e0a5SBagalkote, Sreenivas /* 579c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 580c4a3e0a5SBagalkote, Sreenivas */ 581c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 582c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 583c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 584c4a3e0a5SBagalkote, Sreenivas 585c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 586c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 587c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 588c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 589c4a3e0a5SBagalkote, Sreenivas 590c4a3e0a5SBagalkote, Sreenivas /* 591c4a3e0a5SBagalkote, Sreenivas * Memory size information 592c4a3e0a5SBagalkote, Sreenivas */ 593c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 594c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 595c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 596c4a3e0a5SBagalkote, Sreenivas 597c4a3e0a5SBagalkote, Sreenivas /* 598c4a3e0a5SBagalkote, Sreenivas * Error counters 599c4a3e0a5SBagalkote, Sreenivas */ 600c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 601c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 602c4a3e0a5SBagalkote, Sreenivas 603c4a3e0a5SBagalkote, Sreenivas /* 604c4a3e0a5SBagalkote, Sreenivas * Cluster information 605c4a3e0a5SBagalkote, Sreenivas */ 606c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 607c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 608c4a3e0a5SBagalkote, Sreenivas 609c4a3e0a5SBagalkote, Sreenivas /* 610c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 611c4a3e0a5SBagalkote, Sreenivas */ 612c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 613c4a3e0a5SBagalkote, Sreenivas 614c4a3e0a5SBagalkote, Sreenivas /* 615c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 616c4a3e0a5SBagalkote, Sreenivas */ 617c4a3e0a5SBagalkote, Sreenivas struct { 618c4a3e0a5SBagalkote, Sreenivas 619c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 620c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 621c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 622c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 623c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 624c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 625c4a3e0a5SBagalkote, Sreenivas 626c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 627c4a3e0a5SBagalkote, Sreenivas 628c4a3e0a5SBagalkote, Sreenivas struct { 629c4a3e0a5SBagalkote, Sreenivas 630c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 631c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 632c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 633c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 634c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 635c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 636c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 637c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 638c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 639c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 640c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 641c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 642c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 643c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 644c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 645c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 646c4a3e0a5SBagalkote, Sreenivas 647c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 648c4a3e0a5SBagalkote, Sreenivas 649c4a3e0a5SBagalkote, Sreenivas struct { 650c4a3e0a5SBagalkote, Sreenivas 651c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 652c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 653c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 654c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 655c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 656c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 657c4a3e0a5SBagalkote, Sreenivas 658c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 659c4a3e0a5SBagalkote, Sreenivas 660c4a3e0a5SBagalkote, Sreenivas struct { 661c4a3e0a5SBagalkote, Sreenivas 662c4a3e0a5SBagalkote, Sreenivas u8 min; 663c4a3e0a5SBagalkote, Sreenivas u8 max; 664c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 665c4a3e0a5SBagalkote, Sreenivas 666c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 667c4a3e0a5SBagalkote, Sreenivas 668c4a3e0a5SBagalkote, Sreenivas struct { 669c4a3e0a5SBagalkote, Sreenivas 670c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 671c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 672c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 673c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 674c4a3e0a5SBagalkote, Sreenivas 675c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 676c4a3e0a5SBagalkote, Sreenivas 677c4a3e0a5SBagalkote, Sreenivas struct { 678c4a3e0a5SBagalkote, Sreenivas 679c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 680c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 681c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 682c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 683c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 684c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 685c4a3e0a5SBagalkote, Sreenivas 686c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 687c4a3e0a5SBagalkote, Sreenivas 688c4a3e0a5SBagalkote, Sreenivas /* 689c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 690c4a3e0a5SBagalkote, Sreenivas */ 691c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 692c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 693c4a3e0a5SBagalkote, Sreenivas 694c4a3e0a5SBagalkote, Sreenivas /* 695c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 696c4a3e0a5SBagalkote, Sreenivas */ 697c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 698c4a3e0a5SBagalkote, Sreenivas 699c4a3e0a5SBagalkote, Sreenivas /* 700c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 701c4a3e0a5SBagalkote, Sreenivas */ 702c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 703c4a3e0a5SBagalkote, Sreenivas 704c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 705c4a3e0a5SBagalkote, Sreenivas 70681e403ceSYang, Bo } __packed; 707c4a3e0a5SBagalkote, Sreenivas 708c4a3e0a5SBagalkote, Sreenivas /* 709c4a3e0a5SBagalkote, Sreenivas * =============================== 710c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 711c4a3e0a5SBagalkote, Sreenivas * =============================== 712c4a3e0a5SBagalkote, Sreenivas */ 713c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 714c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 715c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 716c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 717c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 718c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 719c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 720c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 7216bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256 72281e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 72381e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 724bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 725bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 726c4a3e0a5SBagalkote, Sreenivas 7271fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024) 72842a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128) 729658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 730658dcedbSSumant Patro 73105e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 73205e9ebbeSSumant Patro 733d532dbe2Sbo yang /* Frame Type */ 734d532dbe2Sbo yang #define IO_FRAME 0 735d532dbe2Sbo yang #define PTHRU_FRAME 1 736d532dbe2Sbo yang 737c4a3e0a5SBagalkote, Sreenivas /* 738c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 739c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 740c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 741c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 742c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 743c4a3e0a5SBagalkote, Sreenivas */ 744c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 7452a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 746c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 747c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 74805e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 749c4a3e0a5SBagalkote, Sreenivas 750c4a3e0a5SBagalkote, Sreenivas /* 751c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 752c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 753c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 754c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 755c4a3e0a5SBagalkote, Sreenivas * is shown below 756c4a3e0a5SBagalkote, Sreenivas */ 757c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 7587bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 759c4a3e0a5SBagalkote, Sreenivas 760c8e858feSadam radford #define MEGASAS_MAX_MSIX_QUEUES 16 761c4a3e0a5SBagalkote, Sreenivas /* 762c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 763c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 764c4a3e0a5SBagalkote, Sreenivas */ 765c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 766c4a3e0a5SBagalkote, Sreenivas 76739a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 76839a98554Sbo yang 76939a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 77039a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 77139a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 77239a98554Sbo yang 773c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 77414faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 775ad84db2eSbo yang #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10) 776c4a3e0a5SBagalkote, Sreenivas 777f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 7786610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 7796610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 78087911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 78187911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 7820e98936cSSumant Patro 78339a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 78439a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 78539a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 7860e98936cSSumant Patro /* 7870e98936cSSumant Patro * register set for both 1068 and 1078 controllers 7880e98936cSSumant Patro * structure extended for 1078 registers 7890e98936cSSumant Patro */ 790c4a3e0a5SBagalkote, Sreenivas 791f9876f0bSSumant Patro struct megasas_register_set { 7929c915a8cSadam radford u32 doorbell; /*0000h*/ 7939c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/ 7949c915a8cSadam radford u32 fusion_host_diag; /*0008h*/ 7959c915a8cSadam radford u32 reserved_01; /*000Ch*/ 796c4a3e0a5SBagalkote, Sreenivas 797c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 798c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 799c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 800c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 801c4a3e0a5SBagalkote, Sreenivas 802c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 803c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 804c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 805c4a3e0a5SBagalkote, Sreenivas 806c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 807c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 808c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 809c4a3e0a5SBagalkote, Sreenivas 810c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 811c4a3e0a5SBagalkote, Sreenivas 812c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 813c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 814c4a3e0a5SBagalkote, Sreenivas 8159c915a8cSadam radford u32 reserved_2[9]; /*0048h*/ 8169c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/ 8179c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/ 818c4a3e0a5SBagalkote, Sreenivas 819f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 820f9876f0bSSumant Patro 821f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 822f9876f0bSSumant Patro 823f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 8249c915a8cSadam radford u32 outbound_scratch_pad_2; /*00B4h*/ 825f9876f0bSSumant Patro 8269c915a8cSadam radford u32 reserved_4[2]; /*00B8h*/ 827f9876f0bSSumant Patro 828f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 829f9876f0bSSumant Patro 830f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 831f9876f0bSSumant Patro 832f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 83339a98554Sbo yang u32 res_6[11]; /*CCh*/ 83439a98554Sbo yang u32 host_diag; 83539a98554Sbo yang u32 seq_offset; 83639a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 837c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 838c4a3e0a5SBagalkote, Sreenivas 839c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 840c4a3e0a5SBagalkote, Sreenivas 841c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 842c4a3e0a5SBagalkote, Sreenivas u32 length; 843c4a3e0a5SBagalkote, Sreenivas 844c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 845c4a3e0a5SBagalkote, Sreenivas 846c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 847c4a3e0a5SBagalkote, Sreenivas 848c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 849c4a3e0a5SBagalkote, Sreenivas u32 length; 850c4a3e0a5SBagalkote, Sreenivas 851c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 852c4a3e0a5SBagalkote, Sreenivas 853f4c9a131SYang, Bo struct megasas_sge_skinny { 854f4c9a131SYang, Bo u64 phys_addr; 855f4c9a131SYang, Bo u32 length; 856f4c9a131SYang, Bo u32 flag; 857f4c9a131SYang, Bo } __packed; 858f4c9a131SYang, Bo 859c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 860c4a3e0a5SBagalkote, Sreenivas 861c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 862c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 863f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 864c4a3e0a5SBagalkote, Sreenivas 865c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 866c4a3e0a5SBagalkote, Sreenivas 867c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 868c4a3e0a5SBagalkote, Sreenivas 869c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 870c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 871c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 872c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 873c4a3e0a5SBagalkote, Sreenivas 874c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 875c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 876c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 877c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 878c4a3e0a5SBagalkote, Sreenivas 879c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 880c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 881c4a3e0a5SBagalkote, Sreenivas 882c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 883c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 884c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 885c4a3e0a5SBagalkote, Sreenivas 886c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 887c4a3e0a5SBagalkote, Sreenivas 888c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 889c4a3e0a5SBagalkote, Sreenivas 890c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 891c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 892c4a3e0a5SBagalkote, Sreenivas 893c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 894c4a3e0a5SBagalkote, Sreenivas 895c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 896c4a3e0a5SBagalkote, Sreenivas 897c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 898c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 899c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 900c4a3e0a5SBagalkote, Sreenivas 901c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 902c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 903c4a3e0a5SBagalkote, Sreenivas 904c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 905c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 906c4a3e0a5SBagalkote, Sreenivas 907c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 908c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 909c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 910c4a3e0a5SBagalkote, Sreenivas 911c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 912c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 913c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 914c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 915c4a3e0a5SBagalkote, Sreenivas 916c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 917c4a3e0a5SBagalkote, Sreenivas 918c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 919c4a3e0a5SBagalkote, Sreenivas 920c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 921c4a3e0a5SBagalkote, Sreenivas 922c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 923c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 924c4a3e0a5SBagalkote, Sreenivas 925c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 926c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 927c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 928c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 929c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 930c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 931c4a3e0a5SBagalkote, Sreenivas 932c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 933c4a3e0a5SBagalkote, Sreenivas 934c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 935c4a3e0a5SBagalkote, Sreenivas 936c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 937c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 938c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 939c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 940c4a3e0a5SBagalkote, Sreenivas 941c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 942c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 943c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 944c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 945c4a3e0a5SBagalkote, Sreenivas 946c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 947c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 948c4a3e0a5SBagalkote, Sreenivas 949c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 950c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 951c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 952c4a3e0a5SBagalkote, Sreenivas 953c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 954c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 955c4a3e0a5SBagalkote, Sreenivas 956c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 957c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 958c4a3e0a5SBagalkote, Sreenivas 959c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 960c4a3e0a5SBagalkote, Sreenivas 961c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 962c4a3e0a5SBagalkote, Sreenivas 963c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 964c4a3e0a5SBagalkote, Sreenivas 965c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 966c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 967c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 968c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 969c4a3e0a5SBagalkote, Sreenivas 970c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 971c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 972c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 973c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 974c4a3e0a5SBagalkote, Sreenivas 975c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 976c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 977c4a3e0a5SBagalkote, Sreenivas 978c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 979c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 980c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 981c4a3e0a5SBagalkote, Sreenivas 982c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 983c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 984c4a3e0a5SBagalkote, Sreenivas 985c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 986c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 987c4a3e0a5SBagalkote, Sreenivas 988c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 989c4a3e0a5SBagalkote, Sreenivas 990c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 991c4a3e0a5SBagalkote, Sreenivas 992c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 993c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 994c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 995c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 996c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 997c4a3e0a5SBagalkote, Sreenivas 998c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 999c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1000c4a3e0a5SBagalkote, Sreenivas 1001c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1002c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1003c4a3e0a5SBagalkote, Sreenivas 1004c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1005c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 1006c4a3e0a5SBagalkote, Sreenivas 1007c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 1008c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 1009c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 1010c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 1011c4a3e0a5SBagalkote, Sreenivas } mbox; 1012c4a3e0a5SBagalkote, Sreenivas 1013c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1014c4a3e0a5SBagalkote, Sreenivas 1015c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1016c4a3e0a5SBagalkote, Sreenivas 1017c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 1018c4a3e0a5SBagalkote, Sreenivas 1019c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1020c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1021c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1022c4a3e0a5SBagalkote, Sreenivas 1023c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 1024c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 1025c4a3e0a5SBagalkote, Sreenivas 1026c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1027c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1028c4a3e0a5SBagalkote, Sreenivas 1029c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1030c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 1031c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 1032c4a3e0a5SBagalkote, Sreenivas 1033c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 1034c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 1035c4a3e0a5SBagalkote, Sreenivas 1036c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 1037c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 1038c4a3e0a5SBagalkote, Sreenivas 1039c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 1040c4a3e0a5SBagalkote, Sreenivas 1041c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1042c4a3e0a5SBagalkote, Sreenivas 1043c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1044c4a3e0a5SBagalkote, Sreenivas 1045c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1046c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1047c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1048c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1049c4a3e0a5SBagalkote, Sreenivas 1050c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1051c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1052c4a3e0a5SBagalkote, Sreenivas 1053c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1054c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1055c4a3e0a5SBagalkote, Sreenivas 1056c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1057c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1058c4a3e0a5SBagalkote, Sreenivas 1059c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1060c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 1061c4a3e0a5SBagalkote, Sreenivas 1062c4a3e0a5SBagalkote, Sreenivas union { 1063c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1064c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1065c4a3e0a5SBagalkote, Sreenivas } sgl; 1066c4a3e0a5SBagalkote, Sreenivas 1067c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1068c4a3e0a5SBagalkote, Sreenivas 1069c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1070c4a3e0a5SBagalkote, Sreenivas 1071c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1072c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1073c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1074c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1075c4a3e0a5SBagalkote, Sreenivas 1076c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1077c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1078c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1079c4a3e0a5SBagalkote, Sreenivas 1080c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1081c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1082c4a3e0a5SBagalkote, Sreenivas 1083c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1084c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1085c4a3e0a5SBagalkote, Sreenivas 1086c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1087c4a3e0a5SBagalkote, Sreenivas 1088c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 1089c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 1090c4a3e0a5SBagalkote, Sreenivas 1091c4a3e0a5SBagalkote, Sreenivas union { 1092c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1093c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1094c4a3e0a5SBagalkote, Sreenivas } sgl; 1095c4a3e0a5SBagalkote, Sreenivas 1096c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1097c4a3e0a5SBagalkote, Sreenivas 1098c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1099c4a3e0a5SBagalkote, Sreenivas 1100c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1101c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1102c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1103c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1104c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1105c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1106c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1107c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1108c4a3e0a5SBagalkote, Sreenivas 1109c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1110c4a3e0a5SBagalkote, Sreenivas }; 1111c4a3e0a5SBagalkote, Sreenivas 1112c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1113c4a3e0a5SBagalkote, Sreenivas 1114c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 1115c4a3e0a5SBagalkote, Sreenivas 1116c4a3e0a5SBagalkote, Sreenivas struct { 1117c4a3e0a5SBagalkote, Sreenivas u16 locale; 1118c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1119c4a3e0a5SBagalkote, Sreenivas s8 class; 1120c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 1121c4a3e0a5SBagalkote, Sreenivas 1122c4a3e0a5SBagalkote, Sreenivas u32 word; 1123c4a3e0a5SBagalkote, Sreenivas 1124c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1125c4a3e0a5SBagalkote, Sreenivas 1126c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 1127c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 1128c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 1129c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 1130c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 1131c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 1132c4a3e0a5SBagalkote, Sreenivas 1133c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1134c4a3e0a5SBagalkote, Sreenivas 1135c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1136c4a3e0a5SBagalkote, Sreenivas 1137c4a3e0a5SBagalkote, Sreenivas u16 progress; 1138c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 1139c4a3e0a5SBagalkote, Sreenivas 1140c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1141c4a3e0a5SBagalkote, Sreenivas 1142c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1143c4a3e0a5SBagalkote, Sreenivas 1144c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1145c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1146c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1147c4a3e0a5SBagalkote, Sreenivas 1148c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1149c4a3e0a5SBagalkote, Sreenivas 1150c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1151c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1152c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1153c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1154c4a3e0a5SBagalkote, Sreenivas 1155c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1156c4a3e0a5SBagalkote, Sreenivas 1157c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1158c4a3e0a5SBagalkote, Sreenivas 1159c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1160c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 1161c4a3e0a5SBagalkote, Sreenivas u32 code; 1162c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1163c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1164c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1165c4a3e0a5SBagalkote, Sreenivas 1166c4a3e0a5SBagalkote, Sreenivas union { 1167c4a3e0a5SBagalkote, Sreenivas struct { 1168c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1169c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1170c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1171c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1172c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1173c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1174c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1175c4a3e0a5SBagalkote, Sreenivas 1176c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1177c4a3e0a5SBagalkote, Sreenivas 1178c4a3e0a5SBagalkote, Sreenivas struct { 1179c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1180c4a3e0a5SBagalkote, Sreenivas u64 count; 1181c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1182c4a3e0a5SBagalkote, Sreenivas 1183c4a3e0a5SBagalkote, Sreenivas struct { 1184c4a3e0a5SBagalkote, Sreenivas u64 lba; 1185c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1186c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1187c4a3e0a5SBagalkote, Sreenivas 1188c4a3e0a5SBagalkote, Sreenivas struct { 1189c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1190c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 1191c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 1192c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1193c4a3e0a5SBagalkote, Sreenivas 1194c4a3e0a5SBagalkote, Sreenivas struct { 1195c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1196c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1197c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1198c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1199c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1200c4a3e0a5SBagalkote, Sreenivas 1201c4a3e0a5SBagalkote, Sreenivas struct { 1202c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1203c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1204c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1205c4a3e0a5SBagalkote, Sreenivas 1206c4a3e0a5SBagalkote, Sreenivas struct { 1207c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1208c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1209c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1210c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1211c4a3e0a5SBagalkote, Sreenivas 1212c4a3e0a5SBagalkote, Sreenivas struct { 1213c4a3e0a5SBagalkote, Sreenivas u64 strip; 1214c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1215c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1216c4a3e0a5SBagalkote, Sreenivas 1217c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1218c4a3e0a5SBagalkote, Sreenivas 1219c4a3e0a5SBagalkote, Sreenivas struct { 1220c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1221c4a3e0a5SBagalkote, Sreenivas u32 err; 1222c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1223c4a3e0a5SBagalkote, Sreenivas 1224c4a3e0a5SBagalkote, Sreenivas struct { 1225c4a3e0a5SBagalkote, Sreenivas u64 lba; 1226c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1227c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1228c4a3e0a5SBagalkote, Sreenivas 1229c4a3e0a5SBagalkote, Sreenivas struct { 1230c4a3e0a5SBagalkote, Sreenivas u64 lba; 1231c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1232c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1233c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1234c4a3e0a5SBagalkote, Sreenivas 1235c4a3e0a5SBagalkote, Sreenivas struct { 1236c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1237c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1238c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1239c4a3e0a5SBagalkote, Sreenivas 1240c4a3e0a5SBagalkote, Sreenivas struct { 1241c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1242c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1243c4a3e0a5SBagalkote, Sreenivas u32 newState; 1244c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1245c4a3e0a5SBagalkote, Sreenivas 1246c4a3e0a5SBagalkote, Sreenivas struct { 1247c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1248c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1249c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1250c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1251c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1252c4a3e0a5SBagalkote, Sreenivas 1253c4a3e0a5SBagalkote, Sreenivas u32 rate; 1254c4a3e0a5SBagalkote, Sreenivas char str[96]; 1255c4a3e0a5SBagalkote, Sreenivas 1256c4a3e0a5SBagalkote, Sreenivas struct { 1257c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1258c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1259c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1260c4a3e0a5SBagalkote, Sreenivas 1261c4a3e0a5SBagalkote, Sreenivas struct { 1262c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1263c4a3e0a5SBagalkote, Sreenivas u32 elog; 1264c4a3e0a5SBagalkote, Sreenivas char str[64]; 1265c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1266c4a3e0a5SBagalkote, Sreenivas 1267c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1268c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1269c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1270c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1271c4a3e0a5SBagalkote, Sreenivas } args; 1272c4a3e0a5SBagalkote, Sreenivas 1273c4a3e0a5SBagalkote, Sreenivas char description[128]; 1274c4a3e0a5SBagalkote, Sreenivas 1275c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1276c4a3e0a5SBagalkote, Sreenivas 12777e8a75f4SYang, Bo struct megasas_aen_event { 12787e8a75f4SYang, Bo struct work_struct hotplug_work; 12797e8a75f4SYang, Bo struct megasas_instance *instance; 12807e8a75f4SYang, Bo }; 12817e8a75f4SYang, Bo 1282c8e858feSadam radford struct megasas_irq_context { 1283c8e858feSadam radford struct megasas_instance *instance; 1284c8e858feSadam radford u32 MSIxIndex; 1285c8e858feSadam radford }; 1286c8e858feSadam radford 1287c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1288c4a3e0a5SBagalkote, Sreenivas 1289c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1290c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1291c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1292c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1293c4a3e0a5SBagalkote, Sreenivas 1294c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1295c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1296c4a3e0a5SBagalkote, Sreenivas 1297c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1298c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1299c4a3e0a5SBagalkote, Sreenivas 130081e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1301bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1302c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1303c4a3e0a5SBagalkote, Sreenivas 1304c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1305c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 13069c915a8cSadam radford /* For Fusion its num IOCTL cmds, for others MFI based its 13079c915a8cSadam radford max_fw_cmds */ 13089c915a8cSadam radford u16 max_mfi_cmds; 1309c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 13107e8a75f4SYang, Bo struct megasas_aen_event *ev; 1311c4a3e0a5SBagalkote, Sreenivas 1312c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1313c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 131439a98554Sbo yang /* used to sync fire the cmd to fw */ 1315c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 131639a98554Sbo yang /* used to sync fire the cmd to fw */ 131739a98554Sbo yang spinlock_t hba_lock; 13187343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 13197343eb65Sbo yang spinlock_t completion_lock; 1320c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1321c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1322c4a3e0a5SBagalkote, Sreenivas 1323c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1324c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1325c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1326e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1327c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1328c4a3e0a5SBagalkote, Sreenivas 1329c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1330c4a3e0a5SBagalkote, Sreenivas 1331c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1332c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1333c4a3e0a5SBagalkote, Sreenivas 1334c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1335c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 133639a98554Sbo yang u32 fw_support_ieee; 1337c4a3e0a5SBagalkote, Sreenivas 1338e4a082c7SSumant Patro atomic_t fw_outstanding; 133939a98554Sbo yang atomic_t fw_reset_no_pci_access; 13401341c939SSumant Patro 13411341c939SSumant Patro struct megasas_instance_template *instancet; 13425d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 134339a98554Sbo yang struct work_struct work_init; 134405e9ebbeSSumant Patro 134505e9ebbeSSumant Patro u8 flag; 1346c3518837SYang, Bo u8 unload; 1347f4c9a131SYang, Bo u8 flag_ieee; 134839a98554Sbo yang u8 issuepend_done; 134939a98554Sbo yang u8 disableOnlineCtrlReset; 135039a98554Sbo yang u8 adprecovery; 135105e9ebbeSSumant Patro unsigned long last_time; 135239a98554Sbo yang u32 mfiStatus; 135339a98554Sbo yang u32 last_seq_num; 1354ad84db2eSbo yang 1355ad84db2eSbo yang struct timer_list io_completion_timer; 135639a98554Sbo yang struct list_head internal_reset_pending_q; 135780d9da98Sadam radford 135825985edcSLucas De Marchi /* Ptr to hba specific information */ 13599c915a8cSadam radford void *ctrl_context; 1360c8e858feSadam radford unsigned int msix_vectors; 1361c8e858feSadam radford struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 1362c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 13639c915a8cSadam radford u64 map_id; 13649c915a8cSadam radford struct megasas_cmd *map_update_cmd; 1365b6d5d880Sadam radford unsigned long bar; 13669c915a8cSadam radford long reset_flags; 13679c915a8cSadam radford struct mutex reset_mutex; 136839a98554Sbo yang }; 136939a98554Sbo yang 137039a98554Sbo yang enum { 137139a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 137239a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 137339a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 137439a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 137539a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 137639a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1377c4a3e0a5SBagalkote, Sreenivas }; 1378c4a3e0a5SBagalkote, Sreenivas 13790c79e681SYang, Bo struct megasas_instance_template { 13800c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 13810c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 13820c79e681SYang, Bo 13830c79e681SYang, Bo void (*enable_intr)(struct megasas_register_set __iomem *) ; 13840c79e681SYang, Bo void (*disable_intr)(struct megasas_register_set __iomem *); 13850c79e681SYang, Bo 13860c79e681SYang, Bo int (*clear_intr)(struct megasas_register_set __iomem *); 13870c79e681SYang, Bo 13880c79e681SYang, Bo u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 138939a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 139039a98554Sbo yang struct megasas_register_set __iomem *); 139139a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 139239a98554Sbo yang struct megasas_register_set __iomem *); 1393cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp); 1394cd50ba8eSadam radford void (*tasklet)(unsigned long); 1395cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *); 1396cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *, 1397cd50ba8eSadam radford struct scsi_cmnd *); 1398cd50ba8eSadam radford void (*issue_dcmd) (struct megasas_instance *instance, 1399cd50ba8eSadam radford struct megasas_cmd *cmd); 14000c79e681SYang, Bo }; 14010c79e681SYang, Bo 1402c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1403c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1404c4a3e0a5SBagalkote, Sreenivas 1405c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1406c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1407c4a3e0a5SBagalkote, Sreenivas scp->device->id 1408c4a3e0a5SBagalkote, Sreenivas 1409c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1410c4a3e0a5SBagalkote, Sreenivas 1411c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1412c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1413c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1414c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1415c4a3e0a5SBagalkote, Sreenivas 1416c4a3e0a5SBagalkote, Sreenivas u32 index; 1417c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1418c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 141939a98554Sbo yang u8 abort_aen; 142039a98554Sbo yang u8 retry_for_fw_reset; 142139a98554Sbo yang 1422c4a3e0a5SBagalkote, Sreenivas 1423c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1424c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1425c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 14269c915a8cSadam radford union { 14279c915a8cSadam radford struct { 14289c915a8cSadam radford u16 smid; 14299c915a8cSadam radford u16 resvd; 14309c915a8cSadam radford } context; 1431c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1432c4a3e0a5SBagalkote, Sreenivas }; 14339c915a8cSadam radford }; 1434c4a3e0a5SBagalkote, Sreenivas 1435c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1436c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1437c4a3e0a5SBagalkote, Sreenivas 1438c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1439c4a3e0a5SBagalkote, Sreenivas 1440c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1441c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1442c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1443c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1444c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1445c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1446c4a3e0a5SBagalkote, Sreenivas union { 1447c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1448c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1449c4a3e0a5SBagalkote, Sreenivas } frame; 1450c4a3e0a5SBagalkote, Sreenivas 1451c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1452c4a3e0a5SBagalkote, Sreenivas 1453c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1454c4a3e0a5SBagalkote, Sreenivas 1455c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1456c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1457c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1458c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1459c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1460c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1461c4a3e0a5SBagalkote, Sreenivas 1462c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1463c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1464c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1465c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1466c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1467c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1468c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1469c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1470c4a3e0a5SBagalkote, Sreenivas union { 1471c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1472c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1473c4a3e0a5SBagalkote, Sreenivas } frame; 1474c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1475c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1476c4a3e0a5SBagalkote, Sreenivas 14770e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1478c4a3e0a5SBagalkote, Sreenivas #endif 1479c4a3e0a5SBagalkote, Sreenivas 1480cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1481c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1482c4a3e0a5SBagalkote, Sreenivas 1483c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1484c4a3e0a5SBagalkote, Sreenivas 1485c4a3e0a5SBagalkote, Sreenivas u16 count; 1486c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1487c4a3e0a5SBagalkote, Sreenivas int max_index; 1488c4a3e0a5SBagalkote, Sreenivas }; 1489c4a3e0a5SBagalkote, Sreenivas 149066192dfeSadam radford #define msi_control_reg(base) (base + PCI_MSI_FLAGS) 149166192dfeSadam radford #define PCI_MSIX_FLAGS_ENABLE (1 << 15) 149266192dfeSadam radford 1493c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1494