1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * 3c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 4c4a3e0a5SBagalkote, Sreenivas * 5f28cd7cfSbo yang * Copyright (c) 2003-2005 LSI Corporation. 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 9c4a3e0a5SBagalkote, Sreenivas * as published by the Free Software Foundation; either version 10c4a3e0a5SBagalkote, Sreenivas * 2 of the License, or (at your option) any later version. 11c4a3e0a5SBagalkote, Sreenivas * 12c4a3e0a5SBagalkote, Sreenivas * FILE : megaraid_sas.h 13c4a3e0a5SBagalkote, Sreenivas */ 14c4a3e0a5SBagalkote, Sreenivas 15c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 16c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 17c4a3e0a5SBagalkote, Sreenivas 18a69b74d3SRandy Dunlap /* 19c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 20c4a3e0a5SBagalkote, Sreenivas */ 2124541f99SYang, Bo #define MEGASAS_VERSION "00.00.04.01" 2224541f99SYang, Bo #define MEGASAS_RELDATE "July 24, 2008" 2324541f99SYang, Bo #define MEGASAS_EXT_VERSION "Thu July 24 11:41:51 PST 2008" 240e98936cSSumant Patro 250e98936cSSumant Patro /* 260e98936cSSumant Patro * Device IDs 270e98936cSSumant Patro */ 280e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 29af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 300e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 316610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 326610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 3387911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 3487911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 350e98936cSSumant Patro 36c4a3e0a5SBagalkote, Sreenivas /* 37c4a3e0a5SBagalkote, Sreenivas * ===================================== 38c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 39c4a3e0a5SBagalkote, Sreenivas * ===================================== 40c4a3e0a5SBagalkote, Sreenivas */ 41c4a3e0a5SBagalkote, Sreenivas 42c4a3e0a5SBagalkote, Sreenivas /* 43c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 44c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 45c4a3e0a5SBagalkote, Sreenivas * "message frames" 46c4a3e0a5SBagalkote, Sreenivas */ 47c4a3e0a5SBagalkote, Sreenivas 48a69b74d3SRandy Dunlap /* 49c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 50c4a3e0a5SBagalkote, Sreenivas */ 51c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 52c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 53c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 54c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 55c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 56c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 57c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 58e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 59c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 60c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 61c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 62c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 63c4a3e0a5SBagalkote, Sreenivas 64c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 65c4a3e0a5SBagalkote, Sreenivas 66a69b74d3SRandy Dunlap /* 67c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 68c4a3e0a5SBagalkote, Sreenivas * 69c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 70c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 71c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 72c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 73e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 74e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 75c4a3e0a5SBagalkote, Sreenivas */ 76e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 77c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 78c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 79c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 80e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 81e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 82e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 83e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 84e3bbff9fSSumant Patro MFI_INIT_ABORT 85c4a3e0a5SBagalkote, Sreenivas 86a69b74d3SRandy Dunlap /* 87c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 88c4a3e0a5SBagalkote, Sreenivas */ 89c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 90c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 91c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 92c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 93c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 94c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 95c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 96c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 97c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 98c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 99c4a3e0a5SBagalkote, Sreenivas 100a69b74d3SRandy Dunlap /* 101c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 102c4a3e0a5SBagalkote, Sreenivas */ 103c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 104c4a3e0a5SBagalkote, Sreenivas 105a69b74d3SRandy Dunlap /* 106c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 107c4a3e0a5SBagalkote, Sreenivas */ 108c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 109c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 110c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 111c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 112c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 113c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 114c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 115c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 116c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 117c4a3e0a5SBagalkote, Sreenivas 118c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 119c4a3e0a5SBagalkote, Sreenivas 120c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 121c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 122c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 123c4a3e0a5SBagalkote, Sreenivas 124c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 12531ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 126c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 127c4a3e0a5SBagalkote, Sreenivas 128c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 129c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 130c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 131c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 132c4a3e0a5SBagalkote, Sreenivas 133c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 134c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 135c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 136c4a3e0a5SBagalkote, Sreenivas 137a69b74d3SRandy Dunlap /* 138c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 139c4a3e0a5SBagalkote, Sreenivas */ 140c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 141c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 142c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 143c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 144c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 145c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 146c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 147c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 148c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 149c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 150c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 151c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 152c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 153c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 154c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 155c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 156c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 157c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 158c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 159c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 160c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 161c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 162c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 163c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 164c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 165c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 166c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 167c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 168c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 169c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 170c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 171c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 172c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 173c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 174c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 175c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 176c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 177c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 178c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 179c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 180c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 181c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 182c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 183c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 184c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 185c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 186c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 187c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 188c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 189c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 190c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 191c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 192c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 193c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 194c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 195c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 196c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 197c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 198c4a3e0a5SBagalkote, Sreenivas 199c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 200c4a3e0a5SBagalkote, Sreenivas }; 201c4a3e0a5SBagalkote, Sreenivas 202c4a3e0a5SBagalkote, Sreenivas /* 203c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 204c4a3e0a5SBagalkote, Sreenivas */ 205c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 206c4a3e0a5SBagalkote, Sreenivas 207c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 208c4a3e0a5SBagalkote, Sreenivas 209c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 210c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 211c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 212c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 213c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 214c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 215c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 216c4a3e0a5SBagalkote, Sreenivas 217c4a3e0a5SBagalkote, Sreenivas }; 218c4a3e0a5SBagalkote, Sreenivas 219c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 220c4a3e0a5SBagalkote, Sreenivas 221c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 222c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 223c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 224c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 225c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 226c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 227c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 228c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 229c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 230c4a3e0a5SBagalkote, Sreenivas 231c4a3e0a5SBagalkote, Sreenivas }; 232c4a3e0a5SBagalkote, Sreenivas 233c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 234c4a3e0a5SBagalkote, Sreenivas 235c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 236c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 237c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 238c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 239c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 240c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 241c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 242c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 243c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 244c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 245c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 246c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 247c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 248c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 249c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 250c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 251c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 252c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 253c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 254c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 255c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 256c4a3e0a5SBagalkote, Sreenivas 257c4a3e0a5SBagalkote, Sreenivas }; 258c4a3e0a5SBagalkote, Sreenivas 259c4a3e0a5SBagalkote, Sreenivas /* 260c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 261c4a3e0a5SBagalkote, Sreenivas */ 262c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 263c4a3e0a5SBagalkote, Sreenivas 264c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 265c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 266c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 267c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 268c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 269c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 270c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 271c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 272c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 273c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 274c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 275c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 276c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 277c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 278c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 279c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 280c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 281c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 282c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 283c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 284c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 285c4a3e0a5SBagalkote, Sreenivas u8 reserved[38]; 286c4a3e0a5SBagalkote, Sreenivas 287c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 288c4a3e0a5SBagalkote, Sreenivas 289c4a3e0a5SBagalkote, Sreenivas /* 290c4a3e0a5SBagalkote, Sreenivas * SAS controller information 291c4a3e0a5SBagalkote, Sreenivas */ 292c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 293c4a3e0a5SBagalkote, Sreenivas 294c4a3e0a5SBagalkote, Sreenivas /* 295c4a3e0a5SBagalkote, Sreenivas * PCI device information 296c4a3e0a5SBagalkote, Sreenivas */ 297c4a3e0a5SBagalkote, Sreenivas struct { 298c4a3e0a5SBagalkote, Sreenivas 299c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 300c4a3e0a5SBagalkote, Sreenivas u16 device_id; 301c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 302c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 303c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 304c4a3e0a5SBagalkote, Sreenivas 305c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 306c4a3e0a5SBagalkote, Sreenivas 307c4a3e0a5SBagalkote, Sreenivas /* 308c4a3e0a5SBagalkote, Sreenivas * Host interface information 309c4a3e0a5SBagalkote, Sreenivas */ 310c4a3e0a5SBagalkote, Sreenivas struct { 311c4a3e0a5SBagalkote, Sreenivas 312c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 313c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 314c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 315c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 316c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 317c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 318c4a3e0a5SBagalkote, Sreenivas u8 port_count; 319c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 320c4a3e0a5SBagalkote, Sreenivas 321c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 322c4a3e0a5SBagalkote, Sreenivas 323c4a3e0a5SBagalkote, Sreenivas /* 324c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 325c4a3e0a5SBagalkote, Sreenivas */ 326c4a3e0a5SBagalkote, Sreenivas struct { 327c4a3e0a5SBagalkote, Sreenivas 328c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 329c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 330c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 331c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 332c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 333c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 334c4a3e0a5SBagalkote, Sreenivas u8 port_count; 335c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 336c4a3e0a5SBagalkote, Sreenivas 337c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 338c4a3e0a5SBagalkote, Sreenivas 339c4a3e0a5SBagalkote, Sreenivas /* 340c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 341c4a3e0a5SBagalkote, Sreenivas */ 342c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 343c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 344c4a3e0a5SBagalkote, Sreenivas 345c4a3e0a5SBagalkote, Sreenivas struct { 346c4a3e0a5SBagalkote, Sreenivas 347c4a3e0a5SBagalkote, Sreenivas char name[8]; 348c4a3e0a5SBagalkote, Sreenivas char version[32]; 349c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 350c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 351c4a3e0a5SBagalkote, Sreenivas 352c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 353c4a3e0a5SBagalkote, Sreenivas 354c4a3e0a5SBagalkote, Sreenivas /* 355c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 356c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 357c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 358c4a3e0a5SBagalkote, Sreenivas * terminated 359c4a3e0a5SBagalkote, Sreenivas */ 360c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 361c4a3e0a5SBagalkote, Sreenivas 362c4a3e0a5SBagalkote, Sreenivas struct { 363c4a3e0a5SBagalkote, Sreenivas 364c4a3e0a5SBagalkote, Sreenivas char name[8]; 365c4a3e0a5SBagalkote, Sreenivas char version[32]; 366c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 367c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 368c4a3e0a5SBagalkote, Sreenivas 369c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 370c4a3e0a5SBagalkote, Sreenivas 371c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 372c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 373c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 374c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 375c4a3e0a5SBagalkote, Sreenivas 376c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 377c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 378c4a3e0a5SBagalkote, Sreenivas 379c4a3e0a5SBagalkote, Sreenivas /* 380c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 381c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 382c4a3e0a5SBagalkote, Sreenivas */ 383c4a3e0a5SBagalkote, Sreenivas struct { 384c4a3e0a5SBagalkote, Sreenivas 385c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 386c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 387c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 388c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 389c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 390c4a3e0a5SBagalkote, Sreenivas 391c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 392c4a3e0a5SBagalkote, Sreenivas 393c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 394c4a3e0a5SBagalkote, Sreenivas 395c4a3e0a5SBagalkote, Sreenivas /* 396c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 397c4a3e0a5SBagalkote, Sreenivas */ 398c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 399c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 400c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 401c4a3e0a5SBagalkote, Sreenivas 402c4a3e0a5SBagalkote, Sreenivas /* 403c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 404c4a3e0a5SBagalkote, Sreenivas */ 405c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 406c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 407c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 408c4a3e0a5SBagalkote, Sreenivas 409c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 410c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 411c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 412c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 413c4a3e0a5SBagalkote, Sreenivas 414c4a3e0a5SBagalkote, Sreenivas /* 415c4a3e0a5SBagalkote, Sreenivas * Memory size information 416c4a3e0a5SBagalkote, Sreenivas */ 417c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 418c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 419c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 420c4a3e0a5SBagalkote, Sreenivas 421c4a3e0a5SBagalkote, Sreenivas /* 422c4a3e0a5SBagalkote, Sreenivas * Error counters 423c4a3e0a5SBagalkote, Sreenivas */ 424c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 425c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 426c4a3e0a5SBagalkote, Sreenivas 427c4a3e0a5SBagalkote, Sreenivas /* 428c4a3e0a5SBagalkote, Sreenivas * Cluster information 429c4a3e0a5SBagalkote, Sreenivas */ 430c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 431c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 432c4a3e0a5SBagalkote, Sreenivas 433c4a3e0a5SBagalkote, Sreenivas /* 434c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 435c4a3e0a5SBagalkote, Sreenivas */ 436c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 437c4a3e0a5SBagalkote, Sreenivas 438c4a3e0a5SBagalkote, Sreenivas /* 439c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 440c4a3e0a5SBagalkote, Sreenivas */ 441c4a3e0a5SBagalkote, Sreenivas struct { 442c4a3e0a5SBagalkote, Sreenivas 443c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 444c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 445c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 446c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 447c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 448c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 449c4a3e0a5SBagalkote, Sreenivas 450c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 451c4a3e0a5SBagalkote, Sreenivas 452c4a3e0a5SBagalkote, Sreenivas struct { 453c4a3e0a5SBagalkote, Sreenivas 454c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 455c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 456c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 457c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 458c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 459c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 460c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 461c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 462c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 463c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 464c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 465c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 466c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 467c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 468c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 469c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 470c4a3e0a5SBagalkote, Sreenivas 471c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 472c4a3e0a5SBagalkote, Sreenivas 473c4a3e0a5SBagalkote, Sreenivas struct { 474c4a3e0a5SBagalkote, Sreenivas 475c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 476c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 477c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 478c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 479c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 480c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 481c4a3e0a5SBagalkote, Sreenivas 482c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 483c4a3e0a5SBagalkote, Sreenivas 484c4a3e0a5SBagalkote, Sreenivas struct { 485c4a3e0a5SBagalkote, Sreenivas 486c4a3e0a5SBagalkote, Sreenivas u8 min; 487c4a3e0a5SBagalkote, Sreenivas u8 max; 488c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 489c4a3e0a5SBagalkote, Sreenivas 490c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 491c4a3e0a5SBagalkote, Sreenivas 492c4a3e0a5SBagalkote, Sreenivas struct { 493c4a3e0a5SBagalkote, Sreenivas 494c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 495c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 496c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 497c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 498c4a3e0a5SBagalkote, Sreenivas 499c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 500c4a3e0a5SBagalkote, Sreenivas 501c4a3e0a5SBagalkote, Sreenivas struct { 502c4a3e0a5SBagalkote, Sreenivas 503c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 504c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 505c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 506c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 507c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 508c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 509c4a3e0a5SBagalkote, Sreenivas 510c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 511c4a3e0a5SBagalkote, Sreenivas 512c4a3e0a5SBagalkote, Sreenivas /* 513c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 514c4a3e0a5SBagalkote, Sreenivas */ 515c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 516c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 517c4a3e0a5SBagalkote, Sreenivas 518c4a3e0a5SBagalkote, Sreenivas /* 519c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 520c4a3e0a5SBagalkote, Sreenivas */ 521c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 522c4a3e0a5SBagalkote, Sreenivas 523c4a3e0a5SBagalkote, Sreenivas /* 524c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 525c4a3e0a5SBagalkote, Sreenivas */ 526c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 527c4a3e0a5SBagalkote, Sreenivas 528c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 529c4a3e0a5SBagalkote, Sreenivas 530c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 531c4a3e0a5SBagalkote, Sreenivas 532c4a3e0a5SBagalkote, Sreenivas /* 533c4a3e0a5SBagalkote, Sreenivas * =============================== 534c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 535c4a3e0a5SBagalkote, Sreenivas * =============================== 536c4a3e0a5SBagalkote, Sreenivas */ 537c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 538c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 539c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 540c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 541c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 542c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 543c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 544c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 545c4a3e0a5SBagalkote, Sreenivas 546658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 547658dcedbSSumant Patro 54805e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 54905e9ebbeSSumant Patro 550d532dbe2Sbo yang /* Frame Type */ 551d532dbe2Sbo yang #define IO_FRAME 0 552d532dbe2Sbo yang #define PTHRU_FRAME 1 553d532dbe2Sbo yang 554c4a3e0a5SBagalkote, Sreenivas /* 555c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 556c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 557c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 558c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 559c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 560c4a3e0a5SBagalkote, Sreenivas */ 561c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 5622a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 563c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 564c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 56505e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 566c4a3e0a5SBagalkote, Sreenivas 567c4a3e0a5SBagalkote, Sreenivas /* 568c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 569c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 570c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 571c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 572c4a3e0a5SBagalkote, Sreenivas * is shown below 573c4a3e0a5SBagalkote, Sreenivas */ 574c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 575c4a3e0a5SBagalkote, Sreenivas 576c4a3e0a5SBagalkote, Sreenivas /* 577c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 578c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 579c4a3e0a5SBagalkote, Sreenivas */ 580c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 581c4a3e0a5SBagalkote, Sreenivas 582c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 58314faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 584ad84db2eSbo yang #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10) 585c4a3e0a5SBagalkote, Sreenivas 586f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 5876610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 5886610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 58987911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 59087911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 5910e98936cSSumant Patro 5920e98936cSSumant Patro /* 5930e98936cSSumant Patro * register set for both 1068 and 1078 controllers 5940e98936cSSumant Patro * structure extended for 1078 registers 5950e98936cSSumant Patro */ 596c4a3e0a5SBagalkote, Sreenivas 597f9876f0bSSumant Patro struct megasas_register_set { 598c4a3e0a5SBagalkote, Sreenivas u32 reserved_0[4]; /*0000h*/ 599c4a3e0a5SBagalkote, Sreenivas 600c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 601c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 602c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 603c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 604c4a3e0a5SBagalkote, Sreenivas 605c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 606c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 607c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 608c4a3e0a5SBagalkote, Sreenivas 609c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 610c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 611c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 612c4a3e0a5SBagalkote, Sreenivas 613c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 614c4a3e0a5SBagalkote, Sreenivas 615c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 616c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 617c4a3e0a5SBagalkote, Sreenivas 618f9876f0bSSumant Patro u32 reserved_2[22]; /*0048h*/ 619c4a3e0a5SBagalkote, Sreenivas 620f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 621f9876f0bSSumant Patro 622f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 623f9876f0bSSumant Patro 624f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 625f9876f0bSSumant Patro 626f9876f0bSSumant Patro u32 reserved_4[3]; /*00B4h*/ 627f9876f0bSSumant Patro 628f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 629f9876f0bSSumant Patro 630f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 631f9876f0bSSumant Patro 632f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 633f9876f0bSSumant Patro u32 index_registers[820]; /*00CCh*/ 634c4a3e0a5SBagalkote, Sreenivas 635c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 636c4a3e0a5SBagalkote, Sreenivas 637c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 638c4a3e0a5SBagalkote, Sreenivas 639c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 640c4a3e0a5SBagalkote, Sreenivas u32 length; 641c4a3e0a5SBagalkote, Sreenivas 642c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 643c4a3e0a5SBagalkote, Sreenivas 644c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 645c4a3e0a5SBagalkote, Sreenivas 646c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 647c4a3e0a5SBagalkote, Sreenivas u32 length; 648c4a3e0a5SBagalkote, Sreenivas 649c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 650c4a3e0a5SBagalkote, Sreenivas 651c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 652c4a3e0a5SBagalkote, Sreenivas 653c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 654c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 655c4a3e0a5SBagalkote, Sreenivas 656c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 657c4a3e0a5SBagalkote, Sreenivas 658c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 659c4a3e0a5SBagalkote, Sreenivas 660c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 661c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 662c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 663c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 664c4a3e0a5SBagalkote, Sreenivas 665c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 666c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 667c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 668c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 669c4a3e0a5SBagalkote, Sreenivas 670c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 671c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 672c4a3e0a5SBagalkote, Sreenivas 673c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 674c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 675c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 676c4a3e0a5SBagalkote, Sreenivas 677c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 678c4a3e0a5SBagalkote, Sreenivas 679c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 680c4a3e0a5SBagalkote, Sreenivas 681c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 682c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 683c4a3e0a5SBagalkote, Sreenivas 684c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 685c4a3e0a5SBagalkote, Sreenivas 686c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 687c4a3e0a5SBagalkote, Sreenivas 688c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 689c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 690c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 691c4a3e0a5SBagalkote, Sreenivas 692c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 693c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 694c4a3e0a5SBagalkote, Sreenivas 695c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 696c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 697c4a3e0a5SBagalkote, Sreenivas 698c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 699c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 700c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 701c4a3e0a5SBagalkote, Sreenivas 702c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 703c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 704c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 705c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 706c4a3e0a5SBagalkote, Sreenivas 707c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 708c4a3e0a5SBagalkote, Sreenivas 709c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 710c4a3e0a5SBagalkote, Sreenivas 711c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 712c4a3e0a5SBagalkote, Sreenivas 713c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 714c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 715c4a3e0a5SBagalkote, Sreenivas 716c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 717c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 718c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 719c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 720c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 721c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 722c4a3e0a5SBagalkote, Sreenivas 723c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 724c4a3e0a5SBagalkote, Sreenivas 725c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 726c4a3e0a5SBagalkote, Sreenivas 727c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 728c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 729c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 730c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 731c4a3e0a5SBagalkote, Sreenivas 732c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 733c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 734c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 735c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 736c4a3e0a5SBagalkote, Sreenivas 737c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 738c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 739c4a3e0a5SBagalkote, Sreenivas 740c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 741c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 742c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 743c4a3e0a5SBagalkote, Sreenivas 744c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 745c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 746c4a3e0a5SBagalkote, Sreenivas 747c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 748c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 749c4a3e0a5SBagalkote, Sreenivas 750c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 751c4a3e0a5SBagalkote, Sreenivas 752c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 753c4a3e0a5SBagalkote, Sreenivas 754c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 755c4a3e0a5SBagalkote, Sreenivas 756c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 757c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 758c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 759c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 760c4a3e0a5SBagalkote, Sreenivas 761c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 762c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 763c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 764c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 765c4a3e0a5SBagalkote, Sreenivas 766c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 767c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 768c4a3e0a5SBagalkote, Sreenivas 769c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 770c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 771c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 772c4a3e0a5SBagalkote, Sreenivas 773c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 774c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 775c4a3e0a5SBagalkote, Sreenivas 776c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 777c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 778c4a3e0a5SBagalkote, Sreenivas 779c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 780c4a3e0a5SBagalkote, Sreenivas 781c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 782c4a3e0a5SBagalkote, Sreenivas 783c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 784c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 785c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 786c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 787c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 788c4a3e0a5SBagalkote, Sreenivas 789c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 790c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 791c4a3e0a5SBagalkote, Sreenivas 792c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 793c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 794c4a3e0a5SBagalkote, Sreenivas 795c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 796c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 797c4a3e0a5SBagalkote, Sreenivas 798c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 799c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 800c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 801c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 802c4a3e0a5SBagalkote, Sreenivas } mbox; 803c4a3e0a5SBagalkote, Sreenivas 804c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 805c4a3e0a5SBagalkote, Sreenivas 806c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 807c4a3e0a5SBagalkote, Sreenivas 808c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 809c4a3e0a5SBagalkote, Sreenivas 810c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 811c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 812c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 813c4a3e0a5SBagalkote, Sreenivas 814c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 815c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 816c4a3e0a5SBagalkote, Sreenivas 817c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 818c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 819c4a3e0a5SBagalkote, Sreenivas 820c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 821c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 822c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 823c4a3e0a5SBagalkote, Sreenivas 824c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 825c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 826c4a3e0a5SBagalkote, Sreenivas 827c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 828c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 829c4a3e0a5SBagalkote, Sreenivas 830c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 831c4a3e0a5SBagalkote, Sreenivas 832c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 833c4a3e0a5SBagalkote, Sreenivas 834c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 835c4a3e0a5SBagalkote, Sreenivas 836c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 837c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 838c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 839c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 840c4a3e0a5SBagalkote, Sreenivas 841c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 842c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 843c4a3e0a5SBagalkote, Sreenivas 844c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 845c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 846c4a3e0a5SBagalkote, Sreenivas 847c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 848c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 849c4a3e0a5SBagalkote, Sreenivas 850c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 851c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 852c4a3e0a5SBagalkote, Sreenivas 853c4a3e0a5SBagalkote, Sreenivas union { 854c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 855c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 856c4a3e0a5SBagalkote, Sreenivas } sgl; 857c4a3e0a5SBagalkote, Sreenivas 858c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 859c4a3e0a5SBagalkote, Sreenivas 860c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 861c4a3e0a5SBagalkote, Sreenivas 862c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 863c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 864c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 865c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 866c4a3e0a5SBagalkote, Sreenivas 867c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 868c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 869c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 870c4a3e0a5SBagalkote, Sreenivas 871c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 872c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 873c4a3e0a5SBagalkote, Sreenivas 874c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 875c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 876c4a3e0a5SBagalkote, Sreenivas 877c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 878c4a3e0a5SBagalkote, Sreenivas 879c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 880c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 881c4a3e0a5SBagalkote, Sreenivas 882c4a3e0a5SBagalkote, Sreenivas union { 883c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 884c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 885c4a3e0a5SBagalkote, Sreenivas } sgl; 886c4a3e0a5SBagalkote, Sreenivas 887c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 888c4a3e0a5SBagalkote, Sreenivas 889c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 890c4a3e0a5SBagalkote, Sreenivas 891c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 892c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 893c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 894c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 895c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 896c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 897c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 898c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 899c4a3e0a5SBagalkote, Sreenivas 900c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 901c4a3e0a5SBagalkote, Sreenivas }; 902c4a3e0a5SBagalkote, Sreenivas 903c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 904c4a3e0a5SBagalkote, Sreenivas 905c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 906c4a3e0a5SBagalkote, Sreenivas 907c4a3e0a5SBagalkote, Sreenivas struct { 908c4a3e0a5SBagalkote, Sreenivas u16 locale; 909c4a3e0a5SBagalkote, Sreenivas u8 reserved; 910c4a3e0a5SBagalkote, Sreenivas s8 class; 911c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 912c4a3e0a5SBagalkote, Sreenivas 913c4a3e0a5SBagalkote, Sreenivas u32 word; 914c4a3e0a5SBagalkote, Sreenivas 915c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 916c4a3e0a5SBagalkote, Sreenivas 917c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 918c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 919c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 920c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 921c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 922c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 923c4a3e0a5SBagalkote, Sreenivas 924c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 925c4a3e0a5SBagalkote, Sreenivas 926c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 927c4a3e0a5SBagalkote, Sreenivas 928c4a3e0a5SBagalkote, Sreenivas u16 progress; 929c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 930c4a3e0a5SBagalkote, Sreenivas 931c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 932c4a3e0a5SBagalkote, Sreenivas 933c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 934c4a3e0a5SBagalkote, Sreenivas 935c4a3e0a5SBagalkote, Sreenivas u16 target_id; 936c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 937c4a3e0a5SBagalkote, Sreenivas u8 reserved; 938c4a3e0a5SBagalkote, Sreenivas 939c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 940c4a3e0a5SBagalkote, Sreenivas 941c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 942c4a3e0a5SBagalkote, Sreenivas u16 device_id; 943c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 944c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 945c4a3e0a5SBagalkote, Sreenivas 946c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 947c4a3e0a5SBagalkote, Sreenivas 948c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 949c4a3e0a5SBagalkote, Sreenivas 950c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 951c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 952c4a3e0a5SBagalkote, Sreenivas u32 code; 953c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 954c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 955c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 956c4a3e0a5SBagalkote, Sreenivas 957c4a3e0a5SBagalkote, Sreenivas union { 958c4a3e0a5SBagalkote, Sreenivas struct { 959c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 960c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 961c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 962c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 963c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 964c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 965c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 966c4a3e0a5SBagalkote, Sreenivas 967c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 968c4a3e0a5SBagalkote, Sreenivas 969c4a3e0a5SBagalkote, Sreenivas struct { 970c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 971c4a3e0a5SBagalkote, Sreenivas u64 count; 972c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 973c4a3e0a5SBagalkote, Sreenivas 974c4a3e0a5SBagalkote, Sreenivas struct { 975c4a3e0a5SBagalkote, Sreenivas u64 lba; 976c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 977c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 978c4a3e0a5SBagalkote, Sreenivas 979c4a3e0a5SBagalkote, Sreenivas struct { 980c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 981c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 982c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 983c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 984c4a3e0a5SBagalkote, Sreenivas 985c4a3e0a5SBagalkote, Sreenivas struct { 986c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 987c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 988c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 989c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 990c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 991c4a3e0a5SBagalkote, Sreenivas 992c4a3e0a5SBagalkote, Sreenivas struct { 993c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 994c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 995c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 996c4a3e0a5SBagalkote, Sreenivas 997c4a3e0a5SBagalkote, Sreenivas struct { 998c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 999c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1000c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1001c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1002c4a3e0a5SBagalkote, Sreenivas 1003c4a3e0a5SBagalkote, Sreenivas struct { 1004c4a3e0a5SBagalkote, Sreenivas u64 strip; 1005c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1006c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1007c4a3e0a5SBagalkote, Sreenivas 1008c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1009c4a3e0a5SBagalkote, Sreenivas 1010c4a3e0a5SBagalkote, Sreenivas struct { 1011c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1012c4a3e0a5SBagalkote, Sreenivas u32 err; 1013c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1014c4a3e0a5SBagalkote, Sreenivas 1015c4a3e0a5SBagalkote, Sreenivas struct { 1016c4a3e0a5SBagalkote, Sreenivas u64 lba; 1017c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1018c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1019c4a3e0a5SBagalkote, Sreenivas 1020c4a3e0a5SBagalkote, Sreenivas struct { 1021c4a3e0a5SBagalkote, Sreenivas u64 lba; 1022c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1023c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1024c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1025c4a3e0a5SBagalkote, Sreenivas 1026c4a3e0a5SBagalkote, Sreenivas struct { 1027c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1028c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1029c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1030c4a3e0a5SBagalkote, Sreenivas 1031c4a3e0a5SBagalkote, Sreenivas struct { 1032c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1033c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1034c4a3e0a5SBagalkote, Sreenivas u32 newState; 1035c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1036c4a3e0a5SBagalkote, Sreenivas 1037c4a3e0a5SBagalkote, Sreenivas struct { 1038c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1039c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1040c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1041c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1042c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1043c4a3e0a5SBagalkote, Sreenivas 1044c4a3e0a5SBagalkote, Sreenivas u32 rate; 1045c4a3e0a5SBagalkote, Sreenivas char str[96]; 1046c4a3e0a5SBagalkote, Sreenivas 1047c4a3e0a5SBagalkote, Sreenivas struct { 1048c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1049c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1050c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1051c4a3e0a5SBagalkote, Sreenivas 1052c4a3e0a5SBagalkote, Sreenivas struct { 1053c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1054c4a3e0a5SBagalkote, Sreenivas u32 elog; 1055c4a3e0a5SBagalkote, Sreenivas char str[64]; 1056c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1057c4a3e0a5SBagalkote, Sreenivas 1058c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1059c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1060c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1061c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1062c4a3e0a5SBagalkote, Sreenivas } args; 1063c4a3e0a5SBagalkote, Sreenivas 1064c4a3e0a5SBagalkote, Sreenivas char description[128]; 1065c4a3e0a5SBagalkote, Sreenivas 1066c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1067c4a3e0a5SBagalkote, Sreenivas 10681341c939SSumant Patro struct megasas_instance_template { 10691341c939SSumant Patro void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *); 10701341c939SSumant Patro 10711341c939SSumant Patro void (*enable_intr)(struct megasas_register_set __iomem *) ; 1072b274cab7SSumant Patro void (*disable_intr)(struct megasas_register_set __iomem *); 10731341c939SSumant Patro 10741341c939SSumant Patro int (*clear_intr)(struct megasas_register_set __iomem *); 10751341c939SSumant Patro 10761341c939SSumant Patro u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 10771341c939SSumant Patro }; 10781341c939SSumant Patro 1079c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1080c4a3e0a5SBagalkote, Sreenivas 1081c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1082c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1083c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1084c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1085c4a3e0a5SBagalkote, Sreenivas 1086c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1087c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1088c4a3e0a5SBagalkote, Sreenivas 1089c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1090c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1091c4a3e0a5SBagalkote, Sreenivas 1092c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1093c4a3e0a5SBagalkote, Sreenivas 1094c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1095c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 1096c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 1097c4a3e0a5SBagalkote, Sreenivas 1098c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1099c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 1100c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 11017343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 11027343eb65Sbo yang spinlock_t completion_lock; 1103c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1104c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1105c4a3e0a5SBagalkote, Sreenivas 1106c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1107c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1108c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1109e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1110c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1111c4a3e0a5SBagalkote, Sreenivas 1112c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1113c4a3e0a5SBagalkote, Sreenivas 1114c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1115c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1116c4a3e0a5SBagalkote, Sreenivas 1117c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1118c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 1119c4a3e0a5SBagalkote, Sreenivas 1120e4a082c7SSumant Patro atomic_t fw_outstanding; 1121c4a3e0a5SBagalkote, Sreenivas u32 hw_crit_error; 11221341c939SSumant Patro 11231341c939SSumant Patro struct megasas_instance_template *instancet; 11245d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 112505e9ebbeSSumant Patro 112605e9ebbeSSumant Patro u8 flag; 1127c3518837SYang, Bo u8 unload; 112805e9ebbeSSumant Patro unsigned long last_time; 1129ad84db2eSbo yang 1130ad84db2eSbo yang struct timer_list io_completion_timer; 1131c4a3e0a5SBagalkote, Sreenivas }; 1132c4a3e0a5SBagalkote, Sreenivas 1133c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1134c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1135c4a3e0a5SBagalkote, Sreenivas 1136c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1137c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1138c4a3e0a5SBagalkote, Sreenivas scp->device->id 1139c4a3e0a5SBagalkote, Sreenivas 1140c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1141c4a3e0a5SBagalkote, Sreenivas 1142c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1143c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1144c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1145c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1146c4a3e0a5SBagalkote, Sreenivas 1147c4a3e0a5SBagalkote, Sreenivas u32 index; 1148c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1149c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 1150c4a3e0a5SBagalkote, Sreenivas u16 abort_aen; 1151c4a3e0a5SBagalkote, Sreenivas 1152c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1153c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1154c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 1155c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1156c4a3e0a5SBagalkote, Sreenivas }; 1157c4a3e0a5SBagalkote, Sreenivas 1158c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1159c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1160c4a3e0a5SBagalkote, Sreenivas 1161c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1162c4a3e0a5SBagalkote, Sreenivas 1163c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1164c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1165c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1166c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1167c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1168c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1169c4a3e0a5SBagalkote, Sreenivas union { 1170c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1171c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1172c4a3e0a5SBagalkote, Sreenivas } frame; 1173c4a3e0a5SBagalkote, Sreenivas 1174c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1175c4a3e0a5SBagalkote, Sreenivas 1176c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1177c4a3e0a5SBagalkote, Sreenivas 1178c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1179c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1180c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1181c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1182c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1183c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1184c4a3e0a5SBagalkote, Sreenivas 1185c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1186c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1187c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1188c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1189c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1190c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1191c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1192c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1193c4a3e0a5SBagalkote, Sreenivas union { 1194c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1195c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1196c4a3e0a5SBagalkote, Sreenivas } frame; 1197c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1198c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1199c4a3e0a5SBagalkote, Sreenivas 12000e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1201c4a3e0a5SBagalkote, Sreenivas #endif 1202c4a3e0a5SBagalkote, Sreenivas 1203cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1204c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1205c4a3e0a5SBagalkote, Sreenivas 1206c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1207c4a3e0a5SBagalkote, Sreenivas 1208c4a3e0a5SBagalkote, Sreenivas u16 count; 1209c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1210c4a3e0a5SBagalkote, Sreenivas int max_index; 1211c4a3e0a5SBagalkote, Sreenivas }; 1212c4a3e0a5SBagalkote, Sreenivas 1213c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1214