1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * 3c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 4c4a3e0a5SBagalkote, Sreenivas * 5f28cd7cfSbo yang * Copyright (c) 2003-2005 LSI Corporation. 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 9c4a3e0a5SBagalkote, Sreenivas * as published by the Free Software Foundation; either version 10c4a3e0a5SBagalkote, Sreenivas * 2 of the License, or (at your option) any later version. 11c4a3e0a5SBagalkote, Sreenivas * 12c4a3e0a5SBagalkote, Sreenivas * FILE : megaraid_sas.h 13c4a3e0a5SBagalkote, Sreenivas */ 14c4a3e0a5SBagalkote, Sreenivas 15c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 16c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 17c4a3e0a5SBagalkote, Sreenivas 18a69b74d3SRandy Dunlap /* 19c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 20c4a3e0a5SBagalkote, Sreenivas */ 2124541f99SYang, Bo #define MEGASAS_VERSION "00.00.04.01" 2224541f99SYang, Bo #define MEGASAS_RELDATE "July 24, 2008" 2324541f99SYang, Bo #define MEGASAS_EXT_VERSION "Thu July 24 11:41:51 PST 2008" 240e98936cSSumant Patro 250e98936cSSumant Patro /* 260e98936cSSumant Patro * Device IDs 270e98936cSSumant Patro */ 280e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 29af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 300e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 316610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 326610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 3387911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 3487911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 350e98936cSSumant Patro 36c4a3e0a5SBagalkote, Sreenivas /* 37c4a3e0a5SBagalkote, Sreenivas * ===================================== 38c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 39c4a3e0a5SBagalkote, Sreenivas * ===================================== 40c4a3e0a5SBagalkote, Sreenivas */ 41c4a3e0a5SBagalkote, Sreenivas 42c4a3e0a5SBagalkote, Sreenivas /* 43c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 44c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 45c4a3e0a5SBagalkote, Sreenivas * "message frames" 46c4a3e0a5SBagalkote, Sreenivas */ 47c4a3e0a5SBagalkote, Sreenivas 48a69b74d3SRandy Dunlap /* 49c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 50c4a3e0a5SBagalkote, Sreenivas */ 51c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 52c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 53c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 54c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 55c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 56c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 57c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 58e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 59c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 60c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 61c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 62c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 63c4a3e0a5SBagalkote, Sreenivas 64c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 65c4a3e0a5SBagalkote, Sreenivas 66a69b74d3SRandy Dunlap /* 67c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 68c4a3e0a5SBagalkote, Sreenivas * 69c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 70c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 71c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 72c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 73e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 74e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 75c4a3e0a5SBagalkote, Sreenivas */ 76e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 77c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 78c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 79c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 80e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 81e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 82e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 83e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 84e3bbff9fSSumant Patro MFI_INIT_ABORT 85c4a3e0a5SBagalkote, Sreenivas 86a69b74d3SRandy Dunlap /* 87c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 88c4a3e0a5SBagalkote, Sreenivas */ 89c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 90c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 91c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 92c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 93c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 94c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 95c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 96c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 97c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 98c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 99c4a3e0a5SBagalkote, Sreenivas 100a69b74d3SRandy Dunlap /* 101c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 102c4a3e0a5SBagalkote, Sreenivas */ 103c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 104c4a3e0a5SBagalkote, Sreenivas 105a69b74d3SRandy Dunlap /* 106c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 107c4a3e0a5SBagalkote, Sreenivas */ 108c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 109c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 110c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 111c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 112c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 113c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 114c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 115c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 116c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 117c4a3e0a5SBagalkote, Sreenivas 118c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 119c4a3e0a5SBagalkote, Sreenivas 120c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 121c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 122c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 123c4a3e0a5SBagalkote, Sreenivas 124c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 12531ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 126c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 127c4a3e0a5SBagalkote, Sreenivas 128c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 129c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 130c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 131c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 132c4a3e0a5SBagalkote, Sreenivas 133c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 134c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 135c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 13681e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 137c4a3e0a5SBagalkote, Sreenivas 138a69b74d3SRandy Dunlap /* 139c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 140c4a3e0a5SBagalkote, Sreenivas */ 141c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 142c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 143c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 144c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 145c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 146c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 147c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 148c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 149c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 150c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 151c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 152c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 153c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 154c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 155c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 156c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 157c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 158c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 159c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 160c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 161c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 162c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 163c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 164c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 165c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 166c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 167c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 168c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 169c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 170c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 171c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 172c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 173c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 174c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 175c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 176c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 177c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 178c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 179c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 180c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 181c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 182c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 183c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 184c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 185c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 186c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 187c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 188c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 189c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 190c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 191c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 192c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 193c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 194c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 195c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 196c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 197c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 198c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 199c4a3e0a5SBagalkote, Sreenivas 200c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 201c4a3e0a5SBagalkote, Sreenivas }; 202c4a3e0a5SBagalkote, Sreenivas 203c4a3e0a5SBagalkote, Sreenivas /* 204c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 205c4a3e0a5SBagalkote, Sreenivas */ 206c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 207c4a3e0a5SBagalkote, Sreenivas 208c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 209c4a3e0a5SBagalkote, Sreenivas 210c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 211c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 212c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 213c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 214c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 215c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 216c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 217c4a3e0a5SBagalkote, Sreenivas 218c4a3e0a5SBagalkote, Sreenivas }; 219c4a3e0a5SBagalkote, Sreenivas 220c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 221c4a3e0a5SBagalkote, Sreenivas 222c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 223c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 224c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 225c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 226c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 227c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 228c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 229c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 230c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 231c4a3e0a5SBagalkote, Sreenivas 232c4a3e0a5SBagalkote, Sreenivas }; 233c4a3e0a5SBagalkote, Sreenivas 234c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 235c4a3e0a5SBagalkote, Sreenivas 236c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 237c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 238c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 239c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 240c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 241c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 242c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 243c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 244c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 245c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 246c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 247c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 248c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 249c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 250c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 251c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 252c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 253c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 254c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 255c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 256c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 25781e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 25881e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 25981e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 26081e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 26181e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 26281e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 26381e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 26481e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 26581e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 26681e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 26781e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 26881e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 26981e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 27081e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 27181e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 27281e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 273c4a3e0a5SBagalkote, Sreenivas }; 274c4a3e0a5SBagalkote, Sreenivas 275c4a3e0a5SBagalkote, Sreenivas /* 27681e403ceSYang, Bo * define constants for device list query options 27781e403ceSYang, Bo */ 27881e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 27981e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 28081e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 28181e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 28281e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 28381e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 28481e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 28581e403ceSYang, Bo }; 28681e403ceSYang, Bo 28781e403ceSYang, Bo enum MR_PD_STATE { 28881e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 28981e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 29081e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 29181e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 29281e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 29381e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 29481e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 29581e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 29681e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 29781e403ceSYang, Bo }; 29881e403ceSYang, Bo 29981e403ceSYang, Bo 30081e403ceSYang, Bo /* 30181e403ceSYang, Bo * defines the physical drive address structure 30281e403ceSYang, Bo */ 30381e403ceSYang, Bo struct MR_PD_ADDRESS { 30481e403ceSYang, Bo u16 deviceId; 30581e403ceSYang, Bo u16 enclDeviceId; 30681e403ceSYang, Bo 30781e403ceSYang, Bo union { 30881e403ceSYang, Bo struct { 30981e403ceSYang, Bo u8 enclIndex; 31081e403ceSYang, Bo u8 slotNumber; 31181e403ceSYang, Bo } mrPdAddress; 31281e403ceSYang, Bo struct { 31381e403ceSYang, Bo u8 enclPosition; 31481e403ceSYang, Bo u8 enclConnectorIndex; 31581e403ceSYang, Bo } mrEnclAddress; 31681e403ceSYang, Bo }; 31781e403ceSYang, Bo u8 scsiDevType; 31881e403ceSYang, Bo union { 31981e403ceSYang, Bo u8 connectedPortBitmap; 32081e403ceSYang, Bo u8 connectedPortNumbers; 32181e403ceSYang, Bo }; 32281e403ceSYang, Bo u64 sasAddr[2]; 32381e403ceSYang, Bo } __packed; 32481e403ceSYang, Bo 32581e403ceSYang, Bo /* 32681e403ceSYang, Bo * defines the physical drive list structure 32781e403ceSYang, Bo */ 32881e403ceSYang, Bo struct MR_PD_LIST { 32981e403ceSYang, Bo u32 size; 33081e403ceSYang, Bo u32 count; 33181e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 33281e403ceSYang, Bo } __packed; 33381e403ceSYang, Bo 33481e403ceSYang, Bo struct megasas_pd_list { 33581e403ceSYang, Bo u16 tid; 33681e403ceSYang, Bo u8 driveType; 33781e403ceSYang, Bo u8 driveState; 33881e403ceSYang, Bo } __packed; 33981e403ceSYang, Bo 34081e403ceSYang, Bo /* 341c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 342c4a3e0a5SBagalkote, Sreenivas */ 343c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 344c4a3e0a5SBagalkote, Sreenivas 345c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 346c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 347c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 348c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 349c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 350c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 351c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 352c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 353c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 354c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 355c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 356c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 357c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 358c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 359c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 360c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 361c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 362c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 363c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 364c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 365c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 366c4a3e0a5SBagalkote, Sreenivas u8 reserved[38]; 367c4a3e0a5SBagalkote, Sreenivas 36881e403ceSYang, Bo } __packed; 369c4a3e0a5SBagalkote, Sreenivas 370c4a3e0a5SBagalkote, Sreenivas /* 371c4a3e0a5SBagalkote, Sreenivas * SAS controller information 372c4a3e0a5SBagalkote, Sreenivas */ 373c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 374c4a3e0a5SBagalkote, Sreenivas 375c4a3e0a5SBagalkote, Sreenivas /* 376c4a3e0a5SBagalkote, Sreenivas * PCI device information 377c4a3e0a5SBagalkote, Sreenivas */ 378c4a3e0a5SBagalkote, Sreenivas struct { 379c4a3e0a5SBagalkote, Sreenivas 380c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 381c4a3e0a5SBagalkote, Sreenivas u16 device_id; 382c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 383c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 384c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 385c4a3e0a5SBagalkote, Sreenivas 386c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 387c4a3e0a5SBagalkote, Sreenivas 388c4a3e0a5SBagalkote, Sreenivas /* 389c4a3e0a5SBagalkote, Sreenivas * Host interface information 390c4a3e0a5SBagalkote, Sreenivas */ 391c4a3e0a5SBagalkote, Sreenivas struct { 392c4a3e0a5SBagalkote, Sreenivas 393c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 394c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 395c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 396c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 397c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 398c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 399c4a3e0a5SBagalkote, Sreenivas u8 port_count; 400c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 401c4a3e0a5SBagalkote, Sreenivas 402c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 403c4a3e0a5SBagalkote, Sreenivas 404c4a3e0a5SBagalkote, Sreenivas /* 405c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 406c4a3e0a5SBagalkote, Sreenivas */ 407c4a3e0a5SBagalkote, Sreenivas struct { 408c4a3e0a5SBagalkote, Sreenivas 409c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 410c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 411c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 412c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 413c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 414c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 415c4a3e0a5SBagalkote, Sreenivas u8 port_count; 416c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 417c4a3e0a5SBagalkote, Sreenivas 418c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 419c4a3e0a5SBagalkote, Sreenivas 420c4a3e0a5SBagalkote, Sreenivas /* 421c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 422c4a3e0a5SBagalkote, Sreenivas */ 423c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 424c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 425c4a3e0a5SBagalkote, Sreenivas 426c4a3e0a5SBagalkote, Sreenivas struct { 427c4a3e0a5SBagalkote, Sreenivas 428c4a3e0a5SBagalkote, Sreenivas char name[8]; 429c4a3e0a5SBagalkote, Sreenivas char version[32]; 430c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 431c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 432c4a3e0a5SBagalkote, Sreenivas 433c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 434c4a3e0a5SBagalkote, Sreenivas 435c4a3e0a5SBagalkote, Sreenivas /* 436c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 437c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 438c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 439c4a3e0a5SBagalkote, Sreenivas * terminated 440c4a3e0a5SBagalkote, Sreenivas */ 441c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 442c4a3e0a5SBagalkote, Sreenivas 443c4a3e0a5SBagalkote, Sreenivas struct { 444c4a3e0a5SBagalkote, Sreenivas 445c4a3e0a5SBagalkote, Sreenivas char name[8]; 446c4a3e0a5SBagalkote, Sreenivas char version[32]; 447c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 448c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 449c4a3e0a5SBagalkote, Sreenivas 450c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 451c4a3e0a5SBagalkote, Sreenivas 452c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 453c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 454c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 455c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 456c4a3e0a5SBagalkote, Sreenivas 457c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 458c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 459c4a3e0a5SBagalkote, Sreenivas 460c4a3e0a5SBagalkote, Sreenivas /* 461c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 462c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 463c4a3e0a5SBagalkote, Sreenivas */ 464c4a3e0a5SBagalkote, Sreenivas struct { 465c4a3e0a5SBagalkote, Sreenivas 466c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 467c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 468c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 469c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 470c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 471c4a3e0a5SBagalkote, Sreenivas 472c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 473c4a3e0a5SBagalkote, Sreenivas 474c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 475c4a3e0a5SBagalkote, Sreenivas 476c4a3e0a5SBagalkote, Sreenivas /* 477c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 478c4a3e0a5SBagalkote, Sreenivas */ 479c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 480c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 481c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 482c4a3e0a5SBagalkote, Sreenivas 483c4a3e0a5SBagalkote, Sreenivas /* 484c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 485c4a3e0a5SBagalkote, Sreenivas */ 486c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 487c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 488c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 489c4a3e0a5SBagalkote, Sreenivas 490c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 491c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 492c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 493c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 494c4a3e0a5SBagalkote, Sreenivas 495c4a3e0a5SBagalkote, Sreenivas /* 496c4a3e0a5SBagalkote, Sreenivas * Memory size information 497c4a3e0a5SBagalkote, Sreenivas */ 498c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 499c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 500c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 501c4a3e0a5SBagalkote, Sreenivas 502c4a3e0a5SBagalkote, Sreenivas /* 503c4a3e0a5SBagalkote, Sreenivas * Error counters 504c4a3e0a5SBagalkote, Sreenivas */ 505c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 506c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 507c4a3e0a5SBagalkote, Sreenivas 508c4a3e0a5SBagalkote, Sreenivas /* 509c4a3e0a5SBagalkote, Sreenivas * Cluster information 510c4a3e0a5SBagalkote, Sreenivas */ 511c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 512c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 513c4a3e0a5SBagalkote, Sreenivas 514c4a3e0a5SBagalkote, Sreenivas /* 515c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 516c4a3e0a5SBagalkote, Sreenivas */ 517c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 518c4a3e0a5SBagalkote, Sreenivas 519c4a3e0a5SBagalkote, Sreenivas /* 520c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 521c4a3e0a5SBagalkote, Sreenivas */ 522c4a3e0a5SBagalkote, Sreenivas struct { 523c4a3e0a5SBagalkote, Sreenivas 524c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 525c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 526c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 527c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 528c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 529c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 530c4a3e0a5SBagalkote, Sreenivas 531c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 532c4a3e0a5SBagalkote, Sreenivas 533c4a3e0a5SBagalkote, Sreenivas struct { 534c4a3e0a5SBagalkote, Sreenivas 535c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 536c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 537c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 538c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 539c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 540c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 541c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 542c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 543c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 544c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 545c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 546c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 547c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 548c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 549c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 550c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 551c4a3e0a5SBagalkote, Sreenivas 552c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 553c4a3e0a5SBagalkote, Sreenivas 554c4a3e0a5SBagalkote, Sreenivas struct { 555c4a3e0a5SBagalkote, Sreenivas 556c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 557c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 558c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 559c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 560c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 561c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 562c4a3e0a5SBagalkote, Sreenivas 563c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 564c4a3e0a5SBagalkote, Sreenivas 565c4a3e0a5SBagalkote, Sreenivas struct { 566c4a3e0a5SBagalkote, Sreenivas 567c4a3e0a5SBagalkote, Sreenivas u8 min; 568c4a3e0a5SBagalkote, Sreenivas u8 max; 569c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 570c4a3e0a5SBagalkote, Sreenivas 571c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 572c4a3e0a5SBagalkote, Sreenivas 573c4a3e0a5SBagalkote, Sreenivas struct { 574c4a3e0a5SBagalkote, Sreenivas 575c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 576c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 577c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 578c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 579c4a3e0a5SBagalkote, Sreenivas 580c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 581c4a3e0a5SBagalkote, Sreenivas 582c4a3e0a5SBagalkote, Sreenivas struct { 583c4a3e0a5SBagalkote, Sreenivas 584c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 585c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 586c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 587c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 588c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 589c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 590c4a3e0a5SBagalkote, Sreenivas 591c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 592c4a3e0a5SBagalkote, Sreenivas 593c4a3e0a5SBagalkote, Sreenivas /* 594c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 595c4a3e0a5SBagalkote, Sreenivas */ 596c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 597c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 598c4a3e0a5SBagalkote, Sreenivas 599c4a3e0a5SBagalkote, Sreenivas /* 600c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 601c4a3e0a5SBagalkote, Sreenivas */ 602c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 603c4a3e0a5SBagalkote, Sreenivas 604c4a3e0a5SBagalkote, Sreenivas /* 605c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 606c4a3e0a5SBagalkote, Sreenivas */ 607c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 608c4a3e0a5SBagalkote, Sreenivas 609c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 610c4a3e0a5SBagalkote, Sreenivas 61181e403ceSYang, Bo } __packed; 612c4a3e0a5SBagalkote, Sreenivas 613c4a3e0a5SBagalkote, Sreenivas /* 614c4a3e0a5SBagalkote, Sreenivas * =============================== 615c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 616c4a3e0a5SBagalkote, Sreenivas * =============================== 617c4a3e0a5SBagalkote, Sreenivas */ 618c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 619c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 620c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 621c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 622c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 623c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 624c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 625c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 62681e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 62781e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 628c4a3e0a5SBagalkote, Sreenivas 629658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 630658dcedbSSumant Patro 63105e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 63205e9ebbeSSumant Patro 633d532dbe2Sbo yang /* Frame Type */ 634d532dbe2Sbo yang #define IO_FRAME 0 635d532dbe2Sbo yang #define PTHRU_FRAME 1 636d532dbe2Sbo yang 637c4a3e0a5SBagalkote, Sreenivas /* 638c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 639c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 640c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 641c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 642c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 643c4a3e0a5SBagalkote, Sreenivas */ 644c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 6452a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 646c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 647c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 64805e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 649c4a3e0a5SBagalkote, Sreenivas 650c4a3e0a5SBagalkote, Sreenivas /* 651c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 652c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 653c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 654c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 655c4a3e0a5SBagalkote, Sreenivas * is shown below 656c4a3e0a5SBagalkote, Sreenivas */ 657c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 658c4a3e0a5SBagalkote, Sreenivas 659c4a3e0a5SBagalkote, Sreenivas /* 660c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 661c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 662c4a3e0a5SBagalkote, Sreenivas */ 663c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 664c4a3e0a5SBagalkote, Sreenivas 665c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 66614faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 667ad84db2eSbo yang #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10) 668c4a3e0a5SBagalkote, Sreenivas 669f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 6706610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 6716610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 67287911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 67387911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 6740e98936cSSumant Patro 6750e98936cSSumant Patro /* 6760e98936cSSumant Patro * register set for both 1068 and 1078 controllers 6770e98936cSSumant Patro * structure extended for 1078 registers 6780e98936cSSumant Patro */ 679c4a3e0a5SBagalkote, Sreenivas 680f9876f0bSSumant Patro struct megasas_register_set { 681c4a3e0a5SBagalkote, Sreenivas u32 reserved_0[4]; /*0000h*/ 682c4a3e0a5SBagalkote, Sreenivas 683c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 684c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 685c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 686c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 687c4a3e0a5SBagalkote, Sreenivas 688c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 689c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 690c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 691c4a3e0a5SBagalkote, Sreenivas 692c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 693c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 694c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 695c4a3e0a5SBagalkote, Sreenivas 696c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 697c4a3e0a5SBagalkote, Sreenivas 698c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 699c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 700c4a3e0a5SBagalkote, Sreenivas 701f9876f0bSSumant Patro u32 reserved_2[22]; /*0048h*/ 702c4a3e0a5SBagalkote, Sreenivas 703f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 704f9876f0bSSumant Patro 705f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 706f9876f0bSSumant Patro 707f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 708f9876f0bSSumant Patro 709f9876f0bSSumant Patro u32 reserved_4[3]; /*00B4h*/ 710f9876f0bSSumant Patro 711f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 712f9876f0bSSumant Patro 713f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 714f9876f0bSSumant Patro 715f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 716f9876f0bSSumant Patro u32 index_registers[820]; /*00CCh*/ 717c4a3e0a5SBagalkote, Sreenivas 718c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 719c4a3e0a5SBagalkote, Sreenivas 720c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 721c4a3e0a5SBagalkote, Sreenivas 722c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 723c4a3e0a5SBagalkote, Sreenivas u32 length; 724c4a3e0a5SBagalkote, Sreenivas 725c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 726c4a3e0a5SBagalkote, Sreenivas 727c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 728c4a3e0a5SBagalkote, Sreenivas 729c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 730c4a3e0a5SBagalkote, Sreenivas u32 length; 731c4a3e0a5SBagalkote, Sreenivas 732c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 733c4a3e0a5SBagalkote, Sreenivas 734c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 735c4a3e0a5SBagalkote, Sreenivas 736c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 737c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 738c4a3e0a5SBagalkote, Sreenivas 739c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 740c4a3e0a5SBagalkote, Sreenivas 741c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 742c4a3e0a5SBagalkote, Sreenivas 743c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 744c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 745c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 746c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 747c4a3e0a5SBagalkote, Sreenivas 748c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 749c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 750c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 751c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 752c4a3e0a5SBagalkote, Sreenivas 753c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 754c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 755c4a3e0a5SBagalkote, Sreenivas 756c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 757c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 758c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 759c4a3e0a5SBagalkote, Sreenivas 760c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 761c4a3e0a5SBagalkote, Sreenivas 762c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 763c4a3e0a5SBagalkote, Sreenivas 764c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 765c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 766c4a3e0a5SBagalkote, Sreenivas 767c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 768c4a3e0a5SBagalkote, Sreenivas 769c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 770c4a3e0a5SBagalkote, Sreenivas 771c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 772c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 773c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 774c4a3e0a5SBagalkote, Sreenivas 775c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 776c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 777c4a3e0a5SBagalkote, Sreenivas 778c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 779c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 780c4a3e0a5SBagalkote, Sreenivas 781c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 782c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 783c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 784c4a3e0a5SBagalkote, Sreenivas 785c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 786c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 787c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 788c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 789c4a3e0a5SBagalkote, Sreenivas 790c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 791c4a3e0a5SBagalkote, Sreenivas 792c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 793c4a3e0a5SBagalkote, Sreenivas 794c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 795c4a3e0a5SBagalkote, Sreenivas 796c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 797c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 798c4a3e0a5SBagalkote, Sreenivas 799c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 800c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 801c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 802c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 803c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 804c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 805c4a3e0a5SBagalkote, Sreenivas 806c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 807c4a3e0a5SBagalkote, Sreenivas 808c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 809c4a3e0a5SBagalkote, Sreenivas 810c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 811c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 812c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 813c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 814c4a3e0a5SBagalkote, Sreenivas 815c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 816c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 817c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 818c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 819c4a3e0a5SBagalkote, Sreenivas 820c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 821c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 822c4a3e0a5SBagalkote, Sreenivas 823c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 824c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 825c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 826c4a3e0a5SBagalkote, Sreenivas 827c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 828c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 829c4a3e0a5SBagalkote, Sreenivas 830c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 831c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 832c4a3e0a5SBagalkote, Sreenivas 833c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 834c4a3e0a5SBagalkote, Sreenivas 835c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 836c4a3e0a5SBagalkote, Sreenivas 837c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 838c4a3e0a5SBagalkote, Sreenivas 839c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 840c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 841c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 842c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 843c4a3e0a5SBagalkote, Sreenivas 844c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 845c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 846c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 847c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 848c4a3e0a5SBagalkote, Sreenivas 849c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 850c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 851c4a3e0a5SBagalkote, Sreenivas 852c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 853c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 854c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 855c4a3e0a5SBagalkote, Sreenivas 856c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 857c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 858c4a3e0a5SBagalkote, Sreenivas 859c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 860c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 861c4a3e0a5SBagalkote, Sreenivas 862c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 863c4a3e0a5SBagalkote, Sreenivas 864c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 865c4a3e0a5SBagalkote, Sreenivas 866c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 867c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 868c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 869c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 870c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 871c4a3e0a5SBagalkote, Sreenivas 872c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 873c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 874c4a3e0a5SBagalkote, Sreenivas 875c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 876c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 877c4a3e0a5SBagalkote, Sreenivas 878c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 879c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 880c4a3e0a5SBagalkote, Sreenivas 881c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 882c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 883c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 884c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 885c4a3e0a5SBagalkote, Sreenivas } mbox; 886c4a3e0a5SBagalkote, Sreenivas 887c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 888c4a3e0a5SBagalkote, Sreenivas 889c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 890c4a3e0a5SBagalkote, Sreenivas 891c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 892c4a3e0a5SBagalkote, Sreenivas 893c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 894c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 895c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 896c4a3e0a5SBagalkote, Sreenivas 897c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 898c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 899c4a3e0a5SBagalkote, Sreenivas 900c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 901c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 902c4a3e0a5SBagalkote, Sreenivas 903c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 904c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 905c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 906c4a3e0a5SBagalkote, Sreenivas 907c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 908c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 909c4a3e0a5SBagalkote, Sreenivas 910c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 911c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 912c4a3e0a5SBagalkote, Sreenivas 913c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 914c4a3e0a5SBagalkote, Sreenivas 915c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 916c4a3e0a5SBagalkote, Sreenivas 917c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 918c4a3e0a5SBagalkote, Sreenivas 919c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 920c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 921c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 922c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 923c4a3e0a5SBagalkote, Sreenivas 924c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 925c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 926c4a3e0a5SBagalkote, Sreenivas 927c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 928c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 929c4a3e0a5SBagalkote, Sreenivas 930c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 931c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 932c4a3e0a5SBagalkote, Sreenivas 933c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 934c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 935c4a3e0a5SBagalkote, Sreenivas 936c4a3e0a5SBagalkote, Sreenivas union { 937c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 938c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 939c4a3e0a5SBagalkote, Sreenivas } sgl; 940c4a3e0a5SBagalkote, Sreenivas 941c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 942c4a3e0a5SBagalkote, Sreenivas 943c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 944c4a3e0a5SBagalkote, Sreenivas 945c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 946c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 947c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 948c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 949c4a3e0a5SBagalkote, Sreenivas 950c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 951c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 952c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 953c4a3e0a5SBagalkote, Sreenivas 954c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 955c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 956c4a3e0a5SBagalkote, Sreenivas 957c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 958c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 959c4a3e0a5SBagalkote, Sreenivas 960c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 961c4a3e0a5SBagalkote, Sreenivas 962c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 963c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 964c4a3e0a5SBagalkote, Sreenivas 965c4a3e0a5SBagalkote, Sreenivas union { 966c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 967c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 968c4a3e0a5SBagalkote, Sreenivas } sgl; 969c4a3e0a5SBagalkote, Sreenivas 970c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 971c4a3e0a5SBagalkote, Sreenivas 972c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 973c4a3e0a5SBagalkote, Sreenivas 974c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 975c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 976c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 977c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 978c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 979c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 980c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 981c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 982c4a3e0a5SBagalkote, Sreenivas 983c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 984c4a3e0a5SBagalkote, Sreenivas }; 985c4a3e0a5SBagalkote, Sreenivas 986c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 987c4a3e0a5SBagalkote, Sreenivas 988c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 989c4a3e0a5SBagalkote, Sreenivas 990c4a3e0a5SBagalkote, Sreenivas struct { 991c4a3e0a5SBagalkote, Sreenivas u16 locale; 992c4a3e0a5SBagalkote, Sreenivas u8 reserved; 993c4a3e0a5SBagalkote, Sreenivas s8 class; 994c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 995c4a3e0a5SBagalkote, Sreenivas 996c4a3e0a5SBagalkote, Sreenivas u32 word; 997c4a3e0a5SBagalkote, Sreenivas 998c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 999c4a3e0a5SBagalkote, Sreenivas 1000c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 1001c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 1002c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 1003c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 1004c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 1005c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 1006c4a3e0a5SBagalkote, Sreenivas 1007c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1008c4a3e0a5SBagalkote, Sreenivas 1009c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1010c4a3e0a5SBagalkote, Sreenivas 1011c4a3e0a5SBagalkote, Sreenivas u16 progress; 1012c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 1013c4a3e0a5SBagalkote, Sreenivas 1014c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1015c4a3e0a5SBagalkote, Sreenivas 1016c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1017c4a3e0a5SBagalkote, Sreenivas 1018c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1019c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1020c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1021c4a3e0a5SBagalkote, Sreenivas 1022c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1023c4a3e0a5SBagalkote, Sreenivas 1024c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1025c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1026c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1027c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1028c4a3e0a5SBagalkote, Sreenivas 1029c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1030c4a3e0a5SBagalkote, Sreenivas 1031c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1032c4a3e0a5SBagalkote, Sreenivas 1033c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1034c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 1035c4a3e0a5SBagalkote, Sreenivas u32 code; 1036c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1037c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1038c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1039c4a3e0a5SBagalkote, Sreenivas 1040c4a3e0a5SBagalkote, Sreenivas union { 1041c4a3e0a5SBagalkote, Sreenivas struct { 1042c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1043c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1044c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1045c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1046c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1047c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1048c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1049c4a3e0a5SBagalkote, Sreenivas 1050c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1051c4a3e0a5SBagalkote, Sreenivas 1052c4a3e0a5SBagalkote, Sreenivas struct { 1053c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1054c4a3e0a5SBagalkote, Sreenivas u64 count; 1055c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1056c4a3e0a5SBagalkote, Sreenivas 1057c4a3e0a5SBagalkote, Sreenivas struct { 1058c4a3e0a5SBagalkote, Sreenivas u64 lba; 1059c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1060c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1061c4a3e0a5SBagalkote, Sreenivas 1062c4a3e0a5SBagalkote, Sreenivas struct { 1063c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1064c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 1065c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 1066c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1067c4a3e0a5SBagalkote, Sreenivas 1068c4a3e0a5SBagalkote, Sreenivas struct { 1069c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1070c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1071c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1072c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1073c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1074c4a3e0a5SBagalkote, Sreenivas 1075c4a3e0a5SBagalkote, Sreenivas struct { 1076c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1077c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1078c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1079c4a3e0a5SBagalkote, Sreenivas 1080c4a3e0a5SBagalkote, Sreenivas struct { 1081c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1082c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1083c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1084c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1085c4a3e0a5SBagalkote, Sreenivas 1086c4a3e0a5SBagalkote, Sreenivas struct { 1087c4a3e0a5SBagalkote, Sreenivas u64 strip; 1088c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1089c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1090c4a3e0a5SBagalkote, Sreenivas 1091c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1092c4a3e0a5SBagalkote, Sreenivas 1093c4a3e0a5SBagalkote, Sreenivas struct { 1094c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1095c4a3e0a5SBagalkote, Sreenivas u32 err; 1096c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1097c4a3e0a5SBagalkote, Sreenivas 1098c4a3e0a5SBagalkote, Sreenivas struct { 1099c4a3e0a5SBagalkote, Sreenivas u64 lba; 1100c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1101c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1102c4a3e0a5SBagalkote, Sreenivas 1103c4a3e0a5SBagalkote, Sreenivas struct { 1104c4a3e0a5SBagalkote, Sreenivas u64 lba; 1105c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1106c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1107c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1108c4a3e0a5SBagalkote, Sreenivas 1109c4a3e0a5SBagalkote, Sreenivas struct { 1110c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1111c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1112c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1113c4a3e0a5SBagalkote, Sreenivas 1114c4a3e0a5SBagalkote, Sreenivas struct { 1115c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1116c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1117c4a3e0a5SBagalkote, Sreenivas u32 newState; 1118c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1119c4a3e0a5SBagalkote, Sreenivas 1120c4a3e0a5SBagalkote, Sreenivas struct { 1121c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1122c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1123c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1124c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1125c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1126c4a3e0a5SBagalkote, Sreenivas 1127c4a3e0a5SBagalkote, Sreenivas u32 rate; 1128c4a3e0a5SBagalkote, Sreenivas char str[96]; 1129c4a3e0a5SBagalkote, Sreenivas 1130c4a3e0a5SBagalkote, Sreenivas struct { 1131c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1132c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1133c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1134c4a3e0a5SBagalkote, Sreenivas 1135c4a3e0a5SBagalkote, Sreenivas struct { 1136c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1137c4a3e0a5SBagalkote, Sreenivas u32 elog; 1138c4a3e0a5SBagalkote, Sreenivas char str[64]; 1139c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1140c4a3e0a5SBagalkote, Sreenivas 1141c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1142c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1143c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1144c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1145c4a3e0a5SBagalkote, Sreenivas } args; 1146c4a3e0a5SBagalkote, Sreenivas 1147c4a3e0a5SBagalkote, Sreenivas char description[128]; 1148c4a3e0a5SBagalkote, Sreenivas 1149c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1150c4a3e0a5SBagalkote, Sreenivas 11511341c939SSumant Patro struct megasas_instance_template { 11521341c939SSumant Patro void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *); 11531341c939SSumant Patro 11541341c939SSumant Patro void (*enable_intr)(struct megasas_register_set __iomem *) ; 1155b274cab7SSumant Patro void (*disable_intr)(struct megasas_register_set __iomem *); 11561341c939SSumant Patro 11571341c939SSumant Patro int (*clear_intr)(struct megasas_register_set __iomem *); 11581341c939SSumant Patro 11591341c939SSumant Patro u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 11601341c939SSumant Patro }; 11611341c939SSumant Patro 1162c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1163c4a3e0a5SBagalkote, Sreenivas 1164c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1165c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1166c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1167c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1168c4a3e0a5SBagalkote, Sreenivas 1169c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1170c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1171c4a3e0a5SBagalkote, Sreenivas 1172c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1173c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1174c4a3e0a5SBagalkote, Sreenivas 117581e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1176c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1177c4a3e0a5SBagalkote, Sreenivas 1178c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1179c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 1180c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 1181c4a3e0a5SBagalkote, Sreenivas 1182c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1183c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 1184c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 11857343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 11867343eb65Sbo yang spinlock_t completion_lock; 1187c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1188c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1189c4a3e0a5SBagalkote, Sreenivas 1190c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1191c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1192c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1193e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1194c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1195c4a3e0a5SBagalkote, Sreenivas 1196c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1197c4a3e0a5SBagalkote, Sreenivas 1198c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1199c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1200c4a3e0a5SBagalkote, Sreenivas 1201c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1202c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 1203c4a3e0a5SBagalkote, Sreenivas 1204e4a082c7SSumant Patro atomic_t fw_outstanding; 1205c4a3e0a5SBagalkote, Sreenivas u32 hw_crit_error; 12061341c939SSumant Patro 12071341c939SSumant Patro struct megasas_instance_template *instancet; 12085d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 120905e9ebbeSSumant Patro 121005e9ebbeSSumant Patro u8 flag; 1211c3518837SYang, Bo u8 unload; 121205e9ebbeSSumant Patro unsigned long last_time; 1213ad84db2eSbo yang 1214ad84db2eSbo yang struct timer_list io_completion_timer; 1215c4a3e0a5SBagalkote, Sreenivas }; 1216c4a3e0a5SBagalkote, Sreenivas 1217c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1218c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1219c4a3e0a5SBagalkote, Sreenivas 1220c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1221c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1222c4a3e0a5SBagalkote, Sreenivas scp->device->id 1223c4a3e0a5SBagalkote, Sreenivas 1224c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1225c4a3e0a5SBagalkote, Sreenivas 1226c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1227c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1228c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1229c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1230c4a3e0a5SBagalkote, Sreenivas 1231c4a3e0a5SBagalkote, Sreenivas u32 index; 1232c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1233c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 1234c4a3e0a5SBagalkote, Sreenivas u16 abort_aen; 1235c4a3e0a5SBagalkote, Sreenivas 1236c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1237c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1238c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 1239c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1240c4a3e0a5SBagalkote, Sreenivas }; 1241c4a3e0a5SBagalkote, Sreenivas 1242c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1243c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1244c4a3e0a5SBagalkote, Sreenivas 1245c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1246c4a3e0a5SBagalkote, Sreenivas 1247c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1248c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1249c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1250c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1251c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1252c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1253c4a3e0a5SBagalkote, Sreenivas union { 1254c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1255c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1256c4a3e0a5SBagalkote, Sreenivas } frame; 1257c4a3e0a5SBagalkote, Sreenivas 1258c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1259c4a3e0a5SBagalkote, Sreenivas 1260c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1261c4a3e0a5SBagalkote, Sreenivas 1262c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1263c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1264c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1265c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1266c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1267c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1268c4a3e0a5SBagalkote, Sreenivas 1269c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1270c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1271c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1272c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1273c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1274c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1275c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1276c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1277c4a3e0a5SBagalkote, Sreenivas union { 1278c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1279c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1280c4a3e0a5SBagalkote, Sreenivas } frame; 1281c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1282c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1283c4a3e0a5SBagalkote, Sreenivas 12840e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1285c4a3e0a5SBagalkote, Sreenivas #endif 1286c4a3e0a5SBagalkote, Sreenivas 1287cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1288c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1289c4a3e0a5SBagalkote, Sreenivas 1290c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1291c4a3e0a5SBagalkote, Sreenivas 1292c4a3e0a5SBagalkote, Sreenivas u16 count; 1293c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1294c4a3e0a5SBagalkote, Sreenivas int max_index; 1295c4a3e0a5SBagalkote, Sreenivas }; 1296c4a3e0a5SBagalkote, Sreenivas 1297c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1298