1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * 3c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 4c4a3e0a5SBagalkote, Sreenivas * 5c4a3e0a5SBagalkote, Sreenivas * Copyright (c) 2003-2005 LSI Logic Corporation. 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 9c4a3e0a5SBagalkote, Sreenivas * as published by the Free Software Foundation; either version 10c4a3e0a5SBagalkote, Sreenivas * 2 of the License, or (at your option) any later version. 11c4a3e0a5SBagalkote, Sreenivas * 12c4a3e0a5SBagalkote, Sreenivas * FILE : megaraid_sas.h 13c4a3e0a5SBagalkote, Sreenivas */ 14c4a3e0a5SBagalkote, Sreenivas 15c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 16c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 17c4a3e0a5SBagalkote, Sreenivas 18a69b74d3SRandy Dunlap /* 19c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 20c4a3e0a5SBagalkote, Sreenivas */ 2105e9ebbeSSumant Patro #define MEGASAS_VERSION "00.00.03.10-rc5" 2205e9ebbeSSumant Patro #define MEGASAS_RELDATE "May 17, 2007" 2305e9ebbeSSumant Patro #define MEGASAS_EXT_VERSION "Thu May 17 10:09:32 PDT 2007" 240e98936cSSumant Patro 250e98936cSSumant Patro /* 260e98936cSSumant Patro * Device IDs 270e98936cSSumant Patro */ 280e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 290e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 300e98936cSSumant Patro 31c4a3e0a5SBagalkote, Sreenivas /* 32c4a3e0a5SBagalkote, Sreenivas * ===================================== 33c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 34c4a3e0a5SBagalkote, Sreenivas * ===================================== 35c4a3e0a5SBagalkote, Sreenivas */ 36c4a3e0a5SBagalkote, Sreenivas 37c4a3e0a5SBagalkote, Sreenivas /* 38c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 39c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 40c4a3e0a5SBagalkote, Sreenivas * "message frames" 41c4a3e0a5SBagalkote, Sreenivas */ 42c4a3e0a5SBagalkote, Sreenivas 43a69b74d3SRandy Dunlap /* 44c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 45c4a3e0a5SBagalkote, Sreenivas */ 46c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 47c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 48c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 49c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 50c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 51c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 52c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 53e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 54c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 55c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 56c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 57c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 58c4a3e0a5SBagalkote, Sreenivas 59c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 60c4a3e0a5SBagalkote, Sreenivas 61a69b74d3SRandy Dunlap /* 62c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 63c4a3e0a5SBagalkote, Sreenivas * 64c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 65c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 66c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 67c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 68e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 69e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 70c4a3e0a5SBagalkote, Sreenivas */ 71e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 72c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 73c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 74c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 75e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 76e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 77e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 78e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 79e3bbff9fSSumant Patro MFI_INIT_ABORT 80c4a3e0a5SBagalkote, Sreenivas 81a69b74d3SRandy Dunlap /* 82c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 83c4a3e0a5SBagalkote, Sreenivas */ 84c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 85c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 86c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 87c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 88c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 89c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 90c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 91c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 92c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 93c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 94c4a3e0a5SBagalkote, Sreenivas 95a69b74d3SRandy Dunlap /* 96c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 97c4a3e0a5SBagalkote, Sreenivas */ 98c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 99c4a3e0a5SBagalkote, Sreenivas 100a69b74d3SRandy Dunlap /* 101c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 102c4a3e0a5SBagalkote, Sreenivas */ 103c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 104c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 105c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 106c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 107c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 108c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 109c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 110c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 111c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 112c4a3e0a5SBagalkote, Sreenivas 113c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 114c4a3e0a5SBagalkote, Sreenivas 115c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 116c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 117c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 118c4a3e0a5SBagalkote, Sreenivas 119c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 12031ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 121c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 122c4a3e0a5SBagalkote, Sreenivas 123c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 124c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 125c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 126c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 127c4a3e0a5SBagalkote, Sreenivas 128c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 129c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 130c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 131c4a3e0a5SBagalkote, Sreenivas 132a69b74d3SRandy Dunlap /* 133c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 134c4a3e0a5SBagalkote, Sreenivas */ 135c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 136c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 137c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 138c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 139c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 140c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 141c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 142c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 143c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 144c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 145c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 146c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 147c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 148c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 149c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 150c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 151c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 152c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 153c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 154c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 155c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 156c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 157c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 158c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 159c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 160c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 161c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 162c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 163c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 164c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 165c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 166c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 167c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 168c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 169c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 170c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 171c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 172c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 173c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 174c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 175c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 176c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 177c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 178c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 179c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 180c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 181c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 182c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 183c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 184c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 185c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 186c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 187c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 188c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 189c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 190c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 191c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 192c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 193c4a3e0a5SBagalkote, Sreenivas 194c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 195c4a3e0a5SBagalkote, Sreenivas }; 196c4a3e0a5SBagalkote, Sreenivas 197c4a3e0a5SBagalkote, Sreenivas /* 198c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 199c4a3e0a5SBagalkote, Sreenivas */ 200c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 201c4a3e0a5SBagalkote, Sreenivas 202c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 203c4a3e0a5SBagalkote, Sreenivas 204c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 205c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 206c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 207c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 208c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 209c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 210c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 211c4a3e0a5SBagalkote, Sreenivas 212c4a3e0a5SBagalkote, Sreenivas }; 213c4a3e0a5SBagalkote, Sreenivas 214c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 215c4a3e0a5SBagalkote, Sreenivas 216c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 217c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 218c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 219c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 220c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 221c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 222c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 223c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 224c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 225c4a3e0a5SBagalkote, Sreenivas 226c4a3e0a5SBagalkote, Sreenivas }; 227c4a3e0a5SBagalkote, Sreenivas 228c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 229c4a3e0a5SBagalkote, Sreenivas 230c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 231c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 232c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 233c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 234c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 235c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 236c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 237c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 238c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 239c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 240c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 241c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 242c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 243c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 244c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 245c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 246c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 247c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 248c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 249c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 250c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 251c4a3e0a5SBagalkote, Sreenivas 252c4a3e0a5SBagalkote, Sreenivas }; 253c4a3e0a5SBagalkote, Sreenivas 254c4a3e0a5SBagalkote, Sreenivas /* 255c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 256c4a3e0a5SBagalkote, Sreenivas */ 257c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 258c4a3e0a5SBagalkote, Sreenivas 259c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 260c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 261c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 262c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 263c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 264c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 265c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 266c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 267c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 268c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 269c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 270c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 271c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 272c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 273c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 274c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 275c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 276c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 277c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 278c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 279c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 280c4a3e0a5SBagalkote, Sreenivas u8 reserved[38]; 281c4a3e0a5SBagalkote, Sreenivas 282c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 283c4a3e0a5SBagalkote, Sreenivas 284c4a3e0a5SBagalkote, Sreenivas /* 285c4a3e0a5SBagalkote, Sreenivas * SAS controller information 286c4a3e0a5SBagalkote, Sreenivas */ 287c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 288c4a3e0a5SBagalkote, Sreenivas 289c4a3e0a5SBagalkote, Sreenivas /* 290c4a3e0a5SBagalkote, Sreenivas * PCI device information 291c4a3e0a5SBagalkote, Sreenivas */ 292c4a3e0a5SBagalkote, Sreenivas struct { 293c4a3e0a5SBagalkote, Sreenivas 294c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 295c4a3e0a5SBagalkote, Sreenivas u16 device_id; 296c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 297c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 298c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 299c4a3e0a5SBagalkote, Sreenivas 300c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 301c4a3e0a5SBagalkote, Sreenivas 302c4a3e0a5SBagalkote, Sreenivas /* 303c4a3e0a5SBagalkote, Sreenivas * Host interface information 304c4a3e0a5SBagalkote, Sreenivas */ 305c4a3e0a5SBagalkote, Sreenivas struct { 306c4a3e0a5SBagalkote, Sreenivas 307c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 308c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 309c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 310c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 311c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 312c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 313c4a3e0a5SBagalkote, Sreenivas u8 port_count; 314c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 315c4a3e0a5SBagalkote, Sreenivas 316c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 317c4a3e0a5SBagalkote, Sreenivas 318c4a3e0a5SBagalkote, Sreenivas /* 319c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 320c4a3e0a5SBagalkote, Sreenivas */ 321c4a3e0a5SBagalkote, Sreenivas struct { 322c4a3e0a5SBagalkote, Sreenivas 323c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 324c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 325c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 326c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 327c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 328c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 329c4a3e0a5SBagalkote, Sreenivas u8 port_count; 330c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 331c4a3e0a5SBagalkote, Sreenivas 332c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 333c4a3e0a5SBagalkote, Sreenivas 334c4a3e0a5SBagalkote, Sreenivas /* 335c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 336c4a3e0a5SBagalkote, Sreenivas */ 337c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 338c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 339c4a3e0a5SBagalkote, Sreenivas 340c4a3e0a5SBagalkote, Sreenivas struct { 341c4a3e0a5SBagalkote, Sreenivas 342c4a3e0a5SBagalkote, Sreenivas char name[8]; 343c4a3e0a5SBagalkote, Sreenivas char version[32]; 344c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 345c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 346c4a3e0a5SBagalkote, Sreenivas 347c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 348c4a3e0a5SBagalkote, Sreenivas 349c4a3e0a5SBagalkote, Sreenivas /* 350c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 351c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 352c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 353c4a3e0a5SBagalkote, Sreenivas * terminated 354c4a3e0a5SBagalkote, Sreenivas */ 355c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 356c4a3e0a5SBagalkote, Sreenivas 357c4a3e0a5SBagalkote, Sreenivas struct { 358c4a3e0a5SBagalkote, Sreenivas 359c4a3e0a5SBagalkote, Sreenivas char name[8]; 360c4a3e0a5SBagalkote, Sreenivas char version[32]; 361c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 362c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 363c4a3e0a5SBagalkote, Sreenivas 364c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 365c4a3e0a5SBagalkote, Sreenivas 366c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 367c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 368c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 369c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 370c4a3e0a5SBagalkote, Sreenivas 371c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 372c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 373c4a3e0a5SBagalkote, Sreenivas 374c4a3e0a5SBagalkote, Sreenivas /* 375c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 376c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 377c4a3e0a5SBagalkote, Sreenivas */ 378c4a3e0a5SBagalkote, Sreenivas struct { 379c4a3e0a5SBagalkote, Sreenivas 380c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 381c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 382c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 383c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 384c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 385c4a3e0a5SBagalkote, Sreenivas 386c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 387c4a3e0a5SBagalkote, Sreenivas 388c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 389c4a3e0a5SBagalkote, Sreenivas 390c4a3e0a5SBagalkote, Sreenivas /* 391c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 392c4a3e0a5SBagalkote, Sreenivas */ 393c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 394c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 395c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 396c4a3e0a5SBagalkote, Sreenivas 397c4a3e0a5SBagalkote, Sreenivas /* 398c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 399c4a3e0a5SBagalkote, Sreenivas */ 400c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 401c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 402c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 403c4a3e0a5SBagalkote, Sreenivas 404c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 405c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 406c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 407c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 408c4a3e0a5SBagalkote, Sreenivas 409c4a3e0a5SBagalkote, Sreenivas /* 410c4a3e0a5SBagalkote, Sreenivas * Memory size information 411c4a3e0a5SBagalkote, Sreenivas */ 412c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 413c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 414c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 415c4a3e0a5SBagalkote, Sreenivas 416c4a3e0a5SBagalkote, Sreenivas /* 417c4a3e0a5SBagalkote, Sreenivas * Error counters 418c4a3e0a5SBagalkote, Sreenivas */ 419c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 420c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 421c4a3e0a5SBagalkote, Sreenivas 422c4a3e0a5SBagalkote, Sreenivas /* 423c4a3e0a5SBagalkote, Sreenivas * Cluster information 424c4a3e0a5SBagalkote, Sreenivas */ 425c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 426c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 427c4a3e0a5SBagalkote, Sreenivas 428c4a3e0a5SBagalkote, Sreenivas /* 429c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 430c4a3e0a5SBagalkote, Sreenivas */ 431c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 432c4a3e0a5SBagalkote, Sreenivas 433c4a3e0a5SBagalkote, Sreenivas /* 434c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 435c4a3e0a5SBagalkote, Sreenivas */ 436c4a3e0a5SBagalkote, Sreenivas struct { 437c4a3e0a5SBagalkote, Sreenivas 438c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 439c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 440c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 441c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 442c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 443c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 444c4a3e0a5SBagalkote, Sreenivas 445c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 446c4a3e0a5SBagalkote, Sreenivas 447c4a3e0a5SBagalkote, Sreenivas struct { 448c4a3e0a5SBagalkote, Sreenivas 449c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 450c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 451c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 452c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 453c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 454c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 455c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 456c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 457c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 458c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 459c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 460c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 461c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 462c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 463c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 464c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 465c4a3e0a5SBagalkote, Sreenivas 466c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 467c4a3e0a5SBagalkote, Sreenivas 468c4a3e0a5SBagalkote, Sreenivas struct { 469c4a3e0a5SBagalkote, Sreenivas 470c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 471c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 472c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 473c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 474c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 475c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 476c4a3e0a5SBagalkote, Sreenivas 477c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 478c4a3e0a5SBagalkote, Sreenivas 479c4a3e0a5SBagalkote, Sreenivas struct { 480c4a3e0a5SBagalkote, Sreenivas 481c4a3e0a5SBagalkote, Sreenivas u8 min; 482c4a3e0a5SBagalkote, Sreenivas u8 max; 483c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 484c4a3e0a5SBagalkote, Sreenivas 485c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 486c4a3e0a5SBagalkote, Sreenivas 487c4a3e0a5SBagalkote, Sreenivas struct { 488c4a3e0a5SBagalkote, Sreenivas 489c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 490c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 491c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 492c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 493c4a3e0a5SBagalkote, Sreenivas 494c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 495c4a3e0a5SBagalkote, Sreenivas 496c4a3e0a5SBagalkote, Sreenivas struct { 497c4a3e0a5SBagalkote, Sreenivas 498c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 499c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 500c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 501c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 502c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 503c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 504c4a3e0a5SBagalkote, Sreenivas 505c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 506c4a3e0a5SBagalkote, Sreenivas 507c4a3e0a5SBagalkote, Sreenivas /* 508c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 509c4a3e0a5SBagalkote, Sreenivas */ 510c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 511c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 512c4a3e0a5SBagalkote, Sreenivas 513c4a3e0a5SBagalkote, Sreenivas /* 514c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 515c4a3e0a5SBagalkote, Sreenivas */ 516c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 517c4a3e0a5SBagalkote, Sreenivas 518c4a3e0a5SBagalkote, Sreenivas /* 519c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 520c4a3e0a5SBagalkote, Sreenivas */ 521c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 522c4a3e0a5SBagalkote, Sreenivas 523c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 524c4a3e0a5SBagalkote, Sreenivas 525c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 526c4a3e0a5SBagalkote, Sreenivas 527c4a3e0a5SBagalkote, Sreenivas /* 528c4a3e0a5SBagalkote, Sreenivas * =============================== 529c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 530c4a3e0a5SBagalkote, Sreenivas * =============================== 531c4a3e0a5SBagalkote, Sreenivas */ 532c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 533c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 534c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 535c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 536c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 537c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 538c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 539c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 540c4a3e0a5SBagalkote, Sreenivas 541658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 542658dcedbSSumant Patro 54305e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 54405e9ebbeSSumant Patro 545c4a3e0a5SBagalkote, Sreenivas /* 546c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 547c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 548c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 549c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 550c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 551c4a3e0a5SBagalkote, Sreenivas */ 552c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 5532a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 554c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 555c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 55605e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 557c4a3e0a5SBagalkote, Sreenivas 558c4a3e0a5SBagalkote, Sreenivas /* 559c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 560c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 561c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 562c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 563c4a3e0a5SBagalkote, Sreenivas * is shown below 564c4a3e0a5SBagalkote, Sreenivas */ 565c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 566c4a3e0a5SBagalkote, Sreenivas 567c4a3e0a5SBagalkote, Sreenivas /* 568c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 569c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 570c4a3e0a5SBagalkote, Sreenivas */ 571c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 572c4a3e0a5SBagalkote, Sreenivas 573c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 57414faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 575c4a3e0a5SBagalkote, Sreenivas 576f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 5770e98936cSSumant Patro 5780e98936cSSumant Patro /* 5790e98936cSSumant Patro * register set for both 1068 and 1078 controllers 5800e98936cSSumant Patro * structure extended for 1078 registers 5810e98936cSSumant Patro */ 582c4a3e0a5SBagalkote, Sreenivas 583f9876f0bSSumant Patro struct megasas_register_set { 584c4a3e0a5SBagalkote, Sreenivas u32 reserved_0[4]; /*0000h*/ 585c4a3e0a5SBagalkote, Sreenivas 586c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 587c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 588c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 589c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 590c4a3e0a5SBagalkote, Sreenivas 591c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 592c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 593c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 594c4a3e0a5SBagalkote, Sreenivas 595c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 596c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 597c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 598c4a3e0a5SBagalkote, Sreenivas 599c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 600c4a3e0a5SBagalkote, Sreenivas 601c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 602c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 603c4a3e0a5SBagalkote, Sreenivas 604f9876f0bSSumant Patro u32 reserved_2[22]; /*0048h*/ 605c4a3e0a5SBagalkote, Sreenivas 606f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 607f9876f0bSSumant Patro 608f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 609f9876f0bSSumant Patro 610f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 611f9876f0bSSumant Patro 612f9876f0bSSumant Patro u32 reserved_4[3]; /*00B4h*/ 613f9876f0bSSumant Patro 614f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 615f9876f0bSSumant Patro 616f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 617f9876f0bSSumant Patro 618f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 619f9876f0bSSumant Patro u32 index_registers[820]; /*00CCh*/ 620c4a3e0a5SBagalkote, Sreenivas 621c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 622c4a3e0a5SBagalkote, Sreenivas 623c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 624c4a3e0a5SBagalkote, Sreenivas 625c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 626c4a3e0a5SBagalkote, Sreenivas u32 length; 627c4a3e0a5SBagalkote, Sreenivas 628c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 629c4a3e0a5SBagalkote, Sreenivas 630c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 631c4a3e0a5SBagalkote, Sreenivas 632c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 633c4a3e0a5SBagalkote, Sreenivas u32 length; 634c4a3e0a5SBagalkote, Sreenivas 635c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 636c4a3e0a5SBagalkote, Sreenivas 637c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 638c4a3e0a5SBagalkote, Sreenivas 639c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 640c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 641c4a3e0a5SBagalkote, Sreenivas 642c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 643c4a3e0a5SBagalkote, Sreenivas 644c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 645c4a3e0a5SBagalkote, Sreenivas 646c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 647c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 648c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 649c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 650c4a3e0a5SBagalkote, Sreenivas 651c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 652c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 653c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 654c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 655c4a3e0a5SBagalkote, Sreenivas 656c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 657c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 658c4a3e0a5SBagalkote, Sreenivas 659c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 660c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 661c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 662c4a3e0a5SBagalkote, Sreenivas 663c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 664c4a3e0a5SBagalkote, Sreenivas 665c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 666c4a3e0a5SBagalkote, Sreenivas 667c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 668c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 669c4a3e0a5SBagalkote, Sreenivas 670c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 671c4a3e0a5SBagalkote, Sreenivas 672c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 673c4a3e0a5SBagalkote, Sreenivas 674c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 675c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 676c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 677c4a3e0a5SBagalkote, Sreenivas 678c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 679c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 680c4a3e0a5SBagalkote, Sreenivas 681c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 682c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 683c4a3e0a5SBagalkote, Sreenivas 684c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 685c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 686c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 687c4a3e0a5SBagalkote, Sreenivas 688c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 689c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 690c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 691c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 692c4a3e0a5SBagalkote, Sreenivas 693c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 694c4a3e0a5SBagalkote, Sreenivas 695c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 696c4a3e0a5SBagalkote, Sreenivas 697c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 698c4a3e0a5SBagalkote, Sreenivas 699c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 700c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 701c4a3e0a5SBagalkote, Sreenivas 702c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 703c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 704c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 705c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 706c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 707c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 708c4a3e0a5SBagalkote, Sreenivas 709c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 710c4a3e0a5SBagalkote, Sreenivas 711c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 712c4a3e0a5SBagalkote, Sreenivas 713c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 714c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 715c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 716c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 717c4a3e0a5SBagalkote, Sreenivas 718c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 719c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 720c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 721c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 722c4a3e0a5SBagalkote, Sreenivas 723c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 724c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 725c4a3e0a5SBagalkote, Sreenivas 726c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 727c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 728c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 729c4a3e0a5SBagalkote, Sreenivas 730c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 731c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 732c4a3e0a5SBagalkote, Sreenivas 733c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 734c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 735c4a3e0a5SBagalkote, Sreenivas 736c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 737c4a3e0a5SBagalkote, Sreenivas 738c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 739c4a3e0a5SBagalkote, Sreenivas 740c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 741c4a3e0a5SBagalkote, Sreenivas 742c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 743c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 744c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 745c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 746c4a3e0a5SBagalkote, Sreenivas 747c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 748c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 749c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 750c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 751c4a3e0a5SBagalkote, Sreenivas 752c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 753c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 754c4a3e0a5SBagalkote, Sreenivas 755c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 756c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 757c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 758c4a3e0a5SBagalkote, Sreenivas 759c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 760c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 761c4a3e0a5SBagalkote, Sreenivas 762c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 763c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 764c4a3e0a5SBagalkote, Sreenivas 765c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 766c4a3e0a5SBagalkote, Sreenivas 767c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 768c4a3e0a5SBagalkote, Sreenivas 769c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 770c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 771c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 772c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 773c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 774c4a3e0a5SBagalkote, Sreenivas 775c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 776c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 777c4a3e0a5SBagalkote, Sreenivas 778c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 779c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 780c4a3e0a5SBagalkote, Sreenivas 781c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 782c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 783c4a3e0a5SBagalkote, Sreenivas 784c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 785c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 786c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 787c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 788c4a3e0a5SBagalkote, Sreenivas } mbox; 789c4a3e0a5SBagalkote, Sreenivas 790c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 791c4a3e0a5SBagalkote, Sreenivas 792c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 793c4a3e0a5SBagalkote, Sreenivas 794c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 795c4a3e0a5SBagalkote, Sreenivas 796c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 797c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 798c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 799c4a3e0a5SBagalkote, Sreenivas 800c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 801c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 802c4a3e0a5SBagalkote, Sreenivas 803c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 804c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 805c4a3e0a5SBagalkote, Sreenivas 806c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 807c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 808c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 809c4a3e0a5SBagalkote, Sreenivas 810c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 811c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 812c4a3e0a5SBagalkote, Sreenivas 813c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 814c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 815c4a3e0a5SBagalkote, Sreenivas 816c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 817c4a3e0a5SBagalkote, Sreenivas 818c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 819c4a3e0a5SBagalkote, Sreenivas 820c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 821c4a3e0a5SBagalkote, Sreenivas 822c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 823c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 824c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 825c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 826c4a3e0a5SBagalkote, Sreenivas 827c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 828c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 829c4a3e0a5SBagalkote, Sreenivas 830c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 831c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 832c4a3e0a5SBagalkote, Sreenivas 833c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 834c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 835c4a3e0a5SBagalkote, Sreenivas 836c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 837c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 838c4a3e0a5SBagalkote, Sreenivas 839c4a3e0a5SBagalkote, Sreenivas union { 840c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 841c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 842c4a3e0a5SBagalkote, Sreenivas } sgl; 843c4a3e0a5SBagalkote, Sreenivas 844c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 845c4a3e0a5SBagalkote, Sreenivas 846c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 847c4a3e0a5SBagalkote, Sreenivas 848c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 849c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 850c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 851c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 852c4a3e0a5SBagalkote, Sreenivas 853c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 854c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 855c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 856c4a3e0a5SBagalkote, Sreenivas 857c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 858c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 859c4a3e0a5SBagalkote, Sreenivas 860c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 861c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 862c4a3e0a5SBagalkote, Sreenivas 863c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 864c4a3e0a5SBagalkote, Sreenivas 865c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 866c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 867c4a3e0a5SBagalkote, Sreenivas 868c4a3e0a5SBagalkote, Sreenivas union { 869c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 870c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 871c4a3e0a5SBagalkote, Sreenivas } sgl; 872c4a3e0a5SBagalkote, Sreenivas 873c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 874c4a3e0a5SBagalkote, Sreenivas 875c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 876c4a3e0a5SBagalkote, Sreenivas 877c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 878c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 879c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 880c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 881c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 882c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 883c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 884c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 885c4a3e0a5SBagalkote, Sreenivas 886c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 887c4a3e0a5SBagalkote, Sreenivas }; 888c4a3e0a5SBagalkote, Sreenivas 889c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 890c4a3e0a5SBagalkote, Sreenivas 891c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 892c4a3e0a5SBagalkote, Sreenivas 893c4a3e0a5SBagalkote, Sreenivas struct { 894c4a3e0a5SBagalkote, Sreenivas u16 locale; 895c4a3e0a5SBagalkote, Sreenivas u8 reserved; 896c4a3e0a5SBagalkote, Sreenivas s8 class; 897c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 898c4a3e0a5SBagalkote, Sreenivas 899c4a3e0a5SBagalkote, Sreenivas u32 word; 900c4a3e0a5SBagalkote, Sreenivas 901c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 902c4a3e0a5SBagalkote, Sreenivas 903c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 904c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 905c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 906c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 907c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 908c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 909c4a3e0a5SBagalkote, Sreenivas 910c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 911c4a3e0a5SBagalkote, Sreenivas 912c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 913c4a3e0a5SBagalkote, Sreenivas 914c4a3e0a5SBagalkote, Sreenivas u16 progress; 915c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 916c4a3e0a5SBagalkote, Sreenivas 917c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 918c4a3e0a5SBagalkote, Sreenivas 919c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 920c4a3e0a5SBagalkote, Sreenivas 921c4a3e0a5SBagalkote, Sreenivas u16 target_id; 922c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 923c4a3e0a5SBagalkote, Sreenivas u8 reserved; 924c4a3e0a5SBagalkote, Sreenivas 925c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 926c4a3e0a5SBagalkote, Sreenivas 927c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 928c4a3e0a5SBagalkote, Sreenivas u16 device_id; 929c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 930c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 931c4a3e0a5SBagalkote, Sreenivas 932c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 933c4a3e0a5SBagalkote, Sreenivas 934c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 935c4a3e0a5SBagalkote, Sreenivas 936c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 937c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 938c4a3e0a5SBagalkote, Sreenivas u32 code; 939c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 940c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 941c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 942c4a3e0a5SBagalkote, Sreenivas 943c4a3e0a5SBagalkote, Sreenivas union { 944c4a3e0a5SBagalkote, Sreenivas struct { 945c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 946c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 947c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 948c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 949c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 950c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 951c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 952c4a3e0a5SBagalkote, Sreenivas 953c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 954c4a3e0a5SBagalkote, Sreenivas 955c4a3e0a5SBagalkote, Sreenivas struct { 956c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 957c4a3e0a5SBagalkote, Sreenivas u64 count; 958c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 959c4a3e0a5SBagalkote, Sreenivas 960c4a3e0a5SBagalkote, Sreenivas struct { 961c4a3e0a5SBagalkote, Sreenivas u64 lba; 962c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 963c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 964c4a3e0a5SBagalkote, Sreenivas 965c4a3e0a5SBagalkote, Sreenivas struct { 966c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 967c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 968c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 969c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 970c4a3e0a5SBagalkote, Sreenivas 971c4a3e0a5SBagalkote, Sreenivas struct { 972c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 973c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 974c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 975c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 976c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 977c4a3e0a5SBagalkote, Sreenivas 978c4a3e0a5SBagalkote, Sreenivas struct { 979c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 980c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 981c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 982c4a3e0a5SBagalkote, Sreenivas 983c4a3e0a5SBagalkote, Sreenivas struct { 984c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 985c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 986c4a3e0a5SBagalkote, Sreenivas u32 new_state; 987c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 988c4a3e0a5SBagalkote, Sreenivas 989c4a3e0a5SBagalkote, Sreenivas struct { 990c4a3e0a5SBagalkote, Sreenivas u64 strip; 991c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 992c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 993c4a3e0a5SBagalkote, Sreenivas 994c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 995c4a3e0a5SBagalkote, Sreenivas 996c4a3e0a5SBagalkote, Sreenivas struct { 997c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 998c4a3e0a5SBagalkote, Sreenivas u32 err; 999c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1000c4a3e0a5SBagalkote, Sreenivas 1001c4a3e0a5SBagalkote, Sreenivas struct { 1002c4a3e0a5SBagalkote, Sreenivas u64 lba; 1003c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1004c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1005c4a3e0a5SBagalkote, Sreenivas 1006c4a3e0a5SBagalkote, Sreenivas struct { 1007c4a3e0a5SBagalkote, Sreenivas u64 lba; 1008c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1009c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1010c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1011c4a3e0a5SBagalkote, Sreenivas 1012c4a3e0a5SBagalkote, Sreenivas struct { 1013c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1014c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1015c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1016c4a3e0a5SBagalkote, Sreenivas 1017c4a3e0a5SBagalkote, Sreenivas struct { 1018c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1019c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1020c4a3e0a5SBagalkote, Sreenivas u32 newState; 1021c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1022c4a3e0a5SBagalkote, Sreenivas 1023c4a3e0a5SBagalkote, Sreenivas struct { 1024c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1025c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1026c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1027c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1028c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1029c4a3e0a5SBagalkote, Sreenivas 1030c4a3e0a5SBagalkote, Sreenivas u32 rate; 1031c4a3e0a5SBagalkote, Sreenivas char str[96]; 1032c4a3e0a5SBagalkote, Sreenivas 1033c4a3e0a5SBagalkote, Sreenivas struct { 1034c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1035c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1036c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1037c4a3e0a5SBagalkote, Sreenivas 1038c4a3e0a5SBagalkote, Sreenivas struct { 1039c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1040c4a3e0a5SBagalkote, Sreenivas u32 elog; 1041c4a3e0a5SBagalkote, Sreenivas char str[64]; 1042c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1043c4a3e0a5SBagalkote, Sreenivas 1044c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1045c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1046c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1047c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1048c4a3e0a5SBagalkote, Sreenivas } args; 1049c4a3e0a5SBagalkote, Sreenivas 1050c4a3e0a5SBagalkote, Sreenivas char description[128]; 1051c4a3e0a5SBagalkote, Sreenivas 1052c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1053c4a3e0a5SBagalkote, Sreenivas 10541341c939SSumant Patro struct megasas_instance_template { 10551341c939SSumant Patro void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *); 10561341c939SSumant Patro 10571341c939SSumant Patro void (*enable_intr)(struct megasas_register_set __iomem *) ; 1058b274cab7SSumant Patro void (*disable_intr)(struct megasas_register_set __iomem *); 10591341c939SSumant Patro 10601341c939SSumant Patro int (*clear_intr)(struct megasas_register_set __iomem *); 10611341c939SSumant Patro 10621341c939SSumant Patro u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 10631341c939SSumant Patro }; 10641341c939SSumant Patro 1065c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1066c4a3e0a5SBagalkote, Sreenivas 1067c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1068c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1069c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1070c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1071c4a3e0a5SBagalkote, Sreenivas 1072c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1073c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1074c4a3e0a5SBagalkote, Sreenivas 1075c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1076c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1077c4a3e0a5SBagalkote, Sreenivas 1078c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1079c4a3e0a5SBagalkote, Sreenivas 1080c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1081c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 1082c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 1083c4a3e0a5SBagalkote, Sreenivas 1084c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1085c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 1086c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 10877343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 10887343eb65Sbo yang spinlock_t completion_lock; 1089c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1090c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1091c4a3e0a5SBagalkote, Sreenivas 1092c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1093c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1094c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1095e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1096c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1097c4a3e0a5SBagalkote, Sreenivas 1098c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1099c4a3e0a5SBagalkote, Sreenivas 1100c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1101c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1102c4a3e0a5SBagalkote, Sreenivas 1103c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1104c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 1105c4a3e0a5SBagalkote, Sreenivas 1106e4a082c7SSumant Patro atomic_t fw_outstanding; 1107c4a3e0a5SBagalkote, Sreenivas u32 hw_crit_error; 11081341c939SSumant Patro 11091341c939SSumant Patro struct megasas_instance_template *instancet; 11105d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 111105e9ebbeSSumant Patro 111205e9ebbeSSumant Patro u8 flag; 111305e9ebbeSSumant Patro unsigned long last_time; 1114c4a3e0a5SBagalkote, Sreenivas }; 1115c4a3e0a5SBagalkote, Sreenivas 1116c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1117c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1118c4a3e0a5SBagalkote, Sreenivas 1119c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1120c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1121c4a3e0a5SBagalkote, Sreenivas scp->device->id 1122c4a3e0a5SBagalkote, Sreenivas 1123c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1124c4a3e0a5SBagalkote, Sreenivas 1125c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1126c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1127c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1128c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1129c4a3e0a5SBagalkote, Sreenivas 1130c4a3e0a5SBagalkote, Sreenivas u32 index; 1131c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1132c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 1133c4a3e0a5SBagalkote, Sreenivas u16 abort_aen; 1134c4a3e0a5SBagalkote, Sreenivas 1135c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1136c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1137c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 1138c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1139c4a3e0a5SBagalkote, Sreenivas }; 1140c4a3e0a5SBagalkote, Sreenivas 1141c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1142c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1143c4a3e0a5SBagalkote, Sreenivas 1144c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1145c4a3e0a5SBagalkote, Sreenivas 1146c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1147c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1148c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1149c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1150c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1151c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1152c4a3e0a5SBagalkote, Sreenivas union { 1153c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1154c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1155c4a3e0a5SBagalkote, Sreenivas } frame; 1156c4a3e0a5SBagalkote, Sreenivas 1157c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1158c4a3e0a5SBagalkote, Sreenivas 1159c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1160c4a3e0a5SBagalkote, Sreenivas 1161c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1162c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1163c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1164c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1165c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1166c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1167c4a3e0a5SBagalkote, Sreenivas 1168c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1169c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1170c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1171c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1172c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1173c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1174c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1175c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1176c4a3e0a5SBagalkote, Sreenivas union { 1177c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1178c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1179c4a3e0a5SBagalkote, Sreenivas } frame; 1180c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1181c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1182c4a3e0a5SBagalkote, Sreenivas 11830e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1184c4a3e0a5SBagalkote, Sreenivas #endif 1185c4a3e0a5SBagalkote, Sreenivas 1186cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1187c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1188c4a3e0a5SBagalkote, Sreenivas 1189c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1190c4a3e0a5SBagalkote, Sreenivas 1191c4a3e0a5SBagalkote, Sreenivas u16 count; 1192c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1193c4a3e0a5SBagalkote, Sreenivas int max_index; 1194c4a3e0a5SBagalkote, Sreenivas }; 1195c4a3e0a5SBagalkote, Sreenivas 1196c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1197