1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 3c4a3e0a5SBagalkote, Sreenivas * 4e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2003-2013 LSI Corporation 5365597cfSShivasharan S * Copyright (c) 2013-2016 Avago Technologies 6365597cfSShivasharan S * Copyright (c) 2016-2018 Broadcom Inc. 7c4a3e0a5SBagalkote, Sreenivas * 8c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 9c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 103f1530c1Sadam radford * as published by the Free Software Foundation; either version 2 113f1530c1Sadam radford * of the License, or (at your option) any later version. 123f1530c1Sadam radford * 133f1530c1Sadam radford * This program is distributed in the hope that it will be useful, 143f1530c1Sadam radford * but WITHOUT ANY WARRANTY; without even the implied warranty of 153f1530c1Sadam radford * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 163f1530c1Sadam radford * GNU General Public License for more details. 173f1530c1Sadam radford * 183f1530c1Sadam radford * You should have received a copy of the GNU General Public License 19e399065bSSumit.Saxena@avagotech.com * along with this program. If not, see <http://www.gnu.org/licenses/>. 20c4a3e0a5SBagalkote, Sreenivas * 21c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h 223f1530c1Sadam radford * 23365597cfSShivasharan S * Authors: Broadcom Inc. 24365597cfSShivasharan S * Kashyap Desai <kashyap.desai@broadcom.com> 25365597cfSShivasharan S * Sumit Saxena <sumit.saxena@broadcom.com> 263f1530c1Sadam radford * 27365597cfSShivasharan S * Send feedback to: megaraidlinux.pdl@broadcom.com 28c4a3e0a5SBagalkote, Sreenivas */ 29c4a3e0a5SBagalkote, Sreenivas 30c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 31c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 32c4a3e0a5SBagalkote, Sreenivas 33a69b74d3SRandy Dunlap /* 34c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 35c4a3e0a5SBagalkote, Sreenivas */ 360de05405SShivasharan S #define MEGASAS_VERSION "07.707.51.00-rc1" 370de05405SShivasharan S #define MEGASAS_RELDATE "February 7, 2019" 380e98936cSSumant Patro 390e98936cSSumant Patro /* 400e98936cSSumant Patro * Device IDs 410e98936cSSumant Patro */ 420e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 43af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 440e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 456610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 466610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 4787911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 4887911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 499c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b 50229fe47cSadam radford #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 5136807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d 5221d3c710SSumit.Saxena@lsi.com #define PCI_DEVICE_ID_LSI_FURY 0x005f 5390c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 5490c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 557364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 567364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 5745f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_VENTURA 0x0014 58754f1baeSShivasharan S #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015 5945f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_HARPOON 0x0016 6045f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 6145f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B 6245f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C 63469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1 64469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2 65469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5 66469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6 670e98936cSSumant Patro 68c4a3e0a5SBagalkote, Sreenivas /* 6939b72c3cSSumit.Saxena@lsi.com * Intel HBA SSDIDs 7039b72c3cSSumit.Saxena@lsi.com */ 7139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 7239b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 7339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 7439b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 7539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 7639b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 777364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 7839b72c3cSSumit.Saxena@lsi.com 7939b72c3cSSumit.Saxena@lsi.com /* 8090c204bcSsumit.saxena@avagotech.com * Intruder HBA SSDIDs 8190c204bcSsumit.saxena@avagotech.com */ 8290c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID1 0x9371 8390c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID2 0x9390 8490c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID3 0x9370 8590c204bcSsumit.saxena@avagotech.com 8690c204bcSsumit.saxena@avagotech.com /* 8739b72c3cSSumit.Saxena@lsi.com * Intel HBA branding 8839b72c3cSSumit.Saxena@lsi.com */ 8939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_BRANDING \ 9039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC080" 9139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_BRANDING \ 9239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC040" 9339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_BRANDING \ 9439b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3SC008" 9539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_BRANDING \ 9639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3MC044" 9739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_BRANDING \ 9839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC080" 9939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_BRANDING \ 10039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC040" 1017364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 1027364d34bSsumit.saxena@avagotech.com "Intel(R) Integrated RAID Module RMS3BC160" 10339b72c3cSSumit.Saxena@lsi.com 10439b72c3cSSumit.Saxena@lsi.com /* 105c4a3e0a5SBagalkote, Sreenivas * ===================================== 106c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 107c4a3e0a5SBagalkote, Sreenivas * ===================================== 108c4a3e0a5SBagalkote, Sreenivas */ 109c4a3e0a5SBagalkote, Sreenivas 110c4a3e0a5SBagalkote, Sreenivas /* 111c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 112c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 113c4a3e0a5SBagalkote, Sreenivas * "message frames" 114c4a3e0a5SBagalkote, Sreenivas */ 115c4a3e0a5SBagalkote, Sreenivas 116a69b74d3SRandy Dunlap /* 117c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 118c4a3e0a5SBagalkote, Sreenivas */ 119c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 120c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 121c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 122c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 123c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 124c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 125c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 126e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 127c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 128c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 129c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 130c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 131fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_FORCE_OCR 0x00000080 132fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_DMADONE 0x00000008 133fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 13439a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 1357e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002 136c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 137c4a3e0a5SBagalkote, Sreenivas 138a69b74d3SRandy Dunlap /* 139c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 140c4a3e0a5SBagalkote, Sreenivas * 141c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 142c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 143c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 144c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 145e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 146e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 147f0c21df6SShivasharan S * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump 148c4a3e0a5SBagalkote, Sreenivas */ 14939a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 15039a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 15139a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 15239a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 15339a98554Sbo yang 15439a98554Sbo yang #define MFI_ADP_RESET 0x00000040 155e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 156c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 157c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 158c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 159e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 160e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 161e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 162e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 163e3bbff9fSSumant Patro MFI_INIT_ABORT 164f0c21df6SShivasharan S #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100 165179ac142SSumit Saxena #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 166c4a3e0a5SBagalkote, Sreenivas 167a69b74d3SRandy Dunlap /* 168c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 169c4a3e0a5SBagalkote, Sreenivas */ 170c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 171c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 172c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 173c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 174c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 175c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 176c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 177c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 178c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 179c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 180f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 181c4a3e0a5SBagalkote, Sreenivas 1824026e9aaSSumit.Saxena@avagotech.com /* Driver internal */ 1834026e9aaSSumit.Saxena@avagotech.com #define DRV_DCMD_POLLED_MODE 0x1 1846d40afbcSSumit Saxena #define DRV_DCMD_SKIP_REFIRE 0x2 1854026e9aaSSumit.Saxena@avagotech.com 186a69b74d3SRandy Dunlap /* 187c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 188c4a3e0a5SBagalkote, Sreenivas */ 189c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 190c4a3e0a5SBagalkote, Sreenivas 191a69b74d3SRandy Dunlap /* 192c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 193c4a3e0a5SBagalkote, Sreenivas */ 19482add4e1SShivasharan S enum MFI_CMD_OP { 19582add4e1SShivasharan S MFI_CMD_INIT = 0x0, 19682add4e1SShivasharan S MFI_CMD_LD_READ = 0x1, 19782add4e1SShivasharan S MFI_CMD_LD_WRITE = 0x2, 19882add4e1SShivasharan S MFI_CMD_LD_SCSI_IO = 0x3, 19982add4e1SShivasharan S MFI_CMD_PD_SCSI_IO = 0x4, 20082add4e1SShivasharan S MFI_CMD_DCMD = 0x5, 20182add4e1SShivasharan S MFI_CMD_ABORT = 0x6, 20282add4e1SShivasharan S MFI_CMD_SMP = 0x7, 20382add4e1SShivasharan S MFI_CMD_STP = 0x8, 204f870bcbeSShivasharan S MFI_CMD_NVME = 0x9, 20582add4e1SShivasharan S MFI_CMD_OP_COUNT, 20682add4e1SShivasharan S MFI_CMD_INVALID = 0xff 20782add4e1SShivasharan S }; 208c4a3e0a5SBagalkote, Sreenivas 209c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 210bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 21121c9e160Sadam radford #define MR_DCMD_LD_LIST_QUERY 0x03010100 212c4a3e0a5SBagalkote, Sreenivas 213c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 214c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 215c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 216c4a3e0a5SBagalkote, Sreenivas 217c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 21831ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 219c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 220c4a3e0a5SBagalkote, Sreenivas 221c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 222c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 223c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 224c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 225c4a3e0a5SBagalkote, Sreenivas 226c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 227c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 228c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 22981e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 230c4a3e0a5SBagalkote, Sreenivas 231fc62b3fcSSumit.Saxena@avagotech.com #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 232fc62b3fcSSumit.Saxena@avagotech.com #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 2332216c305SSumit Saxena #define MR_DCMD_PD_GET_INFO 0x02020000 234fc62b3fcSSumit.Saxena@avagotech.com 235a69b74d3SRandy Dunlap /* 236bc93d425SSumit.Saxena@lsi.com * Global functions 237bc93d425SSumit.Saxena@lsi.com */ 2385f19f7c8SShivasharan S extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id); 239bc93d425SSumit.Saxena@lsi.com 240bc93d425SSumit.Saxena@lsi.com 241bc93d425SSumit.Saxena@lsi.com /* 242c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 243c4a3e0a5SBagalkote, Sreenivas */ 244c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 245c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 246c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 247c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 248c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 249c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 250c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 251c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 252c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 253c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 254c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 255c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 256c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 257c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 258c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 259c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 260c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 261c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 262c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 263c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 264c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 265c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 266c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 267c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 268c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 269c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 270c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 271c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 272c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 273c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 274c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 275c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 276c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 277c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 278c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 279c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 280c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 281c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 282c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 283c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 284c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 285c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 286c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 287c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 288c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 289c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 290c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 291c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 292c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 293c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 294c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 295c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 296c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 297c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 298c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 299c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 300c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 301c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 30236807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 303c4a3e0a5SBagalkote, Sreenivas 304c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 305c4a3e0a5SBagalkote, Sreenivas }; 306c4a3e0a5SBagalkote, Sreenivas 307714f5177Ssumit.saxena@avagotech.com enum mfi_evt_class { 308714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEBUG = -2, 309714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_PROGRESS = -1, 310714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_INFO = 0, 311714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_WARNING = 1, 312714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_CRITICAL = 2, 313714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_FATAL = 3, 314714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEAD = 4 315714f5177Ssumit.saxena@avagotech.com }; 316714f5177Ssumit.saxena@avagotech.com 317c4a3e0a5SBagalkote, Sreenivas /* 318fc62b3fcSSumit.Saxena@avagotech.com * Crash dump related defines 319fc62b3fcSSumit.Saxena@avagotech.com */ 320fc62b3fcSSumit.Saxena@avagotech.com #define MAX_CRASH_DUMP_SIZE 512 321fc62b3fcSSumit.Saxena@avagotech.com #define CRASH_DMA_BUF_SIZE (1024 * 1024) 322fc62b3fcSSumit.Saxena@avagotech.com 323fc62b3fcSSumit.Saxena@avagotech.com enum MR_FW_CRASH_DUMP_STATE { 324fc62b3fcSSumit.Saxena@avagotech.com UNAVAILABLE = 0, 325fc62b3fcSSumit.Saxena@avagotech.com AVAILABLE = 1, 326fc62b3fcSSumit.Saxena@avagotech.com COPYING = 2, 327fc62b3fcSSumit.Saxena@avagotech.com COPIED = 3, 328fc62b3fcSSumit.Saxena@avagotech.com COPY_ERROR = 4, 329fc62b3fcSSumit.Saxena@avagotech.com }; 330fc62b3fcSSumit.Saxena@avagotech.com 331fc62b3fcSSumit.Saxena@avagotech.com enum _MR_CRASH_BUF_STATUS { 332fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_OFF = 0, 333fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_ON = 1, 334fc62b3fcSSumit.Saxena@avagotech.com }; 335fc62b3fcSSumit.Saxena@avagotech.com 336fc62b3fcSSumit.Saxena@avagotech.com /* 337c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 338c4a3e0a5SBagalkote, Sreenivas */ 339c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 340c4a3e0a5SBagalkote, Sreenivas 341c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 342c4a3e0a5SBagalkote, Sreenivas 343c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 344c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 345c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 346c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 347c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 348c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 349c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 350c4a3e0a5SBagalkote, Sreenivas 351c4a3e0a5SBagalkote, Sreenivas }; 352c4a3e0a5SBagalkote, Sreenivas 353c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 354c4a3e0a5SBagalkote, Sreenivas 355c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 356c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 357c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 358c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 359c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 360c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 361c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 362c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 363c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 364c4a3e0a5SBagalkote, Sreenivas 365c4a3e0a5SBagalkote, Sreenivas }; 366c4a3e0a5SBagalkote, Sreenivas 367c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 368c4a3e0a5SBagalkote, Sreenivas 369c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 370c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 371c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 372c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 373c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 374c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 375c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 376c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 377c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 378c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 379c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 380c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 381c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 382c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 383c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 384c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 385c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 386c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 387c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 388c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 389c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 39081e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 39181e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 39281e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 39381e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 39481e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 39581e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 39681e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 39781e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 39881e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 39981e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 40081e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 40181e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 40281e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 40381e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 40481e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 40581e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 406c4a3e0a5SBagalkote, Sreenivas }; 407c4a3e0a5SBagalkote, Sreenivas 408357ae967Ssumit.saxena@avagotech.com 409357ae967Ssumit.saxena@avagotech.com #define SGE_BUFFER_SIZE 4096 4108f67c8c5SSumit Saxena #define MEGASAS_CLUSTER_ID_SIZE 16 411c4a3e0a5SBagalkote, Sreenivas /* 41281e403ceSYang, Bo * define constants for device list query options 41381e403ceSYang, Bo */ 41481e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 41581e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 41681e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 41781e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 41881e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 41981e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 42081e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 42181e403ceSYang, Bo }; 42281e403ceSYang, Bo 42321c9e160Sadam radford enum MR_LD_QUERY_TYPE { 42421c9e160Sadam radford MR_LD_QUERY_TYPE_ALL = 0, 42521c9e160Sadam radford MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 42621c9e160Sadam radford MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 42721c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 42821c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 42921c9e160Sadam radford }; 43021c9e160Sadam radford 43121c9e160Sadam radford 4327e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 4337e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 4347e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 4357e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 4367e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 4377e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 4387e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 4397e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 4407e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 441c4bd2654Ssumit.saxena@avagotech.com #define MR_EVT_CTRL_PROP_CHANGED 0x012f 4427e8a75f4SYang, Bo 44381e403ceSYang, Bo enum MR_PD_STATE { 44481e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 44581e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 44681e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 44781e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 44881e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 44981e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 45081e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 45181e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 45281e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 45381e403ceSYang, Bo }; 45481e403ceSYang, Bo 4552216c305SSumit Saxena union MR_PD_REF { 4562216c305SSumit Saxena struct { 4572216c305SSumit Saxena u16 deviceId; 4582216c305SSumit Saxena u16 seqNum; 4592216c305SSumit Saxena } mrPdRef; 4602216c305SSumit Saxena u32 ref; 4612216c305SSumit Saxena }; 4622216c305SSumit Saxena 4632216c305SSumit Saxena /* 4642216c305SSumit Saxena * define the DDF Type bit structure 4652216c305SSumit Saxena */ 4662216c305SSumit Saxena union MR_PD_DDF_TYPE { 4672216c305SSumit Saxena struct { 4682216c305SSumit Saxena union { 4692216c305SSumit Saxena struct { 4702216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 4712216c305SSumit Saxena u16 forcedPDGUID:1; 4722216c305SSumit Saxena u16 inVD:1; 4732216c305SSumit Saxena u16 isGlobalSpare:1; 4742216c305SSumit Saxena u16 isSpare:1; 4752216c305SSumit Saxena u16 isForeign:1; 4762216c305SSumit Saxena u16 reserved:7; 4772216c305SSumit Saxena u16 intf:4; 4782216c305SSumit Saxena #else 4792216c305SSumit Saxena u16 intf:4; 4802216c305SSumit Saxena u16 reserved:7; 4812216c305SSumit Saxena u16 isForeign:1; 4822216c305SSumit Saxena u16 isSpare:1; 4832216c305SSumit Saxena u16 isGlobalSpare:1; 4842216c305SSumit Saxena u16 inVD:1; 4852216c305SSumit Saxena u16 forcedPDGUID:1; 4862216c305SSumit Saxena #endif 4872216c305SSumit Saxena } pdType; 4882216c305SSumit Saxena u16 type; 4892216c305SSumit Saxena }; 4902216c305SSumit Saxena u16 reserved; 4912216c305SSumit Saxena } ddf; 4922216c305SSumit Saxena struct { 4932216c305SSumit Saxena u32 reserved; 4942216c305SSumit Saxena } nonDisk; 4952216c305SSumit Saxena u32 type; 4962216c305SSumit Saxena } __packed; 4972216c305SSumit Saxena 4982216c305SSumit Saxena /* 4992216c305SSumit Saxena * defines the progress structure 5002216c305SSumit Saxena */ 5012216c305SSumit Saxena union MR_PROGRESS { 5022216c305SSumit Saxena struct { 5032216c305SSumit Saxena u16 progress; 5042216c305SSumit Saxena union { 5052216c305SSumit Saxena u16 elapsedSecs; 5062216c305SSumit Saxena u16 elapsedSecsForLastPercent; 5072216c305SSumit Saxena }; 5082216c305SSumit Saxena } mrProgress; 5092216c305SSumit Saxena u32 w; 5102216c305SSumit Saxena } __packed; 5112216c305SSumit Saxena 5122216c305SSumit Saxena /* 5132216c305SSumit Saxena * defines the physical drive progress structure 5142216c305SSumit Saxena */ 5152216c305SSumit Saxena struct MR_PD_PROGRESS { 5162216c305SSumit Saxena struct { 5172216c305SSumit Saxena #ifndef MFI_BIG_ENDIAN 5182216c305SSumit Saxena u32 rbld:1; 5192216c305SSumit Saxena u32 patrol:1; 5202216c305SSumit Saxena u32 clear:1; 5212216c305SSumit Saxena u32 copyBack:1; 5222216c305SSumit Saxena u32 erase:1; 5232216c305SSumit Saxena u32 locate:1; 5242216c305SSumit Saxena u32 reserved:26; 5252216c305SSumit Saxena #else 5262216c305SSumit Saxena u32 reserved:26; 5272216c305SSumit Saxena u32 locate:1; 5282216c305SSumit Saxena u32 erase:1; 5292216c305SSumit Saxena u32 copyBack:1; 5302216c305SSumit Saxena u32 clear:1; 5312216c305SSumit Saxena u32 patrol:1; 5322216c305SSumit Saxena u32 rbld:1; 5332216c305SSumit Saxena #endif 5342216c305SSumit Saxena } active; 5352216c305SSumit Saxena union MR_PROGRESS rbld; 5362216c305SSumit Saxena union MR_PROGRESS patrol; 5372216c305SSumit Saxena union { 5382216c305SSumit Saxena union MR_PROGRESS clear; 5392216c305SSumit Saxena union MR_PROGRESS erase; 5402216c305SSumit Saxena }; 5412216c305SSumit Saxena 5422216c305SSumit Saxena struct { 5432216c305SSumit Saxena #ifndef MFI_BIG_ENDIAN 5442216c305SSumit Saxena u32 rbld:1; 5452216c305SSumit Saxena u32 patrol:1; 5462216c305SSumit Saxena u32 clear:1; 5472216c305SSumit Saxena u32 copyBack:1; 5482216c305SSumit Saxena u32 erase:1; 5492216c305SSumit Saxena u32 reserved:27; 5502216c305SSumit Saxena #else 5512216c305SSumit Saxena u32 reserved:27; 5522216c305SSumit Saxena u32 erase:1; 5532216c305SSumit Saxena u32 copyBack:1; 5542216c305SSumit Saxena u32 clear:1; 5552216c305SSumit Saxena u32 patrol:1; 5562216c305SSumit Saxena u32 rbld:1; 5572216c305SSumit Saxena #endif 5582216c305SSumit Saxena } pause; 5592216c305SSumit Saxena 5602216c305SSumit Saxena union MR_PROGRESS reserved[3]; 5612216c305SSumit Saxena } __packed; 5622216c305SSumit Saxena 5632216c305SSumit Saxena struct MR_PD_INFO { 5642216c305SSumit Saxena union MR_PD_REF ref; 5652216c305SSumit Saxena u8 inquiryData[96]; 5662216c305SSumit Saxena u8 vpdPage83[64]; 5672216c305SSumit Saxena u8 notSupported; 5682216c305SSumit Saxena u8 scsiDevType; 5692216c305SSumit Saxena 5702216c305SSumit Saxena union { 5712216c305SSumit Saxena u8 connectedPortBitmap; 5722216c305SSumit Saxena u8 connectedPortNumbers; 5732216c305SSumit Saxena }; 5742216c305SSumit Saxena 5752216c305SSumit Saxena u8 deviceSpeed; 5762216c305SSumit Saxena u32 mediaErrCount; 5772216c305SSumit Saxena u32 otherErrCount; 5782216c305SSumit Saxena u32 predFailCount; 5792216c305SSumit Saxena u32 lastPredFailEventSeqNum; 5802216c305SSumit Saxena 5812216c305SSumit Saxena u16 fwState; 5822216c305SSumit Saxena u8 disabledForRemoval; 5832216c305SSumit Saxena u8 linkSpeed; 5842216c305SSumit Saxena union MR_PD_DDF_TYPE state; 5852216c305SSumit Saxena 5862216c305SSumit Saxena struct { 5872216c305SSumit Saxena u8 count; 5882216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 5892216c305SSumit Saxena u8 isPathBroken:4; 5902216c305SSumit Saxena u8 reserved3:3; 5912216c305SSumit Saxena u8 widePortCapable:1; 5922216c305SSumit Saxena #else 5932216c305SSumit Saxena u8 widePortCapable:1; 5942216c305SSumit Saxena u8 reserved3:3; 5952216c305SSumit Saxena u8 isPathBroken:4; 5962216c305SSumit Saxena #endif 5972216c305SSumit Saxena 5982216c305SSumit Saxena u8 connectorIndex[2]; 5992216c305SSumit Saxena u8 reserved[4]; 6002216c305SSumit Saxena u64 sasAddr[2]; 6012216c305SSumit Saxena u8 reserved2[16]; 6022216c305SSumit Saxena } pathInfo; 6032216c305SSumit Saxena 6042216c305SSumit Saxena u64 rawSize; 6052216c305SSumit Saxena u64 nonCoercedSize; 6062216c305SSumit Saxena u64 coercedSize; 6072216c305SSumit Saxena u16 enclDeviceId; 6082216c305SSumit Saxena u8 enclIndex; 6092216c305SSumit Saxena 6102216c305SSumit Saxena union { 6112216c305SSumit Saxena u8 slotNumber; 6122216c305SSumit Saxena u8 enclConnectorIndex; 6132216c305SSumit Saxena }; 6142216c305SSumit Saxena 6152216c305SSumit Saxena struct MR_PD_PROGRESS progInfo; 6162216c305SSumit Saxena u8 badBlockTableFull; 6172216c305SSumit Saxena u8 unusableInCurrentConfig; 6182216c305SSumit Saxena u8 vpdPage83Ext[64]; 6192216c305SSumit Saxena u8 powerState; 6202216c305SSumit Saxena u8 enclPosition; 6212216c305SSumit Saxena u32 allowedOps; 6222216c305SSumit Saxena u16 copyBackPartnerId; 6232216c305SSumit Saxena u16 enclPartnerDeviceId; 6242216c305SSumit Saxena struct { 6252216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6262216c305SSumit Saxena u16 fdeCapable:1; 6272216c305SSumit Saxena u16 fdeEnabled:1; 6282216c305SSumit Saxena u16 secured:1; 6292216c305SSumit Saxena u16 locked:1; 6302216c305SSumit Saxena u16 foreign:1; 6312216c305SSumit Saxena u16 needsEKM:1; 6322216c305SSumit Saxena u16 reserved:10; 6332216c305SSumit Saxena #else 6342216c305SSumit Saxena u16 reserved:10; 6352216c305SSumit Saxena u16 needsEKM:1; 6362216c305SSumit Saxena u16 foreign:1; 6372216c305SSumit Saxena u16 locked:1; 6382216c305SSumit Saxena u16 secured:1; 6392216c305SSumit Saxena u16 fdeEnabled:1; 6402216c305SSumit Saxena u16 fdeCapable:1; 6412216c305SSumit Saxena #endif 6422216c305SSumit Saxena } security; 6432216c305SSumit Saxena u8 mediaType; 6442216c305SSumit Saxena u8 notCertified; 6452216c305SSumit Saxena u8 bridgeVendor[8]; 6462216c305SSumit Saxena u8 bridgeProductIdentification[16]; 6472216c305SSumit Saxena u8 bridgeProductRevisionLevel[4]; 6482216c305SSumit Saxena u8 satBridgeExists; 6492216c305SSumit Saxena 6502216c305SSumit Saxena u8 interfaceType; 6512216c305SSumit Saxena u8 temperature; 6522216c305SSumit Saxena u8 emulatedBlockSize; 6532216c305SSumit Saxena u16 userDataBlockSize; 6542216c305SSumit Saxena u16 reserved2; 6552216c305SSumit Saxena 6562216c305SSumit Saxena struct { 6572216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6582216c305SSumit Saxena u32 piType:3; 6592216c305SSumit Saxena u32 piFormatted:1; 6602216c305SSumit Saxena u32 piEligible:1; 6612216c305SSumit Saxena u32 NCQ:1; 6622216c305SSumit Saxena u32 WCE:1; 6632216c305SSumit Saxena u32 commissionedSpare:1; 6642216c305SSumit Saxena u32 emergencySpare:1; 6652216c305SSumit Saxena u32 ineligibleForSSCD:1; 6662216c305SSumit Saxena u32 ineligibleForLd:1; 6672216c305SSumit Saxena u32 useSSEraseType:1; 6682216c305SSumit Saxena u32 wceUnchanged:1; 6692216c305SSumit Saxena u32 supportScsiUnmap:1; 6702216c305SSumit Saxena u32 reserved:18; 6712216c305SSumit Saxena #else 6722216c305SSumit Saxena u32 reserved:18; 6732216c305SSumit Saxena u32 supportScsiUnmap:1; 6742216c305SSumit Saxena u32 wceUnchanged:1; 6752216c305SSumit Saxena u32 useSSEraseType:1; 6762216c305SSumit Saxena u32 ineligibleForLd:1; 6772216c305SSumit Saxena u32 ineligibleForSSCD:1; 6782216c305SSumit Saxena u32 emergencySpare:1; 6792216c305SSumit Saxena u32 commissionedSpare:1; 6802216c305SSumit Saxena u32 WCE:1; 6812216c305SSumit Saxena u32 NCQ:1; 6822216c305SSumit Saxena u32 piEligible:1; 6832216c305SSumit Saxena u32 piFormatted:1; 6842216c305SSumit Saxena u32 piType:3; 6852216c305SSumit Saxena #endif 6862216c305SSumit Saxena } properties; 6872216c305SSumit Saxena 6882216c305SSumit Saxena u64 shieldDiagCompletionTime; 6892216c305SSumit Saxena u8 shieldCounter; 6902216c305SSumit Saxena 6912216c305SSumit Saxena u8 linkSpeedOther; 6922216c305SSumit Saxena u8 reserved4[2]; 6932216c305SSumit Saxena 6942216c305SSumit Saxena struct { 6952216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6962216c305SSumit Saxena u32 bbmErrCountSupported:1; 6972216c305SSumit Saxena u32 bbmErrCount:31; 6982216c305SSumit Saxena #else 6992216c305SSumit Saxena u32 bbmErrCount:31; 7002216c305SSumit Saxena u32 bbmErrCountSupported:1; 7012216c305SSumit Saxena #endif 7022216c305SSumit Saxena } bbmErr; 7032216c305SSumit Saxena 7042216c305SSumit Saxena u8 reserved1[512-428]; 7052216c305SSumit Saxena } __packed; 70681e403ceSYang, Bo 70781e403ceSYang, Bo /* 70896188a89SShivasharan S * Definition of structure used to expose attributes of VD or JBOD 70996188a89SShivasharan S * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP 71096188a89SShivasharan S * is fired by driver) 71196188a89SShivasharan S */ 71296188a89SShivasharan S struct MR_TARGET_PROPERTIES { 71396188a89SShivasharan S u32 max_io_size_kb; 71496188a89SShivasharan S u32 device_qdepth; 71596188a89SShivasharan S u32 sector_size; 716e9495e2dSShivasharan S u8 reset_tmo; 717e9495e2dSShivasharan S u8 reserved[499]; 71896188a89SShivasharan S } __packed; 71996188a89SShivasharan S 72096188a89SShivasharan S /* 72181e403ceSYang, Bo * defines the physical drive address structure 72281e403ceSYang, Bo */ 72381e403ceSYang, Bo struct MR_PD_ADDRESS { 7249ab9ed38SChristoph Hellwig __le16 deviceId; 72581e403ceSYang, Bo u16 enclDeviceId; 72681e403ceSYang, Bo 72781e403ceSYang, Bo union { 72881e403ceSYang, Bo struct { 72981e403ceSYang, Bo u8 enclIndex; 73081e403ceSYang, Bo u8 slotNumber; 73181e403ceSYang, Bo } mrPdAddress; 73281e403ceSYang, Bo struct { 73381e403ceSYang, Bo u8 enclPosition; 73481e403ceSYang, Bo u8 enclConnectorIndex; 73581e403ceSYang, Bo } mrEnclAddress; 73681e403ceSYang, Bo }; 73781e403ceSYang, Bo u8 scsiDevType; 73881e403ceSYang, Bo union { 73981e403ceSYang, Bo u8 connectedPortBitmap; 74081e403ceSYang, Bo u8 connectedPortNumbers; 74181e403ceSYang, Bo }; 74281e403ceSYang, Bo u64 sasAddr[2]; 74381e403ceSYang, Bo } __packed; 74481e403ceSYang, Bo 74581e403ceSYang, Bo /* 74681e403ceSYang, Bo * defines the physical drive list structure 74781e403ceSYang, Bo */ 74881e403ceSYang, Bo struct MR_PD_LIST { 7499ab9ed38SChristoph Hellwig __le32 size; 7509ab9ed38SChristoph Hellwig __le32 count; 75181e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 75281e403ceSYang, Bo } __packed; 75381e403ceSYang, Bo 75481e403ceSYang, Bo struct megasas_pd_list { 75581e403ceSYang, Bo u16 tid; 75681e403ceSYang, Bo u8 driveType; 75781e403ceSYang, Bo u8 driveState; 75881e403ceSYang, Bo } __packed; 75981e403ceSYang, Bo 76081e403ceSYang, Bo /* 761bdc6fb8dSYang, Bo * defines the logical drive reference structure 762bdc6fb8dSYang, Bo */ 763bdc6fb8dSYang, Bo union MR_LD_REF { 764bdc6fb8dSYang, Bo struct { 765bdc6fb8dSYang, Bo u8 targetId; 766bdc6fb8dSYang, Bo u8 reserved; 7679ab9ed38SChristoph Hellwig __le16 seqNum; 768bdc6fb8dSYang, Bo }; 7699ab9ed38SChristoph Hellwig __le32 ref; 770bdc6fb8dSYang, Bo } __packed; 771bdc6fb8dSYang, Bo 772bdc6fb8dSYang, Bo /* 773bdc6fb8dSYang, Bo * defines the logical drive list structure 774bdc6fb8dSYang, Bo */ 775bdc6fb8dSYang, Bo struct MR_LD_LIST { 7769ab9ed38SChristoph Hellwig __le32 ldCount; 7779ab9ed38SChristoph Hellwig __le32 reserved; 778bdc6fb8dSYang, Bo struct { 779bdc6fb8dSYang, Bo union MR_LD_REF ref; 780bdc6fb8dSYang, Bo u8 state; 781bdc6fb8dSYang, Bo u8 reserved[3]; 7829ab9ed38SChristoph Hellwig __le64 size; 78351087a86SSumit.Saxena@avagotech.com } ldList[MAX_LOGICAL_DRIVES_EXT]; 784bdc6fb8dSYang, Bo } __packed; 785bdc6fb8dSYang, Bo 78621c9e160Sadam radford struct MR_LD_TARGETID_LIST { 7879ab9ed38SChristoph Hellwig __le32 size; 7889ab9ed38SChristoph Hellwig __le32 count; 78921c9e160Sadam radford u8 pad[3]; 79051087a86SSumit.Saxena@avagotech.com u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 79121c9e160Sadam radford }; 79221c9e160Sadam radford 793f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST_ENTRY { 794f6fe5731SShivasharan S struct { 795f6fe5731SShivasharan S union { 796f6fe5731SShivasharan S struct { 797f6fe5731SShivasharan S #if defined(__BIG_ENDIAN_BITFIELD) 798f6fe5731SShivasharan S u8 reserved:7; 799f6fe5731SShivasharan S u8 is_sys_pd:1; 800f6fe5731SShivasharan S #else 801f6fe5731SShivasharan S u8 is_sys_pd:1; 802f6fe5731SShivasharan S u8 reserved:7; 803f6fe5731SShivasharan S #endif 804f6fe5731SShivasharan S } bits; 805f6fe5731SShivasharan S u8 byte; 806f6fe5731SShivasharan S } u; 807f6fe5731SShivasharan S } flags; 808f6fe5731SShivasharan S u8 scsi_type; 809f6fe5731SShivasharan S __le16 target_id; 810a3742d68SShivasharan S u8 reserved[4]; 811f6fe5731SShivasharan S __le64 sas_addr[2]; 812f6fe5731SShivasharan S } __packed; 813f6fe5731SShivasharan S 814f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST { 815f6fe5731SShivasharan S __le32 size; 816f6fe5731SShivasharan S __le32 count; 817a3742d68SShivasharan S __le32 reserved[2]; 818f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST_ENTRY host_device_list[1]; 819f6fe5731SShivasharan S } __packed; 820f6fe5731SShivasharan S 821f6fe5731SShivasharan S #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \ 822f6fe5731SShivasharan S (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \ 823f6fe5731SShivasharan S (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1))) 824f6fe5731SShivasharan S 82521c9e160Sadam radford 826bdc6fb8dSYang, Bo /* 827c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 828c4a3e0a5SBagalkote, Sreenivas */ 829c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 830c4a3e0a5SBagalkote, Sreenivas 831c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 832c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 833c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 834c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 835c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 836c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 837c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 838c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 839c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 840c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 841c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 842c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 843c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 844c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 845c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 846c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 847c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 848c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 849c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 850c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 851c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 85239a98554Sbo yang u8 maintainPdFailHistory; 85339a98554Sbo yang u8 disallowHostRequestReordering; 85439a98554Sbo yang u8 abortCCOnError; 85539a98554Sbo yang u8 loadBalanceMode; 85639a98554Sbo yang u8 disableAutoDetectBackplane; 857c4a3e0a5SBagalkote, Sreenivas 85839a98554Sbo yang u8 snapVDSpace; 85939a98554Sbo yang 86039a98554Sbo yang /* 86139a98554Sbo yang * Add properties that can be controlled by 86239a98554Sbo yang * a bit in the following structure. 86339a98554Sbo yang */ 86439a98554Sbo yang struct { 86594cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 86694cd65ddSSumit.Saxena@lsi.com u32 reserved:18; 86794cd65ddSSumit.Saxena@lsi.com u32 enableJBOD:1; 86894cd65ddSSumit.Saxena@lsi.com u32 disableSpinDownHS:1; 86994cd65ddSSumit.Saxena@lsi.com u32 allowBootWithPinnedCache:1; 87094cd65ddSSumit.Saxena@lsi.com u32 disableOnlineCtrlReset:1; 87194cd65ddSSumit.Saxena@lsi.com u32 enableSecretKeyControl:1; 87294cd65ddSSumit.Saxena@lsi.com u32 autoEnhancedImport:1; 87394cd65ddSSumit.Saxena@lsi.com u32 enableSpinDownUnconfigured:1; 87494cd65ddSSumit.Saxena@lsi.com u32 SSDPatrolReadEnabled:1; 87594cd65ddSSumit.Saxena@lsi.com u32 SSDSMARTerEnabled:1; 87694cd65ddSSumit.Saxena@lsi.com u32 disableNCQ:1; 87794cd65ddSSumit.Saxena@lsi.com u32 useFdeOnly:1; 87894cd65ddSSumit.Saxena@lsi.com u32 prCorrectUnconfiguredAreas:1; 87994cd65ddSSumit.Saxena@lsi.com u32 SMARTerEnabled:1; 88094cd65ddSSumit.Saxena@lsi.com u32 copyBackDisabled:1; 88194cd65ddSSumit.Saxena@lsi.com #else 88239a98554Sbo yang u32 copyBackDisabled:1; 88339a98554Sbo yang u32 SMARTerEnabled:1; 88439a98554Sbo yang u32 prCorrectUnconfiguredAreas:1; 88539a98554Sbo yang u32 useFdeOnly:1; 88639a98554Sbo yang u32 disableNCQ:1; 88739a98554Sbo yang u32 SSDSMARTerEnabled:1; 88839a98554Sbo yang u32 SSDPatrolReadEnabled:1; 88939a98554Sbo yang u32 enableSpinDownUnconfigured:1; 89039a98554Sbo yang u32 autoEnhancedImport:1; 89139a98554Sbo yang u32 enableSecretKeyControl:1; 89239a98554Sbo yang u32 disableOnlineCtrlReset:1; 89339a98554Sbo yang u32 allowBootWithPinnedCache:1; 89439a98554Sbo yang u32 disableSpinDownHS:1; 89539a98554Sbo yang u32 enableJBOD:1; 89639a98554Sbo yang u32 reserved:18; 89794cd65ddSSumit.Saxena@lsi.com #endif 89839a98554Sbo yang } OnOffProperties; 899f0c21df6SShivasharan S 900f0c21df6SShivasharan S union { 90139a98554Sbo yang u8 autoSnapVDSpace; 90239a98554Sbo yang u8 viewSpace; 903f0c21df6SShivasharan S struct { 904f0c21df6SShivasharan S #if defined(__BIG_ENDIAN_BITFIELD) 905f6fe5731SShivasharan S u16 reserved3:9; 906f6fe5731SShivasharan S u16 enable_fw_dev_list:1; 907f6fe5731SShivasharan S u16 reserved2:1; 908f0c21df6SShivasharan S u16 enable_snap_dump:1; 909f0c21df6SShivasharan S u16 reserved1:4; 910f0c21df6SShivasharan S #else 911f0c21df6SShivasharan S u16 reserved1:4; 912f0c21df6SShivasharan S u16 enable_snap_dump:1; 913f6fe5731SShivasharan S u16 reserved2:1; 914f6fe5731SShivasharan S u16 enable_fw_dev_list:1; 915f6fe5731SShivasharan S u16 reserved3:9; 916f0c21df6SShivasharan S #endif 917f0c21df6SShivasharan S } on_off_properties2; 918f0c21df6SShivasharan S }; 9199ab9ed38SChristoph Hellwig __le16 spinDownTime; 92039a98554Sbo yang u8 reserved[24]; 92181e403ceSYang, Bo } __packed; 922c4a3e0a5SBagalkote, Sreenivas 923c4a3e0a5SBagalkote, Sreenivas /* 924c4a3e0a5SBagalkote, Sreenivas * SAS controller information 925c4a3e0a5SBagalkote, Sreenivas */ 926c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 927c4a3e0a5SBagalkote, Sreenivas 928c4a3e0a5SBagalkote, Sreenivas /* 929c4a3e0a5SBagalkote, Sreenivas * PCI device information 930c4a3e0a5SBagalkote, Sreenivas */ 931c4a3e0a5SBagalkote, Sreenivas struct { 932c4a3e0a5SBagalkote, Sreenivas 9339ab9ed38SChristoph Hellwig __le16 vendor_id; 9349ab9ed38SChristoph Hellwig __le16 device_id; 9359ab9ed38SChristoph Hellwig __le16 sub_vendor_id; 9369ab9ed38SChristoph Hellwig __le16 sub_device_id; 937c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 938c4a3e0a5SBagalkote, Sreenivas 939c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 940c4a3e0a5SBagalkote, Sreenivas 941c4a3e0a5SBagalkote, Sreenivas /* 942c4a3e0a5SBagalkote, Sreenivas * Host interface information 943c4a3e0a5SBagalkote, Sreenivas */ 944c4a3e0a5SBagalkote, Sreenivas struct { 945c4a3e0a5SBagalkote, Sreenivas 946c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 947c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 948c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 949c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 950229fe47cSadam radford u8 SRIOV:1; 951229fe47cSadam radford u8 reserved_0:3; 952c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 953c4a3e0a5SBagalkote, Sreenivas u8 port_count; 954c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 955c4a3e0a5SBagalkote, Sreenivas 956c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 957c4a3e0a5SBagalkote, Sreenivas 958c4a3e0a5SBagalkote, Sreenivas /* 959c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 960c4a3e0a5SBagalkote, Sreenivas */ 961c4a3e0a5SBagalkote, Sreenivas struct { 962c4a3e0a5SBagalkote, Sreenivas 963c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 964c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 965c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 966c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 967c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 968c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 969c4a3e0a5SBagalkote, Sreenivas u8 port_count; 970c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 971c4a3e0a5SBagalkote, Sreenivas 972c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 973c4a3e0a5SBagalkote, Sreenivas 974c4a3e0a5SBagalkote, Sreenivas /* 975c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 976c4a3e0a5SBagalkote, Sreenivas */ 9779ab9ed38SChristoph Hellwig __le32 image_check_word; 9789ab9ed38SChristoph Hellwig __le32 image_component_count; 979c4a3e0a5SBagalkote, Sreenivas 980c4a3e0a5SBagalkote, Sreenivas struct { 981c4a3e0a5SBagalkote, Sreenivas 982c4a3e0a5SBagalkote, Sreenivas char name[8]; 983c4a3e0a5SBagalkote, Sreenivas char version[32]; 984c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 985c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 986c4a3e0a5SBagalkote, Sreenivas 987c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 988c4a3e0a5SBagalkote, Sreenivas 989c4a3e0a5SBagalkote, Sreenivas /* 990c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 991c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 992c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 993c4a3e0a5SBagalkote, Sreenivas * terminated 994c4a3e0a5SBagalkote, Sreenivas */ 9959ab9ed38SChristoph Hellwig __le32 pending_image_component_count; 996c4a3e0a5SBagalkote, Sreenivas 997c4a3e0a5SBagalkote, Sreenivas struct { 998c4a3e0a5SBagalkote, Sreenivas 999c4a3e0a5SBagalkote, Sreenivas char name[8]; 1000c4a3e0a5SBagalkote, Sreenivas char version[32]; 1001c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 1002c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 1003c4a3e0a5SBagalkote, Sreenivas 1004c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 1005c4a3e0a5SBagalkote, Sreenivas 1006c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 1007c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 1008c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 1009c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 1010c4a3e0a5SBagalkote, Sreenivas 1011c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 1012c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 1013c4a3e0a5SBagalkote, Sreenivas 1014c4a3e0a5SBagalkote, Sreenivas /* 1015c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 1016c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 1017c4a3e0a5SBagalkote, Sreenivas */ 1018c4a3e0a5SBagalkote, Sreenivas struct { 1019c4a3e0a5SBagalkote, Sreenivas 1020c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 1021c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 1022c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 1023c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 1024c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 1025c4a3e0a5SBagalkote, Sreenivas 1026c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 1027c4a3e0a5SBagalkote, Sreenivas 10289ab9ed38SChristoph Hellwig __le32 current_fw_time; 1029c4a3e0a5SBagalkote, Sreenivas 1030c4a3e0a5SBagalkote, Sreenivas /* 1031c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 1032c4a3e0a5SBagalkote, Sreenivas */ 10339ab9ed38SChristoph Hellwig __le16 max_concurrent_cmds; 10349ab9ed38SChristoph Hellwig __le16 max_sge_count; 10359ab9ed38SChristoph Hellwig __le32 max_request_size; 1036c4a3e0a5SBagalkote, Sreenivas 1037c4a3e0a5SBagalkote, Sreenivas /* 1038c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 1039c4a3e0a5SBagalkote, Sreenivas */ 10409ab9ed38SChristoph Hellwig __le16 ld_present_count; 10419ab9ed38SChristoph Hellwig __le16 ld_degraded_count; 10429ab9ed38SChristoph Hellwig __le16 ld_offline_count; 1043c4a3e0a5SBagalkote, Sreenivas 10449ab9ed38SChristoph Hellwig __le16 pd_present_count; 10459ab9ed38SChristoph Hellwig __le16 pd_disk_present_count; 10469ab9ed38SChristoph Hellwig __le16 pd_disk_pred_failure_count; 10479ab9ed38SChristoph Hellwig __le16 pd_disk_failed_count; 1048c4a3e0a5SBagalkote, Sreenivas 1049c4a3e0a5SBagalkote, Sreenivas /* 1050c4a3e0a5SBagalkote, Sreenivas * Memory size information 1051c4a3e0a5SBagalkote, Sreenivas */ 10529ab9ed38SChristoph Hellwig __le16 nvram_size; 10539ab9ed38SChristoph Hellwig __le16 memory_size; 10549ab9ed38SChristoph Hellwig __le16 flash_size; 1055c4a3e0a5SBagalkote, Sreenivas 1056c4a3e0a5SBagalkote, Sreenivas /* 1057c4a3e0a5SBagalkote, Sreenivas * Error counters 1058c4a3e0a5SBagalkote, Sreenivas */ 10599ab9ed38SChristoph Hellwig __le16 mem_correctable_error_count; 10609ab9ed38SChristoph Hellwig __le16 mem_uncorrectable_error_count; 1061c4a3e0a5SBagalkote, Sreenivas 1062c4a3e0a5SBagalkote, Sreenivas /* 1063c4a3e0a5SBagalkote, Sreenivas * Cluster information 1064c4a3e0a5SBagalkote, Sreenivas */ 1065c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 1066c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 1067c4a3e0a5SBagalkote, Sreenivas 1068c4a3e0a5SBagalkote, Sreenivas /* 1069c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 1070c4a3e0a5SBagalkote, Sreenivas */ 10719ab9ed38SChristoph Hellwig __le16 max_strips_per_io; 1072c4a3e0a5SBagalkote, Sreenivas 1073c4a3e0a5SBagalkote, Sreenivas /* 1074c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 1075c4a3e0a5SBagalkote, Sreenivas */ 1076c4a3e0a5SBagalkote, Sreenivas struct { 1077c4a3e0a5SBagalkote, Sreenivas 1078c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 1079c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 1080c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 1081c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 1082c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 1083c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1084c4a3e0a5SBagalkote, Sreenivas 1085c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 1086c4a3e0a5SBagalkote, Sreenivas 1087c4a3e0a5SBagalkote, Sreenivas struct { 1088c4a3e0a5SBagalkote, Sreenivas 1089c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 1090c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 1091c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 1092c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 1093c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 1094c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 1095c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 1096c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 1097c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 1098c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 1099c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 1100c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 1101c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 1102c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 1103c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 1104c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 1105c4a3e0a5SBagalkote, Sreenivas 1106c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 1107c4a3e0a5SBagalkote, Sreenivas 1108c4a3e0a5SBagalkote, Sreenivas struct { 1109c4a3e0a5SBagalkote, Sreenivas 1110c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 1111c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 1112c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 1113c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 1114c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 1115c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1116c4a3e0a5SBagalkote, Sreenivas 1117c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 1118c4a3e0a5SBagalkote, Sreenivas 1119c4a3e0a5SBagalkote, Sreenivas struct { 1120c4a3e0a5SBagalkote, Sreenivas 1121c4a3e0a5SBagalkote, Sreenivas u8 min; 1122c4a3e0a5SBagalkote, Sreenivas u8 max; 1123c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1124c4a3e0a5SBagalkote, Sreenivas 1125c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 1126c4a3e0a5SBagalkote, Sreenivas 1127c4a3e0a5SBagalkote, Sreenivas struct { 1128c4a3e0a5SBagalkote, Sreenivas 1129c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 1130c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 1131c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 1132c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 1133c4a3e0a5SBagalkote, Sreenivas 1134c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 1135c4a3e0a5SBagalkote, Sreenivas 1136c4a3e0a5SBagalkote, Sreenivas struct { 1137c4a3e0a5SBagalkote, Sreenivas 1138c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 1139c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 1140c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 1141c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 1142c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 1143c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1144c4a3e0a5SBagalkote, Sreenivas 1145c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 1146c4a3e0a5SBagalkote, Sreenivas 1147c4a3e0a5SBagalkote, Sreenivas /* 1148c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 1149c4a3e0a5SBagalkote, Sreenivas */ 1150c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 1151c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 1152c4a3e0a5SBagalkote, Sreenivas 1153c4a3e0a5SBagalkote, Sreenivas /* 1154c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 1155c4a3e0a5SBagalkote, Sreenivas */ 1156c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 1157c4a3e0a5SBagalkote, Sreenivas 1158c4a3e0a5SBagalkote, Sreenivas /* 1159c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 1160c4a3e0a5SBagalkote, Sreenivas */ 1161c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 1162c4a3e0a5SBagalkote, Sreenivas 1163c4a3e0a5SBagalkote, Sreenivas 1164bc93d425SSumit.Saxena@lsi.com /* 1165bc93d425SSumit.Saxena@lsi.com * If adapterOperations.supportMoreThan8Phys is set, 1166bc93d425SSumit.Saxena@lsi.com * and deviceInterface.portCount is greater than 8, 1167bc93d425SSumit.Saxena@lsi.com * SAS Addrs for first 8 ports shall be populated in 1168bc93d425SSumit.Saxena@lsi.com * deviceInterface.portAddr, and the rest shall be 1169bc93d425SSumit.Saxena@lsi.com * populated in deviceInterfacePortAddr2. 1170bc93d425SSumit.Saxena@lsi.com */ 11719ab9ed38SChristoph Hellwig __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1172bc93d425SSumit.Saxena@lsi.com u8 reserved3[128]; /*6e0h */ 1173bc93d425SSumit.Saxena@lsi.com 1174bc93d425SSumit.Saxena@lsi.com struct { /*760h */ 1175bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_0:4; 1176bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_0:12; 1177bc93d425SSumit.Saxena@lsi.com 1178bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1:4; 1179bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1:12; 1180bc93d425SSumit.Saxena@lsi.com 1181bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_5:4; 1182bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_5:12; 1183bc93d425SSumit.Saxena@lsi.com 1184bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E:4; 1185bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E:12; 1186bc93d425SSumit.Saxena@lsi.com 1187bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_6:4; 1188bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_6:12; 1189bc93d425SSumit.Saxena@lsi.com 1190bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_10:4; 1191bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_10:12; 1192bc93d425SSumit.Saxena@lsi.com 1193bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_50:4; 1194bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_50:12; 1195bc93d425SSumit.Saxena@lsi.com 1196bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_60:4; 1197bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_60:12; 1198bc93d425SSumit.Saxena@lsi.com 1199bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E_RLQ0:4; 1200bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E_RLQ0:12; 1201bc93d425SSumit.Saxena@lsi.com 1202bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E0_RLQ0:4; 1203bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E0_RLQ0:12; 1204bc93d425SSumit.Saxena@lsi.com 1205bc93d425SSumit.Saxena@lsi.com u16 reserved[6]; 1206bc93d425SSumit.Saxena@lsi.com } pdsForRaidLevels; 1207bc93d425SSumit.Saxena@lsi.com 12089ab9ed38SChristoph Hellwig __le16 maxPds; /*780h */ 12099ab9ed38SChristoph Hellwig __le16 maxDedHSPs; /*782h */ 12109ab9ed38SChristoph Hellwig __le16 maxGlobalHSP; /*784h */ 12119ab9ed38SChristoph Hellwig __le16 ddfSize; /*786h */ 1212bc93d425SSumit.Saxena@lsi.com u8 maxLdsPerArray; /*788h */ 1213bc93d425SSumit.Saxena@lsi.com u8 partitionsInDDF; /*789h */ 1214bc93d425SSumit.Saxena@lsi.com u8 lockKeyBinding; /*78ah */ 1215bc93d425SSumit.Saxena@lsi.com u8 maxPITsPerLd; /*78bh */ 1216bc93d425SSumit.Saxena@lsi.com u8 maxViewsPerLd; /*78ch */ 1217bc93d425SSumit.Saxena@lsi.com u8 maxTargetId; /*78dh */ 12189ab9ed38SChristoph Hellwig __le16 maxBvlVdSize; /*78eh */ 1219bc93d425SSumit.Saxena@lsi.com 12209ab9ed38SChristoph Hellwig __le16 maxConfigurableSSCSize; /*790h */ 12219ab9ed38SChristoph Hellwig __le16 currentSSCsize; /*792h */ 1222bc93d425SSumit.Saxena@lsi.com 1223bc93d425SSumit.Saxena@lsi.com char expanderFwVersion[12]; /*794h */ 1224bc93d425SSumit.Saxena@lsi.com 12259ab9ed38SChristoph Hellwig __le16 PFKTrialTimeRemaining; /*7A0h */ 1226bc93d425SSumit.Saxena@lsi.com 12279ab9ed38SChristoph Hellwig __le16 cacheMemorySize; /*7A2h */ 1228bc93d425SSumit.Saxena@lsi.com 1229bc93d425SSumit.Saxena@lsi.com struct { /*7A4h */ 123094cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 1231229fe47cSadam radford u32 reserved:5; 1232229fe47cSadam radford u32 activePassive:2; 1233229fe47cSadam radford u32 supportConfigAutoBalance:1; 1234229fe47cSadam radford u32 mpio:1; 1235229fe47cSadam radford u32 supportDataLDonSSCArray:1; 1236229fe47cSadam radford u32 supportPointInTimeProgress:1; 123794cd65ddSSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 123894cd65ddSSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 123994cd65ddSSumit.Saxena@lsi.com u32 headlessMode:1; 124094cd65ddSSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 124194cd65ddSSumit.Saxena@lsi.com u32 supportResetNow:1; 124294cd65ddSSumit.Saxena@lsi.com u32 realTimeScheduler:1; 124394cd65ddSSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 124494cd65ddSSumit.Saxena@lsi.com u32 supportPerfTuning:1; 124594cd65ddSSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 124694cd65ddSSumit.Saxena@lsi.com u32 supportJBOD:1; 124794cd65ddSSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 124894cd65ddSSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 124994cd65ddSSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 125094cd65ddSSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 125194cd65ddSSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 125294cd65ddSSumit.Saxena@lsi.com u32 supportShieldState:1; 125394cd65ddSSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 125494cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType3:1; 125594cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType2:1; 125694cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType1:1; 125794cd65ddSSumit.Saxena@lsi.com u32 supportPIcontroller:1; 125894cd65ddSSumit.Saxena@lsi.com #else 1259bc93d425SSumit.Saxena@lsi.com u32 supportPIcontroller:1; 1260bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType1:1; 1261bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType2:1; 1262bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType3:1; 1263bc93d425SSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 1264bc93d425SSumit.Saxena@lsi.com u32 supportShieldState:1; 1265bc93d425SSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 1266bc93d425SSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 1267bc93d425SSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 1268bc93d425SSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 1269bc93d425SSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 1270bc93d425SSumit.Saxena@lsi.com u32 supportJBOD:1; 1271bc93d425SSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 1272bc93d425SSumit.Saxena@lsi.com u32 supportPerfTuning:1; 1273bc93d425SSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 1274bc93d425SSumit.Saxena@lsi.com u32 realTimeScheduler:1; 1275bc93d425SSumit.Saxena@lsi.com 1276bc93d425SSumit.Saxena@lsi.com u32 supportResetNow:1; 1277bc93d425SSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 1278bc93d425SSumit.Saxena@lsi.com u32 headlessMode:1; 1279bc93d425SSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 1280bc93d425SSumit.Saxena@lsi.com 1281bc93d425SSumit.Saxena@lsi.com 1282bc93d425SSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 1283229fe47cSadam radford u32 supportPointInTimeProgress:1; 1284229fe47cSadam radford u32 supportDataLDonSSCArray:1; 1285229fe47cSadam radford u32 mpio:1; 1286229fe47cSadam radford u32 supportConfigAutoBalance:1; 1287229fe47cSadam radford u32 activePassive:2; 1288229fe47cSadam radford u32 reserved:5; 128994cd65ddSSumit.Saxena@lsi.com #endif 1290bc93d425SSumit.Saxena@lsi.com } adapterOperations2; 1291bc93d425SSumit.Saxena@lsi.com 1292bc93d425SSumit.Saxena@lsi.com u8 driverVersion[32]; /*7A8h */ 1293bc93d425SSumit.Saxena@lsi.com u8 maxDAPdCountSpinup60; /*7C8h */ 1294bc93d425SSumit.Saxena@lsi.com u8 temperatureROC; /*7C9h */ 1295bc93d425SSumit.Saxena@lsi.com u8 temperatureCtrl; /*7CAh */ 1296bc93d425SSumit.Saxena@lsi.com u8 reserved4; /*7CBh */ 12979ab9ed38SChristoph Hellwig __le16 maxConfigurablePds; /*7CCh */ 1298bc93d425SSumit.Saxena@lsi.com 1299bc93d425SSumit.Saxena@lsi.com 1300bc93d425SSumit.Saxena@lsi.com u8 reserved5[2]; /*0x7CDh */ 1301bc93d425SSumit.Saxena@lsi.com 1302bc93d425SSumit.Saxena@lsi.com /* 1303bc93d425SSumit.Saxena@lsi.com * HA cluster information 1304bc93d425SSumit.Saxena@lsi.com */ 1305bc93d425SSumit.Saxena@lsi.com struct { 130651087a86SSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 13078f67c8c5SSumit Saxena u32 reserved:25; 13088f67c8c5SSumit Saxena u32 passive:1; 130951087a86SSumit.Saxena@avagotech.com u32 premiumFeatureMismatch:1; 131051087a86SSumit.Saxena@avagotech.com u32 ctrlPropIncompatible:1; 131151087a86SSumit.Saxena@avagotech.com u32 fwVersionMismatch:1; 131251087a86SSumit.Saxena@avagotech.com u32 hwIncompatible:1; 131351087a86SSumit.Saxena@avagotech.com u32 peerIsIncompatible:1; 131451087a86SSumit.Saxena@avagotech.com u32 peerIsPresent:1; 131551087a86SSumit.Saxena@avagotech.com #else 1316bc93d425SSumit.Saxena@lsi.com u32 peerIsPresent:1; 1317bc93d425SSumit.Saxena@lsi.com u32 peerIsIncompatible:1; 1318bc93d425SSumit.Saxena@lsi.com u32 hwIncompatible:1; 1319bc93d425SSumit.Saxena@lsi.com u32 fwVersionMismatch:1; 1320bc93d425SSumit.Saxena@lsi.com u32 ctrlPropIncompatible:1; 1321bc93d425SSumit.Saxena@lsi.com u32 premiumFeatureMismatch:1; 13228f67c8c5SSumit Saxena u32 passive:1; 13238f67c8c5SSumit Saxena u32 reserved:25; 132451087a86SSumit.Saxena@avagotech.com #endif 1325bc93d425SSumit.Saxena@lsi.com } cluster; 1326bc93d425SSumit.Saxena@lsi.com 13278f67c8c5SSumit Saxena char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1328229fe47cSadam radford struct { 1329229fe47cSadam radford u8 maxVFsSupported; /*0x7E4*/ 1330229fe47cSadam radford u8 numVFsEnabled; /*0x7E5*/ 1331229fe47cSadam radford u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1332229fe47cSadam radford u8 reserved; /*0x7E7*/ 1333229fe47cSadam radford } iov; 1334bc93d425SSumit.Saxena@lsi.com 1335fc62b3fcSSumit.Saxena@avagotech.com struct { 1336fc62b3fcSSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 13373761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 13383761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 13390be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 13400be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 13410be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 13420be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 13437497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 13447497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 13457497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 13467497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 13477497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 13487497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 13497497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 13507497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 13517497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 13527497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 13537497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 13547497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 13557497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 1356fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 135751087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 135851087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 135951087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 136051087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 136151087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 1362fc62b3fcSSumit.Saxena@avagotech.com #else 136351087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 136451087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 136551087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 136651087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 136751087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 1368fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 13697497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 13707497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 13717497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 13727497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 13737497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 13747497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 13757497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 13767497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 13777497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 13787497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 13797497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 13807497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 13817497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 13820be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 13830be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 13840be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 13850be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 13863761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 13873761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 1388fc62b3fcSSumit.Saxena@avagotech.com #endif 1389fc62b3fcSSumit.Saxena@avagotech.com } adapterOperations3; 1390fc62b3fcSSumit.Saxena@avagotech.com 1391ede7c3ceSSasikumar Chandrasekaran struct { 1392ede7c3ceSSasikumar Chandrasekaran #if defined(__BIG_ENDIAN_BITFIELD) 1393ede7c3ceSSasikumar Chandrasekaran u8 reserved:7; 1394ede7c3ceSSasikumar Chandrasekaran /* Indicates whether the CPLD image is part of 1395ede7c3ceSSasikumar Chandrasekaran * the package and stored in flash 1396ede7c3ceSSasikumar Chandrasekaran */ 1397ede7c3ceSSasikumar Chandrasekaran u8 cpld_in_flash:1; 1398ede7c3ceSSasikumar Chandrasekaran #else 1399ede7c3ceSSasikumar Chandrasekaran u8 cpld_in_flash:1; 1400ede7c3ceSSasikumar Chandrasekaran u8 reserved:7; 1401ede7c3ceSSasikumar Chandrasekaran #endif 1402ede7c3ceSSasikumar Chandrasekaran u8 reserved1[3]; 1403ede7c3ceSSasikumar Chandrasekaran /* Null terminated string. Has the version 1404ede7c3ceSSasikumar Chandrasekaran * information if cpld_in_flash = FALSE 1405ede7c3ceSSasikumar Chandrasekaran */ 1406ede7c3ceSSasikumar Chandrasekaran u8 userCodeDefinition[12]; 1407ede7c3ceSSasikumar Chandrasekaran } cpld; /* Valid only if upgradableCPLD is TRUE */ 1408ede7c3ceSSasikumar Chandrasekaran 1409ede7c3ceSSasikumar Chandrasekaran struct { 1410ede7c3ceSSasikumar Chandrasekaran #if defined(__BIG_ENDIAN_BITFIELD) 1411f870bcbeSShivasharan S u16 reserved:2; 1412f870bcbeSShivasharan S u16 support_nvme_passthru:1; 1413f870bcbeSShivasharan S u16 support_pl_debug_info:1; 1414f870bcbeSShivasharan S u16 support_flash_comp_info:1; 1415f870bcbeSShivasharan S u16 support_host_info:1; 1416f870bcbeSShivasharan S u16 support_dual_fw_update:1; 1417f870bcbeSShivasharan S u16 support_ssc_rev3:1; 1418ede7c3ceSSasikumar Chandrasekaran u16 fw_swaps_bbu_vpd_info:1; 1419ede7c3ceSSasikumar Chandrasekaran u16 support_pd_map_target_id:1; 1420ede7c3ceSSasikumar Chandrasekaran u16 support_ses_ctrl_in_multipathcfg:1; 1421ede7c3ceSSasikumar Chandrasekaran u16 image_upload_supported:1; 1422ede7c3ceSSasikumar Chandrasekaran u16 support_encrypted_mfc:1; 1423ede7c3ceSSasikumar Chandrasekaran u16 supported_enc_algo:1; 1424ede7c3ceSSasikumar Chandrasekaran u16 support_ibutton_less:1; 1425ede7c3ceSSasikumar Chandrasekaran u16 ctrl_info_ext_supported:1; 1426ede7c3ceSSasikumar Chandrasekaran #else 1427ede7c3ceSSasikumar Chandrasekaran 1428ede7c3ceSSasikumar Chandrasekaran u16 ctrl_info_ext_supported:1; 1429ede7c3ceSSasikumar Chandrasekaran u16 support_ibutton_less:1; 1430ede7c3ceSSasikumar Chandrasekaran u16 supported_enc_algo:1; 1431ede7c3ceSSasikumar Chandrasekaran u16 support_encrypted_mfc:1; 1432ede7c3ceSSasikumar Chandrasekaran u16 image_upload_supported:1; 1433ede7c3ceSSasikumar Chandrasekaran /* FW supports LUN based association and target port based */ 1434ede7c3ceSSasikumar Chandrasekaran u16 support_ses_ctrl_in_multipathcfg:1; 1435ede7c3ceSSasikumar Chandrasekaran /* association for the SES device connected in multipath mode */ 1436ede7c3ceSSasikumar Chandrasekaran /* FW defines Jbod target Id within MR_PD_CFG_SEQ */ 1437ede7c3ceSSasikumar Chandrasekaran u16 support_pd_map_target_id:1; 1438ede7c3ceSSasikumar Chandrasekaran /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to 1439ede7c3ceSSasikumar Chandrasekaran * provide the data in little endian order 1440ede7c3ceSSasikumar Chandrasekaran */ 1441ede7c3ceSSasikumar Chandrasekaran u16 fw_swaps_bbu_vpd_info:1; 1442f870bcbeSShivasharan S u16 support_ssc_rev3:1; 1443f870bcbeSShivasharan S /* FW supports CacheCade 3.0, only one SSCD creation allowed */ 1444f870bcbeSShivasharan S u16 support_dual_fw_update:1; 1445f870bcbeSShivasharan S /* FW supports dual firmware update feature */ 1446f870bcbeSShivasharan S u16 support_host_info:1; 1447f870bcbeSShivasharan S /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */ 1448f870bcbeSShivasharan S u16 support_flash_comp_info:1; 1449f870bcbeSShivasharan S /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */ 1450f870bcbeSShivasharan S u16 support_pl_debug_info:1; 1451f870bcbeSShivasharan S /* FW supports retrieval of PL debug information through apps */ 1452f870bcbeSShivasharan S u16 support_nvme_passthru:1; 1453f870bcbeSShivasharan S /* FW supports NVMe passthru commands */ 1454f870bcbeSShivasharan S u16 reserved:2; 1455ede7c3ceSSasikumar Chandrasekaran #endif 1456ede7c3ceSSasikumar Chandrasekaran } adapter_operations4; 1457ede7c3ceSSasikumar Chandrasekaran u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */ 1458e9495e2dSShivasharan S 1459e9495e2dSShivasharan S u32 size; 1460e9495e2dSShivasharan S u32 pad1; 1461e9495e2dSShivasharan S 1462e9495e2dSShivasharan S u8 reserved6[64]; 1463e9495e2dSShivasharan S 1464e9495e2dSShivasharan S u32 rsvdForAdptOp[64]; 1465e9495e2dSShivasharan S 1466e9495e2dSShivasharan S u8 reserved7[3]; 1467e9495e2dSShivasharan S 1468e9495e2dSShivasharan S u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */ 1469e9495e2dSShivasharan S u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */ 1470e9495e2dSShivasharan S u8 reserved8[3]; 147181e403ceSYang, Bo } __packed; 1472c4a3e0a5SBagalkote, Sreenivas 1473c4a3e0a5SBagalkote, Sreenivas /* 1474c4a3e0a5SBagalkote, Sreenivas * =============================== 1475c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 1476c4a3e0a5SBagalkote, Sreenivas * =============================== 1477c4a3e0a5SBagalkote, Sreenivas */ 1478c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 147951087a86SSumit.Saxena@avagotech.com #define MEGASAS_MAX_LD_CHANNELS 2 1480c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1481c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 1482c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1483c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 1484c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 14856bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256 148681e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 148781e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1488bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1489bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1490c4a3e0a5SBagalkote, Sreenivas 14911fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024) 149242a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1493658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 1494658dcedbSSumant Patro 149505e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 149605e9ebbeSSumant Patro 1497def0eab3SShivasharan S /* Driver's internal Logging levels*/ 1498def0eab3SShivasharan S #define OCR_LOGS (1 << 0) 1499def0eab3SShivasharan S 150011c71cb4SSumit Saxena #define SCAN_PD_CHANNEL 0x1 150111c71cb4SSumit Saxena #define SCAN_VD_CHANNEL 0x2 150290dc9d98SSumit.Saxena@avagotech.com 1503c3e385a1SSumit Saxena #define MEGASAS_KDUMP_QUEUE_DEPTH 100 1504a48ba0ecSShivasharan S #define MR_LARGE_IO_MIN_SIZE (32 * 1024) 1505a48ba0ecSShivasharan S #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4 1506c3e385a1SSumit Saxena 15077497cde8SSumit.Saxena@avagotech.com enum MR_SCSI_CMD_TYPE { 15087497cde8SSumit.Saxena@avagotech.com READ_WRITE_LDIO = 0, 15097497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_LDIO = 1, 15107497cde8SSumit.Saxena@avagotech.com READ_WRITE_SYSPDIO = 2, 15117497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_SYSPDIO = 3, 15127497cde8SSumit.Saxena@avagotech.com }; 15137497cde8SSumit.Saxena@avagotech.com 15146d40afbcSSumit Saxena enum DCMD_TIMEOUT_ACTION { 15156d40afbcSSumit Saxena INITIATE_OCR = 0, 15166d40afbcSSumit Saxena KILL_ADAPTER = 1, 15176d40afbcSSumit Saxena IGNORE_TIMEOUT = 2, 15186d40afbcSSumit Saxena }; 1519308ec459SSumit Saxena 1520308ec459SSumit Saxena enum FW_BOOT_CONTEXT { 1521308ec459SSumit Saxena PROBE_CONTEXT = 0, 1522308ec459SSumit Saxena OCR_CONTEXT = 1, 1523308ec459SSumit Saxena }; 1524308ec459SSumit Saxena 1525d532dbe2Sbo yang /* Frame Type */ 1526d532dbe2Sbo yang #define IO_FRAME 0 1527d532dbe2Sbo yang #define PTHRU_FRAME 1 1528d532dbe2Sbo yang 1529c4a3e0a5SBagalkote, Sreenivas /* 1530c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 1531c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1532c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 1533c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 1534c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1535c4a3e0a5SBagalkote, Sreenivas */ 1536c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 15372a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1538c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 1539c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 154005e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1541c5daa6a9Sadam radford #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1542e9495e2dSShivasharan S #define MEGASAS_DEFAULT_TM_TIMEOUT 50 1543c4a3e0a5SBagalkote, Sreenivas /* 1544c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 1545c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 1546c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 1547c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1548c4a3e0a5SBagalkote, Sreenivas * is shown below 1549c4a3e0a5SBagalkote, Sreenivas */ 1550c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 15517bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 1552ec779595SShivasharan S #define MEGASAS_FUSION_INTERNAL_CMDS 8 1553ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_IOCTL_CMDS 3 1554f26ac3a1SSumit.Saxena@avagotech.com #define MEGASAS_MFI_IOCTL_CMDS 27 1555c4a3e0a5SBagalkote, Sreenivas 1556d46a3ad6SSumit.Saxena@lsi.com #define MEGASAS_MAX_MSIX_QUEUES 128 1557c4a3e0a5SBagalkote, Sreenivas /* 1558c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1559c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 1560c4a3e0a5SBagalkote, Sreenivas */ 1561c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1562c4a3e0a5SBagalkote, Sreenivas 156339a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 156439a98554Sbo yang 156539a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 156639a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 156739a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 156839a98554Sbo yang 1569c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 157014faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 15716d40afbcSSumit Saxena #define MFI_IO_TIMEOUT_SECS 180 1572229fe47cSadam radford #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1573229fe47cSadam radford #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 157444e8d693SShivasharan S #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF 1 1575229fe47cSadam radford #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1576f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 15776610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 15786610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 157987911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 158087911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 15810e98936cSSumant Patro 158239a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 158339a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 158439a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 1585d46a3ad6SSumit.Saxena@lsi.com 1586d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1587d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1588d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1589d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_MSIX_REG_ARRAY 16 1590179ac142SSumit Saxena #define MR_RDPQ_MODE_OFFSET 0X00800000 1591d889344eSSasikumar Chandrasekaran 1592d889344eSSasikumar Chandrasekaran #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1593d889344eSSasikumar Chandrasekaran #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1594d889344eSSasikumar Chandrasekaran #define MR_MIN_MAP_SIZE 0x10000 1595d889344eSSasikumar Chandrasekaran /* 64k */ 1596d889344eSSasikumar Chandrasekaran 1597d0fc91d6SKashyap Desai #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 1598d0fc91d6SKashyap Desai 1599107a60ddSShivasharan S #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25) 1600107a60ddSShivasharan S 16013f6194afSShivasharan S #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000 16023f6194afSShivasharan S #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20 16033f6194afSShivasharan S #define MEGASAS_WATCHDOG_WAIT_COUNT 50 16043f6194afSShivasharan S 1605c365178fSShivasharan S enum MR_ADAPTER_TYPE { 1606c365178fSShivasharan S MFI_SERIES = 1, 1607c365178fSShivasharan S THUNDERBOLT_SERIES = 2, 1608c365178fSShivasharan S INVADER_SERIES = 3, 1609c365178fSShivasharan S VENTURA_SERIES = 4, 1610154a7cdeSShivasharan S AERO_SERIES = 5, 1611c365178fSShivasharan S }; 1612c365178fSShivasharan S 16130e98936cSSumant Patro /* 16140e98936cSSumant Patro * register set for both 1068 and 1078 controllers 16150e98936cSSumant Patro * structure extended for 1078 registers 16160e98936cSSumant Patro */ 1617c4a3e0a5SBagalkote, Sreenivas 1618f9876f0bSSumant Patro struct megasas_register_set { 16199c915a8cSadam radford u32 doorbell; /*0000h*/ 16209c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/ 16219c915a8cSadam radford u32 fusion_host_diag; /*0008h*/ 16229c915a8cSadam radford u32 reserved_01; /*000Ch*/ 1623c4a3e0a5SBagalkote, Sreenivas 1624c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 1625c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 1626c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 1627c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 1628c4a3e0a5SBagalkote, Sreenivas 1629c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 1630c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 1631c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 1632c4a3e0a5SBagalkote, Sreenivas 1633c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 1634c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 1635c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 1636c4a3e0a5SBagalkote, Sreenivas 1637c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 1638c4a3e0a5SBagalkote, Sreenivas 1639c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 1640c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 1641c4a3e0a5SBagalkote, Sreenivas 16429c915a8cSadam radford u32 reserved_2[9]; /*0048h*/ 16439c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/ 16449c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/ 1645c4a3e0a5SBagalkote, Sreenivas 1646f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 1647f9876f0bSSumant Patro 1648f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 1649f9876f0bSSumant Patro 165081b76452SShivasharan S u32 outbound_scratch_pad_0; /*00B0h*/ 165181b76452SShivasharan S u32 outbound_scratch_pad_1; /*00B4h*/ 165281b76452SShivasharan S u32 outbound_scratch_pad_2; /*00B8h*/ 165381b76452SShivasharan S u32 outbound_scratch_pad_3; /*00BCh*/ 1654f9876f0bSSumant Patro 1655f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 1656f9876f0bSSumant Patro 1657f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 1658f9876f0bSSumant Patro 165945f4f2ebSSasikumar Chandrasekaran u32 inbound_single_queue_port; /*00C8h*/ 166039a98554Sbo yang u32 res_6[11]; /*CCh*/ 166139a98554Sbo yang u32 host_diag; 166239a98554Sbo yang u32 seq_offset; 166339a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 1664c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1665c4a3e0a5SBagalkote, Sreenivas 1666c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 1667c4a3e0a5SBagalkote, Sreenivas 16689ab9ed38SChristoph Hellwig __le32 phys_addr; 16699ab9ed38SChristoph Hellwig __le32 length; 1670c4a3e0a5SBagalkote, Sreenivas 1671c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1672c4a3e0a5SBagalkote, Sreenivas 1673c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 1674c4a3e0a5SBagalkote, Sreenivas 16759ab9ed38SChristoph Hellwig __le64 phys_addr; 16769ab9ed38SChristoph Hellwig __le32 length; 1677c4a3e0a5SBagalkote, Sreenivas 1678c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1679c4a3e0a5SBagalkote, Sreenivas 1680f4c9a131SYang, Bo struct megasas_sge_skinny { 16819ab9ed38SChristoph Hellwig __le64 phys_addr; 16829ab9ed38SChristoph Hellwig __le32 length; 16839ab9ed38SChristoph Hellwig __le32 flag; 1684f4c9a131SYang, Bo } __packed; 1685f4c9a131SYang, Bo 1686c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 1687c4a3e0a5SBagalkote, Sreenivas 1688c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 1689c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 1690f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 1691c4a3e0a5SBagalkote, Sreenivas 1692c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1693c4a3e0a5SBagalkote, Sreenivas 1694c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 1695c4a3e0a5SBagalkote, Sreenivas 1696c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1697c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1698c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1699c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1700c4a3e0a5SBagalkote, Sreenivas 1701c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1702c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1703c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1704c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1705c4a3e0a5SBagalkote, Sreenivas 17069ab9ed38SChristoph Hellwig __le32 context; /*08h */ 17079ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1708c4a3e0a5SBagalkote, Sreenivas 17099ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 17109ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 17119ab9ed38SChristoph Hellwig __le32 data_xferlen; /*14h */ 1712c4a3e0a5SBagalkote, Sreenivas 1713c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1714c4a3e0a5SBagalkote, Sreenivas 1715c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 1716c4a3e0a5SBagalkote, Sreenivas 1717c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 1718c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 1719c4a3e0a5SBagalkote, Sreenivas 1720c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1721c4a3e0a5SBagalkote, Sreenivas 1722d46a3ad6SSumit.Saxena@lsi.com typedef union _MFI_CAPABILITIES { 1723d46a3ad6SSumit.Saxena@lsi.com struct { 172494cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 1725f6fe5731SShivasharan S u32 reserved:16; 1726f6fe5731SShivasharan S u32 support_fw_exposed_dev_list:1; 1727f870bcbeSShivasharan S u32 support_nvme_passthru:1; 1728107a60ddSShivasharan S u32 support_64bit_mode:1; 1729ede7c3ceSSasikumar Chandrasekaran u32 support_pd_map_target_id:1; 173052b62ac7SSumit Saxena u32 support_qd_throttling:1; 17318f05024cSSumit Saxena u32 support_fp_rlbypass:1; 17328f05024cSSumit Saxena u32 support_vfid_in_ioframe:1; 1733bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 17340be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 17357497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 17367497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 1737d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 173851087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 17397497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 174094cd65ddSSumit.Saxena@lsi.com u32 support_additional_msix:1; 174194cd65ddSSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 174294cd65ddSSumit.Saxena@lsi.com #else 1743d46a3ad6SSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 1744d46a3ad6SSumit.Saxena@lsi.com u32 support_additional_msix:1; 17457497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 174651087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 1747d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 17487497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 17497497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 17500be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 1751bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 17528f05024cSSumit Saxena u32 support_vfid_in_ioframe:1; 17538f05024cSSumit Saxena u32 support_fp_rlbypass:1; 175452b62ac7SSumit Saxena u32 support_qd_throttling:1; 1755ede7c3ceSSasikumar Chandrasekaran u32 support_pd_map_target_id:1; 1756107a60ddSShivasharan S u32 support_64bit_mode:1; 1757f870bcbeSShivasharan S u32 support_nvme_passthru:1; 1758f6fe5731SShivasharan S u32 support_fw_exposed_dev_list:1; 1759f6fe5731SShivasharan S u32 reserved:16; 176094cd65ddSSumit.Saxena@lsi.com #endif 1761d46a3ad6SSumit.Saxena@lsi.com } mfi_capabilities; 17629ab9ed38SChristoph Hellwig __le32 reg; 1763d46a3ad6SSumit.Saxena@lsi.com } MFI_CAPABILITIES; 1764d46a3ad6SSumit.Saxena@lsi.com 1765c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 1766c4a3e0a5SBagalkote, Sreenivas 1767c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1768c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1769c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1770c4a3e0a5SBagalkote, Sreenivas 1771c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 1772d46a3ad6SSumit.Saxena@lsi.com MFI_CAPABILITIES driver_operations; /*04h*/ 1773c4a3e0a5SBagalkote, Sreenivas 17749ab9ed38SChristoph Hellwig __le32 context; /*08h */ 17759ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1776c4a3e0a5SBagalkote, Sreenivas 17779ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 17789ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 17799ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1780c4a3e0a5SBagalkote, Sreenivas 17819ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_lo; /*18h */ 17829ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_hi; /*1Ch */ 17839ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_lo; /*20h */ 17849ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_hi; /*24h */ 17859ab9ed38SChristoph Hellwig __le32 reserved_4[2]; /*28h */ 17869ab9ed38SChristoph Hellwig __le32 system_info_lo; /*30h */ 17879ab9ed38SChristoph Hellwig __le32 system_info_hi; /*34h */ 17889ab9ed38SChristoph Hellwig __le32 reserved_5[2]; /*38h */ 1789c4a3e0a5SBagalkote, Sreenivas 1790c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1791c4a3e0a5SBagalkote, Sreenivas 1792c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 1793c4a3e0a5SBagalkote, Sreenivas 17949ab9ed38SChristoph Hellwig __le32 init_flags; /*00h */ 17959ab9ed38SChristoph Hellwig __le32 reply_queue_entries; /*04h */ 1796c4a3e0a5SBagalkote, Sreenivas 17979ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_lo; /*08h */ 17989ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 17999ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_lo; /*10h */ 18009ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_hi; /*14h */ 18019ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_lo; /*18h */ 18029ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_hi; /*1Ch */ 1803c4a3e0a5SBagalkote, Sreenivas 1804c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1805c4a3e0a5SBagalkote, Sreenivas 1806c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 1807c4a3e0a5SBagalkote, Sreenivas 1808c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1809c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1810c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1811c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1812c4a3e0a5SBagalkote, Sreenivas 1813c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1814c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 1815c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 1816c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1817c4a3e0a5SBagalkote, Sreenivas 18189ab9ed38SChristoph Hellwig __le32 context; /*08h */ 18199ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1820c4a3e0a5SBagalkote, Sreenivas 18219ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 18229ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 18239ab9ed38SChristoph Hellwig __le32 lba_count; /*14h */ 1824c4a3e0a5SBagalkote, Sreenivas 18259ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 18269ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1827c4a3e0a5SBagalkote, Sreenivas 18289ab9ed38SChristoph Hellwig __le32 start_lba_lo; /*20h */ 18299ab9ed38SChristoph Hellwig __le32 start_lba_hi; /*24h */ 1830c4a3e0a5SBagalkote, Sreenivas 1831c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1832c4a3e0a5SBagalkote, Sreenivas 1833c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1834c4a3e0a5SBagalkote, Sreenivas 1835c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 1836c4a3e0a5SBagalkote, Sreenivas 1837c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1838c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1839c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1840c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1841c4a3e0a5SBagalkote, Sreenivas 1842c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1843c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1844c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1845c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1846c4a3e0a5SBagalkote, Sreenivas 18479ab9ed38SChristoph Hellwig __le32 context; /*08h */ 18489ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1849c4a3e0a5SBagalkote, Sreenivas 18509ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 18519ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 18529ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1853c4a3e0a5SBagalkote, Sreenivas 18549ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 18559ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1856c4a3e0a5SBagalkote, Sreenivas 1857c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 1858c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 1859c4a3e0a5SBagalkote, Sreenivas 1860c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1861c4a3e0a5SBagalkote, Sreenivas 1862c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 1863c4a3e0a5SBagalkote, Sreenivas 1864c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1865c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1866c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1867c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 1868c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1869c4a3e0a5SBagalkote, Sreenivas 18709ab9ed38SChristoph Hellwig __le32 context; /*08h */ 18719ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1872c4a3e0a5SBagalkote, Sreenivas 18739ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 18749ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1875c4a3e0a5SBagalkote, Sreenivas 18769ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 18779ab9ed38SChristoph Hellwig __le32 opcode; /*18h */ 1878c4a3e0a5SBagalkote, Sreenivas 1879c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 1880c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 18819ab9ed38SChristoph Hellwig __le16 s[6]; 18829ab9ed38SChristoph Hellwig __le32 w[3]; 1883c4a3e0a5SBagalkote, Sreenivas } mbox; 1884c4a3e0a5SBagalkote, Sreenivas 1885c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1886c4a3e0a5SBagalkote, Sreenivas 1887c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1888c4a3e0a5SBagalkote, Sreenivas 1889c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 1890c4a3e0a5SBagalkote, Sreenivas 1891c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1892c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1893c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1894c4a3e0a5SBagalkote, Sreenivas 1895c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 18969ab9ed38SChristoph Hellwig __le32 reserved_2; /*04h */ 1897c4a3e0a5SBagalkote, Sreenivas 18989ab9ed38SChristoph Hellwig __le32 context; /*08h */ 18999ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1900c4a3e0a5SBagalkote, Sreenivas 19019ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 19029ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 19039ab9ed38SChristoph Hellwig __le32 reserved_4; /*14h */ 1904c4a3e0a5SBagalkote, Sreenivas 19059ab9ed38SChristoph Hellwig __le32 abort_context; /*18h */ 19069ab9ed38SChristoph Hellwig __le32 pad_1; /*1Ch */ 1907c4a3e0a5SBagalkote, Sreenivas 19089ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_lo; /*20h */ 19099ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_hi; /*24h */ 1910c4a3e0a5SBagalkote, Sreenivas 19119ab9ed38SChristoph Hellwig __le32 reserved_5[6]; /*28h */ 1912c4a3e0a5SBagalkote, Sreenivas 1913c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1914c4a3e0a5SBagalkote, Sreenivas 1915c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1916c4a3e0a5SBagalkote, Sreenivas 1917c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1918c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1919c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1920c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1921c4a3e0a5SBagalkote, Sreenivas 1922c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1923c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1924c4a3e0a5SBagalkote, Sreenivas 19259ab9ed38SChristoph Hellwig __le32 context; /*08h */ 19269ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1927c4a3e0a5SBagalkote, Sreenivas 19289ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 19299ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1930c4a3e0a5SBagalkote, Sreenivas 19319ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 19329ab9ed38SChristoph Hellwig __le64 sas_addr; /*18h */ 1933c4a3e0a5SBagalkote, Sreenivas 1934c4a3e0a5SBagalkote, Sreenivas union { 1935c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1936c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1937c4a3e0a5SBagalkote, Sreenivas } sgl; 1938c4a3e0a5SBagalkote, Sreenivas 1939c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1940c4a3e0a5SBagalkote, Sreenivas 1941c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1942c4a3e0a5SBagalkote, Sreenivas 1943c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1944c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1945c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1946c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1947c4a3e0a5SBagalkote, Sreenivas 1948c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1949c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1950c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1951c4a3e0a5SBagalkote, Sreenivas 19529ab9ed38SChristoph Hellwig __le32 context; /*08h */ 19539ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1954c4a3e0a5SBagalkote, Sreenivas 19559ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 19569ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1957c4a3e0a5SBagalkote, Sreenivas 19589ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1959c4a3e0a5SBagalkote, Sreenivas 19609ab9ed38SChristoph Hellwig __le16 fis[10]; /*18h */ 19619ab9ed38SChristoph Hellwig __le32 stp_flags; 1962c4a3e0a5SBagalkote, Sreenivas 1963c4a3e0a5SBagalkote, Sreenivas union { 1964c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1965c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1966c4a3e0a5SBagalkote, Sreenivas } sgl; 1967c4a3e0a5SBagalkote, Sreenivas 1968c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1969c4a3e0a5SBagalkote, Sreenivas 1970c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1971c4a3e0a5SBagalkote, Sreenivas 1972c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1973c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1974c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1975c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1976c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1977c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1978c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1979c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1980c4a3e0a5SBagalkote, Sreenivas 1981c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1982c4a3e0a5SBagalkote, Sreenivas }; 1983c4a3e0a5SBagalkote, Sreenivas 198418365b13SSumit Saxena /** 198518365b13SSumit Saxena * struct MR_PRIV_DEVICE - sdev private hostdata 198618365b13SSumit Saxena * @is_tm_capable: firmware managed tm_capable flag 198718365b13SSumit Saxena * @tm_busy: TM request is in progress 198818365b13SSumit Saxena */ 198918365b13SSumit Saxena struct MR_PRIV_DEVICE { 199018365b13SSumit Saxena bool is_tm_capable; 199118365b13SSumit Saxena bool tm_busy; 1992a48ba0ecSShivasharan S atomic_t r1_ldio_hint; 199315dd0381SShivasharan S u8 interface_type; 1994e9495e2dSShivasharan S u8 task_abort_tmo; 1995e9495e2dSShivasharan S u8 target_reset_tmo; 199618365b13SSumit Saxena }; 1997c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1998c4a3e0a5SBagalkote, Sreenivas 1999c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 2000c4a3e0a5SBagalkote, Sreenivas 2001c4a3e0a5SBagalkote, Sreenivas struct { 2002be26374bSSumit.Saxena@lsi.com #ifndef __BIG_ENDIAN_BITFIELD 2003c4a3e0a5SBagalkote, Sreenivas u16 locale; 2004c4a3e0a5SBagalkote, Sreenivas u8 reserved; 2005c4a3e0a5SBagalkote, Sreenivas s8 class; 2006be26374bSSumit.Saxena@lsi.com #else 2007be26374bSSumit.Saxena@lsi.com s8 class; 2008be26374bSSumit.Saxena@lsi.com u8 reserved; 2009be26374bSSumit.Saxena@lsi.com u16 locale; 2010be26374bSSumit.Saxena@lsi.com #endif 2011c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 2012c4a3e0a5SBagalkote, Sreenivas 2013c4a3e0a5SBagalkote, Sreenivas u32 word; 2014c4a3e0a5SBagalkote, Sreenivas 2015c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2016c4a3e0a5SBagalkote, Sreenivas 2017c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 20189ab9ed38SChristoph Hellwig __le32 newest_seq_num; 20199ab9ed38SChristoph Hellwig __le32 oldest_seq_num; 20209ab9ed38SChristoph Hellwig __le32 clear_seq_num; 20219ab9ed38SChristoph Hellwig __le32 shutdown_seq_num; 20229ab9ed38SChristoph Hellwig __le32 boot_seq_num; 2023c4a3e0a5SBagalkote, Sreenivas 2024c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2025c4a3e0a5SBagalkote, Sreenivas 2026c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 2027c4a3e0a5SBagalkote, Sreenivas 20289ab9ed38SChristoph Hellwig __le16 progress; 20299ab9ed38SChristoph Hellwig __le16 elapsed_seconds; 2030c4a3e0a5SBagalkote, Sreenivas 2031c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2032c4a3e0a5SBagalkote, Sreenivas 2033c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 2034c4a3e0a5SBagalkote, Sreenivas 2035c4a3e0a5SBagalkote, Sreenivas u16 target_id; 2036c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 2037c4a3e0a5SBagalkote, Sreenivas u8 reserved; 2038c4a3e0a5SBagalkote, Sreenivas 2039c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2040c4a3e0a5SBagalkote, Sreenivas 2041c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 2042c4a3e0a5SBagalkote, Sreenivas u16 device_id; 2043c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 2044c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 2045c4a3e0a5SBagalkote, Sreenivas 2046c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2047c4a3e0a5SBagalkote, Sreenivas 2048c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 2049c4a3e0a5SBagalkote, Sreenivas 20509ab9ed38SChristoph Hellwig __le32 seq_num; 20519ab9ed38SChristoph Hellwig __le32 time_stamp; 20529ab9ed38SChristoph Hellwig __le32 code; 2053c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 2054c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 2055c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 2056c4a3e0a5SBagalkote, Sreenivas 2057c4a3e0a5SBagalkote, Sreenivas union { 2058c4a3e0a5SBagalkote, Sreenivas struct { 2059c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2060c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 2061c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 2062c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 2063c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 2064c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 2065c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 2066c4a3e0a5SBagalkote, Sreenivas 2067c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2068c4a3e0a5SBagalkote, Sreenivas 2069c4a3e0a5SBagalkote, Sreenivas struct { 2070c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 20719ab9ed38SChristoph Hellwig __le64 count; 2072c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 2073c4a3e0a5SBagalkote, Sreenivas 2074c4a3e0a5SBagalkote, Sreenivas struct { 20759ab9ed38SChristoph Hellwig __le64 lba; 2076c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2077c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 2078c4a3e0a5SBagalkote, Sreenivas 2079c4a3e0a5SBagalkote, Sreenivas struct { 2080c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 20819ab9ed38SChristoph Hellwig __le32 prevOwner; 20829ab9ed38SChristoph Hellwig __le32 newOwner; 2083c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 2084c4a3e0a5SBagalkote, Sreenivas 2085c4a3e0a5SBagalkote, Sreenivas struct { 2086c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 2087c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 2088c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2089c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2090c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 2091c4a3e0a5SBagalkote, Sreenivas 2092c4a3e0a5SBagalkote, Sreenivas struct { 2093c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2094c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 2095c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 2096c4a3e0a5SBagalkote, Sreenivas 2097c4a3e0a5SBagalkote, Sreenivas struct { 2098c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2099c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 2100c4a3e0a5SBagalkote, Sreenivas u32 new_state; 2101c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 2102c4a3e0a5SBagalkote, Sreenivas 2103c4a3e0a5SBagalkote, Sreenivas struct { 2104c4a3e0a5SBagalkote, Sreenivas u64 strip; 2105c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2106c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 2107c4a3e0a5SBagalkote, Sreenivas 2108c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2109c4a3e0a5SBagalkote, Sreenivas 2110c4a3e0a5SBagalkote, Sreenivas struct { 2111c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2112c4a3e0a5SBagalkote, Sreenivas u32 err; 2113c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 2114c4a3e0a5SBagalkote, Sreenivas 2115c4a3e0a5SBagalkote, Sreenivas struct { 2116c4a3e0a5SBagalkote, Sreenivas u64 lba; 2117c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2118c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 2119c4a3e0a5SBagalkote, Sreenivas 2120c4a3e0a5SBagalkote, Sreenivas struct { 2121c4a3e0a5SBagalkote, Sreenivas u64 lba; 2122c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2123c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 2124c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 2125c4a3e0a5SBagalkote, Sreenivas 2126c4a3e0a5SBagalkote, Sreenivas struct { 2127c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2128c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 2129c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 2130c4a3e0a5SBagalkote, Sreenivas 2131c4a3e0a5SBagalkote, Sreenivas struct { 2132c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 2133c4a3e0a5SBagalkote, Sreenivas u32 prevState; 2134c4a3e0a5SBagalkote, Sreenivas u32 newState; 2135c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 2136c4a3e0a5SBagalkote, Sreenivas 2137c4a3e0a5SBagalkote, Sreenivas struct { 2138c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 21399ab9ed38SChristoph Hellwig __le16 deviceId; 2140c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 2141c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 2142c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 2143c4a3e0a5SBagalkote, Sreenivas 2144c4a3e0a5SBagalkote, Sreenivas u32 rate; 2145c4a3e0a5SBagalkote, Sreenivas char str[96]; 2146c4a3e0a5SBagalkote, Sreenivas 2147c4a3e0a5SBagalkote, Sreenivas struct { 2148c4a3e0a5SBagalkote, Sreenivas u32 rtc; 2149c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 2150c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 2151c4a3e0a5SBagalkote, Sreenivas 2152c4a3e0a5SBagalkote, Sreenivas struct { 2153c4a3e0a5SBagalkote, Sreenivas u32 ecar; 2154c4a3e0a5SBagalkote, Sreenivas u32 elog; 2155c4a3e0a5SBagalkote, Sreenivas char str[64]; 2156c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 2157c4a3e0a5SBagalkote, Sreenivas 2158c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 21599ab9ed38SChristoph Hellwig __le16 s[48]; 21609ab9ed38SChristoph Hellwig __le32 w[24]; 21619ab9ed38SChristoph Hellwig __le64 d[12]; 2162c4a3e0a5SBagalkote, Sreenivas } args; 2163c4a3e0a5SBagalkote, Sreenivas 2164c4a3e0a5SBagalkote, Sreenivas char description[128]; 2165c4a3e0a5SBagalkote, Sreenivas 2166c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2167c4a3e0a5SBagalkote, Sreenivas 21687e8a75f4SYang, Bo struct megasas_aen_event { 2169c1d390d8SXiaotian Feng struct delayed_work hotplug_work; 21707e8a75f4SYang, Bo struct megasas_instance *instance; 21717e8a75f4SYang, Bo }; 21727e8a75f4SYang, Bo 2173c8e858feSadam radford struct megasas_irq_context { 2174c8e858feSadam radford struct megasas_instance *instance; 2175c8e858feSadam radford u32 MSIxIndex; 217662a04f81SShivasharan S u32 os_irq; 217762a04f81SShivasharan S struct irq_poll irqpoll; 217862a04f81SShivasharan S bool irq_poll_scheduled; 2179c8e858feSadam radford }; 2180c8e858feSadam radford 21815765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO { 21825765c5b8SSumit.Saxena@avagotech.com u8 infoVersion; 21835765c5b8SSumit.Saxena@avagotech.com u8 systemIdLength; 21845765c5b8SSumit.Saxena@avagotech.com u16 reserved0; 21855765c5b8SSumit.Saxena@avagotech.com u8 systemId[64]; 21865765c5b8SSumit.Saxena@avagotech.com u8 reserved[1980]; 21875765c5b8SSumit.Saxena@avagotech.com }; 21885765c5b8SSumit.Saxena@avagotech.com 21892216c305SSumit Saxena enum MR_PD_TYPE { 21902216c305SSumit Saxena UNKNOWN_DRIVE = 0, 21912216c305SSumit Saxena PARALLEL_SCSI = 1, 21922216c305SSumit Saxena SAS_PD = 2, 21932216c305SSumit Saxena SATA_PD = 3, 21942216c305SSumit Saxena FC_PD = 4, 219515dd0381SShivasharan S NVME_PD = 5, 21962216c305SSumit Saxena }; 21972216c305SSumit Saxena 21982216c305SSumit Saxena /* JBOD Queue depth definitions */ 21992216c305SSumit Saxena #define MEGASAS_SATA_QD 32 22002216c305SSumit Saxena #define MEGASAS_SAS_QD 64 22012216c305SSumit Saxena #define MEGASAS_DEFAULT_PD_QD 64 220215dd0381SShivasharan S #define MEGASAS_NVME_QD 32 220315dd0381SShivasharan S 220415dd0381SShivasharan S #define MR_DEFAULT_NVME_PAGE_SIZE 4096 220515dd0381SShivasharan S #define MR_DEFAULT_NVME_PAGE_SHIFT 12 220615dd0381SShivasharan S #define MR_DEFAULT_NVME_MDTS_KB 128 220715dd0381SShivasharan S #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 22082216c305SSumit Saxena 2209c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 2210c4a3e0a5SBagalkote, Sreenivas 2211adbe5523SMing Lei unsigned int *reply_map; 22129ab9ed38SChristoph Hellwig __le32 *producer; 2213c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 22149ab9ed38SChristoph Hellwig __le32 *consumer; 2215c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 22165765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO *system_info_buf; 22175765c5b8SSumit.Saxena@avagotech.com dma_addr_t system_info_h; 2218229fe47cSadam radford struct MR_LD_VF_AFFILIATION *vf_affiliation; 2219229fe47cSadam radford dma_addr_t vf_affiliation_h; 2220229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2221229fe47cSadam radford dma_addr_t vf_affiliation_111_h; 2222229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2223229fe47cSadam radford dma_addr_t hb_host_mem_h; 22242216c305SSumit Saxena struct MR_PD_INFO *pd_info; 22252216c305SSumit Saxena dma_addr_t pd_info_h; 222696188a89SShivasharan S struct MR_TARGET_PROPERTIES *tgt_prop; 222796188a89SShivasharan S dma_addr_t tgt_prop_h; 2228c4a3e0a5SBagalkote, Sreenivas 22299ab9ed38SChristoph Hellwig __le32 *reply_queue; 2230c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 2231c4a3e0a5SBagalkote, Sreenivas 2232fc62b3fcSSumit.Saxena@avagotech.com u32 *crash_dump_buf; 2233fc62b3fcSSumit.Saxena@avagotech.com dma_addr_t crash_dump_h; 22349b3d028fSShivasharan S 22359b3d028fSShivasharan S struct MR_PD_LIST *pd_list_buf; 22369b3d028fSShivasharan S dma_addr_t pd_list_buf_h; 22379b3d028fSShivasharan S 22389b3d028fSShivasharan S struct megasas_ctrl_info *ctrl_info_buf; 22399b3d028fSShivasharan S dma_addr_t ctrl_info_buf_h; 22409b3d028fSShivasharan S 22419b3d028fSShivasharan S struct MR_LD_LIST *ld_list_buf; 22429b3d028fSShivasharan S dma_addr_t ld_list_buf_h; 22439b3d028fSShivasharan S 22449b3d028fSShivasharan S struct MR_LD_TARGETID_LIST *ld_targetid_list_buf; 22459b3d028fSShivasharan S dma_addr_t ld_targetid_list_buf_h; 22469b3d028fSShivasharan S 2247f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST *host_device_list_buf; 2248f6fe5731SShivasharan S dma_addr_t host_device_list_buf_h; 2249f6fe5731SShivasharan S 2250f0c21df6SShivasharan S struct MR_SNAPDUMP_PROPERTIES *snapdump_prop; 2251f0c21df6SShivasharan S dma_addr_t snapdump_prop_h; 2252f0c21df6SShivasharan S 2253fc62b3fcSSumit.Saxena@avagotech.com void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2254fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_size; 2255fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_state; 2256fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_offset; 2257fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_index; 2258fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_alloc; 2259fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_fw_support; 2260fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_drv_support; 2261fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_app_support; 22627497cde8SSumit.Saxena@avagotech.com u32 secure_jbod_support; 2263ede7c3ceSSasikumar Chandrasekaran u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ 22643761cb4cSsumit.saxena@avagotech.com bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2265fc62b3fcSSumit.Saxena@avagotech.com spinlock_t crashdump_lock; 2266fc62b3fcSSumit.Saxena@avagotech.com 2267c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 22688a232bb3SChristoph Hellwig u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 226981e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2270999ece0aSSumit.Saxena@lsi.com struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2271bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2272c4a3e0a5SBagalkote, Sreenivas s8 init_id; 2273c4a3e0a5SBagalkote, Sreenivas 2274c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 2275c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 227669c337c0SSasikumar Chandrasekaran u16 max_mpt_cmds; 22779c915a8cSadam radford u16 max_mfi_cmds; 2278ae09a6c1SSumit.Saxena@avagotech.com u16 max_scsi_cmds; 2279308ec459SSumit Saxena u16 ldio_threshold; 2280308ec459SSumit Saxena u16 cur_can_queue; 2281c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 22827e8a75f4SYang, Bo struct megasas_aen_event *ev; 2283c4a3e0a5SBagalkote, Sreenivas 2284c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 2285c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 228639a98554Sbo yang /* used to sync fire the cmd to fw */ 228790dc9d98SSumit.Saxena@avagotech.com spinlock_t mfi_pool_lock; 228839a98554Sbo yang /* used to sync fire the cmd to fw */ 228939a98554Sbo yang spinlock_t hba_lock; 22907343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 2291fdd84e25SSasikumar Chandrasekaran spinlock_t stream_lock; 22927343eb65Sbo yang spinlock_t completion_lock; 2293c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 2294c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 2295c4a3e0a5SBagalkote, Sreenivas 2296c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 2297c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 2298c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 2299c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 2300c4a3e0a5SBagalkote, Sreenivas 2301c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 2302c4a3e0a5SBagalkote, Sreenivas 2303c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 2304c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 2305c4a3e0a5SBagalkote, Sreenivas 2306c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 2307c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 230839a98554Sbo yang u32 fw_support_ieee; 230962a04f81SShivasharan S u32 threshold_reply_count; 2310c4a3e0a5SBagalkote, Sreenivas 2311e4a082c7SSumant Patro atomic_t fw_outstanding; 2312308ec459SSumit Saxena atomic_t ldio_outstanding; 231339a98554Sbo yang atomic_t fw_reset_no_pci_access; 231433203bc4SShivasharan S atomic_t ieee_sgl; 231533203bc4SShivasharan S atomic_t prp_sgl; 231633203bc4SShivasharan S atomic_t sge_holes_type1; 231733203bc4SShivasharan S atomic_t sge_holes_type2; 231833203bc4SShivasharan S atomic_t sge_holes_type3; 23191341c939SSumant Patro 23201341c939SSumant Patro struct megasas_instance_template *instancet; 23215d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 232239a98554Sbo yang struct work_struct work_init; 23233f6194afSShivasharan S struct delayed_work fw_fault_work; 23243f6194afSShivasharan S struct workqueue_struct *fw_fault_work_q; 23253f6194afSShivasharan S char fault_handler_work_q_name[48]; 232605e9ebbeSSumant Patro 232705e9ebbeSSumant Patro u8 flag; 2328c3518837SYang, Bo u8 unload; 2329f4c9a131SYang, Bo u8 flag_ieee; 233039a98554Sbo yang u8 issuepend_done; 233139a98554Sbo yang u8 disableOnlineCtrlReset; 2332bc93d425SSumit.Saxena@lsi.com u8 UnevenSpanSupport; 233351087a86SSumit.Saxena@avagotech.com 233451087a86SSumit.Saxena@avagotech.com u8 supportmax256vd; 233530845586SSumit Saxena u8 pd_list_not_supported; 233651087a86SSumit.Saxena@avagotech.com u16 fw_supported_vd_count; 233751087a86SSumit.Saxena@avagotech.com u16 fw_supported_pd_count; 233851087a86SSumit.Saxena@avagotech.com 233951087a86SSumit.Saxena@avagotech.com u16 drv_supported_vd_count; 234051087a86SSumit.Saxena@avagotech.com u16 drv_supported_pd_count; 234151087a86SSumit.Saxena@avagotech.com 23428a01a41dSSumit Saxena atomic_t adprecovery; 234305e9ebbeSSumant Patro unsigned long last_time; 234439a98554Sbo yang u32 mfiStatus; 234539a98554Sbo yang u32 last_seq_num; 2346ad84db2eSbo yang 234739a98554Sbo yang struct list_head internal_reset_pending_q; 234880d9da98Sadam radford 234925985edcSLucas De Marchi /* Ptr to hba specific information */ 23509c915a8cSadam radford void *ctrl_context; 2351c8e858feSadam radford unsigned int msix_vectors; 2352c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 23539c915a8cSadam radford u64 map_id; 23543761cb4cSsumit.saxena@avagotech.com u64 pd_seq_map_id; 23559c915a8cSadam radford struct megasas_cmd *map_update_cmd; 23563761cb4cSsumit.saxena@avagotech.com struct megasas_cmd *jbod_seq_cmd; 2357b6d5d880Sadam radford unsigned long bar; 23589c915a8cSadam radford long reset_flags; 23599c915a8cSadam radford struct mutex reset_mutex; 2360229fe47cSadam radford struct timer_list sriov_heartbeat_timer; 2361229fe47cSadam radford char skip_heartbeat_timer_del; 2362229fe47cSadam radford u8 requestorId; 2363229fe47cSadam radford char PlasmaFW111; 23648f67c8c5SSumit Saxena char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 23658f67c8c5SSumit Saxena u8 peerIsPresent; 23668f67c8c5SSumit Saxena u8 passive; 2367ae09a6c1SSumit.Saxena@avagotech.com u16 throttlequeuedepth; 2368d46a3ad6SSumit.Saxena@lsi.com u8 mask_interrupts; 2369bd5f9484Ssumit.saxena@avagotech.com u16 max_chain_frame_sz; 2370404a8a1aSSumit.Saxena@lsi.com u8 is_imr; 2371179ac142SSumit Saxena u8 is_rdpq; 23725765c5b8SSumit.Saxena@avagotech.com bool dev_handle; 2373d0fc91d6SKashyap Desai bool fw_sync_cache_support; 237421c34006SShivasharan S u32 mfi_frame_size; 23752493c67eSSasikumar Chandrasekaran bool msix_combined; 2376d889344eSSasikumar Chandrasekaran u16 max_raid_mapsize; 2377a48ba0ecSShivasharan S /* preffered count to send as LDIO irrspective of FP capable.*/ 2378a48ba0ecSShivasharan S u8 r1_ldio_hint_default; 237915dd0381SShivasharan S u32 nvme_page_size; 2380c365178fSShivasharan S u8 adapter_type; 2381107a60ddSShivasharan S bool consistent_mask_64bit; 2382f870bcbeSShivasharan S bool support_nvme_passthru; 2383e9495e2dSShivasharan S u8 task_abort_tmo; 2384e9495e2dSShivasharan S u8 max_reset_tmo; 2385f0c21df6SShivasharan S u8 snapdump_wait_time; 2386f6fe5731SShivasharan S u8 enable_fw_dev_list; 238739a98554Sbo yang }; 2388229fe47cSadam radford struct MR_LD_VF_MAP { 2389229fe47cSadam radford u32 size; 2390229fe47cSadam radford union MR_LD_REF ref; 2391229fe47cSadam radford u8 ldVfCount; 2392229fe47cSadam radford u8 reserved[6]; 2393229fe47cSadam radford u8 policy[1]; 2394229fe47cSadam radford }; 2395229fe47cSadam radford 2396229fe47cSadam radford struct MR_LD_VF_AFFILIATION { 2397229fe47cSadam radford u32 size; 2398229fe47cSadam radford u8 ldCount; 2399229fe47cSadam radford u8 vfCount; 2400229fe47cSadam radford u8 thisVf; 2401229fe47cSadam radford u8 reserved[9]; 2402229fe47cSadam radford struct MR_LD_VF_MAP map[1]; 2403229fe47cSadam radford }; 2404229fe47cSadam radford 2405229fe47cSadam radford /* Plasma 1.11 FW backward compatibility structures */ 2406229fe47cSadam radford #define IOV_111_OFFSET 0x7CE 2407229fe47cSadam radford #define MAX_VIRTUAL_FUNCTIONS 8 24084cbfea88SAdam Radford #define MR_LD_ACCESS_HIDDEN 15 2409229fe47cSadam radford 2410229fe47cSadam radford struct IOV_111 { 2411229fe47cSadam radford u8 maxVFsSupported; 2412229fe47cSadam radford u8 numVFsEnabled; 2413229fe47cSadam radford u8 requestorId; 2414229fe47cSadam radford u8 reserved[5]; 2415229fe47cSadam radford }; 2416229fe47cSadam radford 2417229fe47cSadam radford struct MR_LD_VF_MAP_111 { 2418229fe47cSadam radford u8 targetId; 2419229fe47cSadam radford u8 reserved[3]; 2420229fe47cSadam radford u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2421229fe47cSadam radford }; 2422229fe47cSadam radford 2423229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 { 2424229fe47cSadam radford u8 vdCount; 2425229fe47cSadam radford u8 vfCount; 2426229fe47cSadam radford u8 thisVf; 2427229fe47cSadam radford u8 reserved[5]; 2428229fe47cSadam radford struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2429229fe47cSadam radford }; 2430229fe47cSadam radford 2431229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM { 2432229fe47cSadam radford struct { 2433229fe47cSadam radford u32 fwCounter; /* Firmware heart beat counter */ 2434229fe47cSadam radford struct { 2435229fe47cSadam radford u32 debugmode:1; /* 1=Firmware is in debug mode. 2436229fe47cSadam radford Heart beat will not be updated. */ 2437229fe47cSadam radford u32 reserved:31; 2438229fe47cSadam radford } debug; 2439229fe47cSadam radford u32 reserved_fw[6]; 2440229fe47cSadam radford u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2441229fe47cSadam radford u32 reserved_driver[7]; 2442229fe47cSadam radford } HB; 2443229fe47cSadam radford u8 pad[0x400-0x40]; 2444229fe47cSadam radford }; 244539a98554Sbo yang 244639a98554Sbo yang enum { 244739a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 244839a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 244939a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 245039a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 245139a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 2452229fe47cSadam radford MEGASAS_ADPRESET_SM_POLLING = 5, 245339a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2454c4a3e0a5SBagalkote, Sreenivas }; 2455c4a3e0a5SBagalkote, Sreenivas 24560c79e681SYang, Bo struct megasas_instance_template { 24570c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 24580c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 24590c79e681SYang, Bo 2460d46a3ad6SSumit.Saxena@lsi.com void (*enable_intr)(struct megasas_instance *); 2461d46a3ad6SSumit.Saxena@lsi.com void (*disable_intr)(struct megasas_instance *); 24620c79e681SYang, Bo 2463de516379SShivasharan S int (*clear_intr)(struct megasas_instance *); 24640c79e681SYang, Bo 2465de516379SShivasharan S u32 (*read_fw_status_reg)(struct megasas_instance *); 246639a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 246739a98554Sbo yang struct megasas_register_set __iomem *); 246839a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 246939a98554Sbo yang struct megasas_register_set __iomem *); 2470cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp); 2471cd50ba8eSadam radford void (*tasklet)(unsigned long); 2472cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *); 2473cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *, 2474cd50ba8eSadam radford struct scsi_cmnd *); 2475f4fc2093SShivasharan S void (*issue_dcmd)(struct megasas_instance *instance, 2476cd50ba8eSadam radford struct megasas_cmd *cmd); 24770c79e681SYang, Bo }; 24780c79e681SYang, Bo 24793cabd162SShivasharan S #define MEGASAS_IS_LOGICAL(sdev) \ 24803cabd162SShivasharan S ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) 2481c4a3e0a5SBagalkote, Sreenivas 24824a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_DEV_INDEX(scp) \ 24834a5c814dSSumit.Saxena@avagotech.com (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 24844a5c814dSSumit.Saxena@avagotech.com scp->device->id) 24854a5c814dSSumit.Saxena@avagotech.com 24864a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_PD_INDEX(scp) \ 24874a5c814dSSumit.Saxena@avagotech.com ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 24884a5c814dSSumit.Saxena@avagotech.com scp->device->id) 2489c4a3e0a5SBagalkote, Sreenivas 2490c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 2491c4a3e0a5SBagalkote, Sreenivas 2492c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 2493c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 2494c4a3e0a5SBagalkote, Sreenivas u8 *sense; 2495c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 2496c4a3e0a5SBagalkote, Sreenivas 2497c4a3e0a5SBagalkote, Sreenivas u32 index; 2498c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 24992be2a988SSumit.Saxena@avagotech.com u8 cmd_status_drv; 250039a98554Sbo yang u8 abort_aen; 250139a98554Sbo yang u8 retry_for_fw_reset; 250239a98554Sbo yang 2503c4a3e0a5SBagalkote, Sreenivas 2504c4a3e0a5SBagalkote, Sreenivas struct list_head list; 2505c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 25064026e9aaSSumit.Saxena@avagotech.com u8 flags; 250790dc9d98SSumit.Saxena@avagotech.com 2508c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 25099c915a8cSadam radford union { 25109c915a8cSadam radford struct { 25119c915a8cSadam radford u16 smid; 25129c915a8cSadam radford u16 resvd; 25139c915a8cSadam radford } context; 2514c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 2515c4a3e0a5SBagalkote, Sreenivas }; 25169c915a8cSadam radford }; 2517c4a3e0a5SBagalkote, Sreenivas 2518c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 2519c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 2520c4a3e0a5SBagalkote, Sreenivas 2521c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 2522c4a3e0a5SBagalkote, Sreenivas 2523c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2524c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2525c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 2526c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 2527c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 2528c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 2529c4a3e0a5SBagalkote, Sreenivas union { 2530c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 2531c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 2532c4a3e0a5SBagalkote, Sreenivas } frame; 2533c4a3e0a5SBagalkote, Sreenivas 2534c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 2535c4a3e0a5SBagalkote, Sreenivas 2536c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2537c4a3e0a5SBagalkote, Sreenivas 2538c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 2539c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2540c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2541c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 2542c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 2543c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2544c4a3e0a5SBagalkote, Sreenivas 2545c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 2546c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 2547c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2548c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2549c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 2550c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 2551c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 2552c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 2553c4a3e0a5SBagalkote, Sreenivas union { 2554c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 2555c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 2556c4a3e0a5SBagalkote, Sreenivas } frame; 2557c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 2558c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2559c4a3e0a5SBagalkote, Sreenivas 25600e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2561c4a3e0a5SBagalkote, Sreenivas #endif 2562c4a3e0a5SBagalkote, Sreenivas 2563cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2564c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2565c4a3e0a5SBagalkote, Sreenivas 2566c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 2567c4a3e0a5SBagalkote, Sreenivas 2568c4a3e0a5SBagalkote, Sreenivas u16 count; 2569c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2570c4a3e0a5SBagalkote, Sreenivas int max_index; 2571c4a3e0a5SBagalkote, Sreenivas }; 2572c4a3e0a5SBagalkote, Sreenivas 25736d40afbcSSumit Saxena enum MEGASAS_OCR_CAUSE { 25746d40afbcSSumit Saxena FW_FAULT_OCR = 0, 25756d40afbcSSumit Saxena SCSIIO_TIMEOUT_OCR = 1, 25766d40afbcSSumit Saxena MFI_IO_TIMEOUT_OCR = 2, 25776d40afbcSSumit Saxena }; 25786d40afbcSSumit Saxena 25796d40afbcSSumit Saxena enum DCMD_RETURN_STATUS { 25806d40afbcSSumit Saxena DCMD_SUCCESS = 0, 25816d40afbcSSumit Saxena DCMD_TIMEOUT = 1, 25826d40afbcSSumit Saxena DCMD_FAILED = 2, 25836d40afbcSSumit Saxena DCMD_NOT_FIRED = 3, 25846d40afbcSSumit Saxena }; 25856d40afbcSSumit Saxena 258621c9e160Sadam radford u8 258721c9e160Sadam radford MR_BuildRaidContext(struct megasas_instance *instance, 258821c9e160Sadam radford struct IO_REQUEST_INFO *io_info, 258921c9e160Sadam radford struct RAID_CONTEXT *pRAID_Context, 259051087a86SSumit.Saxena@avagotech.com struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2591d2d0358bSShivasharan S u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 259251087a86SSumit.Saxena@avagotech.com struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 259351087a86SSumit.Saxena@avagotech.com u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 259451087a86SSumit.Saxena@avagotech.com u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 25959ab9ed38SChristoph Hellwig __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 259651087a86SSumit.Saxena@avagotech.com u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 259721c9e160Sadam radford 25989ab9ed38SChristoph Hellwig __le16 get_updated_dev_handle(struct megasas_instance *instance, 259933203bc4SShivasharan S struct LD_LOAD_BALANCE_INFO *lbInfo, 260033203bc4SShivasharan S struct IO_REQUEST_INFO *in_info, 260133203bc4SShivasharan S struct MR_DRV_RAID_MAP_ALL *drv_map); 260251087a86SSumit.Saxena@avagotech.com void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 260351087a86SSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo); 2604d009b576SSumit.Saxena@avagotech.com int megasas_get_ctrl_info(struct megasas_instance *instance); 26053761cb4cSsumit.saxena@avagotech.com /* PD sequence */ 26063761cb4cSsumit.saxena@avagotech.com int 26073761cb4cSsumit.saxena@avagotech.com megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2608e9495e2dSShivasharan S void megasas_set_dynamic_target_properties(struct scsi_device *sdev, 2609e9495e2dSShivasharan S bool is_target_prop); 2610e9495e2dSShivasharan S int megasas_get_target_prop(struct megasas_instance *instance, 2611e9495e2dSShivasharan S struct scsi_device *sdev); 2612f0c21df6SShivasharan S void megasas_get_snapdump_properties(struct megasas_instance *instance); 2613e9495e2dSShivasharan S 2614fc62b3fcSSumit.Saxena@avagotech.com int megasas_set_crash_dump_params(struct megasas_instance *instance, 2615fc62b3fcSSumit.Saxena@avagotech.com u8 crash_buf_state); 2616fc62b3fcSSumit.Saxena@avagotech.com void megasas_free_host_crash_buffer(struct megasas_instance *instance); 261751087a86SSumit.Saxena@avagotech.com 261890dc9d98SSumit.Saxena@avagotech.com void megasas_return_cmd_fusion(struct megasas_instance *instance, 261990dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd_fusion *cmd); 262090dc9d98SSumit.Saxena@avagotech.com int megasas_issue_blocked_cmd(struct megasas_instance *instance, 262190dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd, int timeout); 262290dc9d98SSumit.Saxena@avagotech.com void __megasas_return_cmd(struct megasas_instance *instance, 262390dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd); 262490dc9d98SSumit.Saxena@avagotech.com 262590dc9d98SSumit.Saxena@avagotech.com void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 262690dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 26277497cde8SSumit.Saxena@avagotech.com int megasas_cmd_type(struct scsi_cmnd *cmd); 26283761cb4cSsumit.saxena@avagotech.com void megasas_setup_jbod_map(struct megasas_instance *instance); 262990dc9d98SSumit.Saxena@avagotech.com 263018365b13SSumit Saxena void megasas_update_sdev_properties(struct scsi_device *sdev); 263118365b13SSumit Saxena int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 263218365b13SSumit Saxena int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 263318365b13SSumit Saxena int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 263433203bc4SShivasharan S u32 mega_mod64(u64 dividend, u32 divisor); 26355fc499b6SShivasharan S int megasas_alloc_fusion_context(struct megasas_instance *instance); 26365fc499b6SShivasharan S void megasas_free_fusion_context(struct megasas_instance *instance); 26373f6194afSShivasharan S int megasas_fusion_start_watchdog(struct megasas_instance *instance); 26383f6194afSShivasharan S void megasas_fusion_stop_watchdog(struct megasas_instance *instance); 26393f6194afSShivasharan S 2640107a60ddSShivasharan S void megasas_set_dma_settings(struct megasas_instance *instance, 2641107a60ddSShivasharan S struct megasas_dcmd_frame *dcmd, 2642107a60ddSShivasharan S dma_addr_t dma_addr, u32 dma_len); 264378409d4bSShivasharan S int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance, 264478409d4bSShivasharan S bool do_adp_reset, 264578409d4bSShivasharan S int ocr_context); 264662a04f81SShivasharan S int megasas_irqpoll(struct irq_poll *irqpoll, int budget); 2647c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 2648