1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * 3c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 4c4a3e0a5SBagalkote, Sreenivas * 5f28cd7cfSbo yang * Copyright (c) 2003-2005 LSI Corporation. 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 9c4a3e0a5SBagalkote, Sreenivas * as published by the Free Software Foundation; either version 10c4a3e0a5SBagalkote, Sreenivas * 2 of the License, or (at your option) any later version. 11c4a3e0a5SBagalkote, Sreenivas * 12c4a3e0a5SBagalkote, Sreenivas * FILE : megaraid_sas.h 13c4a3e0a5SBagalkote, Sreenivas */ 14c4a3e0a5SBagalkote, Sreenivas 15c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 16c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 17c4a3e0a5SBagalkote, Sreenivas 18a69b74d3SRandy Dunlap /* 19c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 20c4a3e0a5SBagalkote, Sreenivas */ 2163bad45dSYang, Bo #define MEGASAS_VERSION "00.00.04.17.1-rc1" 2263bad45dSYang, Bo #define MEGASAS_RELDATE "Oct. 29, 2009" 2363bad45dSYang, Bo #define MEGASAS_EXT_VERSION "Thu. Oct. 29, 11:41:51 PST 2009" 240e98936cSSumant Patro 250e98936cSSumant Patro /* 260e98936cSSumant Patro * Device IDs 270e98936cSSumant Patro */ 280e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 29af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 300e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 316610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 326610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 3387911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 3487911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 350e98936cSSumant Patro 36c4a3e0a5SBagalkote, Sreenivas /* 37c4a3e0a5SBagalkote, Sreenivas * ===================================== 38c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 39c4a3e0a5SBagalkote, Sreenivas * ===================================== 40c4a3e0a5SBagalkote, Sreenivas */ 41c4a3e0a5SBagalkote, Sreenivas 42c4a3e0a5SBagalkote, Sreenivas /* 43c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 44c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 45c4a3e0a5SBagalkote, Sreenivas * "message frames" 46c4a3e0a5SBagalkote, Sreenivas */ 47c4a3e0a5SBagalkote, Sreenivas 48a69b74d3SRandy Dunlap /* 49c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 50c4a3e0a5SBagalkote, Sreenivas */ 51c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 52c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 53c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 54c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 55c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 56c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 57c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 58e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 59c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 60c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 61c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 62c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 6339a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 64c4a3e0a5SBagalkote, Sreenivas 65c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 66c4a3e0a5SBagalkote, Sreenivas 67a69b74d3SRandy Dunlap /* 68c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 69c4a3e0a5SBagalkote, Sreenivas * 70c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 71c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 72c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 73c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 74e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 75e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 76c4a3e0a5SBagalkote, Sreenivas */ 7739a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 7839a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 7939a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 8039a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 8139a98554Sbo yang 8239a98554Sbo yang #define MFI_ADP_RESET 0x00000040 83e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 84c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 85c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 86c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 87e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 88e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 89e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 90e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 91e3bbff9fSSumant Patro MFI_INIT_ABORT 92c4a3e0a5SBagalkote, Sreenivas 93a69b74d3SRandy Dunlap /* 94c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 95c4a3e0a5SBagalkote, Sreenivas */ 96c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 97c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 98c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 99c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 100c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 101c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 102c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 103c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 104c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 105c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 106f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 107c4a3e0a5SBagalkote, Sreenivas 108a69b74d3SRandy Dunlap /* 109c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 110c4a3e0a5SBagalkote, Sreenivas */ 111c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 112c4a3e0a5SBagalkote, Sreenivas 113a69b74d3SRandy Dunlap /* 114c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 115c4a3e0a5SBagalkote, Sreenivas */ 116c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 117c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 118c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 119c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 120c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 121c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 122c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 123c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 124c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 125c4a3e0a5SBagalkote, Sreenivas 126c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 127bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 128c4a3e0a5SBagalkote, Sreenivas 129c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 130c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 131c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 132c4a3e0a5SBagalkote, Sreenivas 133c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 13431ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 135c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 136c4a3e0a5SBagalkote, Sreenivas 137c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 138c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 139c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 140c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 141c4a3e0a5SBagalkote, Sreenivas 142c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 143c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 144c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 14581e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 146c4a3e0a5SBagalkote, Sreenivas 147a69b74d3SRandy Dunlap /* 148c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 149c4a3e0a5SBagalkote, Sreenivas */ 150c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 151c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 152c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 153c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 154c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 155c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 156c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 157c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 158c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 159c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 160c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 161c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 162c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 163c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 164c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 165c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 166c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 167c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 168c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 169c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 170c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 171c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 172c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 173c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 174c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 175c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 176c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 177c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 178c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 179c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 180c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 181c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 182c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 183c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 184c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 185c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 186c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 187c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 188c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 189c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 190c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 191c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 192c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 193c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 194c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 195c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 196c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 197c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 198c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 199c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 200c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 201c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 202c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 203c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 204c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 205c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 206c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 207c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 208c4a3e0a5SBagalkote, Sreenivas 209c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 210c4a3e0a5SBagalkote, Sreenivas }; 211c4a3e0a5SBagalkote, Sreenivas 212c4a3e0a5SBagalkote, Sreenivas /* 213c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 214c4a3e0a5SBagalkote, Sreenivas */ 215c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 216c4a3e0a5SBagalkote, Sreenivas 217c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 218c4a3e0a5SBagalkote, Sreenivas 219c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 220c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 221c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 222c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 223c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 224c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 225c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 226c4a3e0a5SBagalkote, Sreenivas 227c4a3e0a5SBagalkote, Sreenivas }; 228c4a3e0a5SBagalkote, Sreenivas 229c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 230c4a3e0a5SBagalkote, Sreenivas 231c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 232c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 233c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 234c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 235c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 236c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 237c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 238c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 239c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 240c4a3e0a5SBagalkote, Sreenivas 241c4a3e0a5SBagalkote, Sreenivas }; 242c4a3e0a5SBagalkote, Sreenivas 243c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 244c4a3e0a5SBagalkote, Sreenivas 245c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 246c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 247c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 248c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 249c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 250c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 251c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 252c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 253c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 254c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 255c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 256c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 257c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 258c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 259c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 260c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 261c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 262c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 263c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 264c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 265c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 26681e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 26781e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 26881e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 26981e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 27081e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 27181e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 27281e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 27381e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 27481e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 27581e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 27681e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 27781e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 27881e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 27981e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 28081e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 28181e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 282c4a3e0a5SBagalkote, Sreenivas }; 283c4a3e0a5SBagalkote, Sreenivas 284c4a3e0a5SBagalkote, Sreenivas /* 28581e403ceSYang, Bo * define constants for device list query options 28681e403ceSYang, Bo */ 28781e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 28881e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 28981e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 29081e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 29181e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 29281e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 29381e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 29481e403ceSYang, Bo }; 29581e403ceSYang, Bo 2967e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 2977e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 2987e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 2997e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 3007e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 3017e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 3027e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 3037e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 3047e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 3057e8a75f4SYang, Bo #define MAX_LOGICAL_DRIVES 64 3067e8a75f4SYang, Bo 30781e403ceSYang, Bo enum MR_PD_STATE { 30881e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 30981e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 31081e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 31181e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 31281e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 31381e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 31481e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 31581e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 31681e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 31781e403ceSYang, Bo }; 31881e403ceSYang, Bo 31981e403ceSYang, Bo 32081e403ceSYang, Bo /* 32181e403ceSYang, Bo * defines the physical drive address structure 32281e403ceSYang, Bo */ 32381e403ceSYang, Bo struct MR_PD_ADDRESS { 32481e403ceSYang, Bo u16 deviceId; 32581e403ceSYang, Bo u16 enclDeviceId; 32681e403ceSYang, Bo 32781e403ceSYang, Bo union { 32881e403ceSYang, Bo struct { 32981e403ceSYang, Bo u8 enclIndex; 33081e403ceSYang, Bo u8 slotNumber; 33181e403ceSYang, Bo } mrPdAddress; 33281e403ceSYang, Bo struct { 33381e403ceSYang, Bo u8 enclPosition; 33481e403ceSYang, Bo u8 enclConnectorIndex; 33581e403ceSYang, Bo } mrEnclAddress; 33681e403ceSYang, Bo }; 33781e403ceSYang, Bo u8 scsiDevType; 33881e403ceSYang, Bo union { 33981e403ceSYang, Bo u8 connectedPortBitmap; 34081e403ceSYang, Bo u8 connectedPortNumbers; 34181e403ceSYang, Bo }; 34281e403ceSYang, Bo u64 sasAddr[2]; 34381e403ceSYang, Bo } __packed; 34481e403ceSYang, Bo 34581e403ceSYang, Bo /* 34681e403ceSYang, Bo * defines the physical drive list structure 34781e403ceSYang, Bo */ 34881e403ceSYang, Bo struct MR_PD_LIST { 34981e403ceSYang, Bo u32 size; 35081e403ceSYang, Bo u32 count; 35181e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 35281e403ceSYang, Bo } __packed; 35381e403ceSYang, Bo 35481e403ceSYang, Bo struct megasas_pd_list { 35581e403ceSYang, Bo u16 tid; 35681e403ceSYang, Bo u8 driveType; 35781e403ceSYang, Bo u8 driveState; 35881e403ceSYang, Bo } __packed; 35981e403ceSYang, Bo 36081e403ceSYang, Bo /* 361bdc6fb8dSYang, Bo * defines the logical drive reference structure 362bdc6fb8dSYang, Bo */ 363bdc6fb8dSYang, Bo union MR_LD_REF { 364bdc6fb8dSYang, Bo struct { 365bdc6fb8dSYang, Bo u8 targetId; 366bdc6fb8dSYang, Bo u8 reserved; 367bdc6fb8dSYang, Bo u16 seqNum; 368bdc6fb8dSYang, Bo }; 369bdc6fb8dSYang, Bo u32 ref; 370bdc6fb8dSYang, Bo } __packed; 371bdc6fb8dSYang, Bo 372bdc6fb8dSYang, Bo /* 373bdc6fb8dSYang, Bo * defines the logical drive list structure 374bdc6fb8dSYang, Bo */ 375bdc6fb8dSYang, Bo struct MR_LD_LIST { 376bdc6fb8dSYang, Bo u32 ldCount; 377bdc6fb8dSYang, Bo u32 reserved; 378bdc6fb8dSYang, Bo struct { 379bdc6fb8dSYang, Bo union MR_LD_REF ref; 380bdc6fb8dSYang, Bo u8 state; 381bdc6fb8dSYang, Bo u8 reserved[3]; 382bdc6fb8dSYang, Bo u64 size; 383bdc6fb8dSYang, Bo } ldList[MAX_LOGICAL_DRIVES]; 384bdc6fb8dSYang, Bo } __packed; 385bdc6fb8dSYang, Bo 386bdc6fb8dSYang, Bo /* 387c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 388c4a3e0a5SBagalkote, Sreenivas */ 389c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 390c4a3e0a5SBagalkote, Sreenivas 391c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 392c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 393c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 394c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 395c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 396c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 397c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 398c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 399c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 400c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 401c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 402c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 403c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 404c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 405c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 406c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 407c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 408c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 409c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 410c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 411c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 41239a98554Sbo yang u8 maintainPdFailHistory; 41339a98554Sbo yang u8 disallowHostRequestReordering; 41439a98554Sbo yang u8 abortCCOnError; 41539a98554Sbo yang u8 loadBalanceMode; 41639a98554Sbo yang u8 disableAutoDetectBackplane; 417c4a3e0a5SBagalkote, Sreenivas 41839a98554Sbo yang u8 snapVDSpace; 41939a98554Sbo yang 42039a98554Sbo yang /* 42139a98554Sbo yang * Add properties that can be controlled by 42239a98554Sbo yang * a bit in the following structure. 42339a98554Sbo yang */ 42439a98554Sbo yang 42539a98554Sbo yang struct { 42639a98554Sbo yang u32 copyBackDisabled : 1; 42739a98554Sbo yang u32 SMARTerEnabled : 1; 42839a98554Sbo yang u32 prCorrectUnconfiguredAreas : 1; 42939a98554Sbo yang u32 useFdeOnly : 1; 43039a98554Sbo yang u32 disableNCQ : 1; 43139a98554Sbo yang u32 SSDSMARTerEnabled : 1; 43239a98554Sbo yang u32 SSDPatrolReadEnabled : 1; 43339a98554Sbo yang u32 enableSpinDownUnconfigured : 1; 43439a98554Sbo yang u32 autoEnhancedImport : 1; 43539a98554Sbo yang u32 enableSecretKeyControl : 1; 43639a98554Sbo yang u32 disableOnlineCtrlReset : 1; 43739a98554Sbo yang u32 allowBootWithPinnedCache : 1; 43839a98554Sbo yang u32 disableSpinDownHS : 1; 43939a98554Sbo yang u32 enableJBOD : 1; 44039a98554Sbo yang u32 reserved :18; 44139a98554Sbo yang } OnOffProperties; 44239a98554Sbo yang u8 autoSnapVDSpace; 44339a98554Sbo yang u8 viewSpace; 44439a98554Sbo yang u16 spinDownTime; 44539a98554Sbo yang u8 reserved[24]; 44681e403ceSYang, Bo } __packed; 447c4a3e0a5SBagalkote, Sreenivas 448c4a3e0a5SBagalkote, Sreenivas /* 449c4a3e0a5SBagalkote, Sreenivas * SAS controller information 450c4a3e0a5SBagalkote, Sreenivas */ 451c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 452c4a3e0a5SBagalkote, Sreenivas 453c4a3e0a5SBagalkote, Sreenivas /* 454c4a3e0a5SBagalkote, Sreenivas * PCI device information 455c4a3e0a5SBagalkote, Sreenivas */ 456c4a3e0a5SBagalkote, Sreenivas struct { 457c4a3e0a5SBagalkote, Sreenivas 458c4a3e0a5SBagalkote, Sreenivas u16 vendor_id; 459c4a3e0a5SBagalkote, Sreenivas u16 device_id; 460c4a3e0a5SBagalkote, Sreenivas u16 sub_vendor_id; 461c4a3e0a5SBagalkote, Sreenivas u16 sub_device_id; 462c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 463c4a3e0a5SBagalkote, Sreenivas 464c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 465c4a3e0a5SBagalkote, Sreenivas 466c4a3e0a5SBagalkote, Sreenivas /* 467c4a3e0a5SBagalkote, Sreenivas * Host interface information 468c4a3e0a5SBagalkote, Sreenivas */ 469c4a3e0a5SBagalkote, Sreenivas struct { 470c4a3e0a5SBagalkote, Sreenivas 471c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 472c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 473c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 474c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 475c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 476c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 477c4a3e0a5SBagalkote, Sreenivas u8 port_count; 478c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 479c4a3e0a5SBagalkote, Sreenivas 480c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 481c4a3e0a5SBagalkote, Sreenivas 482c4a3e0a5SBagalkote, Sreenivas /* 483c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 484c4a3e0a5SBagalkote, Sreenivas */ 485c4a3e0a5SBagalkote, Sreenivas struct { 486c4a3e0a5SBagalkote, Sreenivas 487c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 488c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 489c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 490c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 491c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 492c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 493c4a3e0a5SBagalkote, Sreenivas u8 port_count; 494c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 495c4a3e0a5SBagalkote, Sreenivas 496c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 497c4a3e0a5SBagalkote, Sreenivas 498c4a3e0a5SBagalkote, Sreenivas /* 499c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 500c4a3e0a5SBagalkote, Sreenivas */ 501c4a3e0a5SBagalkote, Sreenivas u32 image_check_word; 502c4a3e0a5SBagalkote, Sreenivas u32 image_component_count; 503c4a3e0a5SBagalkote, Sreenivas 504c4a3e0a5SBagalkote, Sreenivas struct { 505c4a3e0a5SBagalkote, Sreenivas 506c4a3e0a5SBagalkote, Sreenivas char name[8]; 507c4a3e0a5SBagalkote, Sreenivas char version[32]; 508c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 509c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 510c4a3e0a5SBagalkote, Sreenivas 511c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 512c4a3e0a5SBagalkote, Sreenivas 513c4a3e0a5SBagalkote, Sreenivas /* 514c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 515c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 516c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 517c4a3e0a5SBagalkote, Sreenivas * terminated 518c4a3e0a5SBagalkote, Sreenivas */ 519c4a3e0a5SBagalkote, Sreenivas u32 pending_image_component_count; 520c4a3e0a5SBagalkote, Sreenivas 521c4a3e0a5SBagalkote, Sreenivas struct { 522c4a3e0a5SBagalkote, Sreenivas 523c4a3e0a5SBagalkote, Sreenivas char name[8]; 524c4a3e0a5SBagalkote, Sreenivas char version[32]; 525c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 526c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 527c4a3e0a5SBagalkote, Sreenivas 528c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 529c4a3e0a5SBagalkote, Sreenivas 530c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 531c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 532c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 533c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 534c4a3e0a5SBagalkote, Sreenivas 535c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 536c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 537c4a3e0a5SBagalkote, Sreenivas 538c4a3e0a5SBagalkote, Sreenivas /* 539c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 540c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 541c4a3e0a5SBagalkote, Sreenivas */ 542c4a3e0a5SBagalkote, Sreenivas struct { 543c4a3e0a5SBagalkote, Sreenivas 544c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 545c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 546c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 547c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 548c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 549c4a3e0a5SBagalkote, Sreenivas 550c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 551c4a3e0a5SBagalkote, Sreenivas 552c4a3e0a5SBagalkote, Sreenivas u32 current_fw_time; 553c4a3e0a5SBagalkote, Sreenivas 554c4a3e0a5SBagalkote, Sreenivas /* 555c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 556c4a3e0a5SBagalkote, Sreenivas */ 557c4a3e0a5SBagalkote, Sreenivas u16 max_concurrent_cmds; 558c4a3e0a5SBagalkote, Sreenivas u16 max_sge_count; 559c4a3e0a5SBagalkote, Sreenivas u32 max_request_size; 560c4a3e0a5SBagalkote, Sreenivas 561c4a3e0a5SBagalkote, Sreenivas /* 562c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 563c4a3e0a5SBagalkote, Sreenivas */ 564c4a3e0a5SBagalkote, Sreenivas u16 ld_present_count; 565c4a3e0a5SBagalkote, Sreenivas u16 ld_degraded_count; 566c4a3e0a5SBagalkote, Sreenivas u16 ld_offline_count; 567c4a3e0a5SBagalkote, Sreenivas 568c4a3e0a5SBagalkote, Sreenivas u16 pd_present_count; 569c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_present_count; 570c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_pred_failure_count; 571c4a3e0a5SBagalkote, Sreenivas u16 pd_disk_failed_count; 572c4a3e0a5SBagalkote, Sreenivas 573c4a3e0a5SBagalkote, Sreenivas /* 574c4a3e0a5SBagalkote, Sreenivas * Memory size information 575c4a3e0a5SBagalkote, Sreenivas */ 576c4a3e0a5SBagalkote, Sreenivas u16 nvram_size; 577c4a3e0a5SBagalkote, Sreenivas u16 memory_size; 578c4a3e0a5SBagalkote, Sreenivas u16 flash_size; 579c4a3e0a5SBagalkote, Sreenivas 580c4a3e0a5SBagalkote, Sreenivas /* 581c4a3e0a5SBagalkote, Sreenivas * Error counters 582c4a3e0a5SBagalkote, Sreenivas */ 583c4a3e0a5SBagalkote, Sreenivas u16 mem_correctable_error_count; 584c4a3e0a5SBagalkote, Sreenivas u16 mem_uncorrectable_error_count; 585c4a3e0a5SBagalkote, Sreenivas 586c4a3e0a5SBagalkote, Sreenivas /* 587c4a3e0a5SBagalkote, Sreenivas * Cluster information 588c4a3e0a5SBagalkote, Sreenivas */ 589c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 590c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 591c4a3e0a5SBagalkote, Sreenivas 592c4a3e0a5SBagalkote, Sreenivas /* 593c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 594c4a3e0a5SBagalkote, Sreenivas */ 595c4a3e0a5SBagalkote, Sreenivas u16 max_strips_per_io; 596c4a3e0a5SBagalkote, Sreenivas 597c4a3e0a5SBagalkote, Sreenivas /* 598c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 599c4a3e0a5SBagalkote, Sreenivas */ 600c4a3e0a5SBagalkote, Sreenivas struct { 601c4a3e0a5SBagalkote, Sreenivas 602c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 603c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 604c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 605c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 606c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 607c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 608c4a3e0a5SBagalkote, Sreenivas 609c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 610c4a3e0a5SBagalkote, Sreenivas 611c4a3e0a5SBagalkote, Sreenivas struct { 612c4a3e0a5SBagalkote, Sreenivas 613c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 614c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 615c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 616c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 617c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 618c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 619c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 620c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 621c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 622c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 623c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 624c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 625c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 626c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 627c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 628c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 629c4a3e0a5SBagalkote, Sreenivas 630c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 631c4a3e0a5SBagalkote, Sreenivas 632c4a3e0a5SBagalkote, Sreenivas struct { 633c4a3e0a5SBagalkote, Sreenivas 634c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 635c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 636c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 637c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 638c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 639c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 640c4a3e0a5SBagalkote, Sreenivas 641c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 642c4a3e0a5SBagalkote, Sreenivas 643c4a3e0a5SBagalkote, Sreenivas struct { 644c4a3e0a5SBagalkote, Sreenivas 645c4a3e0a5SBagalkote, Sreenivas u8 min; 646c4a3e0a5SBagalkote, Sreenivas u8 max; 647c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 648c4a3e0a5SBagalkote, Sreenivas 649c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 650c4a3e0a5SBagalkote, Sreenivas 651c4a3e0a5SBagalkote, Sreenivas struct { 652c4a3e0a5SBagalkote, Sreenivas 653c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 654c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 655c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 656c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 657c4a3e0a5SBagalkote, Sreenivas 658c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 659c4a3e0a5SBagalkote, Sreenivas 660c4a3e0a5SBagalkote, Sreenivas struct { 661c4a3e0a5SBagalkote, Sreenivas 662c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 663c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 664c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 665c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 666c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 667c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 668c4a3e0a5SBagalkote, Sreenivas 669c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 670c4a3e0a5SBagalkote, Sreenivas 671c4a3e0a5SBagalkote, Sreenivas /* 672c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 673c4a3e0a5SBagalkote, Sreenivas */ 674c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 675c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 676c4a3e0a5SBagalkote, Sreenivas 677c4a3e0a5SBagalkote, Sreenivas /* 678c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 679c4a3e0a5SBagalkote, Sreenivas */ 680c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 681c4a3e0a5SBagalkote, Sreenivas 682c4a3e0a5SBagalkote, Sreenivas /* 683c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 684c4a3e0a5SBagalkote, Sreenivas */ 685c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 686c4a3e0a5SBagalkote, Sreenivas 687c4a3e0a5SBagalkote, Sreenivas u8 pad[0x800 - 0x6a0]; 688c4a3e0a5SBagalkote, Sreenivas 68981e403ceSYang, Bo } __packed; 690c4a3e0a5SBagalkote, Sreenivas 691c4a3e0a5SBagalkote, Sreenivas /* 692c4a3e0a5SBagalkote, Sreenivas * =============================== 693c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 694c4a3e0a5SBagalkote, Sreenivas * =============================== 695c4a3e0a5SBagalkote, Sreenivas */ 696c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 697c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD_CHANNELS 2 698c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 699c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 700c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 701c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 702c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 703c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LD 64 70481e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 70581e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 706bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 707bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 708c4a3e0a5SBagalkote, Sreenivas 709658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 710658dcedbSSumant Patro 71105e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 71205e9ebbeSSumant Patro 713d532dbe2Sbo yang /* Frame Type */ 714d532dbe2Sbo yang #define IO_FRAME 0 715d532dbe2Sbo yang #define PTHRU_FRAME 1 716d532dbe2Sbo yang 717c4a3e0a5SBagalkote, Sreenivas /* 718c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 719c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 720c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 721c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 722c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 723c4a3e0a5SBagalkote, Sreenivas */ 724c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 7252a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 726c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 727c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 72805e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 729c4a3e0a5SBagalkote, Sreenivas 730c4a3e0a5SBagalkote, Sreenivas /* 731c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 732c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 733c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 734c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 735c4a3e0a5SBagalkote, Sreenivas * is shown below 736c4a3e0a5SBagalkote, Sreenivas */ 737c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 7387bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 739c4a3e0a5SBagalkote, Sreenivas 740c4a3e0a5SBagalkote, Sreenivas /* 741c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 742c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 743c4a3e0a5SBagalkote, Sreenivas */ 744c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 745c4a3e0a5SBagalkote, Sreenivas 74639a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 74739a98554Sbo yang 74839a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 74939a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 75039a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 75139a98554Sbo yang 752c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 75314faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 754ad84db2eSbo yang #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10) 755c4a3e0a5SBagalkote, Sreenivas 756f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 7576610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 7586610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 75987911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 76087911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 7610e98936cSSumant Patro 76239a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 76339a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 76439a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 7650e98936cSSumant Patro /* 7660e98936cSSumant Patro * register set for both 1068 and 1078 controllers 7670e98936cSSumant Patro * structure extended for 1078 registers 7680e98936cSSumant Patro */ 769c4a3e0a5SBagalkote, Sreenivas 770f9876f0bSSumant Patro struct megasas_register_set { 771c4a3e0a5SBagalkote, Sreenivas u32 reserved_0[4]; /*0000h*/ 772c4a3e0a5SBagalkote, Sreenivas 773c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 774c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 775c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 776c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 777c4a3e0a5SBagalkote, Sreenivas 778c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 779c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 780c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 781c4a3e0a5SBagalkote, Sreenivas 782c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 783c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 784c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 785c4a3e0a5SBagalkote, Sreenivas 786c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 787c4a3e0a5SBagalkote, Sreenivas 788c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 789c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 790c4a3e0a5SBagalkote, Sreenivas 791f9876f0bSSumant Patro u32 reserved_2[22]; /*0048h*/ 792c4a3e0a5SBagalkote, Sreenivas 793f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 794f9876f0bSSumant Patro 795f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 796f9876f0bSSumant Patro 797f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 798f9876f0bSSumant Patro 799f9876f0bSSumant Patro u32 reserved_4[3]; /*00B4h*/ 800f9876f0bSSumant Patro 801f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 802f9876f0bSSumant Patro 803f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 804f9876f0bSSumant Patro 805f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 80639a98554Sbo yang u32 res_6[11]; /*CCh*/ 80739a98554Sbo yang u32 host_diag; 80839a98554Sbo yang u32 seq_offset; 80939a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 810c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 811c4a3e0a5SBagalkote, Sreenivas 812c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 813c4a3e0a5SBagalkote, Sreenivas 814c4a3e0a5SBagalkote, Sreenivas u32 phys_addr; 815c4a3e0a5SBagalkote, Sreenivas u32 length; 816c4a3e0a5SBagalkote, Sreenivas 817c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 818c4a3e0a5SBagalkote, Sreenivas 819c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 820c4a3e0a5SBagalkote, Sreenivas 821c4a3e0a5SBagalkote, Sreenivas u64 phys_addr; 822c4a3e0a5SBagalkote, Sreenivas u32 length; 823c4a3e0a5SBagalkote, Sreenivas 824c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 825c4a3e0a5SBagalkote, Sreenivas 826f4c9a131SYang, Bo struct megasas_sge_skinny { 827f4c9a131SYang, Bo u64 phys_addr; 828f4c9a131SYang, Bo u32 length; 829f4c9a131SYang, Bo u32 flag; 830f4c9a131SYang, Bo } __packed; 831f4c9a131SYang, Bo 832c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 833c4a3e0a5SBagalkote, Sreenivas 834c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 835c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 836f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 837c4a3e0a5SBagalkote, Sreenivas 838c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 839c4a3e0a5SBagalkote, Sreenivas 840c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 841c4a3e0a5SBagalkote, Sreenivas 842c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 843c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 844c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 845c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 846c4a3e0a5SBagalkote, Sreenivas 847c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 848c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 849c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 850c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 851c4a3e0a5SBagalkote, Sreenivas 852c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 853c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 854c4a3e0a5SBagalkote, Sreenivas 855c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 856c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 857c4a3e0a5SBagalkote, Sreenivas u32 data_xferlen; /*14h */ 858c4a3e0a5SBagalkote, Sreenivas 859c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 860c4a3e0a5SBagalkote, Sreenivas 861c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 862c4a3e0a5SBagalkote, Sreenivas 863c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 864c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 865c4a3e0a5SBagalkote, Sreenivas 866c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 867c4a3e0a5SBagalkote, Sreenivas 868c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 869c4a3e0a5SBagalkote, Sreenivas 870c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 871c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 872c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 873c4a3e0a5SBagalkote, Sreenivas 874c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 875c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 876c4a3e0a5SBagalkote, Sreenivas 877c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 878c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 879c4a3e0a5SBagalkote, Sreenivas 880c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 881c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 882c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 883c4a3e0a5SBagalkote, Sreenivas 884c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_lo; /*18h */ 885c4a3e0a5SBagalkote, Sreenivas u32 queue_info_new_phys_addr_hi; /*1Ch */ 886c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_lo; /*20h */ 887c4a3e0a5SBagalkote, Sreenivas u32 queue_info_old_phys_addr_hi; /*24h */ 888c4a3e0a5SBagalkote, Sreenivas 889c4a3e0a5SBagalkote, Sreenivas u32 reserved_4[6]; /*28h */ 890c4a3e0a5SBagalkote, Sreenivas 891c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 892c4a3e0a5SBagalkote, Sreenivas 893c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 894c4a3e0a5SBagalkote, Sreenivas 895c4a3e0a5SBagalkote, Sreenivas u32 init_flags; /*00h */ 896c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_entries; /*04h */ 897c4a3e0a5SBagalkote, Sreenivas 898c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_lo; /*08h */ 899c4a3e0a5SBagalkote, Sreenivas u32 reply_queue_start_phys_addr_hi; /*0Ch */ 900c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_lo; /*10h */ 901c4a3e0a5SBagalkote, Sreenivas u32 producer_index_phys_addr_hi; /*14h */ 902c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_lo; /*18h */ 903c4a3e0a5SBagalkote, Sreenivas u32 consumer_index_phys_addr_hi; /*1Ch */ 904c4a3e0a5SBagalkote, Sreenivas 905c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 906c4a3e0a5SBagalkote, Sreenivas 907c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 908c4a3e0a5SBagalkote, Sreenivas 909c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 910c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 911c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 912c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 913c4a3e0a5SBagalkote, Sreenivas 914c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 915c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 916c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 917c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 918c4a3e0a5SBagalkote, Sreenivas 919c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 920c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 921c4a3e0a5SBagalkote, Sreenivas 922c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 923c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 924c4a3e0a5SBagalkote, Sreenivas u32 lba_count; /*14h */ 925c4a3e0a5SBagalkote, Sreenivas 926c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 927c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 928c4a3e0a5SBagalkote, Sreenivas 929c4a3e0a5SBagalkote, Sreenivas u32 start_lba_lo; /*20h */ 930c4a3e0a5SBagalkote, Sreenivas u32 start_lba_hi; /*24h */ 931c4a3e0a5SBagalkote, Sreenivas 932c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 933c4a3e0a5SBagalkote, Sreenivas 934c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 935c4a3e0a5SBagalkote, Sreenivas 936c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 937c4a3e0a5SBagalkote, Sreenivas 938c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 939c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 940c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 941c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 942c4a3e0a5SBagalkote, Sreenivas 943c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 944c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 945c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 946c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 947c4a3e0a5SBagalkote, Sreenivas 948c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 949c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 950c4a3e0a5SBagalkote, Sreenivas 951c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 952c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 953c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 954c4a3e0a5SBagalkote, Sreenivas 955c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_lo; /*18h */ 956c4a3e0a5SBagalkote, Sreenivas u32 sense_buf_phys_addr_hi; /*1Ch */ 957c4a3e0a5SBagalkote, Sreenivas 958c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 959c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 960c4a3e0a5SBagalkote, Sreenivas 961c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 962c4a3e0a5SBagalkote, Sreenivas 963c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 964c4a3e0a5SBagalkote, Sreenivas 965c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 966c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 967c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 968c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 969c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 970c4a3e0a5SBagalkote, Sreenivas 971c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 972c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 973c4a3e0a5SBagalkote, Sreenivas 974c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 975c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 976c4a3e0a5SBagalkote, Sreenivas 977c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 978c4a3e0a5SBagalkote, Sreenivas u32 opcode; /*18h */ 979c4a3e0a5SBagalkote, Sreenivas 980c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 981c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 982c4a3e0a5SBagalkote, Sreenivas u16 s[6]; 983c4a3e0a5SBagalkote, Sreenivas u32 w[3]; 984c4a3e0a5SBagalkote, Sreenivas } mbox; 985c4a3e0a5SBagalkote, Sreenivas 986c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 987c4a3e0a5SBagalkote, Sreenivas 988c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 989c4a3e0a5SBagalkote, Sreenivas 990c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 991c4a3e0a5SBagalkote, Sreenivas 992c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 993c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 994c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 995c4a3e0a5SBagalkote, Sreenivas 996c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 997c4a3e0a5SBagalkote, Sreenivas u32 reserved_2; /*04h */ 998c4a3e0a5SBagalkote, Sreenivas 999c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1000c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1001c4a3e0a5SBagalkote, Sreenivas 1002c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1003c4a3e0a5SBagalkote, Sreenivas u16 reserved_3; /*12h */ 1004c4a3e0a5SBagalkote, Sreenivas u32 reserved_4; /*14h */ 1005c4a3e0a5SBagalkote, Sreenivas 1006c4a3e0a5SBagalkote, Sreenivas u32 abort_context; /*18h */ 1007c4a3e0a5SBagalkote, Sreenivas u32 pad_1; /*1Ch */ 1008c4a3e0a5SBagalkote, Sreenivas 1009c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_lo; /*20h */ 1010c4a3e0a5SBagalkote, Sreenivas u32 abort_mfi_phys_addr_hi; /*24h */ 1011c4a3e0a5SBagalkote, Sreenivas 1012c4a3e0a5SBagalkote, Sreenivas u32 reserved_5[6]; /*28h */ 1013c4a3e0a5SBagalkote, Sreenivas 1014c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1015c4a3e0a5SBagalkote, Sreenivas 1016c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1017c4a3e0a5SBagalkote, Sreenivas 1018c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1019c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1020c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1021c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1022c4a3e0a5SBagalkote, Sreenivas 1023c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1024c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1025c4a3e0a5SBagalkote, Sreenivas 1026c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1027c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1028c4a3e0a5SBagalkote, Sreenivas 1029c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1030c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1031c4a3e0a5SBagalkote, Sreenivas 1032c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1033c4a3e0a5SBagalkote, Sreenivas u64 sas_addr; /*18h */ 1034c4a3e0a5SBagalkote, Sreenivas 1035c4a3e0a5SBagalkote, Sreenivas union { 1036c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1037c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1038c4a3e0a5SBagalkote, Sreenivas } sgl; 1039c4a3e0a5SBagalkote, Sreenivas 1040c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1041c4a3e0a5SBagalkote, Sreenivas 1042c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1043c4a3e0a5SBagalkote, Sreenivas 1044c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1045c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1046c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1047c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1048c4a3e0a5SBagalkote, Sreenivas 1049c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1050c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1051c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1052c4a3e0a5SBagalkote, Sreenivas 1053c4a3e0a5SBagalkote, Sreenivas u32 context; /*08h */ 1054c4a3e0a5SBagalkote, Sreenivas u32 pad_0; /*0Ch */ 1055c4a3e0a5SBagalkote, Sreenivas 1056c4a3e0a5SBagalkote, Sreenivas u16 flags; /*10h */ 1057c4a3e0a5SBagalkote, Sreenivas u16 timeout; /*12h */ 1058c4a3e0a5SBagalkote, Sreenivas 1059c4a3e0a5SBagalkote, Sreenivas u32 data_xfer_len; /*14h */ 1060c4a3e0a5SBagalkote, Sreenivas 1061c4a3e0a5SBagalkote, Sreenivas u16 fis[10]; /*18h */ 1062c4a3e0a5SBagalkote, Sreenivas u32 stp_flags; 1063c4a3e0a5SBagalkote, Sreenivas 1064c4a3e0a5SBagalkote, Sreenivas union { 1065c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1066c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1067c4a3e0a5SBagalkote, Sreenivas } sgl; 1068c4a3e0a5SBagalkote, Sreenivas 1069c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1070c4a3e0a5SBagalkote, Sreenivas 1071c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1072c4a3e0a5SBagalkote, Sreenivas 1073c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1074c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1075c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1076c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1077c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1078c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1079c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1080c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1081c4a3e0a5SBagalkote, Sreenivas 1082c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1083c4a3e0a5SBagalkote, Sreenivas }; 1084c4a3e0a5SBagalkote, Sreenivas 1085c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1086c4a3e0a5SBagalkote, Sreenivas 1087c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 1088c4a3e0a5SBagalkote, Sreenivas 1089c4a3e0a5SBagalkote, Sreenivas struct { 1090c4a3e0a5SBagalkote, Sreenivas u16 locale; 1091c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1092c4a3e0a5SBagalkote, Sreenivas s8 class; 1093c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 1094c4a3e0a5SBagalkote, Sreenivas 1095c4a3e0a5SBagalkote, Sreenivas u32 word; 1096c4a3e0a5SBagalkote, Sreenivas 1097c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1098c4a3e0a5SBagalkote, Sreenivas 1099c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 1100c4a3e0a5SBagalkote, Sreenivas u32 newest_seq_num; 1101c4a3e0a5SBagalkote, Sreenivas u32 oldest_seq_num; 1102c4a3e0a5SBagalkote, Sreenivas u32 clear_seq_num; 1103c4a3e0a5SBagalkote, Sreenivas u32 shutdown_seq_num; 1104c4a3e0a5SBagalkote, Sreenivas u32 boot_seq_num; 1105c4a3e0a5SBagalkote, Sreenivas 1106c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1107c4a3e0a5SBagalkote, Sreenivas 1108c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1109c4a3e0a5SBagalkote, Sreenivas 1110c4a3e0a5SBagalkote, Sreenivas u16 progress; 1111c4a3e0a5SBagalkote, Sreenivas u16 elapsed_seconds; 1112c4a3e0a5SBagalkote, Sreenivas 1113c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1114c4a3e0a5SBagalkote, Sreenivas 1115c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1116c4a3e0a5SBagalkote, Sreenivas 1117c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1118c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1119c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1120c4a3e0a5SBagalkote, Sreenivas 1121c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1122c4a3e0a5SBagalkote, Sreenivas 1123c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1124c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1125c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1126c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1127c4a3e0a5SBagalkote, Sreenivas 1128c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1129c4a3e0a5SBagalkote, Sreenivas 1130c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1131c4a3e0a5SBagalkote, Sreenivas 1132c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1133c4a3e0a5SBagalkote, Sreenivas u32 time_stamp; 1134c4a3e0a5SBagalkote, Sreenivas u32 code; 1135c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1136c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1137c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1138c4a3e0a5SBagalkote, Sreenivas 1139c4a3e0a5SBagalkote, Sreenivas union { 1140c4a3e0a5SBagalkote, Sreenivas struct { 1141c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1142c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1143c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1144c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1145c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1146c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1147c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1148c4a3e0a5SBagalkote, Sreenivas 1149c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1150c4a3e0a5SBagalkote, Sreenivas 1151c4a3e0a5SBagalkote, Sreenivas struct { 1152c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1153c4a3e0a5SBagalkote, Sreenivas u64 count; 1154c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1155c4a3e0a5SBagalkote, Sreenivas 1156c4a3e0a5SBagalkote, Sreenivas struct { 1157c4a3e0a5SBagalkote, Sreenivas u64 lba; 1158c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1159c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1160c4a3e0a5SBagalkote, Sreenivas 1161c4a3e0a5SBagalkote, Sreenivas struct { 1162c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1163c4a3e0a5SBagalkote, Sreenivas u32 prevOwner; 1164c4a3e0a5SBagalkote, Sreenivas u32 newOwner; 1165c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1166c4a3e0a5SBagalkote, Sreenivas 1167c4a3e0a5SBagalkote, Sreenivas struct { 1168c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1169c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1170c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1171c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1172c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1173c4a3e0a5SBagalkote, Sreenivas 1174c4a3e0a5SBagalkote, Sreenivas struct { 1175c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1176c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1177c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1178c4a3e0a5SBagalkote, Sreenivas 1179c4a3e0a5SBagalkote, Sreenivas struct { 1180c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1181c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1182c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1183c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1184c4a3e0a5SBagalkote, Sreenivas 1185c4a3e0a5SBagalkote, Sreenivas struct { 1186c4a3e0a5SBagalkote, Sreenivas u64 strip; 1187c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1188c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1189c4a3e0a5SBagalkote, Sreenivas 1190c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1191c4a3e0a5SBagalkote, Sreenivas 1192c4a3e0a5SBagalkote, Sreenivas struct { 1193c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1194c4a3e0a5SBagalkote, Sreenivas u32 err; 1195c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1196c4a3e0a5SBagalkote, Sreenivas 1197c4a3e0a5SBagalkote, Sreenivas struct { 1198c4a3e0a5SBagalkote, Sreenivas u64 lba; 1199c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1200c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1201c4a3e0a5SBagalkote, Sreenivas 1202c4a3e0a5SBagalkote, Sreenivas struct { 1203c4a3e0a5SBagalkote, Sreenivas u64 lba; 1204c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1205c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1206c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1207c4a3e0a5SBagalkote, Sreenivas 1208c4a3e0a5SBagalkote, Sreenivas struct { 1209c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1210c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1211c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1212c4a3e0a5SBagalkote, Sreenivas 1213c4a3e0a5SBagalkote, Sreenivas struct { 1214c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1215c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1216c4a3e0a5SBagalkote, Sreenivas u32 newState; 1217c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1218c4a3e0a5SBagalkote, Sreenivas 1219c4a3e0a5SBagalkote, Sreenivas struct { 1220c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 1221c4a3e0a5SBagalkote, Sreenivas u16 deviceId; 1222c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1223c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1224c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1225c4a3e0a5SBagalkote, Sreenivas 1226c4a3e0a5SBagalkote, Sreenivas u32 rate; 1227c4a3e0a5SBagalkote, Sreenivas char str[96]; 1228c4a3e0a5SBagalkote, Sreenivas 1229c4a3e0a5SBagalkote, Sreenivas struct { 1230c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1231c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1232c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1233c4a3e0a5SBagalkote, Sreenivas 1234c4a3e0a5SBagalkote, Sreenivas struct { 1235c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1236c4a3e0a5SBagalkote, Sreenivas u32 elog; 1237c4a3e0a5SBagalkote, Sreenivas char str[64]; 1238c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1239c4a3e0a5SBagalkote, Sreenivas 1240c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 1241c4a3e0a5SBagalkote, Sreenivas u16 s[48]; 1242c4a3e0a5SBagalkote, Sreenivas u32 w[24]; 1243c4a3e0a5SBagalkote, Sreenivas u64 d[12]; 1244c4a3e0a5SBagalkote, Sreenivas } args; 1245c4a3e0a5SBagalkote, Sreenivas 1246c4a3e0a5SBagalkote, Sreenivas char description[128]; 1247c4a3e0a5SBagalkote, Sreenivas 1248c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1249c4a3e0a5SBagalkote, Sreenivas 12507e8a75f4SYang, Bo struct megasas_aen_event { 12517e8a75f4SYang, Bo struct work_struct hotplug_work; 12527e8a75f4SYang, Bo struct megasas_instance *instance; 12537e8a75f4SYang, Bo }; 12547e8a75f4SYang, Bo 1255c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1256c4a3e0a5SBagalkote, Sreenivas 1257c4a3e0a5SBagalkote, Sreenivas u32 *producer; 1258c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 1259c4a3e0a5SBagalkote, Sreenivas u32 *consumer; 1260c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 1261c4a3e0a5SBagalkote, Sreenivas 1262c4a3e0a5SBagalkote, Sreenivas u32 *reply_queue; 1263c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1264c4a3e0a5SBagalkote, Sreenivas 1265c4a3e0a5SBagalkote, Sreenivas unsigned long base_addr; 1266c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 1267c4a3e0a5SBagalkote, Sreenivas 126881e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1269bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1270c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1271c4a3e0a5SBagalkote, Sreenivas 1272c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1273c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 1274c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 12757e8a75f4SYang, Bo struct megasas_aen_event *ev; 1276c4a3e0a5SBagalkote, Sreenivas 1277c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1278c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 127939a98554Sbo yang /* used to sync fire the cmd to fw */ 1280c4a3e0a5SBagalkote, Sreenivas spinlock_t cmd_pool_lock; 128139a98554Sbo yang /* used to sync fire the cmd to fw */ 128239a98554Sbo yang spinlock_t hba_lock; 12837343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 12847343eb65Sbo yang spinlock_t completion_lock; 1285c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1286c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1287c4a3e0a5SBagalkote, Sreenivas 1288c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1289c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1290c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1291e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1292c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1293c4a3e0a5SBagalkote, Sreenivas 1294c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1295c4a3e0a5SBagalkote, Sreenivas 1296c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1297c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1298c4a3e0a5SBagalkote, Sreenivas 1299c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1300c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 130139a98554Sbo yang u32 fw_support_ieee; 1302c4a3e0a5SBagalkote, Sreenivas 1303e4a082c7SSumant Patro atomic_t fw_outstanding; 130439a98554Sbo yang atomic_t fw_reset_no_pci_access; 13051341c939SSumant Patro 13061341c939SSumant Patro struct megasas_instance_template *instancet; 13075d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 130839a98554Sbo yang struct work_struct work_init; 130905e9ebbeSSumant Patro 131005e9ebbeSSumant Patro u8 flag; 1311c3518837SYang, Bo u8 unload; 1312f4c9a131SYang, Bo u8 flag_ieee; 131339a98554Sbo yang u8 issuepend_done; 131439a98554Sbo yang u8 disableOnlineCtrlReset; 131539a98554Sbo yang u8 adprecovery; 131605e9ebbeSSumant Patro unsigned long last_time; 131739a98554Sbo yang u32 mfiStatus; 131839a98554Sbo yang u32 last_seq_num; 1319ad84db2eSbo yang 1320ad84db2eSbo yang struct timer_list io_completion_timer; 132139a98554Sbo yang struct list_head internal_reset_pending_q; 132239a98554Sbo yang }; 132339a98554Sbo yang 132439a98554Sbo yang enum { 132539a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 132639a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 132739a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 132839a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 132939a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 133039a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1331c4a3e0a5SBagalkote, Sreenivas }; 1332c4a3e0a5SBagalkote, Sreenivas 13330c79e681SYang, Bo struct megasas_instance_template { 13340c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 13350c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 13360c79e681SYang, Bo 13370c79e681SYang, Bo void (*enable_intr)(struct megasas_register_set __iomem *) ; 13380c79e681SYang, Bo void (*disable_intr)(struct megasas_register_set __iomem *); 13390c79e681SYang, Bo 13400c79e681SYang, Bo int (*clear_intr)(struct megasas_register_set __iomem *); 13410c79e681SYang, Bo 13420c79e681SYang, Bo u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 134339a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 134439a98554Sbo yang struct megasas_register_set __iomem *); 134539a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 134639a98554Sbo yang struct megasas_register_set __iomem *); 13470c79e681SYang, Bo }; 13480c79e681SYang, Bo 1349c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1350c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1351c4a3e0a5SBagalkote, Sreenivas 1352c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEV_INDEX(inst, scp) \ 1353c4a3e0a5SBagalkote, Sreenivas ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 1354c4a3e0a5SBagalkote, Sreenivas scp->device->id 1355c4a3e0a5SBagalkote, Sreenivas 1356c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1357c4a3e0a5SBagalkote, Sreenivas 1358c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1359c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1360c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1361c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1362c4a3e0a5SBagalkote, Sreenivas 1363c4a3e0a5SBagalkote, Sreenivas u32 index; 1364c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 1365c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; 136639a98554Sbo yang u8 abort_aen; 136739a98554Sbo yang u8 retry_for_fw_reset; 136839a98554Sbo yang 1369c4a3e0a5SBagalkote, Sreenivas 1370c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1371c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 1372c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 1373c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1374c4a3e0a5SBagalkote, Sreenivas }; 1375c4a3e0a5SBagalkote, Sreenivas 1376c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1377c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1378c4a3e0a5SBagalkote, Sreenivas 1379c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1380c4a3e0a5SBagalkote, Sreenivas 1381c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1382c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1383c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1384c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1385c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1386c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1387c4a3e0a5SBagalkote, Sreenivas union { 1388c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1389c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1390c4a3e0a5SBagalkote, Sreenivas } frame; 1391c4a3e0a5SBagalkote, Sreenivas 1392c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1393c4a3e0a5SBagalkote, Sreenivas 1394c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1395c4a3e0a5SBagalkote, Sreenivas 1396c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 1397c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1398c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1399c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 1400c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 1401c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1402c4a3e0a5SBagalkote, Sreenivas 1403c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 1404c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 1405c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1406c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1407c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1408c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1409c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1410c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1411c4a3e0a5SBagalkote, Sreenivas union { 1412c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1413c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1414c4a3e0a5SBagalkote, Sreenivas } frame; 1415c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 1416c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1417c4a3e0a5SBagalkote, Sreenivas 14180e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 1419c4a3e0a5SBagalkote, Sreenivas #endif 1420c4a3e0a5SBagalkote, Sreenivas 1421cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 1422c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 1423c4a3e0a5SBagalkote, Sreenivas 1424c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 1425c4a3e0a5SBagalkote, Sreenivas 1426c4a3e0a5SBagalkote, Sreenivas u16 count; 1427c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1428c4a3e0a5SBagalkote, Sreenivas int max_index; 1429c4a3e0a5SBagalkote, Sreenivas }; 1430c4a3e0a5SBagalkote, Sreenivas 1431c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 1432