1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 3c4a3e0a5SBagalkote, Sreenivas * 4e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2003-2013 LSI Corporation 5e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2013-2014 Avago Technologies 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 93f1530c1Sadam radford * as published by the Free Software Foundation; either version 2 103f1530c1Sadam radford * of the License, or (at your option) any later version. 113f1530c1Sadam radford * 123f1530c1Sadam radford * This program is distributed in the hope that it will be useful, 133f1530c1Sadam radford * but WITHOUT ANY WARRANTY; without even the implied warranty of 143f1530c1Sadam radford * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 153f1530c1Sadam radford * GNU General Public License for more details. 163f1530c1Sadam radford * 173f1530c1Sadam radford * You should have received a copy of the GNU General Public License 18e399065bSSumit.Saxena@avagotech.com * along with this program. If not, see <http://www.gnu.org/licenses/>. 19c4a3e0a5SBagalkote, Sreenivas * 20c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h 213f1530c1Sadam radford * 22e399065bSSumit.Saxena@avagotech.com * Authors: Avago Technologies 23e399065bSSumit.Saxena@avagotech.com * Kashyap Desai <kashyap.desai@avagotech.com> 24e399065bSSumit.Saxena@avagotech.com * Sumit Saxena <sumit.saxena@avagotech.com> 253f1530c1Sadam radford * 26e399065bSSumit.Saxena@avagotech.com * Send feedback to: megaraidlinux.pdl@avagotech.com 273f1530c1Sadam radford * 28e399065bSSumit.Saxena@avagotech.com * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29e399065bSSumit.Saxena@avagotech.com * San Jose, California 95131 30c4a3e0a5SBagalkote, Sreenivas */ 31c4a3e0a5SBagalkote, Sreenivas 32c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 33c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 34c4a3e0a5SBagalkote, Sreenivas 35a69b74d3SRandy Dunlap /* 36c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 37c4a3e0a5SBagalkote, Sreenivas */ 38afb2b5ddSsumit.saxena@avagotech.com #define MEGASAS_VERSION "06.808.16.00-rc1" 39afb2b5ddSsumit.saxena@avagotech.com #define MEGASAS_RELDATE "Oct. 8, 2015" 400e98936cSSumant Patro 410e98936cSSumant Patro /* 420e98936cSSumant Patro * Device IDs 430e98936cSSumant Patro */ 440e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 460e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 476610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 486610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 4987911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 5087911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 519c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52229fe47cSadam radford #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 5336807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d 5421d3c710SSumit.Saxena@lsi.com #define PCI_DEVICE_ID_LSI_FURY 0x005f 5590c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 5690c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 577364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 587364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 590e98936cSSumant Patro 60c4a3e0a5SBagalkote, Sreenivas /* 6139b72c3cSSumit.Saxena@lsi.com * Intel HBA SSDIDs 6239b72c3cSSumit.Saxena@lsi.com */ 6339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 6439b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 6539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 6639b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 6739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 6839b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 697364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 7039b72c3cSSumit.Saxena@lsi.com 7139b72c3cSSumit.Saxena@lsi.com /* 7290c204bcSsumit.saxena@avagotech.com * Intruder HBA SSDIDs 7390c204bcSsumit.saxena@avagotech.com */ 7490c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID1 0x9371 7590c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID2 0x9390 7690c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID3 0x9370 7790c204bcSsumit.saxena@avagotech.com 7890c204bcSsumit.saxena@avagotech.com /* 7939b72c3cSSumit.Saxena@lsi.com * Intel HBA branding 8039b72c3cSSumit.Saxena@lsi.com */ 8139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_BRANDING \ 8239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC080" 8339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_BRANDING \ 8439b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC040" 8539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_BRANDING \ 8639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3SC008" 8739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_BRANDING \ 8839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3MC044" 8939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_BRANDING \ 9039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC080" 9139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_BRANDING \ 9239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC040" 937364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 947364d34bSsumit.saxena@avagotech.com "Intel(R) Integrated RAID Module RMS3BC160" 9539b72c3cSSumit.Saxena@lsi.com 9639b72c3cSSumit.Saxena@lsi.com /* 97c4a3e0a5SBagalkote, Sreenivas * ===================================== 98c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 99c4a3e0a5SBagalkote, Sreenivas * ===================================== 100c4a3e0a5SBagalkote, Sreenivas */ 101c4a3e0a5SBagalkote, Sreenivas 102c4a3e0a5SBagalkote, Sreenivas /* 103c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 104c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 105c4a3e0a5SBagalkote, Sreenivas * "message frames" 106c4a3e0a5SBagalkote, Sreenivas */ 107c4a3e0a5SBagalkote, Sreenivas 108a69b74d3SRandy Dunlap /* 109c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 110c4a3e0a5SBagalkote, Sreenivas */ 111c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 112c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 113c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 114c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 115c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 116c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 117c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 118e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 119c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 120c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 121c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 122c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 123fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_FORCE_OCR 0x00000080 124fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_DMADONE 0x00000008 125fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 12639a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 1277e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002 128c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 129c4a3e0a5SBagalkote, Sreenivas 130a69b74d3SRandy Dunlap /* 131c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 132c4a3e0a5SBagalkote, Sreenivas * 133c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 134c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 135c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 136c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 137e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 138e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 139c4a3e0a5SBagalkote, Sreenivas */ 14039a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 14139a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 14239a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 14339a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 14439a98554Sbo yang 14539a98554Sbo yang #define MFI_ADP_RESET 0x00000040 146e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 147c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 148c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 149c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 150e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 151e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 152e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 153e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 154e3bbff9fSSumant Patro MFI_INIT_ABORT 155c4a3e0a5SBagalkote, Sreenivas 156a69b74d3SRandy Dunlap /* 157c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 158c4a3e0a5SBagalkote, Sreenivas */ 159c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 160c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 161c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 162c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 163c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 164c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 165c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 166c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 167c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 168c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 169f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 170c4a3e0a5SBagalkote, Sreenivas 1714026e9aaSSumit.Saxena@avagotech.com /* Driver internal */ 1724026e9aaSSumit.Saxena@avagotech.com #define DRV_DCMD_POLLED_MODE 0x1 1736d40afbcSSumit Saxena #define DRV_DCMD_SKIP_REFIRE 0x2 1744026e9aaSSumit.Saxena@avagotech.com 175a69b74d3SRandy Dunlap /* 176c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 177c4a3e0a5SBagalkote, Sreenivas */ 178c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 179c4a3e0a5SBagalkote, Sreenivas 180a69b74d3SRandy Dunlap /* 181c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 182c4a3e0a5SBagalkote, Sreenivas */ 183c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 184c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 185c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 186c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 187c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 188c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 189c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 190c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 191c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 192e5f93a36Sadam radford #define MFI_CMD_INVALID 0xff 193c4a3e0a5SBagalkote, Sreenivas 194c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 195bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 19621c9e160Sadam radford #define MR_DCMD_LD_LIST_QUERY 0x03010100 197c4a3e0a5SBagalkote, Sreenivas 198c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 199c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 200c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 201c4a3e0a5SBagalkote, Sreenivas 202c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 20331ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 204c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 205c4a3e0a5SBagalkote, Sreenivas 206c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 207c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 208c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 209c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 210c4a3e0a5SBagalkote, Sreenivas 211c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 212c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 213c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 21481e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 215c4a3e0a5SBagalkote, Sreenivas 216fc62b3fcSSumit.Saxena@avagotech.com #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 217fc62b3fcSSumit.Saxena@avagotech.com #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 218fc62b3fcSSumit.Saxena@avagotech.com 219a69b74d3SRandy Dunlap /* 220bc93d425SSumit.Saxena@lsi.com * Global functions 221bc93d425SSumit.Saxena@lsi.com */ 222bc93d425SSumit.Saxena@lsi.com extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 223bc93d425SSumit.Saxena@lsi.com 224bc93d425SSumit.Saxena@lsi.com 225bc93d425SSumit.Saxena@lsi.com /* 226c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 227c4a3e0a5SBagalkote, Sreenivas */ 228c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 229c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 230c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 231c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 232c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 233c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 234c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 235c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 236c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 237c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 238c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 239c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 240c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 241c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 242c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 243c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 244c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 245c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 246c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 247c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 248c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 249c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 250c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 251c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 252c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 253c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 254c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 255c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 256c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 257c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 258c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 259c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 260c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 261c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 262c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 263c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 264c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 265c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 266c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 267c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 268c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 269c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 270c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 271c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 272c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 273c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 274c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 275c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 276c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 277c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 278c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 279c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 280c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 281c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 282c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 283c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 284c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 285c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 28636807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 287c4a3e0a5SBagalkote, Sreenivas 288c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 289c4a3e0a5SBagalkote, Sreenivas }; 290c4a3e0a5SBagalkote, Sreenivas 291714f5177Ssumit.saxena@avagotech.com enum mfi_evt_class { 292714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEBUG = -2, 293714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_PROGRESS = -1, 294714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_INFO = 0, 295714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_WARNING = 1, 296714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_CRITICAL = 2, 297714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_FATAL = 3, 298714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEAD = 4 299714f5177Ssumit.saxena@avagotech.com }; 300714f5177Ssumit.saxena@avagotech.com 301c4a3e0a5SBagalkote, Sreenivas /* 302fc62b3fcSSumit.Saxena@avagotech.com * Crash dump related defines 303fc62b3fcSSumit.Saxena@avagotech.com */ 304fc62b3fcSSumit.Saxena@avagotech.com #define MAX_CRASH_DUMP_SIZE 512 305fc62b3fcSSumit.Saxena@avagotech.com #define CRASH_DMA_BUF_SIZE (1024 * 1024) 306fc62b3fcSSumit.Saxena@avagotech.com 307fc62b3fcSSumit.Saxena@avagotech.com enum MR_FW_CRASH_DUMP_STATE { 308fc62b3fcSSumit.Saxena@avagotech.com UNAVAILABLE = 0, 309fc62b3fcSSumit.Saxena@avagotech.com AVAILABLE = 1, 310fc62b3fcSSumit.Saxena@avagotech.com COPYING = 2, 311fc62b3fcSSumit.Saxena@avagotech.com COPIED = 3, 312fc62b3fcSSumit.Saxena@avagotech.com COPY_ERROR = 4, 313fc62b3fcSSumit.Saxena@avagotech.com }; 314fc62b3fcSSumit.Saxena@avagotech.com 315fc62b3fcSSumit.Saxena@avagotech.com enum _MR_CRASH_BUF_STATUS { 316fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_OFF = 0, 317fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_ON = 1, 318fc62b3fcSSumit.Saxena@avagotech.com }; 319fc62b3fcSSumit.Saxena@avagotech.com 320fc62b3fcSSumit.Saxena@avagotech.com /* 321c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 322c4a3e0a5SBagalkote, Sreenivas */ 323c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 324c4a3e0a5SBagalkote, Sreenivas 325c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 326c4a3e0a5SBagalkote, Sreenivas 327c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 328c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 329c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 330c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 331c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 332c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 333c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 334c4a3e0a5SBagalkote, Sreenivas 335c4a3e0a5SBagalkote, Sreenivas }; 336c4a3e0a5SBagalkote, Sreenivas 337c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 338c4a3e0a5SBagalkote, Sreenivas 339c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 340c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 341c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 342c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 343c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 344c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 345c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 346c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 347c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 348c4a3e0a5SBagalkote, Sreenivas 349c4a3e0a5SBagalkote, Sreenivas }; 350c4a3e0a5SBagalkote, Sreenivas 351c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 352c4a3e0a5SBagalkote, Sreenivas 353c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 354c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 355c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 356c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 357c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 358c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 359c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 360c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 361c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 362c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 363c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 364c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 365c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 366c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 367c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 368c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 369c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 370c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 371c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 372c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 373c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 37481e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 37581e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 37681e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 37781e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 37881e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 37981e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 38081e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 38181e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 38281e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 38381e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 38481e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 38581e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 38681e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 38781e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 38881e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 38981e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 390c4a3e0a5SBagalkote, Sreenivas }; 391c4a3e0a5SBagalkote, Sreenivas 392357ae967Ssumit.saxena@avagotech.com 393357ae967Ssumit.saxena@avagotech.com #define SGE_BUFFER_SIZE 4096 394c4a3e0a5SBagalkote, Sreenivas /* 39581e403ceSYang, Bo * define constants for device list query options 39681e403ceSYang, Bo */ 39781e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 39881e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 39981e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 40081e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 40181e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 40281e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 40381e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 40481e403ceSYang, Bo }; 40581e403ceSYang, Bo 40621c9e160Sadam radford enum MR_LD_QUERY_TYPE { 40721c9e160Sadam radford MR_LD_QUERY_TYPE_ALL = 0, 40821c9e160Sadam radford MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 40921c9e160Sadam radford MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 41021c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 41121c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 41221c9e160Sadam radford }; 41321c9e160Sadam radford 41421c9e160Sadam radford 4157e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 4167e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 4177e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 4187e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 4197e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 4207e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 4217e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 4227e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 4237e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 424c4bd2654Ssumit.saxena@avagotech.com #define MR_EVT_CTRL_PROP_CHANGED 0x012f 4257e8a75f4SYang, Bo 42681e403ceSYang, Bo enum MR_PD_STATE { 42781e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 42881e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 42981e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 43081e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 43181e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 43281e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 43381e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 43481e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 43581e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 43681e403ceSYang, Bo }; 43781e403ceSYang, Bo 43881e403ceSYang, Bo 43981e403ceSYang, Bo /* 44081e403ceSYang, Bo * defines the physical drive address structure 44181e403ceSYang, Bo */ 44281e403ceSYang, Bo struct MR_PD_ADDRESS { 4439ab9ed38SChristoph Hellwig __le16 deviceId; 44481e403ceSYang, Bo u16 enclDeviceId; 44581e403ceSYang, Bo 44681e403ceSYang, Bo union { 44781e403ceSYang, Bo struct { 44881e403ceSYang, Bo u8 enclIndex; 44981e403ceSYang, Bo u8 slotNumber; 45081e403ceSYang, Bo } mrPdAddress; 45181e403ceSYang, Bo struct { 45281e403ceSYang, Bo u8 enclPosition; 45381e403ceSYang, Bo u8 enclConnectorIndex; 45481e403ceSYang, Bo } mrEnclAddress; 45581e403ceSYang, Bo }; 45681e403ceSYang, Bo u8 scsiDevType; 45781e403ceSYang, Bo union { 45881e403ceSYang, Bo u8 connectedPortBitmap; 45981e403ceSYang, Bo u8 connectedPortNumbers; 46081e403ceSYang, Bo }; 46181e403ceSYang, Bo u64 sasAddr[2]; 46281e403ceSYang, Bo } __packed; 46381e403ceSYang, Bo 46481e403ceSYang, Bo /* 46581e403ceSYang, Bo * defines the physical drive list structure 46681e403ceSYang, Bo */ 46781e403ceSYang, Bo struct MR_PD_LIST { 4689ab9ed38SChristoph Hellwig __le32 size; 4699ab9ed38SChristoph Hellwig __le32 count; 47081e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 47181e403ceSYang, Bo } __packed; 47281e403ceSYang, Bo 47381e403ceSYang, Bo struct megasas_pd_list { 47481e403ceSYang, Bo u16 tid; 47581e403ceSYang, Bo u8 driveType; 47681e403ceSYang, Bo u8 driveState; 47781e403ceSYang, Bo } __packed; 47881e403ceSYang, Bo 47981e403ceSYang, Bo /* 480bdc6fb8dSYang, Bo * defines the logical drive reference structure 481bdc6fb8dSYang, Bo */ 482bdc6fb8dSYang, Bo union MR_LD_REF { 483bdc6fb8dSYang, Bo struct { 484bdc6fb8dSYang, Bo u8 targetId; 485bdc6fb8dSYang, Bo u8 reserved; 4869ab9ed38SChristoph Hellwig __le16 seqNum; 487bdc6fb8dSYang, Bo }; 4889ab9ed38SChristoph Hellwig __le32 ref; 489bdc6fb8dSYang, Bo } __packed; 490bdc6fb8dSYang, Bo 491bdc6fb8dSYang, Bo /* 492bdc6fb8dSYang, Bo * defines the logical drive list structure 493bdc6fb8dSYang, Bo */ 494bdc6fb8dSYang, Bo struct MR_LD_LIST { 4959ab9ed38SChristoph Hellwig __le32 ldCount; 4969ab9ed38SChristoph Hellwig __le32 reserved; 497bdc6fb8dSYang, Bo struct { 498bdc6fb8dSYang, Bo union MR_LD_REF ref; 499bdc6fb8dSYang, Bo u8 state; 500bdc6fb8dSYang, Bo u8 reserved[3]; 5019ab9ed38SChristoph Hellwig __le64 size; 50251087a86SSumit.Saxena@avagotech.com } ldList[MAX_LOGICAL_DRIVES_EXT]; 503bdc6fb8dSYang, Bo } __packed; 504bdc6fb8dSYang, Bo 50521c9e160Sadam radford struct MR_LD_TARGETID_LIST { 5069ab9ed38SChristoph Hellwig __le32 size; 5079ab9ed38SChristoph Hellwig __le32 count; 50821c9e160Sadam radford u8 pad[3]; 50951087a86SSumit.Saxena@avagotech.com u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 51021c9e160Sadam radford }; 51121c9e160Sadam radford 51221c9e160Sadam radford 513bdc6fb8dSYang, Bo /* 514c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 515c4a3e0a5SBagalkote, Sreenivas */ 516c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 517c4a3e0a5SBagalkote, Sreenivas 518c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 519c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 520c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 521c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 522c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 523c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 524c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 525c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 526c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 527c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 528c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 529c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 530c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 531c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 532c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 533c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 534c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 535c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 536c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 537c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 538c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 53939a98554Sbo yang u8 maintainPdFailHistory; 54039a98554Sbo yang u8 disallowHostRequestReordering; 54139a98554Sbo yang u8 abortCCOnError; 54239a98554Sbo yang u8 loadBalanceMode; 54339a98554Sbo yang u8 disableAutoDetectBackplane; 544c4a3e0a5SBagalkote, Sreenivas 54539a98554Sbo yang u8 snapVDSpace; 54639a98554Sbo yang 54739a98554Sbo yang /* 54839a98554Sbo yang * Add properties that can be controlled by 54939a98554Sbo yang * a bit in the following structure. 55039a98554Sbo yang */ 55139a98554Sbo yang struct { 55294cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 55394cd65ddSSumit.Saxena@lsi.com u32 reserved:18; 55494cd65ddSSumit.Saxena@lsi.com u32 enableJBOD:1; 55594cd65ddSSumit.Saxena@lsi.com u32 disableSpinDownHS:1; 55694cd65ddSSumit.Saxena@lsi.com u32 allowBootWithPinnedCache:1; 55794cd65ddSSumit.Saxena@lsi.com u32 disableOnlineCtrlReset:1; 55894cd65ddSSumit.Saxena@lsi.com u32 enableSecretKeyControl:1; 55994cd65ddSSumit.Saxena@lsi.com u32 autoEnhancedImport:1; 56094cd65ddSSumit.Saxena@lsi.com u32 enableSpinDownUnconfigured:1; 56194cd65ddSSumit.Saxena@lsi.com u32 SSDPatrolReadEnabled:1; 56294cd65ddSSumit.Saxena@lsi.com u32 SSDSMARTerEnabled:1; 56394cd65ddSSumit.Saxena@lsi.com u32 disableNCQ:1; 56494cd65ddSSumit.Saxena@lsi.com u32 useFdeOnly:1; 56594cd65ddSSumit.Saxena@lsi.com u32 prCorrectUnconfiguredAreas:1; 56694cd65ddSSumit.Saxena@lsi.com u32 SMARTerEnabled:1; 56794cd65ddSSumit.Saxena@lsi.com u32 copyBackDisabled:1; 56894cd65ddSSumit.Saxena@lsi.com #else 56939a98554Sbo yang u32 copyBackDisabled:1; 57039a98554Sbo yang u32 SMARTerEnabled:1; 57139a98554Sbo yang u32 prCorrectUnconfiguredAreas:1; 57239a98554Sbo yang u32 useFdeOnly:1; 57339a98554Sbo yang u32 disableNCQ:1; 57439a98554Sbo yang u32 SSDSMARTerEnabled:1; 57539a98554Sbo yang u32 SSDPatrolReadEnabled:1; 57639a98554Sbo yang u32 enableSpinDownUnconfigured:1; 57739a98554Sbo yang u32 autoEnhancedImport:1; 57839a98554Sbo yang u32 enableSecretKeyControl:1; 57939a98554Sbo yang u32 disableOnlineCtrlReset:1; 58039a98554Sbo yang u32 allowBootWithPinnedCache:1; 58139a98554Sbo yang u32 disableSpinDownHS:1; 58239a98554Sbo yang u32 enableJBOD:1; 58339a98554Sbo yang u32 reserved:18; 58494cd65ddSSumit.Saxena@lsi.com #endif 58539a98554Sbo yang } OnOffProperties; 58639a98554Sbo yang u8 autoSnapVDSpace; 58739a98554Sbo yang u8 viewSpace; 5889ab9ed38SChristoph Hellwig __le16 spinDownTime; 58939a98554Sbo yang u8 reserved[24]; 59081e403ceSYang, Bo } __packed; 591c4a3e0a5SBagalkote, Sreenivas 592c4a3e0a5SBagalkote, Sreenivas /* 593c4a3e0a5SBagalkote, Sreenivas * SAS controller information 594c4a3e0a5SBagalkote, Sreenivas */ 595c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 596c4a3e0a5SBagalkote, Sreenivas 597c4a3e0a5SBagalkote, Sreenivas /* 598c4a3e0a5SBagalkote, Sreenivas * PCI device information 599c4a3e0a5SBagalkote, Sreenivas */ 600c4a3e0a5SBagalkote, Sreenivas struct { 601c4a3e0a5SBagalkote, Sreenivas 6029ab9ed38SChristoph Hellwig __le16 vendor_id; 6039ab9ed38SChristoph Hellwig __le16 device_id; 6049ab9ed38SChristoph Hellwig __le16 sub_vendor_id; 6059ab9ed38SChristoph Hellwig __le16 sub_device_id; 606c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 607c4a3e0a5SBagalkote, Sreenivas 608c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 609c4a3e0a5SBagalkote, Sreenivas 610c4a3e0a5SBagalkote, Sreenivas /* 611c4a3e0a5SBagalkote, Sreenivas * Host interface information 612c4a3e0a5SBagalkote, Sreenivas */ 613c4a3e0a5SBagalkote, Sreenivas struct { 614c4a3e0a5SBagalkote, Sreenivas 615c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 616c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 617c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 618c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 619229fe47cSadam radford u8 SRIOV:1; 620229fe47cSadam radford u8 reserved_0:3; 621c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 622c4a3e0a5SBagalkote, Sreenivas u8 port_count; 623c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 624c4a3e0a5SBagalkote, Sreenivas 625c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 626c4a3e0a5SBagalkote, Sreenivas 627c4a3e0a5SBagalkote, Sreenivas /* 628c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 629c4a3e0a5SBagalkote, Sreenivas */ 630c4a3e0a5SBagalkote, Sreenivas struct { 631c4a3e0a5SBagalkote, Sreenivas 632c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 633c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 634c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 635c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 636c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 637c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 638c4a3e0a5SBagalkote, Sreenivas u8 port_count; 639c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 640c4a3e0a5SBagalkote, Sreenivas 641c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 642c4a3e0a5SBagalkote, Sreenivas 643c4a3e0a5SBagalkote, Sreenivas /* 644c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 645c4a3e0a5SBagalkote, Sreenivas */ 6469ab9ed38SChristoph Hellwig __le32 image_check_word; 6479ab9ed38SChristoph Hellwig __le32 image_component_count; 648c4a3e0a5SBagalkote, Sreenivas 649c4a3e0a5SBagalkote, Sreenivas struct { 650c4a3e0a5SBagalkote, Sreenivas 651c4a3e0a5SBagalkote, Sreenivas char name[8]; 652c4a3e0a5SBagalkote, Sreenivas char version[32]; 653c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 654c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 655c4a3e0a5SBagalkote, Sreenivas 656c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 657c4a3e0a5SBagalkote, Sreenivas 658c4a3e0a5SBagalkote, Sreenivas /* 659c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 660c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 661c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 662c4a3e0a5SBagalkote, Sreenivas * terminated 663c4a3e0a5SBagalkote, Sreenivas */ 6649ab9ed38SChristoph Hellwig __le32 pending_image_component_count; 665c4a3e0a5SBagalkote, Sreenivas 666c4a3e0a5SBagalkote, Sreenivas struct { 667c4a3e0a5SBagalkote, Sreenivas 668c4a3e0a5SBagalkote, Sreenivas char name[8]; 669c4a3e0a5SBagalkote, Sreenivas char version[32]; 670c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 671c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 672c4a3e0a5SBagalkote, Sreenivas 673c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 674c4a3e0a5SBagalkote, Sreenivas 675c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 676c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 677c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 678c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 679c4a3e0a5SBagalkote, Sreenivas 680c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 681c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 682c4a3e0a5SBagalkote, Sreenivas 683c4a3e0a5SBagalkote, Sreenivas /* 684c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 685c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 686c4a3e0a5SBagalkote, Sreenivas */ 687c4a3e0a5SBagalkote, Sreenivas struct { 688c4a3e0a5SBagalkote, Sreenivas 689c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 690c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 691c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 692c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 693c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 694c4a3e0a5SBagalkote, Sreenivas 695c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 696c4a3e0a5SBagalkote, Sreenivas 6979ab9ed38SChristoph Hellwig __le32 current_fw_time; 698c4a3e0a5SBagalkote, Sreenivas 699c4a3e0a5SBagalkote, Sreenivas /* 700c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 701c4a3e0a5SBagalkote, Sreenivas */ 7029ab9ed38SChristoph Hellwig __le16 max_concurrent_cmds; 7039ab9ed38SChristoph Hellwig __le16 max_sge_count; 7049ab9ed38SChristoph Hellwig __le32 max_request_size; 705c4a3e0a5SBagalkote, Sreenivas 706c4a3e0a5SBagalkote, Sreenivas /* 707c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 708c4a3e0a5SBagalkote, Sreenivas */ 7099ab9ed38SChristoph Hellwig __le16 ld_present_count; 7109ab9ed38SChristoph Hellwig __le16 ld_degraded_count; 7119ab9ed38SChristoph Hellwig __le16 ld_offline_count; 712c4a3e0a5SBagalkote, Sreenivas 7139ab9ed38SChristoph Hellwig __le16 pd_present_count; 7149ab9ed38SChristoph Hellwig __le16 pd_disk_present_count; 7159ab9ed38SChristoph Hellwig __le16 pd_disk_pred_failure_count; 7169ab9ed38SChristoph Hellwig __le16 pd_disk_failed_count; 717c4a3e0a5SBagalkote, Sreenivas 718c4a3e0a5SBagalkote, Sreenivas /* 719c4a3e0a5SBagalkote, Sreenivas * Memory size information 720c4a3e0a5SBagalkote, Sreenivas */ 7219ab9ed38SChristoph Hellwig __le16 nvram_size; 7229ab9ed38SChristoph Hellwig __le16 memory_size; 7239ab9ed38SChristoph Hellwig __le16 flash_size; 724c4a3e0a5SBagalkote, Sreenivas 725c4a3e0a5SBagalkote, Sreenivas /* 726c4a3e0a5SBagalkote, Sreenivas * Error counters 727c4a3e0a5SBagalkote, Sreenivas */ 7289ab9ed38SChristoph Hellwig __le16 mem_correctable_error_count; 7299ab9ed38SChristoph Hellwig __le16 mem_uncorrectable_error_count; 730c4a3e0a5SBagalkote, Sreenivas 731c4a3e0a5SBagalkote, Sreenivas /* 732c4a3e0a5SBagalkote, Sreenivas * Cluster information 733c4a3e0a5SBagalkote, Sreenivas */ 734c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 735c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 736c4a3e0a5SBagalkote, Sreenivas 737c4a3e0a5SBagalkote, Sreenivas /* 738c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 739c4a3e0a5SBagalkote, Sreenivas */ 7409ab9ed38SChristoph Hellwig __le16 max_strips_per_io; 741c4a3e0a5SBagalkote, Sreenivas 742c4a3e0a5SBagalkote, Sreenivas /* 743c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 744c4a3e0a5SBagalkote, Sreenivas */ 745c4a3e0a5SBagalkote, Sreenivas struct { 746c4a3e0a5SBagalkote, Sreenivas 747c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 748c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 749c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 750c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 751c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 752c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 753c4a3e0a5SBagalkote, Sreenivas 754c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 755c4a3e0a5SBagalkote, Sreenivas 756c4a3e0a5SBagalkote, Sreenivas struct { 757c4a3e0a5SBagalkote, Sreenivas 758c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 759c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 760c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 761c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 762c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 763c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 764c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 765c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 766c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 767c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 768c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 769c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 770c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 771c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 772c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 773c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 774c4a3e0a5SBagalkote, Sreenivas 775c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 776c4a3e0a5SBagalkote, Sreenivas 777c4a3e0a5SBagalkote, Sreenivas struct { 778c4a3e0a5SBagalkote, Sreenivas 779c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 780c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 781c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 782c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 783c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 784c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 785c4a3e0a5SBagalkote, Sreenivas 786c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 787c4a3e0a5SBagalkote, Sreenivas 788c4a3e0a5SBagalkote, Sreenivas struct { 789c4a3e0a5SBagalkote, Sreenivas 790c4a3e0a5SBagalkote, Sreenivas u8 min; 791c4a3e0a5SBagalkote, Sreenivas u8 max; 792c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 793c4a3e0a5SBagalkote, Sreenivas 794c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 795c4a3e0a5SBagalkote, Sreenivas 796c4a3e0a5SBagalkote, Sreenivas struct { 797c4a3e0a5SBagalkote, Sreenivas 798c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 799c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 800c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 801c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 802c4a3e0a5SBagalkote, Sreenivas 803c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 804c4a3e0a5SBagalkote, Sreenivas 805c4a3e0a5SBagalkote, Sreenivas struct { 806c4a3e0a5SBagalkote, Sreenivas 807c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 808c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 809c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 810c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 811c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 812c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 813c4a3e0a5SBagalkote, Sreenivas 814c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 815c4a3e0a5SBagalkote, Sreenivas 816c4a3e0a5SBagalkote, Sreenivas /* 817c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 818c4a3e0a5SBagalkote, Sreenivas */ 819c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 820c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 821c4a3e0a5SBagalkote, Sreenivas 822c4a3e0a5SBagalkote, Sreenivas /* 823c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 824c4a3e0a5SBagalkote, Sreenivas */ 825c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 826c4a3e0a5SBagalkote, Sreenivas 827c4a3e0a5SBagalkote, Sreenivas /* 828c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 829c4a3e0a5SBagalkote, Sreenivas */ 830c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 831c4a3e0a5SBagalkote, Sreenivas 832c4a3e0a5SBagalkote, Sreenivas 833bc93d425SSumit.Saxena@lsi.com /* 834bc93d425SSumit.Saxena@lsi.com * If adapterOperations.supportMoreThan8Phys is set, 835bc93d425SSumit.Saxena@lsi.com * and deviceInterface.portCount is greater than 8, 836bc93d425SSumit.Saxena@lsi.com * SAS Addrs for first 8 ports shall be populated in 837bc93d425SSumit.Saxena@lsi.com * deviceInterface.portAddr, and the rest shall be 838bc93d425SSumit.Saxena@lsi.com * populated in deviceInterfacePortAddr2. 839bc93d425SSumit.Saxena@lsi.com */ 8409ab9ed38SChristoph Hellwig __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 841bc93d425SSumit.Saxena@lsi.com u8 reserved3[128]; /*6e0h */ 842bc93d425SSumit.Saxena@lsi.com 843bc93d425SSumit.Saxena@lsi.com struct { /*760h */ 844bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_0:4; 845bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_0:12; 846bc93d425SSumit.Saxena@lsi.com 847bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1:4; 848bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1:12; 849bc93d425SSumit.Saxena@lsi.com 850bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_5:4; 851bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_5:12; 852bc93d425SSumit.Saxena@lsi.com 853bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E:4; 854bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E:12; 855bc93d425SSumit.Saxena@lsi.com 856bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_6:4; 857bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_6:12; 858bc93d425SSumit.Saxena@lsi.com 859bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_10:4; 860bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_10:12; 861bc93d425SSumit.Saxena@lsi.com 862bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_50:4; 863bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_50:12; 864bc93d425SSumit.Saxena@lsi.com 865bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_60:4; 866bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_60:12; 867bc93d425SSumit.Saxena@lsi.com 868bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E_RLQ0:4; 869bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E_RLQ0:12; 870bc93d425SSumit.Saxena@lsi.com 871bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E0_RLQ0:4; 872bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E0_RLQ0:12; 873bc93d425SSumit.Saxena@lsi.com 874bc93d425SSumit.Saxena@lsi.com u16 reserved[6]; 875bc93d425SSumit.Saxena@lsi.com } pdsForRaidLevels; 876bc93d425SSumit.Saxena@lsi.com 8779ab9ed38SChristoph Hellwig __le16 maxPds; /*780h */ 8789ab9ed38SChristoph Hellwig __le16 maxDedHSPs; /*782h */ 8799ab9ed38SChristoph Hellwig __le16 maxGlobalHSP; /*784h */ 8809ab9ed38SChristoph Hellwig __le16 ddfSize; /*786h */ 881bc93d425SSumit.Saxena@lsi.com u8 maxLdsPerArray; /*788h */ 882bc93d425SSumit.Saxena@lsi.com u8 partitionsInDDF; /*789h */ 883bc93d425SSumit.Saxena@lsi.com u8 lockKeyBinding; /*78ah */ 884bc93d425SSumit.Saxena@lsi.com u8 maxPITsPerLd; /*78bh */ 885bc93d425SSumit.Saxena@lsi.com u8 maxViewsPerLd; /*78ch */ 886bc93d425SSumit.Saxena@lsi.com u8 maxTargetId; /*78dh */ 8879ab9ed38SChristoph Hellwig __le16 maxBvlVdSize; /*78eh */ 888bc93d425SSumit.Saxena@lsi.com 8899ab9ed38SChristoph Hellwig __le16 maxConfigurableSSCSize; /*790h */ 8909ab9ed38SChristoph Hellwig __le16 currentSSCsize; /*792h */ 891bc93d425SSumit.Saxena@lsi.com 892bc93d425SSumit.Saxena@lsi.com char expanderFwVersion[12]; /*794h */ 893bc93d425SSumit.Saxena@lsi.com 8949ab9ed38SChristoph Hellwig __le16 PFKTrialTimeRemaining; /*7A0h */ 895bc93d425SSumit.Saxena@lsi.com 8969ab9ed38SChristoph Hellwig __le16 cacheMemorySize; /*7A2h */ 897bc93d425SSumit.Saxena@lsi.com 898bc93d425SSumit.Saxena@lsi.com struct { /*7A4h */ 89994cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 900229fe47cSadam radford u32 reserved:5; 901229fe47cSadam radford u32 activePassive:2; 902229fe47cSadam radford u32 supportConfigAutoBalance:1; 903229fe47cSadam radford u32 mpio:1; 904229fe47cSadam radford u32 supportDataLDonSSCArray:1; 905229fe47cSadam radford u32 supportPointInTimeProgress:1; 90694cd65ddSSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 90794cd65ddSSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 90894cd65ddSSumit.Saxena@lsi.com u32 headlessMode:1; 90994cd65ddSSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 91094cd65ddSSumit.Saxena@lsi.com u32 supportResetNow:1; 91194cd65ddSSumit.Saxena@lsi.com u32 realTimeScheduler:1; 91294cd65ddSSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 91394cd65ddSSumit.Saxena@lsi.com u32 supportPerfTuning:1; 91494cd65ddSSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 91594cd65ddSSumit.Saxena@lsi.com u32 supportJBOD:1; 91694cd65ddSSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 91794cd65ddSSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 91894cd65ddSSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 91994cd65ddSSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 92094cd65ddSSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 92194cd65ddSSumit.Saxena@lsi.com u32 supportShieldState:1; 92294cd65ddSSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 92394cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType3:1; 92494cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType2:1; 92594cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType1:1; 92694cd65ddSSumit.Saxena@lsi.com u32 supportPIcontroller:1; 92794cd65ddSSumit.Saxena@lsi.com #else 928bc93d425SSumit.Saxena@lsi.com u32 supportPIcontroller:1; 929bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType1:1; 930bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType2:1; 931bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType3:1; 932bc93d425SSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 933bc93d425SSumit.Saxena@lsi.com u32 supportShieldState:1; 934bc93d425SSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 935bc93d425SSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 936bc93d425SSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 937bc93d425SSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 938bc93d425SSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 939bc93d425SSumit.Saxena@lsi.com u32 supportJBOD:1; 940bc93d425SSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 941bc93d425SSumit.Saxena@lsi.com u32 supportPerfTuning:1; 942bc93d425SSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 943bc93d425SSumit.Saxena@lsi.com u32 realTimeScheduler:1; 944bc93d425SSumit.Saxena@lsi.com 945bc93d425SSumit.Saxena@lsi.com u32 supportResetNow:1; 946bc93d425SSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 947bc93d425SSumit.Saxena@lsi.com u32 headlessMode:1; 948bc93d425SSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 949bc93d425SSumit.Saxena@lsi.com 950bc93d425SSumit.Saxena@lsi.com 951bc93d425SSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 952229fe47cSadam radford u32 supportPointInTimeProgress:1; 953229fe47cSadam radford u32 supportDataLDonSSCArray:1; 954229fe47cSadam radford u32 mpio:1; 955229fe47cSadam radford u32 supportConfigAutoBalance:1; 956229fe47cSadam radford u32 activePassive:2; 957229fe47cSadam radford u32 reserved:5; 95894cd65ddSSumit.Saxena@lsi.com #endif 959bc93d425SSumit.Saxena@lsi.com } adapterOperations2; 960bc93d425SSumit.Saxena@lsi.com 961bc93d425SSumit.Saxena@lsi.com u8 driverVersion[32]; /*7A8h */ 962bc93d425SSumit.Saxena@lsi.com u8 maxDAPdCountSpinup60; /*7C8h */ 963bc93d425SSumit.Saxena@lsi.com u8 temperatureROC; /*7C9h */ 964bc93d425SSumit.Saxena@lsi.com u8 temperatureCtrl; /*7CAh */ 965bc93d425SSumit.Saxena@lsi.com u8 reserved4; /*7CBh */ 9669ab9ed38SChristoph Hellwig __le16 maxConfigurablePds; /*7CCh */ 967bc93d425SSumit.Saxena@lsi.com 968bc93d425SSumit.Saxena@lsi.com 969bc93d425SSumit.Saxena@lsi.com u8 reserved5[2]; /*0x7CDh */ 970bc93d425SSumit.Saxena@lsi.com 971bc93d425SSumit.Saxena@lsi.com /* 972bc93d425SSumit.Saxena@lsi.com * HA cluster information 973bc93d425SSumit.Saxena@lsi.com */ 974bc93d425SSumit.Saxena@lsi.com struct { 97551087a86SSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 97651087a86SSumit.Saxena@avagotech.com u32 reserved:26; 97751087a86SSumit.Saxena@avagotech.com u32 premiumFeatureMismatch:1; 97851087a86SSumit.Saxena@avagotech.com u32 ctrlPropIncompatible:1; 97951087a86SSumit.Saxena@avagotech.com u32 fwVersionMismatch:1; 98051087a86SSumit.Saxena@avagotech.com u32 hwIncompatible:1; 98151087a86SSumit.Saxena@avagotech.com u32 peerIsIncompatible:1; 98251087a86SSumit.Saxena@avagotech.com u32 peerIsPresent:1; 98351087a86SSumit.Saxena@avagotech.com #else 984bc93d425SSumit.Saxena@lsi.com u32 peerIsPresent:1; 985bc93d425SSumit.Saxena@lsi.com u32 peerIsIncompatible:1; 986bc93d425SSumit.Saxena@lsi.com u32 hwIncompatible:1; 987bc93d425SSumit.Saxena@lsi.com u32 fwVersionMismatch:1; 988bc93d425SSumit.Saxena@lsi.com u32 ctrlPropIncompatible:1; 989bc93d425SSumit.Saxena@lsi.com u32 premiumFeatureMismatch:1; 990bc93d425SSumit.Saxena@lsi.com u32 reserved:26; 99151087a86SSumit.Saxena@avagotech.com #endif 992bc93d425SSumit.Saxena@lsi.com } cluster; 993bc93d425SSumit.Saxena@lsi.com 994bc93d425SSumit.Saxena@lsi.com char clusterId[16]; /*7D4h */ 995229fe47cSadam radford struct { 996229fe47cSadam radford u8 maxVFsSupported; /*0x7E4*/ 997229fe47cSadam radford u8 numVFsEnabled; /*0x7E5*/ 998229fe47cSadam radford u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 999229fe47cSadam radford u8 reserved; /*0x7E7*/ 1000229fe47cSadam radford } iov; 1001bc93d425SSumit.Saxena@lsi.com 1002fc62b3fcSSumit.Saxena@avagotech.com struct { 1003fc62b3fcSSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 10043761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 10053761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 10060be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 10070be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 10080be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 10090be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 10107497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 10117497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 10127497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 10137497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 10147497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 10157497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 10167497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 10177497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 10187497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 10197497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 10207497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 10217497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 10227497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 1023fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 102451087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 102551087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 102651087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 102751087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 102851087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 1029fc62b3fcSSumit.Saxena@avagotech.com #else 103051087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 103151087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 103251087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 103351087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 103451087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 1035fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 10367497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 10377497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 10387497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 10397497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 10407497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 10417497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 10427497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 10437497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 10447497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 10457497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 10467497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 10477497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 10487497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 10490be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 10500be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 10510be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 10520be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 10533761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 10543761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 1055fc62b3fcSSumit.Saxena@avagotech.com #endif 1056fc62b3fcSSumit.Saxena@avagotech.com } adapterOperations3; 1057fc62b3fcSSumit.Saxena@avagotech.com 1058fc62b3fcSSumit.Saxena@avagotech.com u8 pad[0x800-0x7EC]; 105981e403ceSYang, Bo } __packed; 1060c4a3e0a5SBagalkote, Sreenivas 1061c4a3e0a5SBagalkote, Sreenivas /* 1062c4a3e0a5SBagalkote, Sreenivas * =============================== 1063c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 1064c4a3e0a5SBagalkote, Sreenivas * =============================== 1065c4a3e0a5SBagalkote, Sreenivas */ 1066c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 106751087a86SSumit.Saxena@avagotech.com #define MEGASAS_MAX_LD_CHANNELS 2 1068c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1069c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 1070c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1071c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 1072c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 10736bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256 107481e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 107581e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1076bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1077bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1078c4a3e0a5SBagalkote, Sreenivas 10791fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024) 108042a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1081658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 1082658dcedbSSumant Patro 108305e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 108405e9ebbeSSumant Patro 108551087a86SSumit.Saxena@avagotech.com #define VD_EXT_DEBUG 0 108651087a86SSumit.Saxena@avagotech.com 108711c71cb4SSumit Saxena #define SCAN_PD_CHANNEL 0x1 108811c71cb4SSumit Saxena #define SCAN_VD_CHANNEL 0x2 108990dc9d98SSumit.Saxena@avagotech.com 10907497cde8SSumit.Saxena@avagotech.com enum MR_SCSI_CMD_TYPE { 10917497cde8SSumit.Saxena@avagotech.com READ_WRITE_LDIO = 0, 10927497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_LDIO = 1, 10937497cde8SSumit.Saxena@avagotech.com READ_WRITE_SYSPDIO = 2, 10947497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_SYSPDIO = 3, 10957497cde8SSumit.Saxena@avagotech.com }; 10967497cde8SSumit.Saxena@avagotech.com 10976d40afbcSSumit Saxena enum DCMD_TIMEOUT_ACTION { 10986d40afbcSSumit Saxena INITIATE_OCR = 0, 10996d40afbcSSumit Saxena KILL_ADAPTER = 1, 11006d40afbcSSumit Saxena IGNORE_TIMEOUT = 2, 11016d40afbcSSumit Saxena }; 1102d532dbe2Sbo yang /* Frame Type */ 1103d532dbe2Sbo yang #define IO_FRAME 0 1104d532dbe2Sbo yang #define PTHRU_FRAME 1 1105d532dbe2Sbo yang 1106c4a3e0a5SBagalkote, Sreenivas /* 1107c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 1108c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1109c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 1110c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 1111c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1112c4a3e0a5SBagalkote, Sreenivas */ 1113c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 11142a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1115c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 1116c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 111705e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1118c5daa6a9Sadam radford #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 111990dc9d98SSumit.Saxena@avagotech.com #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1120c4a3e0a5SBagalkote, Sreenivas /* 1121c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 1122c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 1123c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 1124c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1125c4a3e0a5SBagalkote, Sreenivas * is shown below 1126c4a3e0a5SBagalkote, Sreenivas */ 1127c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 11287bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 1129ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_INTERNAL_CMDS 5 1130ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_IOCTL_CMDS 3 1131f26ac3a1SSumit.Saxena@avagotech.com #define MEGASAS_MFI_IOCTL_CMDS 27 1132c4a3e0a5SBagalkote, Sreenivas 1133d46a3ad6SSumit.Saxena@lsi.com #define MEGASAS_MAX_MSIX_QUEUES 128 1134c4a3e0a5SBagalkote, Sreenivas /* 1135c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1136c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 1137c4a3e0a5SBagalkote, Sreenivas */ 1138c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1139c4a3e0a5SBagalkote, Sreenivas 114039a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 114139a98554Sbo yang 114239a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 114339a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 114439a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 114539a98554Sbo yang 1146c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 114714faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 11486d40afbcSSumit Saxena #define MFI_IO_TIMEOUT_SECS 180 1149229fe47cSadam radford #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1150229fe47cSadam radford #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1151229fe47cSadam radford #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1152f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 11536610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 11546610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 115587911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 115687911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 11570e98936cSSumant Patro 115839a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 115939a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 116039a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 1161d46a3ad6SSumit.Saxena@lsi.com 1162d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1163d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1164d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1165d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_MSIX_REG_ARRAY 16 11660e98936cSSumant Patro /* 11670e98936cSSumant Patro * register set for both 1068 and 1078 controllers 11680e98936cSSumant Patro * structure extended for 1078 registers 11690e98936cSSumant Patro */ 1170c4a3e0a5SBagalkote, Sreenivas 1171f9876f0bSSumant Patro struct megasas_register_set { 11729c915a8cSadam radford u32 doorbell; /*0000h*/ 11739c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/ 11749c915a8cSadam radford u32 fusion_host_diag; /*0008h*/ 11759c915a8cSadam radford u32 reserved_01; /*000Ch*/ 1176c4a3e0a5SBagalkote, Sreenivas 1177c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 1178c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 1179c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 1180c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 1181c4a3e0a5SBagalkote, Sreenivas 1182c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 1183c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 1184c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 1185c4a3e0a5SBagalkote, Sreenivas 1186c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 1187c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 1188c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 1189c4a3e0a5SBagalkote, Sreenivas 1190c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 1191c4a3e0a5SBagalkote, Sreenivas 1192c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 1193c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 1194c4a3e0a5SBagalkote, Sreenivas 11959c915a8cSadam radford u32 reserved_2[9]; /*0048h*/ 11969c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/ 11979c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/ 1198c4a3e0a5SBagalkote, Sreenivas 1199f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 1200f9876f0bSSumant Patro 1201f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 1202f9876f0bSSumant Patro 1203f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 12049c915a8cSadam radford u32 outbound_scratch_pad_2; /*00B4h*/ 1205f9876f0bSSumant Patro 12069c915a8cSadam radford u32 reserved_4[2]; /*00B8h*/ 1207f9876f0bSSumant Patro 1208f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 1209f9876f0bSSumant Patro 1210f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 1211f9876f0bSSumant Patro 1212f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 121339a98554Sbo yang u32 res_6[11]; /*CCh*/ 121439a98554Sbo yang u32 host_diag; 121539a98554Sbo yang u32 seq_offset; 121639a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 1217c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1218c4a3e0a5SBagalkote, Sreenivas 1219c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 1220c4a3e0a5SBagalkote, Sreenivas 12219ab9ed38SChristoph Hellwig __le32 phys_addr; 12229ab9ed38SChristoph Hellwig __le32 length; 1223c4a3e0a5SBagalkote, Sreenivas 1224c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1225c4a3e0a5SBagalkote, Sreenivas 1226c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 1227c4a3e0a5SBagalkote, Sreenivas 12289ab9ed38SChristoph Hellwig __le64 phys_addr; 12299ab9ed38SChristoph Hellwig __le32 length; 1230c4a3e0a5SBagalkote, Sreenivas 1231c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1232c4a3e0a5SBagalkote, Sreenivas 1233f4c9a131SYang, Bo struct megasas_sge_skinny { 12349ab9ed38SChristoph Hellwig __le64 phys_addr; 12359ab9ed38SChristoph Hellwig __le32 length; 12369ab9ed38SChristoph Hellwig __le32 flag; 1237f4c9a131SYang, Bo } __packed; 1238f4c9a131SYang, Bo 1239c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 1240c4a3e0a5SBagalkote, Sreenivas 1241c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 1242c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 1243f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 1244c4a3e0a5SBagalkote, Sreenivas 1245c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1246c4a3e0a5SBagalkote, Sreenivas 1247c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 1248c4a3e0a5SBagalkote, Sreenivas 1249c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1250c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1251c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1252c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1253c4a3e0a5SBagalkote, Sreenivas 1254c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1255c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1256c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1257c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1258c4a3e0a5SBagalkote, Sreenivas 12599ab9ed38SChristoph Hellwig __le32 context; /*08h */ 12609ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1261c4a3e0a5SBagalkote, Sreenivas 12629ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 12639ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 12649ab9ed38SChristoph Hellwig __le32 data_xferlen; /*14h */ 1265c4a3e0a5SBagalkote, Sreenivas 1266c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1267c4a3e0a5SBagalkote, Sreenivas 1268c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 1269c4a3e0a5SBagalkote, Sreenivas 1270c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 1271c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 1272c4a3e0a5SBagalkote, Sreenivas 1273c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1274c4a3e0a5SBagalkote, Sreenivas 1275d46a3ad6SSumit.Saxena@lsi.com typedef union _MFI_CAPABILITIES { 1276d46a3ad6SSumit.Saxena@lsi.com struct { 127794cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 1278bd5f9484Ssumit.saxena@avagotech.com u32 reserved:23; 1279bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 12800be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 12817497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 12827497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 1283d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 128451087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 12857497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 128694cd65ddSSumit.Saxena@lsi.com u32 support_additional_msix:1; 128794cd65ddSSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 128894cd65ddSSumit.Saxena@lsi.com #else 1289d46a3ad6SSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 1290d46a3ad6SSumit.Saxena@lsi.com u32 support_additional_msix:1; 12917497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 129251087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 1293d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 12947497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 12957497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 12960be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 1297bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 1298bd5f9484Ssumit.saxena@avagotech.com u32 reserved:23; 129994cd65ddSSumit.Saxena@lsi.com #endif 1300d46a3ad6SSumit.Saxena@lsi.com } mfi_capabilities; 13019ab9ed38SChristoph Hellwig __le32 reg; 1302d46a3ad6SSumit.Saxena@lsi.com } MFI_CAPABILITIES; 1303d46a3ad6SSumit.Saxena@lsi.com 1304c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 1305c4a3e0a5SBagalkote, Sreenivas 1306c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1307c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1308c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1309c4a3e0a5SBagalkote, Sreenivas 1310c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 1311d46a3ad6SSumit.Saxena@lsi.com MFI_CAPABILITIES driver_operations; /*04h*/ 1312c4a3e0a5SBagalkote, Sreenivas 13139ab9ed38SChristoph Hellwig __le32 context; /*08h */ 13149ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1315c4a3e0a5SBagalkote, Sreenivas 13169ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 13179ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 13189ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1319c4a3e0a5SBagalkote, Sreenivas 13209ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_lo; /*18h */ 13219ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_hi; /*1Ch */ 13229ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_lo; /*20h */ 13239ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_hi; /*24h */ 13249ab9ed38SChristoph Hellwig __le32 reserved_4[2]; /*28h */ 13259ab9ed38SChristoph Hellwig __le32 system_info_lo; /*30h */ 13269ab9ed38SChristoph Hellwig __le32 system_info_hi; /*34h */ 13279ab9ed38SChristoph Hellwig __le32 reserved_5[2]; /*38h */ 1328c4a3e0a5SBagalkote, Sreenivas 1329c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1330c4a3e0a5SBagalkote, Sreenivas 1331c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 1332c4a3e0a5SBagalkote, Sreenivas 13339ab9ed38SChristoph Hellwig __le32 init_flags; /*00h */ 13349ab9ed38SChristoph Hellwig __le32 reply_queue_entries; /*04h */ 1335c4a3e0a5SBagalkote, Sreenivas 13369ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_lo; /*08h */ 13379ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 13389ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_lo; /*10h */ 13399ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_hi; /*14h */ 13409ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_lo; /*18h */ 13419ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_hi; /*1Ch */ 1342c4a3e0a5SBagalkote, Sreenivas 1343c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1344c4a3e0a5SBagalkote, Sreenivas 1345c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 1346c4a3e0a5SBagalkote, Sreenivas 1347c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1348c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1349c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1350c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1351c4a3e0a5SBagalkote, Sreenivas 1352c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1353c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 1354c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 1355c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1356c4a3e0a5SBagalkote, Sreenivas 13579ab9ed38SChristoph Hellwig __le32 context; /*08h */ 13589ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1359c4a3e0a5SBagalkote, Sreenivas 13609ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 13619ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 13629ab9ed38SChristoph Hellwig __le32 lba_count; /*14h */ 1363c4a3e0a5SBagalkote, Sreenivas 13649ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 13659ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1366c4a3e0a5SBagalkote, Sreenivas 13679ab9ed38SChristoph Hellwig __le32 start_lba_lo; /*20h */ 13689ab9ed38SChristoph Hellwig __le32 start_lba_hi; /*24h */ 1369c4a3e0a5SBagalkote, Sreenivas 1370c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1371c4a3e0a5SBagalkote, Sreenivas 1372c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1373c4a3e0a5SBagalkote, Sreenivas 1374c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 1375c4a3e0a5SBagalkote, Sreenivas 1376c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1377c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1378c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1379c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1380c4a3e0a5SBagalkote, Sreenivas 1381c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1382c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1383c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1384c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1385c4a3e0a5SBagalkote, Sreenivas 13869ab9ed38SChristoph Hellwig __le32 context; /*08h */ 13879ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1388c4a3e0a5SBagalkote, Sreenivas 13899ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 13909ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 13919ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1392c4a3e0a5SBagalkote, Sreenivas 13939ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 13949ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1395c4a3e0a5SBagalkote, Sreenivas 1396c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 1397c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 1398c4a3e0a5SBagalkote, Sreenivas 1399c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1400c4a3e0a5SBagalkote, Sreenivas 1401c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 1402c4a3e0a5SBagalkote, Sreenivas 1403c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1404c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1405c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1406c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 1407c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1408c4a3e0a5SBagalkote, Sreenivas 14099ab9ed38SChristoph Hellwig __le32 context; /*08h */ 14109ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1411c4a3e0a5SBagalkote, Sreenivas 14129ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 14139ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1414c4a3e0a5SBagalkote, Sreenivas 14159ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 14169ab9ed38SChristoph Hellwig __le32 opcode; /*18h */ 1417c4a3e0a5SBagalkote, Sreenivas 1418c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 1419c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 14209ab9ed38SChristoph Hellwig __le16 s[6]; 14219ab9ed38SChristoph Hellwig __le32 w[3]; 1422c4a3e0a5SBagalkote, Sreenivas } mbox; 1423c4a3e0a5SBagalkote, Sreenivas 1424c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1425c4a3e0a5SBagalkote, Sreenivas 1426c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1427c4a3e0a5SBagalkote, Sreenivas 1428c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 1429c4a3e0a5SBagalkote, Sreenivas 1430c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1431c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1432c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1433c4a3e0a5SBagalkote, Sreenivas 1434c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 14359ab9ed38SChristoph Hellwig __le32 reserved_2; /*04h */ 1436c4a3e0a5SBagalkote, Sreenivas 14379ab9ed38SChristoph Hellwig __le32 context; /*08h */ 14389ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1439c4a3e0a5SBagalkote, Sreenivas 14409ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 14419ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 14429ab9ed38SChristoph Hellwig __le32 reserved_4; /*14h */ 1443c4a3e0a5SBagalkote, Sreenivas 14449ab9ed38SChristoph Hellwig __le32 abort_context; /*18h */ 14459ab9ed38SChristoph Hellwig __le32 pad_1; /*1Ch */ 1446c4a3e0a5SBagalkote, Sreenivas 14479ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_lo; /*20h */ 14489ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_hi; /*24h */ 1449c4a3e0a5SBagalkote, Sreenivas 14509ab9ed38SChristoph Hellwig __le32 reserved_5[6]; /*28h */ 1451c4a3e0a5SBagalkote, Sreenivas 1452c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1453c4a3e0a5SBagalkote, Sreenivas 1454c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1455c4a3e0a5SBagalkote, Sreenivas 1456c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1457c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1458c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1459c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1460c4a3e0a5SBagalkote, Sreenivas 1461c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1462c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1463c4a3e0a5SBagalkote, Sreenivas 14649ab9ed38SChristoph Hellwig __le32 context; /*08h */ 14659ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1466c4a3e0a5SBagalkote, Sreenivas 14679ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 14689ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1469c4a3e0a5SBagalkote, Sreenivas 14709ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 14719ab9ed38SChristoph Hellwig __le64 sas_addr; /*18h */ 1472c4a3e0a5SBagalkote, Sreenivas 1473c4a3e0a5SBagalkote, Sreenivas union { 1474c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1475c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1476c4a3e0a5SBagalkote, Sreenivas } sgl; 1477c4a3e0a5SBagalkote, Sreenivas 1478c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1479c4a3e0a5SBagalkote, Sreenivas 1480c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1481c4a3e0a5SBagalkote, Sreenivas 1482c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1483c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1484c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1485c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1486c4a3e0a5SBagalkote, Sreenivas 1487c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1488c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1489c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1490c4a3e0a5SBagalkote, Sreenivas 14919ab9ed38SChristoph Hellwig __le32 context; /*08h */ 14929ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1493c4a3e0a5SBagalkote, Sreenivas 14949ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 14959ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1496c4a3e0a5SBagalkote, Sreenivas 14979ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1498c4a3e0a5SBagalkote, Sreenivas 14999ab9ed38SChristoph Hellwig __le16 fis[10]; /*18h */ 15009ab9ed38SChristoph Hellwig __le32 stp_flags; 1501c4a3e0a5SBagalkote, Sreenivas 1502c4a3e0a5SBagalkote, Sreenivas union { 1503c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1504c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1505c4a3e0a5SBagalkote, Sreenivas } sgl; 1506c4a3e0a5SBagalkote, Sreenivas 1507c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1508c4a3e0a5SBagalkote, Sreenivas 1509c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1510c4a3e0a5SBagalkote, Sreenivas 1511c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1512c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1513c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1514c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1515c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1516c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1517c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1518c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1519c4a3e0a5SBagalkote, Sreenivas 1520c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1521c4a3e0a5SBagalkote, Sreenivas }; 1522c4a3e0a5SBagalkote, Sreenivas 152318365b13SSumit Saxena /** 152418365b13SSumit Saxena * struct MR_PRIV_DEVICE - sdev private hostdata 152518365b13SSumit Saxena * @is_tm_capable: firmware managed tm_capable flag 152618365b13SSumit Saxena * @tm_busy: TM request is in progress 152718365b13SSumit Saxena */ 152818365b13SSumit Saxena struct MR_PRIV_DEVICE { 152918365b13SSumit Saxena bool is_tm_capable; 153018365b13SSumit Saxena bool tm_busy; 153118365b13SSumit Saxena }; 1532c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1533c4a3e0a5SBagalkote, Sreenivas 1534c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 1535c4a3e0a5SBagalkote, Sreenivas 1536c4a3e0a5SBagalkote, Sreenivas struct { 1537be26374bSSumit.Saxena@lsi.com #ifndef __BIG_ENDIAN_BITFIELD 1538c4a3e0a5SBagalkote, Sreenivas u16 locale; 1539c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1540c4a3e0a5SBagalkote, Sreenivas s8 class; 1541be26374bSSumit.Saxena@lsi.com #else 1542be26374bSSumit.Saxena@lsi.com s8 class; 1543be26374bSSumit.Saxena@lsi.com u8 reserved; 1544be26374bSSumit.Saxena@lsi.com u16 locale; 1545be26374bSSumit.Saxena@lsi.com #endif 1546c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 1547c4a3e0a5SBagalkote, Sreenivas 1548c4a3e0a5SBagalkote, Sreenivas u32 word; 1549c4a3e0a5SBagalkote, Sreenivas 1550c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1551c4a3e0a5SBagalkote, Sreenivas 1552c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 15539ab9ed38SChristoph Hellwig __le32 newest_seq_num; 15549ab9ed38SChristoph Hellwig __le32 oldest_seq_num; 15559ab9ed38SChristoph Hellwig __le32 clear_seq_num; 15569ab9ed38SChristoph Hellwig __le32 shutdown_seq_num; 15579ab9ed38SChristoph Hellwig __le32 boot_seq_num; 1558c4a3e0a5SBagalkote, Sreenivas 1559c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1560c4a3e0a5SBagalkote, Sreenivas 1561c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1562c4a3e0a5SBagalkote, Sreenivas 15639ab9ed38SChristoph Hellwig __le16 progress; 15649ab9ed38SChristoph Hellwig __le16 elapsed_seconds; 1565c4a3e0a5SBagalkote, Sreenivas 1566c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1567c4a3e0a5SBagalkote, Sreenivas 1568c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1569c4a3e0a5SBagalkote, Sreenivas 1570c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1571c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1572c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1573c4a3e0a5SBagalkote, Sreenivas 1574c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1575c4a3e0a5SBagalkote, Sreenivas 1576c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1577c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1578c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1579c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1580c4a3e0a5SBagalkote, Sreenivas 1581c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1582c4a3e0a5SBagalkote, Sreenivas 1583c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1584c4a3e0a5SBagalkote, Sreenivas 15859ab9ed38SChristoph Hellwig __le32 seq_num; 15869ab9ed38SChristoph Hellwig __le32 time_stamp; 15879ab9ed38SChristoph Hellwig __le32 code; 1588c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1589c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1590c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1591c4a3e0a5SBagalkote, Sreenivas 1592c4a3e0a5SBagalkote, Sreenivas union { 1593c4a3e0a5SBagalkote, Sreenivas struct { 1594c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1595c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1596c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1597c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1598c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1599c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1600c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1601c4a3e0a5SBagalkote, Sreenivas 1602c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1603c4a3e0a5SBagalkote, Sreenivas 1604c4a3e0a5SBagalkote, Sreenivas struct { 1605c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 16069ab9ed38SChristoph Hellwig __le64 count; 1607c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1608c4a3e0a5SBagalkote, Sreenivas 1609c4a3e0a5SBagalkote, Sreenivas struct { 16109ab9ed38SChristoph Hellwig __le64 lba; 1611c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1612c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1613c4a3e0a5SBagalkote, Sreenivas 1614c4a3e0a5SBagalkote, Sreenivas struct { 1615c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 16169ab9ed38SChristoph Hellwig __le32 prevOwner; 16179ab9ed38SChristoph Hellwig __le32 newOwner; 1618c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1619c4a3e0a5SBagalkote, Sreenivas 1620c4a3e0a5SBagalkote, Sreenivas struct { 1621c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1622c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1623c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1624c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1625c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1626c4a3e0a5SBagalkote, Sreenivas 1627c4a3e0a5SBagalkote, Sreenivas struct { 1628c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1629c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1630c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1631c4a3e0a5SBagalkote, Sreenivas 1632c4a3e0a5SBagalkote, Sreenivas struct { 1633c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1634c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1635c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1636c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1637c4a3e0a5SBagalkote, Sreenivas 1638c4a3e0a5SBagalkote, Sreenivas struct { 1639c4a3e0a5SBagalkote, Sreenivas u64 strip; 1640c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1641c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1642c4a3e0a5SBagalkote, Sreenivas 1643c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1644c4a3e0a5SBagalkote, Sreenivas 1645c4a3e0a5SBagalkote, Sreenivas struct { 1646c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1647c4a3e0a5SBagalkote, Sreenivas u32 err; 1648c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1649c4a3e0a5SBagalkote, Sreenivas 1650c4a3e0a5SBagalkote, Sreenivas struct { 1651c4a3e0a5SBagalkote, Sreenivas u64 lba; 1652c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1653c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1654c4a3e0a5SBagalkote, Sreenivas 1655c4a3e0a5SBagalkote, Sreenivas struct { 1656c4a3e0a5SBagalkote, Sreenivas u64 lba; 1657c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1658c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1659c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1660c4a3e0a5SBagalkote, Sreenivas 1661c4a3e0a5SBagalkote, Sreenivas struct { 1662c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1663c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1664c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1665c4a3e0a5SBagalkote, Sreenivas 1666c4a3e0a5SBagalkote, Sreenivas struct { 1667c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1668c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1669c4a3e0a5SBagalkote, Sreenivas u32 newState; 1670c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1671c4a3e0a5SBagalkote, Sreenivas 1672c4a3e0a5SBagalkote, Sreenivas struct { 1673c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 16749ab9ed38SChristoph Hellwig __le16 deviceId; 1675c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1676c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1677c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1678c4a3e0a5SBagalkote, Sreenivas 1679c4a3e0a5SBagalkote, Sreenivas u32 rate; 1680c4a3e0a5SBagalkote, Sreenivas char str[96]; 1681c4a3e0a5SBagalkote, Sreenivas 1682c4a3e0a5SBagalkote, Sreenivas struct { 1683c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1684c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1685c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1686c4a3e0a5SBagalkote, Sreenivas 1687c4a3e0a5SBagalkote, Sreenivas struct { 1688c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1689c4a3e0a5SBagalkote, Sreenivas u32 elog; 1690c4a3e0a5SBagalkote, Sreenivas char str[64]; 1691c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1692c4a3e0a5SBagalkote, Sreenivas 1693c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 16949ab9ed38SChristoph Hellwig __le16 s[48]; 16959ab9ed38SChristoph Hellwig __le32 w[24]; 16969ab9ed38SChristoph Hellwig __le64 d[12]; 1697c4a3e0a5SBagalkote, Sreenivas } args; 1698c4a3e0a5SBagalkote, Sreenivas 1699c4a3e0a5SBagalkote, Sreenivas char description[128]; 1700c4a3e0a5SBagalkote, Sreenivas 1701c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1702c4a3e0a5SBagalkote, Sreenivas 17037e8a75f4SYang, Bo struct megasas_aen_event { 1704c1d390d8SXiaotian Feng struct delayed_work hotplug_work; 17057e8a75f4SYang, Bo struct megasas_instance *instance; 17067e8a75f4SYang, Bo }; 17077e8a75f4SYang, Bo 1708c8e858feSadam radford struct megasas_irq_context { 1709c8e858feSadam radford struct megasas_instance *instance; 1710c8e858feSadam radford u32 MSIxIndex; 1711c8e858feSadam radford }; 1712c8e858feSadam radford 17135765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO { 17145765c5b8SSumit.Saxena@avagotech.com u8 infoVersion; 17155765c5b8SSumit.Saxena@avagotech.com u8 systemIdLength; 17165765c5b8SSumit.Saxena@avagotech.com u16 reserved0; 17175765c5b8SSumit.Saxena@avagotech.com u8 systemId[64]; 17185765c5b8SSumit.Saxena@avagotech.com u8 reserved[1980]; 17195765c5b8SSumit.Saxena@avagotech.com }; 17205765c5b8SSumit.Saxena@avagotech.com 1721c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1722c4a3e0a5SBagalkote, Sreenivas 17239ab9ed38SChristoph Hellwig __le32 *producer; 1724c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 17259ab9ed38SChristoph Hellwig __le32 *consumer; 1726c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 17275765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO *system_info_buf; 17285765c5b8SSumit.Saxena@avagotech.com dma_addr_t system_info_h; 1729229fe47cSadam radford struct MR_LD_VF_AFFILIATION *vf_affiliation; 1730229fe47cSadam radford dma_addr_t vf_affiliation_h; 1731229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 1732229fe47cSadam radford dma_addr_t vf_affiliation_111_h; 1733229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 1734229fe47cSadam radford dma_addr_t hb_host_mem_h; 1735c4a3e0a5SBagalkote, Sreenivas 17369ab9ed38SChristoph Hellwig __le32 *reply_queue; 1737c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 1738c4a3e0a5SBagalkote, Sreenivas 1739fc62b3fcSSumit.Saxena@avagotech.com u32 *crash_dump_buf; 1740fc62b3fcSSumit.Saxena@avagotech.com dma_addr_t crash_dump_h; 1741fc62b3fcSSumit.Saxena@avagotech.com void *crash_buf[MAX_CRASH_DUMP_SIZE]; 1742fc62b3fcSSumit.Saxena@avagotech.com u32 crash_buf_pages; 1743fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_size; 1744fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_state; 1745fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_offset; 1746fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_index; 1747fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_alloc; 1748fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_fw_support; 1749fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_drv_support; 1750fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_app_support; 17517497cde8SSumit.Saxena@avagotech.com u32 secure_jbod_support; 17523761cb4cSsumit.saxena@avagotech.com bool use_seqnum_jbod_fp; /* Added for PD sequence */ 1753fc62b3fcSSumit.Saxena@avagotech.com spinlock_t crashdump_lock; 1754fc62b3fcSSumit.Saxena@avagotech.com 1755c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 17568a232bb3SChristoph Hellwig u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 175781e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 1758999ece0aSSumit.Saxena@lsi.com struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 1759bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 1760c4a3e0a5SBagalkote, Sreenivas s8 init_id; 1761c4a3e0a5SBagalkote, Sreenivas 1762c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 1763c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 17649c915a8cSadam radford u16 max_mfi_cmds; 1765ae09a6c1SSumit.Saxena@avagotech.com u16 max_scsi_cmds; 1766c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 17677e8a75f4SYang, Bo struct megasas_aen_event *ev; 1768c4a3e0a5SBagalkote, Sreenivas 1769c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 1770c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 177139a98554Sbo yang /* used to sync fire the cmd to fw */ 177290dc9d98SSumit.Saxena@avagotech.com spinlock_t mfi_pool_lock; 177339a98554Sbo yang /* used to sync fire the cmd to fw */ 177439a98554Sbo yang spinlock_t hba_lock; 17757343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 17767343eb65Sbo yang spinlock_t completion_lock; 1777c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 1778c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 1779c4a3e0a5SBagalkote, Sreenivas 1780c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 1781c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 1782c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 1783e5a69e27SMatthias Kaehlcke struct mutex aen_mutex; 1784c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 1785c4a3e0a5SBagalkote, Sreenivas 1786c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 1787c4a3e0a5SBagalkote, Sreenivas 1788c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 1789c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 1790c4a3e0a5SBagalkote, Sreenivas 1791c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 1792c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 179339a98554Sbo yang u32 fw_support_ieee; 1794c4a3e0a5SBagalkote, Sreenivas 1795e4a082c7SSumant Patro atomic_t fw_outstanding; 179639a98554Sbo yang atomic_t fw_reset_no_pci_access; 17971341c939SSumant Patro 17981341c939SSumant Patro struct megasas_instance_template *instancet; 17995d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 180039a98554Sbo yang struct work_struct work_init; 1801fc62b3fcSSumit.Saxena@avagotech.com struct work_struct crash_init; 180205e9ebbeSSumant Patro 180305e9ebbeSSumant Patro u8 flag; 1804c3518837SYang, Bo u8 unload; 1805f4c9a131SYang, Bo u8 flag_ieee; 180639a98554Sbo yang u8 issuepend_done; 180739a98554Sbo yang u8 disableOnlineCtrlReset; 1808bc93d425SSumit.Saxena@lsi.com u8 UnevenSpanSupport; 180951087a86SSumit.Saxena@avagotech.com 181051087a86SSumit.Saxena@avagotech.com u8 supportmax256vd; 1811aed335eeSSumit Saxena u8 allow_fw_scan; 181251087a86SSumit.Saxena@avagotech.com u16 fw_supported_vd_count; 181351087a86SSumit.Saxena@avagotech.com u16 fw_supported_pd_count; 181451087a86SSumit.Saxena@avagotech.com 181551087a86SSumit.Saxena@avagotech.com u16 drv_supported_vd_count; 181651087a86SSumit.Saxena@avagotech.com u16 drv_supported_pd_count; 181751087a86SSumit.Saxena@avagotech.com 181839a98554Sbo yang u8 adprecovery; 181905e9ebbeSSumant Patro unsigned long last_time; 182039a98554Sbo yang u32 mfiStatus; 182139a98554Sbo yang u32 last_seq_num; 1822ad84db2eSbo yang 182339a98554Sbo yang struct list_head internal_reset_pending_q; 182480d9da98Sadam radford 182525985edcSLucas De Marchi /* Ptr to hba specific information */ 18269c915a8cSadam radford void *ctrl_context; 182751087a86SSumit.Saxena@avagotech.com u32 ctrl_context_pages; 182851087a86SSumit.Saxena@avagotech.com struct megasas_ctrl_info *ctrl_info; 1829c8e858feSadam radford unsigned int msix_vectors; 1830c8e858feSadam radford struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 1831c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 18329c915a8cSadam radford u64 map_id; 18333761cb4cSsumit.saxena@avagotech.com u64 pd_seq_map_id; 18349c915a8cSadam radford struct megasas_cmd *map_update_cmd; 18353761cb4cSsumit.saxena@avagotech.com struct megasas_cmd *jbod_seq_cmd; 1836b6d5d880Sadam radford unsigned long bar; 18379c915a8cSadam radford long reset_flags; 18389c915a8cSadam radford struct mutex reset_mutex; 1839229fe47cSadam radford struct timer_list sriov_heartbeat_timer; 1840229fe47cSadam radford char skip_heartbeat_timer_del; 1841229fe47cSadam radford u8 requestorId; 1842229fe47cSadam radford char PlasmaFW111; 1843229fe47cSadam radford char mpio; 1844ae09a6c1SSumit.Saxena@avagotech.com u16 throttlequeuedepth; 1845d46a3ad6SSumit.Saxena@lsi.com u8 mask_interrupts; 1846bd5f9484Ssumit.saxena@avagotech.com u16 max_chain_frame_sz; 1847404a8a1aSSumit.Saxena@lsi.com u8 is_imr; 18485765c5b8SSumit.Saxena@avagotech.com bool dev_handle; 184939a98554Sbo yang }; 1850229fe47cSadam radford struct MR_LD_VF_MAP { 1851229fe47cSadam radford u32 size; 1852229fe47cSadam radford union MR_LD_REF ref; 1853229fe47cSadam radford u8 ldVfCount; 1854229fe47cSadam radford u8 reserved[6]; 1855229fe47cSadam radford u8 policy[1]; 1856229fe47cSadam radford }; 1857229fe47cSadam radford 1858229fe47cSadam radford struct MR_LD_VF_AFFILIATION { 1859229fe47cSadam radford u32 size; 1860229fe47cSadam radford u8 ldCount; 1861229fe47cSadam radford u8 vfCount; 1862229fe47cSadam radford u8 thisVf; 1863229fe47cSadam radford u8 reserved[9]; 1864229fe47cSadam radford struct MR_LD_VF_MAP map[1]; 1865229fe47cSadam radford }; 1866229fe47cSadam radford 1867229fe47cSadam radford /* Plasma 1.11 FW backward compatibility structures */ 1868229fe47cSadam radford #define IOV_111_OFFSET 0x7CE 1869229fe47cSadam radford #define MAX_VIRTUAL_FUNCTIONS 8 18704cbfea88SAdam Radford #define MR_LD_ACCESS_HIDDEN 15 1871229fe47cSadam radford 1872229fe47cSadam radford struct IOV_111 { 1873229fe47cSadam radford u8 maxVFsSupported; 1874229fe47cSadam radford u8 numVFsEnabled; 1875229fe47cSadam radford u8 requestorId; 1876229fe47cSadam radford u8 reserved[5]; 1877229fe47cSadam radford }; 1878229fe47cSadam radford 1879229fe47cSadam radford struct MR_LD_VF_MAP_111 { 1880229fe47cSadam radford u8 targetId; 1881229fe47cSadam radford u8 reserved[3]; 1882229fe47cSadam radford u8 policy[MAX_VIRTUAL_FUNCTIONS]; 1883229fe47cSadam radford }; 1884229fe47cSadam radford 1885229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 { 1886229fe47cSadam radford u8 vdCount; 1887229fe47cSadam radford u8 vfCount; 1888229fe47cSadam radford u8 thisVf; 1889229fe47cSadam radford u8 reserved[5]; 1890229fe47cSadam radford struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 1891229fe47cSadam radford }; 1892229fe47cSadam radford 1893229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM { 1894229fe47cSadam radford struct { 1895229fe47cSadam radford u32 fwCounter; /* Firmware heart beat counter */ 1896229fe47cSadam radford struct { 1897229fe47cSadam radford u32 debugmode:1; /* 1=Firmware is in debug mode. 1898229fe47cSadam radford Heart beat will not be updated. */ 1899229fe47cSadam radford u32 reserved:31; 1900229fe47cSadam radford } debug; 1901229fe47cSadam radford u32 reserved_fw[6]; 1902229fe47cSadam radford u32 driverCounter; /* Driver heart beat counter. 0x20 */ 1903229fe47cSadam radford u32 reserved_driver[7]; 1904229fe47cSadam radford } HB; 1905229fe47cSadam radford u8 pad[0x400-0x40]; 1906229fe47cSadam radford }; 190739a98554Sbo yang 190839a98554Sbo yang enum { 190939a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 191039a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 191139a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 191239a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 191339a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 1914229fe47cSadam radford MEGASAS_ADPRESET_SM_POLLING = 5, 191539a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1916c4a3e0a5SBagalkote, Sreenivas }; 1917c4a3e0a5SBagalkote, Sreenivas 19180c79e681SYang, Bo struct megasas_instance_template { 19190c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 19200c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 19210c79e681SYang, Bo 1922d46a3ad6SSumit.Saxena@lsi.com void (*enable_intr)(struct megasas_instance *); 1923d46a3ad6SSumit.Saxena@lsi.com void (*disable_intr)(struct megasas_instance *); 19240c79e681SYang, Bo 19250c79e681SYang, Bo int (*clear_intr)(struct megasas_register_set __iomem *); 19260c79e681SYang, Bo 19270c79e681SYang, Bo u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 192839a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 192939a98554Sbo yang struct megasas_register_set __iomem *); 193039a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 193139a98554Sbo yang struct megasas_register_set __iomem *); 1932cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp); 1933cd50ba8eSadam radford void (*tasklet)(unsigned long); 1934cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *); 1935cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *, 1936cd50ba8eSadam radford struct scsi_cmnd *); 19376d40afbcSSumit Saxena int (*issue_dcmd)(struct megasas_instance *instance, 1938cd50ba8eSadam radford struct megasas_cmd *cmd); 19390c79e681SYang, Bo }; 19400c79e681SYang, Bo 1941c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 1942c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 1943c4a3e0a5SBagalkote, Sreenivas 19444a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_DEV_INDEX(scp) \ 19454a5c814dSSumit.Saxena@avagotech.com (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 19464a5c814dSSumit.Saxena@avagotech.com scp->device->id) 19474a5c814dSSumit.Saxena@avagotech.com 19484a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_PD_INDEX(scp) \ 19494a5c814dSSumit.Saxena@avagotech.com ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 19504a5c814dSSumit.Saxena@avagotech.com scp->device->id) 1951c4a3e0a5SBagalkote, Sreenivas 1952c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 1953c4a3e0a5SBagalkote, Sreenivas 1954c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 1955c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 1956c4a3e0a5SBagalkote, Sreenivas u8 *sense; 1957c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 1958c4a3e0a5SBagalkote, Sreenivas 1959c4a3e0a5SBagalkote, Sreenivas u32 index; 1960c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 19612be2a988SSumit.Saxena@avagotech.com u8 cmd_status_drv; 196239a98554Sbo yang u8 abort_aen; 196339a98554Sbo yang u8 retry_for_fw_reset; 196439a98554Sbo yang 1965c4a3e0a5SBagalkote, Sreenivas 1966c4a3e0a5SBagalkote, Sreenivas struct list_head list; 1967c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 19684026e9aaSSumit.Saxena@avagotech.com u8 flags; 196990dc9d98SSumit.Saxena@avagotech.com 1970c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 19719c915a8cSadam radford union { 19729c915a8cSadam radford struct { 19739c915a8cSadam radford u16 smid; 19749c915a8cSadam radford u16 resvd; 19759c915a8cSadam radford } context; 1976c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 1977c4a3e0a5SBagalkote, Sreenivas }; 19789c915a8cSadam radford }; 1979c4a3e0a5SBagalkote, Sreenivas 1980c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 1981c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 1982c4a3e0a5SBagalkote, Sreenivas 1983c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 1984c4a3e0a5SBagalkote, Sreenivas 1985c4a3e0a5SBagalkote, Sreenivas u16 host_no; 1986c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 1987c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 1988c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 1989c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 1990c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 1991c4a3e0a5SBagalkote, Sreenivas union { 1992c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 1993c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1994c4a3e0a5SBagalkote, Sreenivas } frame; 1995c4a3e0a5SBagalkote, Sreenivas 1996c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 1997c4a3e0a5SBagalkote, Sreenivas 1998c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1999c4a3e0a5SBagalkote, Sreenivas 2000c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 2001c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2002c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2003c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 2004c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 2005c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2006c4a3e0a5SBagalkote, Sreenivas 2007c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 2008c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 2009c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2010c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2011c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 2012c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 2013c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 2014c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 2015c4a3e0a5SBagalkote, Sreenivas union { 2016c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 2017c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 2018c4a3e0a5SBagalkote, Sreenivas } frame; 2019c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 2020c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2021c4a3e0a5SBagalkote, Sreenivas 20220e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2023c4a3e0a5SBagalkote, Sreenivas #endif 2024c4a3e0a5SBagalkote, Sreenivas 2025cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2026c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2027c4a3e0a5SBagalkote, Sreenivas 2028c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 2029c4a3e0a5SBagalkote, Sreenivas 2030c4a3e0a5SBagalkote, Sreenivas u16 count; 2031c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2032c4a3e0a5SBagalkote, Sreenivas int max_index; 2033c4a3e0a5SBagalkote, Sreenivas }; 2034c4a3e0a5SBagalkote, Sreenivas 20356d40afbcSSumit Saxena enum MEGASAS_OCR_CAUSE { 20366d40afbcSSumit Saxena FW_FAULT_OCR = 0, 20376d40afbcSSumit Saxena SCSIIO_TIMEOUT_OCR = 1, 20386d40afbcSSumit Saxena MFI_IO_TIMEOUT_OCR = 2, 20396d40afbcSSumit Saxena }; 20406d40afbcSSumit Saxena 20416d40afbcSSumit Saxena enum DCMD_RETURN_STATUS { 20426d40afbcSSumit Saxena DCMD_SUCCESS = 0, 20436d40afbcSSumit Saxena DCMD_TIMEOUT = 1, 20446d40afbcSSumit Saxena DCMD_FAILED = 2, 20456d40afbcSSumit Saxena DCMD_NOT_FIRED = 3, 20466d40afbcSSumit Saxena }; 20476d40afbcSSumit Saxena 204821c9e160Sadam radford u8 204921c9e160Sadam radford MR_BuildRaidContext(struct megasas_instance *instance, 205021c9e160Sadam radford struct IO_REQUEST_INFO *io_info, 205121c9e160Sadam radford struct RAID_CONTEXT *pRAID_Context, 205251087a86SSumit.Saxena@avagotech.com struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 205351087a86SSumit.Saxena@avagotech.com u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 205451087a86SSumit.Saxena@avagotech.com struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 205551087a86SSumit.Saxena@avagotech.com u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 205651087a86SSumit.Saxena@avagotech.com u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 20579ab9ed38SChristoph Hellwig __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 205851087a86SSumit.Saxena@avagotech.com u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 205921c9e160Sadam radford 20609ab9ed38SChristoph Hellwig __le16 get_updated_dev_handle(struct megasas_instance *instance, 2061d2552ebeSSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info); 206251087a86SSumit.Saxena@avagotech.com void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 206351087a86SSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo); 2064d009b576SSumit.Saxena@avagotech.com int megasas_get_ctrl_info(struct megasas_instance *instance); 20653761cb4cSsumit.saxena@avagotech.com /* PD sequence */ 20663761cb4cSsumit.saxena@avagotech.com int 20673761cb4cSsumit.saxena@avagotech.com megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2068fc62b3fcSSumit.Saxena@avagotech.com int megasas_set_crash_dump_params(struct megasas_instance *instance, 2069fc62b3fcSSumit.Saxena@avagotech.com u8 crash_buf_state); 2070fc62b3fcSSumit.Saxena@avagotech.com void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2071fc62b3fcSSumit.Saxena@avagotech.com void megasas_fusion_crash_dump_wq(struct work_struct *work); 207251087a86SSumit.Saxena@avagotech.com 207390dc9d98SSumit.Saxena@avagotech.com void megasas_return_cmd_fusion(struct megasas_instance *instance, 207490dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd_fusion *cmd); 207590dc9d98SSumit.Saxena@avagotech.com int megasas_issue_blocked_cmd(struct megasas_instance *instance, 207690dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd, int timeout); 207790dc9d98SSumit.Saxena@avagotech.com void __megasas_return_cmd(struct megasas_instance *instance, 207890dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd); 207990dc9d98SSumit.Saxena@avagotech.com 208090dc9d98SSumit.Saxena@avagotech.com void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 208190dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 20827497cde8SSumit.Saxena@avagotech.com int megasas_cmd_type(struct scsi_cmnd *cmd); 20833761cb4cSsumit.saxena@avagotech.com void megasas_setup_jbod_map(struct megasas_instance *instance); 208490dc9d98SSumit.Saxena@avagotech.com 208518365b13SSumit Saxena void megasas_update_sdev_properties(struct scsi_device *sdev); 208618365b13SSumit Saxena int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 208718365b13SSumit Saxena int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 208818365b13SSumit Saxena int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2089c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 2090