1c4a3e0a5SBagalkote, Sreenivas /* 2c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers 3c4a3e0a5SBagalkote, Sreenivas * 4e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2003-2013 LSI Corporation 5e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2013-2014 Avago Technologies 6c4a3e0a5SBagalkote, Sreenivas * 7c4a3e0a5SBagalkote, Sreenivas * This program is free software; you can redistribute it and/or 8c4a3e0a5SBagalkote, Sreenivas * modify it under the terms of the GNU General Public License 93f1530c1Sadam radford * as published by the Free Software Foundation; either version 2 103f1530c1Sadam radford * of the License, or (at your option) any later version. 113f1530c1Sadam radford * 123f1530c1Sadam radford * This program is distributed in the hope that it will be useful, 133f1530c1Sadam radford * but WITHOUT ANY WARRANTY; without even the implied warranty of 143f1530c1Sadam radford * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 153f1530c1Sadam radford * GNU General Public License for more details. 163f1530c1Sadam radford * 173f1530c1Sadam radford * You should have received a copy of the GNU General Public License 18e399065bSSumit.Saxena@avagotech.com * along with this program. If not, see <http://www.gnu.org/licenses/>. 19c4a3e0a5SBagalkote, Sreenivas * 20c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h 213f1530c1Sadam radford * 22e399065bSSumit.Saxena@avagotech.com * Authors: Avago Technologies 23e399065bSSumit.Saxena@avagotech.com * Kashyap Desai <kashyap.desai@avagotech.com> 24e399065bSSumit.Saxena@avagotech.com * Sumit Saxena <sumit.saxena@avagotech.com> 253f1530c1Sadam radford * 26e399065bSSumit.Saxena@avagotech.com * Send feedback to: megaraidlinux.pdl@avagotech.com 273f1530c1Sadam radford * 28e399065bSSumit.Saxena@avagotech.com * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29e399065bSSumit.Saxena@avagotech.com * San Jose, California 95131 30c4a3e0a5SBagalkote, Sreenivas */ 31c4a3e0a5SBagalkote, Sreenivas 32c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H 33c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H 34c4a3e0a5SBagalkote, Sreenivas 35a69b74d3SRandy Dunlap /* 36c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data 37c4a3e0a5SBagalkote, Sreenivas */ 38afb2b5ddSsumit.saxena@avagotech.com #define MEGASAS_VERSION "06.808.16.00-rc1" 39afb2b5ddSsumit.saxena@avagotech.com #define MEGASAS_RELDATE "Oct. 8, 2015" 400e98936cSSumant Patro 410e98936cSSumant Patro /* 420e98936cSSumant Patro * Device IDs 430e98936cSSumant Patro */ 440e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 460e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 476610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 486610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 4987911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 5087911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 519c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52229fe47cSadam radford #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 5336807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d 5421d3c710SSumit.Saxena@lsi.com #define PCI_DEVICE_ID_LSI_FURY 0x005f 5590c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 5690c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 577364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 587364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 590e98936cSSumant Patro 60c4a3e0a5SBagalkote, Sreenivas /* 6139b72c3cSSumit.Saxena@lsi.com * Intel HBA SSDIDs 6239b72c3cSSumit.Saxena@lsi.com */ 6339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 6439b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 6539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 6639b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 6739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 6839b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 697364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 7039b72c3cSSumit.Saxena@lsi.com 7139b72c3cSSumit.Saxena@lsi.com /* 7290c204bcSsumit.saxena@avagotech.com * Intruder HBA SSDIDs 7390c204bcSsumit.saxena@avagotech.com */ 7490c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID1 0x9371 7590c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID2 0x9390 7690c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID3 0x9370 7790c204bcSsumit.saxena@avagotech.com 7890c204bcSsumit.saxena@avagotech.com /* 7939b72c3cSSumit.Saxena@lsi.com * Intel HBA branding 8039b72c3cSSumit.Saxena@lsi.com */ 8139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_BRANDING \ 8239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC080" 8339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_BRANDING \ 8439b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC040" 8539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_BRANDING \ 8639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3SC008" 8739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_BRANDING \ 8839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3MC044" 8939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_BRANDING \ 9039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC080" 9139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_BRANDING \ 9239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC040" 937364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 947364d34bSsumit.saxena@avagotech.com "Intel(R) Integrated RAID Module RMS3BC160" 9539b72c3cSSumit.Saxena@lsi.com 9639b72c3cSSumit.Saxena@lsi.com /* 97c4a3e0a5SBagalkote, Sreenivas * ===================================== 98c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions 99c4a3e0a5SBagalkote, Sreenivas * ===================================== 100c4a3e0a5SBagalkote, Sreenivas */ 101c4a3e0a5SBagalkote, Sreenivas 102c4a3e0a5SBagalkote, Sreenivas /* 103c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 104c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using 105c4a3e0a5SBagalkote, Sreenivas * "message frames" 106c4a3e0a5SBagalkote, Sreenivas */ 107c4a3e0a5SBagalkote, Sreenivas 108a69b74d3SRandy Dunlap /* 109c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register 110c4a3e0a5SBagalkote, Sreenivas */ 111c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000 112c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000 113c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000 114c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000 115c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 116c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000 117c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000 118e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 119c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000 120c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000 121c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000 122c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000 123fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_FORCE_OCR 0x00000080 124fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_DMADONE 0x00000008 125fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 12639a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001 1277e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002 128c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64 129c4a3e0a5SBagalkote, Sreenivas 130a69b74d3SRandy Dunlap /* 131c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0 132c4a3e0a5SBagalkote, Sreenivas * 133c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds 134c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info 135c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 136c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 137e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug 138e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing 139c4a3e0a5SBagalkote, Sreenivas */ 14039a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 14139a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 14239a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080) 14339a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004) 14439a98554Sbo yang 14539a98554Sbo yang #define MFI_ADP_RESET 0x00000040 146e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001 147c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002 148c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004 149c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 150e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010 151e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020 152e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \ 153e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \ 154e3bbff9fSSumant Patro MFI_INIT_ABORT 155179ac142SSumit Saxena #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 156c4a3e0a5SBagalkote, Sreenivas 157a69b74d3SRandy Dunlap /* 158c4a3e0a5SBagalkote, Sreenivas * MFI frame flags 159c4a3e0a5SBagalkote, Sreenivas */ 160c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 161c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 162c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000 163c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002 164c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000 165c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004 166c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000 167c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008 168c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010 169c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018 170f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020 171c4a3e0a5SBagalkote, Sreenivas 1724026e9aaSSumit.Saxena@avagotech.com /* Driver internal */ 1734026e9aaSSumit.Saxena@avagotech.com #define DRV_DCMD_POLLED_MODE 0x1 1746d40afbcSSumit Saxena #define DRV_DCMD_SKIP_REFIRE 0x2 1754026e9aaSSumit.Saxena@avagotech.com 176a69b74d3SRandy Dunlap /* 177c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status 178c4a3e0a5SBagalkote, Sreenivas */ 179c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF 180c4a3e0a5SBagalkote, Sreenivas 181a69b74d3SRandy Dunlap /* 182c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes 183c4a3e0a5SBagalkote, Sreenivas */ 184c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_INIT 0x00 185c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_READ 0x01 186c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_WRITE 0x02 187c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_LD_SCSI_IO 0x03 188c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_PD_SCSI_IO 0x04 189c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_DCMD 0x05 190c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_ABORT 0x06 191c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_SMP 0x07 192c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STP 0x08 193e5f93a36Sadam radford #define MFI_CMD_INVALID 0xff 194c4a3e0a5SBagalkote, Sreenivas 195c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000 196bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000 19721c9e160Sadam radford #define MR_DCMD_LD_LIST_QUERY 0x03010100 198c4a3e0a5SBagalkote, Sreenivas 199c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 200c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01 201c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02 202c4a3e0a5SBagalkote, Sreenivas 203c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 20431ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 205c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01 206c4a3e0a5SBagalkote, Sreenivas 207c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 208c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300 209c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 210c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 211c4a3e0a5SBagalkote, Sreenivas 212c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000 213c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 214c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 21581e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100 216c4a3e0a5SBagalkote, Sreenivas 217fc62b3fcSSumit.Saxena@avagotech.com #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 218fc62b3fcSSumit.Saxena@avagotech.com #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 2192216c305SSumit Saxena #define MR_DCMD_PD_GET_INFO 0x02020000 220fc62b3fcSSumit.Saxena@avagotech.com 221a69b74d3SRandy Dunlap /* 222bc93d425SSumit.Saxena@lsi.com * Global functions 223bc93d425SSumit.Saxena@lsi.com */ 224bc93d425SSumit.Saxena@lsi.com extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 225bc93d425SSumit.Saxena@lsi.com 226bc93d425SSumit.Saxena@lsi.com 227bc93d425SSumit.Saxena@lsi.com /* 228c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes 229c4a3e0a5SBagalkote, Sreenivas */ 230c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT { 231c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00, 232c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01, 233c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02, 234c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03, 235c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 236c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 237c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 238c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07, 239c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08, 240c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 241c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 242c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 243c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 244c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 245c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 246c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f, 247c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10, 248c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11, 249c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 250c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13, 251c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14, 252c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15, 253c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 254c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 255c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 256c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 257c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 258c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 259c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 260c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 261c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 262c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 263c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 264c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21, 265c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22, 266c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23, 267c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24, 268c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 269c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26, 270c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27, 271c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28, 272c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 273c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 274c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 275c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 276c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 277c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e, 278c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 279c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30, 280c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31, 281c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32, 282c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33, 283c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 284c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 285c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 286c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 287c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 28836807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 289c4a3e0a5SBagalkote, Sreenivas 290c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF 291c4a3e0a5SBagalkote, Sreenivas }; 292c4a3e0a5SBagalkote, Sreenivas 293714f5177Ssumit.saxena@avagotech.com enum mfi_evt_class { 294714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEBUG = -2, 295714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_PROGRESS = -1, 296714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_INFO = 0, 297714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_WARNING = 1, 298714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_CRITICAL = 2, 299714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_FATAL = 3, 300714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEAD = 4 301714f5177Ssumit.saxena@avagotech.com }; 302714f5177Ssumit.saxena@avagotech.com 303c4a3e0a5SBagalkote, Sreenivas /* 304fc62b3fcSSumit.Saxena@avagotech.com * Crash dump related defines 305fc62b3fcSSumit.Saxena@avagotech.com */ 306fc62b3fcSSumit.Saxena@avagotech.com #define MAX_CRASH_DUMP_SIZE 512 307fc62b3fcSSumit.Saxena@avagotech.com #define CRASH_DMA_BUF_SIZE (1024 * 1024) 308fc62b3fcSSumit.Saxena@avagotech.com 309fc62b3fcSSumit.Saxena@avagotech.com enum MR_FW_CRASH_DUMP_STATE { 310fc62b3fcSSumit.Saxena@avagotech.com UNAVAILABLE = 0, 311fc62b3fcSSumit.Saxena@avagotech.com AVAILABLE = 1, 312fc62b3fcSSumit.Saxena@avagotech.com COPYING = 2, 313fc62b3fcSSumit.Saxena@avagotech.com COPIED = 3, 314fc62b3fcSSumit.Saxena@avagotech.com COPY_ERROR = 4, 315fc62b3fcSSumit.Saxena@avagotech.com }; 316fc62b3fcSSumit.Saxena@avagotech.com 317fc62b3fcSSumit.Saxena@avagotech.com enum _MR_CRASH_BUF_STATUS { 318fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_OFF = 0, 319fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_ON = 1, 320fc62b3fcSSumit.Saxena@avagotech.com }; 321fc62b3fcSSumit.Saxena@avagotech.com 322fc62b3fcSSumit.Saxena@avagotech.com /* 323c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame 324c4a3e0a5SBagalkote, Sreenivas */ 325c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12 326c4a3e0a5SBagalkote, Sreenivas 327c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS { 328c4a3e0a5SBagalkote, Sreenivas 329c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2, 330c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1, 331c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0, 332c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1, 333c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2, 334c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3, 335c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4, 336c4a3e0a5SBagalkote, Sreenivas 337c4a3e0a5SBagalkote, Sreenivas }; 338c4a3e0a5SBagalkote, Sreenivas 339c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE { 340c4a3e0a5SBagalkote, Sreenivas 341c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001, 342c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002, 343c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004, 344c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008, 345c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010, 346c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020, 347c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040, 348c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080, 349c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff, 350c4a3e0a5SBagalkote, Sreenivas 351c4a3e0a5SBagalkote, Sreenivas }; 352c4a3e0a5SBagalkote, Sreenivas 353c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS { 354c4a3e0a5SBagalkote, Sreenivas 355c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE, 356c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE, 357c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD, 358c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT, 359c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA, 360c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER, 361c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA, 362c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG, 363c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE, 364c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP, 365c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD, 366c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR, 367c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA, 368c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD, 369c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG, 370c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE, 371c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI, 372c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE, 373c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR, 374c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME, 375c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC, 37681e403ceSYang, Bo MR_EVT_ARGS_LD_PROP, 37781e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE, 37881e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX, 37981e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS, 38081e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL, 38181e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA, 38281e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY, 38381e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING, 38481e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS, 38581e403ceSYang, Bo MR_EVT_ARGS_BITMAP, 38681e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR, 38781e403ceSYang, Bo MR_EVT_ARGS_PD_PD, 38881e403ceSYang, Bo MR_EVT_ARGS_PD_FRU, 38981e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO, 39081e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE, 39181e403ceSYang, Bo MR_EVT_ARGS_GENERIC, 392c4a3e0a5SBagalkote, Sreenivas }; 393c4a3e0a5SBagalkote, Sreenivas 394357ae967Ssumit.saxena@avagotech.com 395357ae967Ssumit.saxena@avagotech.com #define SGE_BUFFER_SIZE 4096 396c4a3e0a5SBagalkote, Sreenivas /* 39781e403ceSYang, Bo * define constants for device list query options 39881e403ceSYang, Bo */ 39981e403ceSYang, Bo enum MR_PD_QUERY_TYPE { 40081e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0, 40181e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1, 40281e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2, 40381e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 40481e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4, 40581e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 40681e403ceSYang, Bo }; 40781e403ceSYang, Bo 40821c9e160Sadam radford enum MR_LD_QUERY_TYPE { 40921c9e160Sadam radford MR_LD_QUERY_TYPE_ALL = 0, 41021c9e160Sadam radford MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 41121c9e160Sadam radford MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 41221c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 41321c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 41421c9e160Sadam radford }; 41521c9e160Sadam radford 41621c9e160Sadam radford 4177e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004 4187e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051 4197e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b 4207e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070 4217e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a 4227e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b 4237e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 4247e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc 4257e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 426c4bd2654Ssumit.saxena@avagotech.com #define MR_EVT_CTRL_PROP_CHANGED 0x012f 4277e8a75f4SYang, Bo 42881e403ceSYang, Bo enum MR_PD_STATE { 42981e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 43081e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 43181e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02, 43281e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10, 43381e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11, 43481e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14, 43581e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18, 43681e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20, 43781e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40, 43881e403ceSYang, Bo }; 43981e403ceSYang, Bo 4402216c305SSumit Saxena union MR_PD_REF { 4412216c305SSumit Saxena struct { 4422216c305SSumit Saxena u16 deviceId; 4432216c305SSumit Saxena u16 seqNum; 4442216c305SSumit Saxena } mrPdRef; 4452216c305SSumit Saxena u32 ref; 4462216c305SSumit Saxena }; 4472216c305SSumit Saxena 4482216c305SSumit Saxena /* 4492216c305SSumit Saxena * define the DDF Type bit structure 4502216c305SSumit Saxena */ 4512216c305SSumit Saxena union MR_PD_DDF_TYPE { 4522216c305SSumit Saxena struct { 4532216c305SSumit Saxena union { 4542216c305SSumit Saxena struct { 4552216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 4562216c305SSumit Saxena u16 forcedPDGUID:1; 4572216c305SSumit Saxena u16 inVD:1; 4582216c305SSumit Saxena u16 isGlobalSpare:1; 4592216c305SSumit Saxena u16 isSpare:1; 4602216c305SSumit Saxena u16 isForeign:1; 4612216c305SSumit Saxena u16 reserved:7; 4622216c305SSumit Saxena u16 intf:4; 4632216c305SSumit Saxena #else 4642216c305SSumit Saxena u16 intf:4; 4652216c305SSumit Saxena u16 reserved:7; 4662216c305SSumit Saxena u16 isForeign:1; 4672216c305SSumit Saxena u16 isSpare:1; 4682216c305SSumit Saxena u16 isGlobalSpare:1; 4692216c305SSumit Saxena u16 inVD:1; 4702216c305SSumit Saxena u16 forcedPDGUID:1; 4712216c305SSumit Saxena #endif 4722216c305SSumit Saxena } pdType; 4732216c305SSumit Saxena u16 type; 4742216c305SSumit Saxena }; 4752216c305SSumit Saxena u16 reserved; 4762216c305SSumit Saxena } ddf; 4772216c305SSumit Saxena struct { 4782216c305SSumit Saxena u32 reserved; 4792216c305SSumit Saxena } nonDisk; 4802216c305SSumit Saxena u32 type; 4812216c305SSumit Saxena } __packed; 4822216c305SSumit Saxena 4832216c305SSumit Saxena /* 4842216c305SSumit Saxena * defines the progress structure 4852216c305SSumit Saxena */ 4862216c305SSumit Saxena union MR_PROGRESS { 4872216c305SSumit Saxena struct { 4882216c305SSumit Saxena u16 progress; 4892216c305SSumit Saxena union { 4902216c305SSumit Saxena u16 elapsedSecs; 4912216c305SSumit Saxena u16 elapsedSecsForLastPercent; 4922216c305SSumit Saxena }; 4932216c305SSumit Saxena } mrProgress; 4942216c305SSumit Saxena u32 w; 4952216c305SSumit Saxena } __packed; 4962216c305SSumit Saxena 4972216c305SSumit Saxena /* 4982216c305SSumit Saxena * defines the physical drive progress structure 4992216c305SSumit Saxena */ 5002216c305SSumit Saxena struct MR_PD_PROGRESS { 5012216c305SSumit Saxena struct { 5022216c305SSumit Saxena #ifndef MFI_BIG_ENDIAN 5032216c305SSumit Saxena u32 rbld:1; 5042216c305SSumit Saxena u32 patrol:1; 5052216c305SSumit Saxena u32 clear:1; 5062216c305SSumit Saxena u32 copyBack:1; 5072216c305SSumit Saxena u32 erase:1; 5082216c305SSumit Saxena u32 locate:1; 5092216c305SSumit Saxena u32 reserved:26; 5102216c305SSumit Saxena #else 5112216c305SSumit Saxena u32 reserved:26; 5122216c305SSumit Saxena u32 locate:1; 5132216c305SSumit Saxena u32 erase:1; 5142216c305SSumit Saxena u32 copyBack:1; 5152216c305SSumit Saxena u32 clear:1; 5162216c305SSumit Saxena u32 patrol:1; 5172216c305SSumit Saxena u32 rbld:1; 5182216c305SSumit Saxena #endif 5192216c305SSumit Saxena } active; 5202216c305SSumit Saxena union MR_PROGRESS rbld; 5212216c305SSumit Saxena union MR_PROGRESS patrol; 5222216c305SSumit Saxena union { 5232216c305SSumit Saxena union MR_PROGRESS clear; 5242216c305SSumit Saxena union MR_PROGRESS erase; 5252216c305SSumit Saxena }; 5262216c305SSumit Saxena 5272216c305SSumit Saxena struct { 5282216c305SSumit Saxena #ifndef MFI_BIG_ENDIAN 5292216c305SSumit Saxena u32 rbld:1; 5302216c305SSumit Saxena u32 patrol:1; 5312216c305SSumit Saxena u32 clear:1; 5322216c305SSumit Saxena u32 copyBack:1; 5332216c305SSumit Saxena u32 erase:1; 5342216c305SSumit Saxena u32 reserved:27; 5352216c305SSumit Saxena #else 5362216c305SSumit Saxena u32 reserved:27; 5372216c305SSumit Saxena u32 erase:1; 5382216c305SSumit Saxena u32 copyBack:1; 5392216c305SSumit Saxena u32 clear:1; 5402216c305SSumit Saxena u32 patrol:1; 5412216c305SSumit Saxena u32 rbld:1; 5422216c305SSumit Saxena #endif 5432216c305SSumit Saxena } pause; 5442216c305SSumit Saxena 5452216c305SSumit Saxena union MR_PROGRESS reserved[3]; 5462216c305SSumit Saxena } __packed; 5472216c305SSumit Saxena 5482216c305SSumit Saxena struct MR_PD_INFO { 5492216c305SSumit Saxena union MR_PD_REF ref; 5502216c305SSumit Saxena u8 inquiryData[96]; 5512216c305SSumit Saxena u8 vpdPage83[64]; 5522216c305SSumit Saxena u8 notSupported; 5532216c305SSumit Saxena u8 scsiDevType; 5542216c305SSumit Saxena 5552216c305SSumit Saxena union { 5562216c305SSumit Saxena u8 connectedPortBitmap; 5572216c305SSumit Saxena u8 connectedPortNumbers; 5582216c305SSumit Saxena }; 5592216c305SSumit Saxena 5602216c305SSumit Saxena u8 deviceSpeed; 5612216c305SSumit Saxena u32 mediaErrCount; 5622216c305SSumit Saxena u32 otherErrCount; 5632216c305SSumit Saxena u32 predFailCount; 5642216c305SSumit Saxena u32 lastPredFailEventSeqNum; 5652216c305SSumit Saxena 5662216c305SSumit Saxena u16 fwState; 5672216c305SSumit Saxena u8 disabledForRemoval; 5682216c305SSumit Saxena u8 linkSpeed; 5692216c305SSumit Saxena union MR_PD_DDF_TYPE state; 5702216c305SSumit Saxena 5712216c305SSumit Saxena struct { 5722216c305SSumit Saxena u8 count; 5732216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 5742216c305SSumit Saxena u8 isPathBroken:4; 5752216c305SSumit Saxena u8 reserved3:3; 5762216c305SSumit Saxena u8 widePortCapable:1; 5772216c305SSumit Saxena #else 5782216c305SSumit Saxena u8 widePortCapable:1; 5792216c305SSumit Saxena u8 reserved3:3; 5802216c305SSumit Saxena u8 isPathBroken:4; 5812216c305SSumit Saxena #endif 5822216c305SSumit Saxena 5832216c305SSumit Saxena u8 connectorIndex[2]; 5842216c305SSumit Saxena u8 reserved[4]; 5852216c305SSumit Saxena u64 sasAddr[2]; 5862216c305SSumit Saxena u8 reserved2[16]; 5872216c305SSumit Saxena } pathInfo; 5882216c305SSumit Saxena 5892216c305SSumit Saxena u64 rawSize; 5902216c305SSumit Saxena u64 nonCoercedSize; 5912216c305SSumit Saxena u64 coercedSize; 5922216c305SSumit Saxena u16 enclDeviceId; 5932216c305SSumit Saxena u8 enclIndex; 5942216c305SSumit Saxena 5952216c305SSumit Saxena union { 5962216c305SSumit Saxena u8 slotNumber; 5972216c305SSumit Saxena u8 enclConnectorIndex; 5982216c305SSumit Saxena }; 5992216c305SSumit Saxena 6002216c305SSumit Saxena struct MR_PD_PROGRESS progInfo; 6012216c305SSumit Saxena u8 badBlockTableFull; 6022216c305SSumit Saxena u8 unusableInCurrentConfig; 6032216c305SSumit Saxena u8 vpdPage83Ext[64]; 6042216c305SSumit Saxena u8 powerState; 6052216c305SSumit Saxena u8 enclPosition; 6062216c305SSumit Saxena u32 allowedOps; 6072216c305SSumit Saxena u16 copyBackPartnerId; 6082216c305SSumit Saxena u16 enclPartnerDeviceId; 6092216c305SSumit Saxena struct { 6102216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6112216c305SSumit Saxena u16 fdeCapable:1; 6122216c305SSumit Saxena u16 fdeEnabled:1; 6132216c305SSumit Saxena u16 secured:1; 6142216c305SSumit Saxena u16 locked:1; 6152216c305SSumit Saxena u16 foreign:1; 6162216c305SSumit Saxena u16 needsEKM:1; 6172216c305SSumit Saxena u16 reserved:10; 6182216c305SSumit Saxena #else 6192216c305SSumit Saxena u16 reserved:10; 6202216c305SSumit Saxena u16 needsEKM:1; 6212216c305SSumit Saxena u16 foreign:1; 6222216c305SSumit Saxena u16 locked:1; 6232216c305SSumit Saxena u16 secured:1; 6242216c305SSumit Saxena u16 fdeEnabled:1; 6252216c305SSumit Saxena u16 fdeCapable:1; 6262216c305SSumit Saxena #endif 6272216c305SSumit Saxena } security; 6282216c305SSumit Saxena u8 mediaType; 6292216c305SSumit Saxena u8 notCertified; 6302216c305SSumit Saxena u8 bridgeVendor[8]; 6312216c305SSumit Saxena u8 bridgeProductIdentification[16]; 6322216c305SSumit Saxena u8 bridgeProductRevisionLevel[4]; 6332216c305SSumit Saxena u8 satBridgeExists; 6342216c305SSumit Saxena 6352216c305SSumit Saxena u8 interfaceType; 6362216c305SSumit Saxena u8 temperature; 6372216c305SSumit Saxena u8 emulatedBlockSize; 6382216c305SSumit Saxena u16 userDataBlockSize; 6392216c305SSumit Saxena u16 reserved2; 6402216c305SSumit Saxena 6412216c305SSumit Saxena struct { 6422216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6432216c305SSumit Saxena u32 piType:3; 6442216c305SSumit Saxena u32 piFormatted:1; 6452216c305SSumit Saxena u32 piEligible:1; 6462216c305SSumit Saxena u32 NCQ:1; 6472216c305SSumit Saxena u32 WCE:1; 6482216c305SSumit Saxena u32 commissionedSpare:1; 6492216c305SSumit Saxena u32 emergencySpare:1; 6502216c305SSumit Saxena u32 ineligibleForSSCD:1; 6512216c305SSumit Saxena u32 ineligibleForLd:1; 6522216c305SSumit Saxena u32 useSSEraseType:1; 6532216c305SSumit Saxena u32 wceUnchanged:1; 6542216c305SSumit Saxena u32 supportScsiUnmap:1; 6552216c305SSumit Saxena u32 reserved:18; 6562216c305SSumit Saxena #else 6572216c305SSumit Saxena u32 reserved:18; 6582216c305SSumit Saxena u32 supportScsiUnmap:1; 6592216c305SSumit Saxena u32 wceUnchanged:1; 6602216c305SSumit Saxena u32 useSSEraseType:1; 6612216c305SSumit Saxena u32 ineligibleForLd:1; 6622216c305SSumit Saxena u32 ineligibleForSSCD:1; 6632216c305SSumit Saxena u32 emergencySpare:1; 6642216c305SSumit Saxena u32 commissionedSpare:1; 6652216c305SSumit Saxena u32 WCE:1; 6662216c305SSumit Saxena u32 NCQ:1; 6672216c305SSumit Saxena u32 piEligible:1; 6682216c305SSumit Saxena u32 piFormatted:1; 6692216c305SSumit Saxena u32 piType:3; 6702216c305SSumit Saxena #endif 6712216c305SSumit Saxena } properties; 6722216c305SSumit Saxena 6732216c305SSumit Saxena u64 shieldDiagCompletionTime; 6742216c305SSumit Saxena u8 shieldCounter; 6752216c305SSumit Saxena 6762216c305SSumit Saxena u8 linkSpeedOther; 6772216c305SSumit Saxena u8 reserved4[2]; 6782216c305SSumit Saxena 6792216c305SSumit Saxena struct { 6802216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD 6812216c305SSumit Saxena u32 bbmErrCountSupported:1; 6822216c305SSumit Saxena u32 bbmErrCount:31; 6832216c305SSumit Saxena #else 6842216c305SSumit Saxena u32 bbmErrCount:31; 6852216c305SSumit Saxena u32 bbmErrCountSupported:1; 6862216c305SSumit Saxena #endif 6872216c305SSumit Saxena } bbmErr; 6882216c305SSumit Saxena 6892216c305SSumit Saxena u8 reserved1[512-428]; 6902216c305SSumit Saxena } __packed; 69181e403ceSYang, Bo 69281e403ceSYang, Bo /* 69381e403ceSYang, Bo * defines the physical drive address structure 69481e403ceSYang, Bo */ 69581e403ceSYang, Bo struct MR_PD_ADDRESS { 6969ab9ed38SChristoph Hellwig __le16 deviceId; 69781e403ceSYang, Bo u16 enclDeviceId; 69881e403ceSYang, Bo 69981e403ceSYang, Bo union { 70081e403ceSYang, Bo struct { 70181e403ceSYang, Bo u8 enclIndex; 70281e403ceSYang, Bo u8 slotNumber; 70381e403ceSYang, Bo } mrPdAddress; 70481e403ceSYang, Bo struct { 70581e403ceSYang, Bo u8 enclPosition; 70681e403ceSYang, Bo u8 enclConnectorIndex; 70781e403ceSYang, Bo } mrEnclAddress; 70881e403ceSYang, Bo }; 70981e403ceSYang, Bo u8 scsiDevType; 71081e403ceSYang, Bo union { 71181e403ceSYang, Bo u8 connectedPortBitmap; 71281e403ceSYang, Bo u8 connectedPortNumbers; 71381e403ceSYang, Bo }; 71481e403ceSYang, Bo u64 sasAddr[2]; 71581e403ceSYang, Bo } __packed; 71681e403ceSYang, Bo 71781e403ceSYang, Bo /* 71881e403ceSYang, Bo * defines the physical drive list structure 71981e403ceSYang, Bo */ 72081e403ceSYang, Bo struct MR_PD_LIST { 7219ab9ed38SChristoph Hellwig __le32 size; 7229ab9ed38SChristoph Hellwig __le32 count; 72381e403ceSYang, Bo struct MR_PD_ADDRESS addr[1]; 72481e403ceSYang, Bo } __packed; 72581e403ceSYang, Bo 72681e403ceSYang, Bo struct megasas_pd_list { 72781e403ceSYang, Bo u16 tid; 72881e403ceSYang, Bo u8 driveType; 72981e403ceSYang, Bo u8 driveState; 7302216c305SSumit Saxena u8 interface; 73181e403ceSYang, Bo } __packed; 73281e403ceSYang, Bo 73381e403ceSYang, Bo /* 734bdc6fb8dSYang, Bo * defines the logical drive reference structure 735bdc6fb8dSYang, Bo */ 736bdc6fb8dSYang, Bo union MR_LD_REF { 737bdc6fb8dSYang, Bo struct { 738bdc6fb8dSYang, Bo u8 targetId; 739bdc6fb8dSYang, Bo u8 reserved; 7409ab9ed38SChristoph Hellwig __le16 seqNum; 741bdc6fb8dSYang, Bo }; 7429ab9ed38SChristoph Hellwig __le32 ref; 743bdc6fb8dSYang, Bo } __packed; 744bdc6fb8dSYang, Bo 745bdc6fb8dSYang, Bo /* 746bdc6fb8dSYang, Bo * defines the logical drive list structure 747bdc6fb8dSYang, Bo */ 748bdc6fb8dSYang, Bo struct MR_LD_LIST { 7499ab9ed38SChristoph Hellwig __le32 ldCount; 7509ab9ed38SChristoph Hellwig __le32 reserved; 751bdc6fb8dSYang, Bo struct { 752bdc6fb8dSYang, Bo union MR_LD_REF ref; 753bdc6fb8dSYang, Bo u8 state; 754bdc6fb8dSYang, Bo u8 reserved[3]; 7559ab9ed38SChristoph Hellwig __le64 size; 75651087a86SSumit.Saxena@avagotech.com } ldList[MAX_LOGICAL_DRIVES_EXT]; 757bdc6fb8dSYang, Bo } __packed; 758bdc6fb8dSYang, Bo 75921c9e160Sadam radford struct MR_LD_TARGETID_LIST { 7609ab9ed38SChristoph Hellwig __le32 size; 7619ab9ed38SChristoph Hellwig __le32 count; 76221c9e160Sadam radford u8 pad[3]; 76351087a86SSumit.Saxena@avagotech.com u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 76421c9e160Sadam radford }; 76521c9e160Sadam radford 76621c9e160Sadam radford 767bdc6fb8dSYang, Bo /* 768c4a3e0a5SBagalkote, Sreenivas * SAS controller properties 769c4a3e0a5SBagalkote, Sreenivas */ 770c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop { 771c4a3e0a5SBagalkote, Sreenivas 772c4a3e0a5SBagalkote, Sreenivas u16 seq_num; 773c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval; 774c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count; 775c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts; 776c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate; 777c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate; 778c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate; 779c4a3e0a5SBagalkote, Sreenivas u8 cc_rate; 780c4a3e0a5SBagalkote, Sreenivas u8 recon_rate; 781c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval; 782c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count; 783c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay; 784c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable; 785c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode; 786c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable; 787c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild; 788c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn; 789c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size; 790c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate; 791c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion; 792c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices; 79339a98554Sbo yang u8 maintainPdFailHistory; 79439a98554Sbo yang u8 disallowHostRequestReordering; 79539a98554Sbo yang u8 abortCCOnError; 79639a98554Sbo yang u8 loadBalanceMode; 79739a98554Sbo yang u8 disableAutoDetectBackplane; 798c4a3e0a5SBagalkote, Sreenivas 79939a98554Sbo yang u8 snapVDSpace; 80039a98554Sbo yang 80139a98554Sbo yang /* 80239a98554Sbo yang * Add properties that can be controlled by 80339a98554Sbo yang * a bit in the following structure. 80439a98554Sbo yang */ 80539a98554Sbo yang struct { 80694cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 80794cd65ddSSumit.Saxena@lsi.com u32 reserved:18; 80894cd65ddSSumit.Saxena@lsi.com u32 enableJBOD:1; 80994cd65ddSSumit.Saxena@lsi.com u32 disableSpinDownHS:1; 81094cd65ddSSumit.Saxena@lsi.com u32 allowBootWithPinnedCache:1; 81194cd65ddSSumit.Saxena@lsi.com u32 disableOnlineCtrlReset:1; 81294cd65ddSSumit.Saxena@lsi.com u32 enableSecretKeyControl:1; 81394cd65ddSSumit.Saxena@lsi.com u32 autoEnhancedImport:1; 81494cd65ddSSumit.Saxena@lsi.com u32 enableSpinDownUnconfigured:1; 81594cd65ddSSumit.Saxena@lsi.com u32 SSDPatrolReadEnabled:1; 81694cd65ddSSumit.Saxena@lsi.com u32 SSDSMARTerEnabled:1; 81794cd65ddSSumit.Saxena@lsi.com u32 disableNCQ:1; 81894cd65ddSSumit.Saxena@lsi.com u32 useFdeOnly:1; 81994cd65ddSSumit.Saxena@lsi.com u32 prCorrectUnconfiguredAreas:1; 82094cd65ddSSumit.Saxena@lsi.com u32 SMARTerEnabled:1; 82194cd65ddSSumit.Saxena@lsi.com u32 copyBackDisabled:1; 82294cd65ddSSumit.Saxena@lsi.com #else 82339a98554Sbo yang u32 copyBackDisabled:1; 82439a98554Sbo yang u32 SMARTerEnabled:1; 82539a98554Sbo yang u32 prCorrectUnconfiguredAreas:1; 82639a98554Sbo yang u32 useFdeOnly:1; 82739a98554Sbo yang u32 disableNCQ:1; 82839a98554Sbo yang u32 SSDSMARTerEnabled:1; 82939a98554Sbo yang u32 SSDPatrolReadEnabled:1; 83039a98554Sbo yang u32 enableSpinDownUnconfigured:1; 83139a98554Sbo yang u32 autoEnhancedImport:1; 83239a98554Sbo yang u32 enableSecretKeyControl:1; 83339a98554Sbo yang u32 disableOnlineCtrlReset:1; 83439a98554Sbo yang u32 allowBootWithPinnedCache:1; 83539a98554Sbo yang u32 disableSpinDownHS:1; 83639a98554Sbo yang u32 enableJBOD:1; 83739a98554Sbo yang u32 reserved:18; 83894cd65ddSSumit.Saxena@lsi.com #endif 83939a98554Sbo yang } OnOffProperties; 84039a98554Sbo yang u8 autoSnapVDSpace; 84139a98554Sbo yang u8 viewSpace; 8429ab9ed38SChristoph Hellwig __le16 spinDownTime; 84339a98554Sbo yang u8 reserved[24]; 84481e403ceSYang, Bo } __packed; 845c4a3e0a5SBagalkote, Sreenivas 846c4a3e0a5SBagalkote, Sreenivas /* 847c4a3e0a5SBagalkote, Sreenivas * SAS controller information 848c4a3e0a5SBagalkote, Sreenivas */ 849c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info { 850c4a3e0a5SBagalkote, Sreenivas 851c4a3e0a5SBagalkote, Sreenivas /* 852c4a3e0a5SBagalkote, Sreenivas * PCI device information 853c4a3e0a5SBagalkote, Sreenivas */ 854c4a3e0a5SBagalkote, Sreenivas struct { 855c4a3e0a5SBagalkote, Sreenivas 8569ab9ed38SChristoph Hellwig __le16 vendor_id; 8579ab9ed38SChristoph Hellwig __le16 device_id; 8589ab9ed38SChristoph Hellwig __le16 sub_vendor_id; 8599ab9ed38SChristoph Hellwig __le16 sub_device_id; 860c4a3e0a5SBagalkote, Sreenivas u8 reserved[24]; 861c4a3e0a5SBagalkote, Sreenivas 862c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 863c4a3e0a5SBagalkote, Sreenivas 864c4a3e0a5SBagalkote, Sreenivas /* 865c4a3e0a5SBagalkote, Sreenivas * Host interface information 866c4a3e0a5SBagalkote, Sreenivas */ 867c4a3e0a5SBagalkote, Sreenivas struct { 868c4a3e0a5SBagalkote, Sreenivas 869c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1; 870c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1; 871c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1; 872c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 873229fe47cSadam radford u8 SRIOV:1; 874229fe47cSadam radford u8 reserved_0:3; 875c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 876c4a3e0a5SBagalkote, Sreenivas u8 port_count; 877c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 878c4a3e0a5SBagalkote, Sreenivas 879c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface; 880c4a3e0a5SBagalkote, Sreenivas 881c4a3e0a5SBagalkote, Sreenivas /* 882c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information 883c4a3e0a5SBagalkote, Sreenivas */ 884c4a3e0a5SBagalkote, Sreenivas struct { 885c4a3e0a5SBagalkote, Sreenivas 886c4a3e0a5SBagalkote, Sreenivas u8 SPI:1; 887c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1; 888c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1; 889c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1; 890c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4; 891c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6]; 892c4a3e0a5SBagalkote, Sreenivas u8 port_count; 893c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8]; 894c4a3e0a5SBagalkote, Sreenivas 895c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface; 896c4a3e0a5SBagalkote, Sreenivas 897c4a3e0a5SBagalkote, Sreenivas /* 898c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated 899c4a3e0a5SBagalkote, Sreenivas */ 9009ab9ed38SChristoph Hellwig __le32 image_check_word; 9019ab9ed38SChristoph Hellwig __le32 image_component_count; 902c4a3e0a5SBagalkote, Sreenivas 903c4a3e0a5SBagalkote, Sreenivas struct { 904c4a3e0a5SBagalkote, Sreenivas 905c4a3e0a5SBagalkote, Sreenivas char name[8]; 906c4a3e0a5SBagalkote, Sreenivas char version[32]; 907c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 908c4a3e0a5SBagalkote, Sreenivas char built_time[16]; 909c4a3e0a5SBagalkote, Sreenivas 910c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8]; 911c4a3e0a5SBagalkote, Sreenivas 912c4a3e0a5SBagalkote, Sreenivas /* 913c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but 914c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be 915c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null 916c4a3e0a5SBagalkote, Sreenivas * terminated 917c4a3e0a5SBagalkote, Sreenivas */ 9189ab9ed38SChristoph Hellwig __le32 pending_image_component_count; 919c4a3e0a5SBagalkote, Sreenivas 920c4a3e0a5SBagalkote, Sreenivas struct { 921c4a3e0a5SBagalkote, Sreenivas 922c4a3e0a5SBagalkote, Sreenivas char name[8]; 923c4a3e0a5SBagalkote, Sreenivas char version[32]; 924c4a3e0a5SBagalkote, Sreenivas char build_date[16]; 925c4a3e0a5SBagalkote, Sreenivas char build_time[16]; 926c4a3e0a5SBagalkote, Sreenivas 927c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8]; 928c4a3e0a5SBagalkote, Sreenivas 929c4a3e0a5SBagalkote, Sreenivas u8 max_arms; 930c4a3e0a5SBagalkote, Sreenivas u8 max_spans; 931c4a3e0a5SBagalkote, Sreenivas u8 max_arrays; 932c4a3e0a5SBagalkote, Sreenivas u8 max_lds; 933c4a3e0a5SBagalkote, Sreenivas 934c4a3e0a5SBagalkote, Sreenivas char product_name[80]; 935c4a3e0a5SBagalkote, Sreenivas char serial_no[32]; 936c4a3e0a5SBagalkote, Sreenivas 937c4a3e0a5SBagalkote, Sreenivas /* 938c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the 939c4a3e0a5SBagalkote, Sreenivas * presence of the hardware 940c4a3e0a5SBagalkote, Sreenivas */ 941c4a3e0a5SBagalkote, Sreenivas struct { 942c4a3e0a5SBagalkote, Sreenivas 943c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 944c4a3e0a5SBagalkote, Sreenivas u32 alarm:1; 945c4a3e0a5SBagalkote, Sreenivas u32 nvram:1; 946c4a3e0a5SBagalkote, Sreenivas u32 uart:1; 947c4a3e0a5SBagalkote, Sreenivas u32 reserved:28; 948c4a3e0a5SBagalkote, Sreenivas 949c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present; 950c4a3e0a5SBagalkote, Sreenivas 9519ab9ed38SChristoph Hellwig __le32 current_fw_time; 952c4a3e0a5SBagalkote, Sreenivas 953c4a3e0a5SBagalkote, Sreenivas /* 954c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes 955c4a3e0a5SBagalkote, Sreenivas */ 9569ab9ed38SChristoph Hellwig __le16 max_concurrent_cmds; 9579ab9ed38SChristoph Hellwig __le16 max_sge_count; 9589ab9ed38SChristoph Hellwig __le32 max_request_size; 959c4a3e0a5SBagalkote, Sreenivas 960c4a3e0a5SBagalkote, Sreenivas /* 961c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts 962c4a3e0a5SBagalkote, Sreenivas */ 9639ab9ed38SChristoph Hellwig __le16 ld_present_count; 9649ab9ed38SChristoph Hellwig __le16 ld_degraded_count; 9659ab9ed38SChristoph Hellwig __le16 ld_offline_count; 966c4a3e0a5SBagalkote, Sreenivas 9679ab9ed38SChristoph Hellwig __le16 pd_present_count; 9689ab9ed38SChristoph Hellwig __le16 pd_disk_present_count; 9699ab9ed38SChristoph Hellwig __le16 pd_disk_pred_failure_count; 9709ab9ed38SChristoph Hellwig __le16 pd_disk_failed_count; 971c4a3e0a5SBagalkote, Sreenivas 972c4a3e0a5SBagalkote, Sreenivas /* 973c4a3e0a5SBagalkote, Sreenivas * Memory size information 974c4a3e0a5SBagalkote, Sreenivas */ 9759ab9ed38SChristoph Hellwig __le16 nvram_size; 9769ab9ed38SChristoph Hellwig __le16 memory_size; 9779ab9ed38SChristoph Hellwig __le16 flash_size; 978c4a3e0a5SBagalkote, Sreenivas 979c4a3e0a5SBagalkote, Sreenivas /* 980c4a3e0a5SBagalkote, Sreenivas * Error counters 981c4a3e0a5SBagalkote, Sreenivas */ 9829ab9ed38SChristoph Hellwig __le16 mem_correctable_error_count; 9839ab9ed38SChristoph Hellwig __le16 mem_uncorrectable_error_count; 984c4a3e0a5SBagalkote, Sreenivas 985c4a3e0a5SBagalkote, Sreenivas /* 986c4a3e0a5SBagalkote, Sreenivas * Cluster information 987c4a3e0a5SBagalkote, Sreenivas */ 988c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted; 989c4a3e0a5SBagalkote, Sreenivas u8 cluster_active; 990c4a3e0a5SBagalkote, Sreenivas 991c4a3e0a5SBagalkote, Sreenivas /* 992c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes 993c4a3e0a5SBagalkote, Sreenivas */ 9949ab9ed38SChristoph Hellwig __le16 max_strips_per_io; 995c4a3e0a5SBagalkote, Sreenivas 996c4a3e0a5SBagalkote, Sreenivas /* 997c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures 998c4a3e0a5SBagalkote, Sreenivas */ 999c4a3e0a5SBagalkote, Sreenivas struct { 1000c4a3e0a5SBagalkote, Sreenivas 1001c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1; 1002c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1; 1003c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1; 1004c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1; 1005c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1; 1006c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1007c4a3e0a5SBagalkote, Sreenivas 1008c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels; 1009c4a3e0a5SBagalkote, Sreenivas 1010c4a3e0a5SBagalkote, Sreenivas struct { 1011c4a3e0a5SBagalkote, Sreenivas 1012c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1; 1013c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1; 1014c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1; 1015c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1; 1016c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1; 1017c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1; 1018c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1; 1019c4a3e0a5SBagalkote, Sreenivas u32 bbu:1; 1020c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1; 1021c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1; 1022c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1; 1023c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1; 1024c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1; 1025c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1; 1026c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1; 1027c4a3e0a5SBagalkote, Sreenivas u32 reserved:17; 1028c4a3e0a5SBagalkote, Sreenivas 1029c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations; 1030c4a3e0a5SBagalkote, Sreenivas 1031c4a3e0a5SBagalkote, Sreenivas struct { 1032c4a3e0a5SBagalkote, Sreenivas 1033c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1; 1034c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1; 1035c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1; 1036c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1; 1037c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1; 1038c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1039c4a3e0a5SBagalkote, Sreenivas 1040c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations; 1041c4a3e0a5SBagalkote, Sreenivas 1042c4a3e0a5SBagalkote, Sreenivas struct { 1043c4a3e0a5SBagalkote, Sreenivas 1044c4a3e0a5SBagalkote, Sreenivas u8 min; 1045c4a3e0a5SBagalkote, Sreenivas u8 max; 1046c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1047c4a3e0a5SBagalkote, Sreenivas 1048c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops; 1049c4a3e0a5SBagalkote, Sreenivas 1050c4a3e0a5SBagalkote, Sreenivas struct { 1051c4a3e0a5SBagalkote, Sreenivas 1052c4a3e0a5SBagalkote, Sreenivas u32 force_online:1; 1053c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1; 1054c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1; 1055c4a3e0a5SBagalkote, Sreenivas u32 reserved:29; 1056c4a3e0a5SBagalkote, Sreenivas 1057c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations; 1058c4a3e0a5SBagalkote, Sreenivas 1059c4a3e0a5SBagalkote, Sreenivas struct { 1060c4a3e0a5SBagalkote, Sreenivas 1061c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1; 1062c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1; 1063c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1; 1064c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1; 1065c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1; 1066c4a3e0a5SBagalkote, Sreenivas u32 reserved:27; 1067c4a3e0a5SBagalkote, Sreenivas 1068c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support; 1069c4a3e0a5SBagalkote, Sreenivas 1070c4a3e0a5SBagalkote, Sreenivas /* 1071c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information 1072c4a3e0a5SBagalkote, Sreenivas */ 1073c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count; 1074c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11]; 1075c4a3e0a5SBagalkote, Sreenivas 1076c4a3e0a5SBagalkote, Sreenivas /* 1077c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items) 1078c4a3e0a5SBagalkote, Sreenivas */ 1079c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties; 1080c4a3e0a5SBagalkote, Sreenivas 1081c4a3e0a5SBagalkote, Sreenivas /* 1082c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis) 1083c4a3e0a5SBagalkote, Sreenivas */ 1084c4a3e0a5SBagalkote, Sreenivas char package_version[0x60]; 1085c4a3e0a5SBagalkote, Sreenivas 1086c4a3e0a5SBagalkote, Sreenivas 1087bc93d425SSumit.Saxena@lsi.com /* 1088bc93d425SSumit.Saxena@lsi.com * If adapterOperations.supportMoreThan8Phys is set, 1089bc93d425SSumit.Saxena@lsi.com * and deviceInterface.portCount is greater than 8, 1090bc93d425SSumit.Saxena@lsi.com * SAS Addrs for first 8 ports shall be populated in 1091bc93d425SSumit.Saxena@lsi.com * deviceInterface.portAddr, and the rest shall be 1092bc93d425SSumit.Saxena@lsi.com * populated in deviceInterfacePortAddr2. 1093bc93d425SSumit.Saxena@lsi.com */ 10949ab9ed38SChristoph Hellwig __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1095bc93d425SSumit.Saxena@lsi.com u8 reserved3[128]; /*6e0h */ 1096bc93d425SSumit.Saxena@lsi.com 1097bc93d425SSumit.Saxena@lsi.com struct { /*760h */ 1098bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_0:4; 1099bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_0:12; 1100bc93d425SSumit.Saxena@lsi.com 1101bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1:4; 1102bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1:12; 1103bc93d425SSumit.Saxena@lsi.com 1104bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_5:4; 1105bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_5:12; 1106bc93d425SSumit.Saxena@lsi.com 1107bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E:4; 1108bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E:12; 1109bc93d425SSumit.Saxena@lsi.com 1110bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_6:4; 1111bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_6:12; 1112bc93d425SSumit.Saxena@lsi.com 1113bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_10:4; 1114bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_10:12; 1115bc93d425SSumit.Saxena@lsi.com 1116bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_50:4; 1117bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_50:12; 1118bc93d425SSumit.Saxena@lsi.com 1119bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_60:4; 1120bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_60:12; 1121bc93d425SSumit.Saxena@lsi.com 1122bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E_RLQ0:4; 1123bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E_RLQ0:12; 1124bc93d425SSumit.Saxena@lsi.com 1125bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E0_RLQ0:4; 1126bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E0_RLQ0:12; 1127bc93d425SSumit.Saxena@lsi.com 1128bc93d425SSumit.Saxena@lsi.com u16 reserved[6]; 1129bc93d425SSumit.Saxena@lsi.com } pdsForRaidLevels; 1130bc93d425SSumit.Saxena@lsi.com 11319ab9ed38SChristoph Hellwig __le16 maxPds; /*780h */ 11329ab9ed38SChristoph Hellwig __le16 maxDedHSPs; /*782h */ 11339ab9ed38SChristoph Hellwig __le16 maxGlobalHSP; /*784h */ 11349ab9ed38SChristoph Hellwig __le16 ddfSize; /*786h */ 1135bc93d425SSumit.Saxena@lsi.com u8 maxLdsPerArray; /*788h */ 1136bc93d425SSumit.Saxena@lsi.com u8 partitionsInDDF; /*789h */ 1137bc93d425SSumit.Saxena@lsi.com u8 lockKeyBinding; /*78ah */ 1138bc93d425SSumit.Saxena@lsi.com u8 maxPITsPerLd; /*78bh */ 1139bc93d425SSumit.Saxena@lsi.com u8 maxViewsPerLd; /*78ch */ 1140bc93d425SSumit.Saxena@lsi.com u8 maxTargetId; /*78dh */ 11419ab9ed38SChristoph Hellwig __le16 maxBvlVdSize; /*78eh */ 1142bc93d425SSumit.Saxena@lsi.com 11439ab9ed38SChristoph Hellwig __le16 maxConfigurableSSCSize; /*790h */ 11449ab9ed38SChristoph Hellwig __le16 currentSSCsize; /*792h */ 1145bc93d425SSumit.Saxena@lsi.com 1146bc93d425SSumit.Saxena@lsi.com char expanderFwVersion[12]; /*794h */ 1147bc93d425SSumit.Saxena@lsi.com 11489ab9ed38SChristoph Hellwig __le16 PFKTrialTimeRemaining; /*7A0h */ 1149bc93d425SSumit.Saxena@lsi.com 11509ab9ed38SChristoph Hellwig __le16 cacheMemorySize; /*7A2h */ 1151bc93d425SSumit.Saxena@lsi.com 1152bc93d425SSumit.Saxena@lsi.com struct { /*7A4h */ 115394cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 1154229fe47cSadam radford u32 reserved:5; 1155229fe47cSadam radford u32 activePassive:2; 1156229fe47cSadam radford u32 supportConfigAutoBalance:1; 1157229fe47cSadam radford u32 mpio:1; 1158229fe47cSadam radford u32 supportDataLDonSSCArray:1; 1159229fe47cSadam radford u32 supportPointInTimeProgress:1; 116094cd65ddSSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 116194cd65ddSSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 116294cd65ddSSumit.Saxena@lsi.com u32 headlessMode:1; 116394cd65ddSSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 116494cd65ddSSumit.Saxena@lsi.com u32 supportResetNow:1; 116594cd65ddSSumit.Saxena@lsi.com u32 realTimeScheduler:1; 116694cd65ddSSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 116794cd65ddSSumit.Saxena@lsi.com u32 supportPerfTuning:1; 116894cd65ddSSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 116994cd65ddSSumit.Saxena@lsi.com u32 supportJBOD:1; 117094cd65ddSSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 117194cd65ddSSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 117294cd65ddSSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 117394cd65ddSSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 117494cd65ddSSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 117594cd65ddSSumit.Saxena@lsi.com u32 supportShieldState:1; 117694cd65ddSSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 117794cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType3:1; 117894cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType2:1; 117994cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType1:1; 118094cd65ddSSumit.Saxena@lsi.com u32 supportPIcontroller:1; 118194cd65ddSSumit.Saxena@lsi.com #else 1182bc93d425SSumit.Saxena@lsi.com u32 supportPIcontroller:1; 1183bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType1:1; 1184bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType2:1; 1185bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType3:1; 1186bc93d425SSumit.Saxena@lsi.com u32 supportLdBBMInfo:1; 1187bc93d425SSumit.Saxena@lsi.com u32 supportShieldState:1; 1188bc93d425SSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1; 1189bc93d425SSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1; 1190bc93d425SSumit.Saxena@lsi.com u32 supportEmergencySpares:1; 1191bc93d425SSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1; 1192bc93d425SSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1; 1193bc93d425SSumit.Saxena@lsi.com u32 supportJBOD:1; 1194bc93d425SSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1; 1195bc93d425SSumit.Saxena@lsi.com u32 supportPerfTuning:1; 1196bc93d425SSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1; 1197bc93d425SSumit.Saxena@lsi.com u32 realTimeScheduler:1; 1198bc93d425SSumit.Saxena@lsi.com 1199bc93d425SSumit.Saxena@lsi.com u32 supportResetNow:1; 1200bc93d425SSumit.Saxena@lsi.com u32 supportEmulatedDrives:1; 1201bc93d425SSumit.Saxena@lsi.com u32 headlessMode:1; 1202bc93d425SSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1; 1203bc93d425SSumit.Saxena@lsi.com 1204bc93d425SSumit.Saxena@lsi.com 1205bc93d425SSumit.Saxena@lsi.com u32 supportUnevenSpans:1; 1206229fe47cSadam radford u32 supportPointInTimeProgress:1; 1207229fe47cSadam radford u32 supportDataLDonSSCArray:1; 1208229fe47cSadam radford u32 mpio:1; 1209229fe47cSadam radford u32 supportConfigAutoBalance:1; 1210229fe47cSadam radford u32 activePassive:2; 1211229fe47cSadam radford u32 reserved:5; 121294cd65ddSSumit.Saxena@lsi.com #endif 1213bc93d425SSumit.Saxena@lsi.com } adapterOperations2; 1214bc93d425SSumit.Saxena@lsi.com 1215bc93d425SSumit.Saxena@lsi.com u8 driverVersion[32]; /*7A8h */ 1216bc93d425SSumit.Saxena@lsi.com u8 maxDAPdCountSpinup60; /*7C8h */ 1217bc93d425SSumit.Saxena@lsi.com u8 temperatureROC; /*7C9h */ 1218bc93d425SSumit.Saxena@lsi.com u8 temperatureCtrl; /*7CAh */ 1219bc93d425SSumit.Saxena@lsi.com u8 reserved4; /*7CBh */ 12209ab9ed38SChristoph Hellwig __le16 maxConfigurablePds; /*7CCh */ 1221bc93d425SSumit.Saxena@lsi.com 1222bc93d425SSumit.Saxena@lsi.com 1223bc93d425SSumit.Saxena@lsi.com u8 reserved5[2]; /*0x7CDh */ 1224bc93d425SSumit.Saxena@lsi.com 1225bc93d425SSumit.Saxena@lsi.com /* 1226bc93d425SSumit.Saxena@lsi.com * HA cluster information 1227bc93d425SSumit.Saxena@lsi.com */ 1228bc93d425SSumit.Saxena@lsi.com struct { 122951087a86SSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 123051087a86SSumit.Saxena@avagotech.com u32 reserved:26; 123151087a86SSumit.Saxena@avagotech.com u32 premiumFeatureMismatch:1; 123251087a86SSumit.Saxena@avagotech.com u32 ctrlPropIncompatible:1; 123351087a86SSumit.Saxena@avagotech.com u32 fwVersionMismatch:1; 123451087a86SSumit.Saxena@avagotech.com u32 hwIncompatible:1; 123551087a86SSumit.Saxena@avagotech.com u32 peerIsIncompatible:1; 123651087a86SSumit.Saxena@avagotech.com u32 peerIsPresent:1; 123751087a86SSumit.Saxena@avagotech.com #else 1238bc93d425SSumit.Saxena@lsi.com u32 peerIsPresent:1; 1239bc93d425SSumit.Saxena@lsi.com u32 peerIsIncompatible:1; 1240bc93d425SSumit.Saxena@lsi.com u32 hwIncompatible:1; 1241bc93d425SSumit.Saxena@lsi.com u32 fwVersionMismatch:1; 1242bc93d425SSumit.Saxena@lsi.com u32 ctrlPropIncompatible:1; 1243bc93d425SSumit.Saxena@lsi.com u32 premiumFeatureMismatch:1; 1244bc93d425SSumit.Saxena@lsi.com u32 reserved:26; 124551087a86SSumit.Saxena@avagotech.com #endif 1246bc93d425SSumit.Saxena@lsi.com } cluster; 1247bc93d425SSumit.Saxena@lsi.com 1248bc93d425SSumit.Saxena@lsi.com char clusterId[16]; /*7D4h */ 1249229fe47cSadam radford struct { 1250229fe47cSadam radford u8 maxVFsSupported; /*0x7E4*/ 1251229fe47cSadam radford u8 numVFsEnabled; /*0x7E5*/ 1252229fe47cSadam radford u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1253229fe47cSadam radford u8 reserved; /*0x7E7*/ 1254229fe47cSadam radford } iov; 1255bc93d425SSumit.Saxena@lsi.com 1256fc62b3fcSSumit.Saxena@avagotech.com struct { 1257fc62b3fcSSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD) 12583761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 12593761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 12600be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 12610be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 12620be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 12630be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 12647497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 12657497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 12667497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 12677497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 12687497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 12697497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 12707497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 12717497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 12727497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 12737497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 12747497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 12757497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 12767497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 1277fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 127851087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 127951087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 128051087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 128151087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 128251087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 1283fc62b3fcSSumit.Saxena@avagotech.com #else 128451087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2; 128551087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1; 128651087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1; 128751087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1; 128851087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1; 1289fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1; 12907497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1; 12917497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1; 12927497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1; 12937497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1; 12947497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1; 12957497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1; 12967497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1; 12977497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1; 12987497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1; 12997497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1; 13007497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1; 13017497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1; 13027497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1; 13030be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1; 13040be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1; 13050be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1; 13060be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1; 13073761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1; 13083761cb4cSsumit.saxena@avagotech.com u32 reserved:7; 1309fc62b3fcSSumit.Saxena@avagotech.com #endif 1310fc62b3fcSSumit.Saxena@avagotech.com } adapterOperations3; 1311fc62b3fcSSumit.Saxena@avagotech.com 1312fc62b3fcSSumit.Saxena@avagotech.com u8 pad[0x800-0x7EC]; 131381e403ceSYang, Bo } __packed; 1314c4a3e0a5SBagalkote, Sreenivas 1315c4a3e0a5SBagalkote, Sreenivas /* 1316c4a3e0a5SBagalkote, Sreenivas * =============================== 1317c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions 1318c4a3e0a5SBagalkote, Sreenivas * =============================== 1319c4a3e0a5SBagalkote, Sreenivas */ 1320c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2 132151087a86SSumit.Saxena@avagotech.com #define MEGASAS_MAX_LD_CHANNELS 2 1322c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1323c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS) 1324c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1325c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1 1326c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8 13276bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256 132881e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 132981e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1330bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1331bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL) 1332c4a3e0a5SBagalkote, Sreenivas 13331fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024) 133442a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1335658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1 1336658dcedbSSumant Patro 133705e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1 133805e9ebbeSSumant Patro 133951087a86SSumit.Saxena@avagotech.com #define VD_EXT_DEBUG 0 134051087a86SSumit.Saxena@avagotech.com 134111c71cb4SSumit Saxena #define SCAN_PD_CHANNEL 0x1 134211c71cb4SSumit Saxena #define SCAN_VD_CHANNEL 0x2 134390dc9d98SSumit.Saxena@avagotech.com 13447497cde8SSumit.Saxena@avagotech.com enum MR_SCSI_CMD_TYPE { 13457497cde8SSumit.Saxena@avagotech.com READ_WRITE_LDIO = 0, 13467497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_LDIO = 1, 13477497cde8SSumit.Saxena@avagotech.com READ_WRITE_SYSPDIO = 2, 13487497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_SYSPDIO = 3, 13497497cde8SSumit.Saxena@avagotech.com }; 13507497cde8SSumit.Saxena@avagotech.com 13516d40afbcSSumit Saxena enum DCMD_TIMEOUT_ACTION { 13526d40afbcSSumit Saxena INITIATE_OCR = 0, 13536d40afbcSSumit Saxena KILL_ADAPTER = 1, 13546d40afbcSSumit Saxena IGNORE_TIMEOUT = 2, 13556d40afbcSSumit Saxena }; 1356d532dbe2Sbo yang /* Frame Type */ 1357d532dbe2Sbo yang #define IO_FRAME 0 1358d532dbe2Sbo yang #define PTHRU_FRAME 1 1359d532dbe2Sbo yang 1360c4a3e0a5SBagalkote, Sreenivas /* 1361c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for 1362c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1363c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While 1364c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message 1365c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1366c4a3e0a5SBagalkote, Sreenivas */ 1367c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180 13682a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1369c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5 1370c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0 137105e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1372c5daa6a9Sadam radford #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 137390dc9d98SSumit.Saxena@avagotech.com #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1374c4a3e0a5SBagalkote, Sreenivas /* 1375c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum 1376c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a 1377c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands 1378c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1379c4a3e0a5SBagalkote, Sreenivas * is shown below 1380c4a3e0a5SBagalkote, Sreenivas */ 1381c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32 13827bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5 1383ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_INTERNAL_CMDS 5 1384ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_IOCTL_CMDS 3 1385f26ac3a1SSumit.Saxena@avagotech.com #define MEGASAS_MFI_IOCTL_CMDS 27 1386c4a3e0a5SBagalkote, Sreenivas 1387d46a3ad6SSumit.Saxena@lsi.com #define MEGASAS_MAX_MSIX_QUEUES 128 1388c4a3e0a5SBagalkote, Sreenivas /* 1389c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1390c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t 1391c4a3e0a5SBagalkote, Sreenivas */ 1392c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1393c4a3e0a5SBagalkote, Sreenivas 139439a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 139539a98554Sbo yang 139639a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 139739a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 139839a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 139939a98554Sbo yang 1400c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002 140114faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60 14026d40afbcSSumit Saxena #define MFI_IO_TIMEOUT_SECS 180 1403229fe47cSadam radford #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1404229fe47cSadam radford #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1405229fe47cSadam radford #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1406f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 14076610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 14086610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 140987911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 141087911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 14110e98936cSSumant Patro 141239a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84 141339a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 141439a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000 1415d46a3ad6SSumit.Saxena@lsi.com 1416d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1417d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1418d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1419d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_MSIX_REG_ARRAY 16 1420179ac142SSumit Saxena #define MR_RDPQ_MODE_OFFSET 0X00800000 14210e98936cSSumant Patro /* 14220e98936cSSumant Patro * register set for both 1068 and 1078 controllers 14230e98936cSSumant Patro * structure extended for 1078 registers 14240e98936cSSumant Patro */ 1425c4a3e0a5SBagalkote, Sreenivas 1426f9876f0bSSumant Patro struct megasas_register_set { 14279c915a8cSadam radford u32 doorbell; /*0000h*/ 14289c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/ 14299c915a8cSadam radford u32 fusion_host_diag; /*0008h*/ 14309c915a8cSadam radford u32 reserved_01; /*000Ch*/ 1431c4a3e0a5SBagalkote, Sreenivas 1432c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/ 1433c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/ 1434c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/ 1435c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/ 1436c4a3e0a5SBagalkote, Sreenivas 1437c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/ 1438c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/ 1439c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/ 1440c4a3e0a5SBagalkote, Sreenivas 1441c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/ 1442c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/ 1443c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/ 1444c4a3e0a5SBagalkote, Sreenivas 1445c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/ 1446c4a3e0a5SBagalkote, Sreenivas 1447c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/ 1448c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/ 1449c4a3e0a5SBagalkote, Sreenivas 14509c915a8cSadam radford u32 reserved_2[9]; /*0048h*/ 14519c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/ 14529c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/ 1453c4a3e0a5SBagalkote, Sreenivas 1454f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/ 1455f9876f0bSSumant Patro 1456f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/ 1457f9876f0bSSumant Patro 1458f9876f0bSSumant Patro u32 outbound_scratch_pad ; /*00B0h*/ 14599c915a8cSadam radford u32 outbound_scratch_pad_2; /*00B4h*/ 1460179ac142SSumit Saxena u32 outbound_scratch_pad_3; /*00B8h*/ 1461f9876f0bSSumant Patro 1462179ac142SSumit Saxena u32 reserved_4; /*00BCh*/ 1463f9876f0bSSumant Patro 1464f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/ 1465f9876f0bSSumant Patro 1466f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/ 1467f9876f0bSSumant Patro 1468f9876f0bSSumant Patro u32 reserved_5; /*00C8h*/ 146939a98554Sbo yang u32 res_6[11]; /*CCh*/ 147039a98554Sbo yang u32 host_diag; 147139a98554Sbo yang u32 seq_offset; 147239a98554Sbo yang u32 index_registers[807]; /*00CCh*/ 1473c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1474c4a3e0a5SBagalkote, Sreenivas 1475c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 { 1476c4a3e0a5SBagalkote, Sreenivas 14779ab9ed38SChristoph Hellwig __le32 phys_addr; 14789ab9ed38SChristoph Hellwig __le32 length; 1479c4a3e0a5SBagalkote, Sreenivas 1480c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1481c4a3e0a5SBagalkote, Sreenivas 1482c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 { 1483c4a3e0a5SBagalkote, Sreenivas 14849ab9ed38SChristoph Hellwig __le64 phys_addr; 14859ab9ed38SChristoph Hellwig __le32 length; 1486c4a3e0a5SBagalkote, Sreenivas 1487c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1488c4a3e0a5SBagalkote, Sreenivas 1489f4c9a131SYang, Bo struct megasas_sge_skinny { 14909ab9ed38SChristoph Hellwig __le64 phys_addr; 14919ab9ed38SChristoph Hellwig __le32 length; 14929ab9ed38SChristoph Hellwig __le32 flag; 1493f4c9a131SYang, Bo } __packed; 1494f4c9a131SYang, Bo 1495c4a3e0a5SBagalkote, Sreenivas union megasas_sgl { 1496c4a3e0a5SBagalkote, Sreenivas 1497c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[1]; 1498c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[1]; 1499f4c9a131SYang, Bo struct megasas_sge_skinny sge_skinny[1]; 1500c4a3e0a5SBagalkote, Sreenivas 1501c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1502c4a3e0a5SBagalkote, Sreenivas 1503c4a3e0a5SBagalkote, Sreenivas struct megasas_header { 1504c4a3e0a5SBagalkote, Sreenivas 1505c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1506c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1507c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1508c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1509c4a3e0a5SBagalkote, Sreenivas 1510c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1511c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1512c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1513c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1514c4a3e0a5SBagalkote, Sreenivas 15159ab9ed38SChristoph Hellwig __le32 context; /*08h */ 15169ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1517c4a3e0a5SBagalkote, Sreenivas 15189ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 15199ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 15209ab9ed38SChristoph Hellwig __le32 data_xferlen; /*14h */ 1521c4a3e0a5SBagalkote, Sreenivas 1522c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1523c4a3e0a5SBagalkote, Sreenivas 1524c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame { 1525c4a3e0a5SBagalkote, Sreenivas 1526c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8]; 1527c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5]; 1528c4a3e0a5SBagalkote, Sreenivas 1529c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1530c4a3e0a5SBagalkote, Sreenivas 1531d46a3ad6SSumit.Saxena@lsi.com typedef union _MFI_CAPABILITIES { 1532d46a3ad6SSumit.Saxena@lsi.com struct { 153394cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD) 15348f05024cSSumit Saxena u32 reserved:21; 15358f05024cSSumit Saxena u32 support_fp_rlbypass:1; 15368f05024cSSumit Saxena u32 support_vfid_in_ioframe:1; 1537bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 15380be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 15397497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 15407497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 1541d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 154251087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 15437497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 154494cd65ddSSumit.Saxena@lsi.com u32 support_additional_msix:1; 154594cd65ddSSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 154694cd65ddSSumit.Saxena@lsi.com #else 1547d46a3ad6SSumit.Saxena@lsi.com u32 support_fp_remote_lun:1; 1548d46a3ad6SSumit.Saxena@lsi.com u32 support_additional_msix:1; 15497497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1; 155051087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1; 1551d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1; 15527497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1; 15537497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1; 15540be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1; 1555bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1; 15568f05024cSSumit Saxena u32 support_vfid_in_ioframe:1; 15578f05024cSSumit Saxena u32 support_fp_rlbypass:1; 15588f05024cSSumit Saxena u32 reserved:21; 155994cd65ddSSumit.Saxena@lsi.com #endif 1560d46a3ad6SSumit.Saxena@lsi.com } mfi_capabilities; 15619ab9ed38SChristoph Hellwig __le32 reg; 1562d46a3ad6SSumit.Saxena@lsi.com } MFI_CAPABILITIES; 1563d46a3ad6SSumit.Saxena@lsi.com 1564c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame { 1565c4a3e0a5SBagalkote, Sreenivas 1566c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1567c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1568c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1569c4a3e0a5SBagalkote, Sreenivas 1570c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 1571d46a3ad6SSumit.Saxena@lsi.com MFI_CAPABILITIES driver_operations; /*04h*/ 1572c4a3e0a5SBagalkote, Sreenivas 15739ab9ed38SChristoph Hellwig __le32 context; /*08h */ 15749ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1575c4a3e0a5SBagalkote, Sreenivas 15769ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 15779ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 15789ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1579c4a3e0a5SBagalkote, Sreenivas 15809ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_lo; /*18h */ 15819ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_hi; /*1Ch */ 15829ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_lo; /*20h */ 15839ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_hi; /*24h */ 15849ab9ed38SChristoph Hellwig __le32 reserved_4[2]; /*28h */ 15859ab9ed38SChristoph Hellwig __le32 system_info_lo; /*30h */ 15869ab9ed38SChristoph Hellwig __le32 system_info_hi; /*34h */ 15879ab9ed38SChristoph Hellwig __le32 reserved_5[2]; /*38h */ 1588c4a3e0a5SBagalkote, Sreenivas 1589c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1590c4a3e0a5SBagalkote, Sreenivas 1591c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info { 1592c4a3e0a5SBagalkote, Sreenivas 15939ab9ed38SChristoph Hellwig __le32 init_flags; /*00h */ 15949ab9ed38SChristoph Hellwig __le32 reply_queue_entries; /*04h */ 1595c4a3e0a5SBagalkote, Sreenivas 15969ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_lo; /*08h */ 15979ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 15989ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_lo; /*10h */ 15999ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_hi; /*14h */ 16009ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_lo; /*18h */ 16019ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_hi; /*1Ch */ 1602c4a3e0a5SBagalkote, Sreenivas 1603c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1604c4a3e0a5SBagalkote, Sreenivas 1605c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame { 1606c4a3e0a5SBagalkote, Sreenivas 1607c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1608c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1609c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1610c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1611c4a3e0a5SBagalkote, Sreenivas 1612c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1613c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */ 1614c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */ 1615c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1616c4a3e0a5SBagalkote, Sreenivas 16179ab9ed38SChristoph Hellwig __le32 context; /*08h */ 16189ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1619c4a3e0a5SBagalkote, Sreenivas 16209ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 16219ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 16229ab9ed38SChristoph Hellwig __le32 lba_count; /*14h */ 1623c4a3e0a5SBagalkote, Sreenivas 16249ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 16259ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1626c4a3e0a5SBagalkote, Sreenivas 16279ab9ed38SChristoph Hellwig __le32 start_lba_lo; /*20h */ 16289ab9ed38SChristoph Hellwig __le32 start_lba_hi; /*24h */ 1629c4a3e0a5SBagalkote, Sreenivas 1630c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1631c4a3e0a5SBagalkote, Sreenivas 1632c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1633c4a3e0a5SBagalkote, Sreenivas 1634c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame { 1635c4a3e0a5SBagalkote, Sreenivas 1636c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1637c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */ 1638c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1639c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */ 1640c4a3e0a5SBagalkote, Sreenivas 1641c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1642c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */ 1643c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */ 1644c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1645c4a3e0a5SBagalkote, Sreenivas 16469ab9ed38SChristoph Hellwig __le32 context; /*08h */ 16479ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1648c4a3e0a5SBagalkote, Sreenivas 16499ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 16509ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 16519ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1652c4a3e0a5SBagalkote, Sreenivas 16539ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */ 16549ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */ 1655c4a3e0a5SBagalkote, Sreenivas 1656c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */ 1657c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */ 1658c4a3e0a5SBagalkote, Sreenivas 1659c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1660c4a3e0a5SBagalkote, Sreenivas 1661c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame { 1662c4a3e0a5SBagalkote, Sreenivas 1663c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1664c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1665c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1666c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */ 1667c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1668c4a3e0a5SBagalkote, Sreenivas 16699ab9ed38SChristoph Hellwig __le32 context; /*08h */ 16709ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1671c4a3e0a5SBagalkote, Sreenivas 16729ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 16739ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1674c4a3e0a5SBagalkote, Sreenivas 16759ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 16769ab9ed38SChristoph Hellwig __le32 opcode; /*18h */ 1677c4a3e0a5SBagalkote, Sreenivas 1678c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */ 1679c4a3e0a5SBagalkote, Sreenivas u8 b[12]; 16809ab9ed38SChristoph Hellwig __le16 s[6]; 16819ab9ed38SChristoph Hellwig __le32 w[3]; 1682c4a3e0a5SBagalkote, Sreenivas } mbox; 1683c4a3e0a5SBagalkote, Sreenivas 1684c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */ 1685c4a3e0a5SBagalkote, Sreenivas 1686c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1687c4a3e0a5SBagalkote, Sreenivas 1688c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame { 1689c4a3e0a5SBagalkote, Sreenivas 1690c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1691c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */ 1692c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1693c4a3e0a5SBagalkote, Sreenivas 1694c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */ 16959ab9ed38SChristoph Hellwig __le32 reserved_2; /*04h */ 1696c4a3e0a5SBagalkote, Sreenivas 16979ab9ed38SChristoph Hellwig __le32 context; /*08h */ 16989ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1699c4a3e0a5SBagalkote, Sreenivas 17009ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 17019ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */ 17029ab9ed38SChristoph Hellwig __le32 reserved_4; /*14h */ 1703c4a3e0a5SBagalkote, Sreenivas 17049ab9ed38SChristoph Hellwig __le32 abort_context; /*18h */ 17059ab9ed38SChristoph Hellwig __le32 pad_1; /*1Ch */ 1706c4a3e0a5SBagalkote, Sreenivas 17079ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_lo; /*20h */ 17089ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_hi; /*24h */ 1709c4a3e0a5SBagalkote, Sreenivas 17109ab9ed38SChristoph Hellwig __le32 reserved_5[6]; /*28h */ 1711c4a3e0a5SBagalkote, Sreenivas 1712c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1713c4a3e0a5SBagalkote, Sreenivas 1714c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame { 1715c4a3e0a5SBagalkote, Sreenivas 1716c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1717c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1718c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1719c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */ 1720c4a3e0a5SBagalkote, Sreenivas 1721c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */ 1722c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1723c4a3e0a5SBagalkote, Sreenivas 17249ab9ed38SChristoph Hellwig __le32 context; /*08h */ 17259ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1726c4a3e0a5SBagalkote, Sreenivas 17279ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 17289ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1729c4a3e0a5SBagalkote, Sreenivas 17309ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 17319ab9ed38SChristoph Hellwig __le64 sas_addr; /*18h */ 1732c4a3e0a5SBagalkote, Sreenivas 1733c4a3e0a5SBagalkote, Sreenivas union { 1734c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1735c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1736c4a3e0a5SBagalkote, Sreenivas } sgl; 1737c4a3e0a5SBagalkote, Sreenivas 1738c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1739c4a3e0a5SBagalkote, Sreenivas 1740c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame { 1741c4a3e0a5SBagalkote, Sreenivas 1742c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */ 1743c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */ 1744c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */ 1745c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */ 1746c4a3e0a5SBagalkote, Sreenivas 1747c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */ 1748c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */ 1749c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */ 1750c4a3e0a5SBagalkote, Sreenivas 17519ab9ed38SChristoph Hellwig __le32 context; /*08h */ 17529ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */ 1753c4a3e0a5SBagalkote, Sreenivas 17549ab9ed38SChristoph Hellwig __le16 flags; /*10h */ 17559ab9ed38SChristoph Hellwig __le16 timeout; /*12h */ 1756c4a3e0a5SBagalkote, Sreenivas 17579ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */ 1758c4a3e0a5SBagalkote, Sreenivas 17599ab9ed38SChristoph Hellwig __le16 fis[10]; /*18h */ 17609ab9ed38SChristoph Hellwig __le32 stp_flags; 1761c4a3e0a5SBagalkote, Sreenivas 1762c4a3e0a5SBagalkote, Sreenivas union { 1763c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1764c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1765c4a3e0a5SBagalkote, Sreenivas } sgl; 1766c4a3e0a5SBagalkote, Sreenivas 1767c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1768c4a3e0a5SBagalkote, Sreenivas 1769c4a3e0a5SBagalkote, Sreenivas union megasas_frame { 1770c4a3e0a5SBagalkote, Sreenivas 1771c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 1772c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init; 1773c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io; 1774c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru; 1775c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd; 1776c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort; 1777c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp; 1778c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp; 1779c4a3e0a5SBagalkote, Sreenivas 1780c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64]; 1781c4a3e0a5SBagalkote, Sreenivas }; 1782c4a3e0a5SBagalkote, Sreenivas 178318365b13SSumit Saxena /** 178418365b13SSumit Saxena * struct MR_PRIV_DEVICE - sdev private hostdata 178518365b13SSumit Saxena * @is_tm_capable: firmware managed tm_capable flag 178618365b13SSumit Saxena * @tm_busy: TM request is in progress 178718365b13SSumit Saxena */ 178818365b13SSumit Saxena struct MR_PRIV_DEVICE { 178918365b13SSumit Saxena bool is_tm_capable; 179018365b13SSumit Saxena bool tm_busy; 179118365b13SSumit Saxena }; 1792c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd; 1793c4a3e0a5SBagalkote, Sreenivas 1794c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale { 1795c4a3e0a5SBagalkote, Sreenivas 1796c4a3e0a5SBagalkote, Sreenivas struct { 1797be26374bSSumit.Saxena@lsi.com #ifndef __BIG_ENDIAN_BITFIELD 1798c4a3e0a5SBagalkote, Sreenivas u16 locale; 1799c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1800c4a3e0a5SBagalkote, Sreenivas s8 class; 1801be26374bSSumit.Saxena@lsi.com #else 1802be26374bSSumit.Saxena@lsi.com s8 class; 1803be26374bSSumit.Saxena@lsi.com u8 reserved; 1804be26374bSSumit.Saxena@lsi.com u16 locale; 1805be26374bSSumit.Saxena@lsi.com #endif 1806c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members; 1807c4a3e0a5SBagalkote, Sreenivas 1808c4a3e0a5SBagalkote, Sreenivas u32 word; 1809c4a3e0a5SBagalkote, Sreenivas 1810c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1811c4a3e0a5SBagalkote, Sreenivas 1812c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info { 18139ab9ed38SChristoph Hellwig __le32 newest_seq_num; 18149ab9ed38SChristoph Hellwig __le32 oldest_seq_num; 18159ab9ed38SChristoph Hellwig __le32 clear_seq_num; 18169ab9ed38SChristoph Hellwig __le32 shutdown_seq_num; 18179ab9ed38SChristoph Hellwig __le32 boot_seq_num; 1818c4a3e0a5SBagalkote, Sreenivas 1819c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1820c4a3e0a5SBagalkote, Sreenivas 1821c4a3e0a5SBagalkote, Sreenivas struct megasas_progress { 1822c4a3e0a5SBagalkote, Sreenivas 18239ab9ed38SChristoph Hellwig __le16 progress; 18249ab9ed38SChristoph Hellwig __le16 elapsed_seconds; 1825c4a3e0a5SBagalkote, Sreenivas 1826c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1827c4a3e0a5SBagalkote, Sreenivas 1828c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld { 1829c4a3e0a5SBagalkote, Sreenivas 1830c4a3e0a5SBagalkote, Sreenivas u16 target_id; 1831c4a3e0a5SBagalkote, Sreenivas u8 ld_index; 1832c4a3e0a5SBagalkote, Sreenivas u8 reserved; 1833c4a3e0a5SBagalkote, Sreenivas 1834c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1835c4a3e0a5SBagalkote, Sreenivas 1836c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd { 1837c4a3e0a5SBagalkote, Sreenivas u16 device_id; 1838c4a3e0a5SBagalkote, Sreenivas u8 encl_index; 1839c4a3e0a5SBagalkote, Sreenivas u8 slot_number; 1840c4a3e0a5SBagalkote, Sreenivas 1841c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1842c4a3e0a5SBagalkote, Sreenivas 1843c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail { 1844c4a3e0a5SBagalkote, Sreenivas 18459ab9ed38SChristoph Hellwig __le32 seq_num; 18469ab9ed38SChristoph Hellwig __le32 time_stamp; 18479ab9ed38SChristoph Hellwig __le32 code; 1848c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl; 1849c4a3e0a5SBagalkote, Sreenivas u8 arg_type; 1850c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15]; 1851c4a3e0a5SBagalkote, Sreenivas 1852c4a3e0a5SBagalkote, Sreenivas union { 1853c4a3e0a5SBagalkote, Sreenivas struct { 1854c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1855c4a3e0a5SBagalkote, Sreenivas u8 cdb_length; 1856c4a3e0a5SBagalkote, Sreenivas u8 sense_length; 1857c4a3e0a5SBagalkote, Sreenivas u8 reserved[2]; 1858c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; 1859c4a3e0a5SBagalkote, Sreenivas u8 sense[64]; 1860c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense; 1861c4a3e0a5SBagalkote, Sreenivas 1862c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1863c4a3e0a5SBagalkote, Sreenivas 1864c4a3e0a5SBagalkote, Sreenivas struct { 1865c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 18669ab9ed38SChristoph Hellwig __le64 count; 1867c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count; 1868c4a3e0a5SBagalkote, Sreenivas 1869c4a3e0a5SBagalkote, Sreenivas struct { 18709ab9ed38SChristoph Hellwig __le64 lba; 1871c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1872c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba; 1873c4a3e0a5SBagalkote, Sreenivas 1874c4a3e0a5SBagalkote, Sreenivas struct { 1875c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 18769ab9ed38SChristoph Hellwig __le32 prevOwner; 18779ab9ed38SChristoph Hellwig __le32 newOwner; 1878c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner; 1879c4a3e0a5SBagalkote, Sreenivas 1880c4a3e0a5SBagalkote, Sreenivas struct { 1881c4a3e0a5SBagalkote, Sreenivas u64 ld_lba; 1882c4a3e0a5SBagalkote, Sreenivas u64 pd_lba; 1883c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1884c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1885c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba; 1886c4a3e0a5SBagalkote, Sreenivas 1887c4a3e0a5SBagalkote, Sreenivas struct { 1888c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1889c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1890c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog; 1891c4a3e0a5SBagalkote, Sreenivas 1892c4a3e0a5SBagalkote, Sreenivas struct { 1893c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1894c4a3e0a5SBagalkote, Sreenivas u32 prev_state; 1895c4a3e0a5SBagalkote, Sreenivas u32 new_state; 1896c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state; 1897c4a3e0a5SBagalkote, Sreenivas 1898c4a3e0a5SBagalkote, Sreenivas struct { 1899c4a3e0a5SBagalkote, Sreenivas u64 strip; 1900c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1901c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip; 1902c4a3e0a5SBagalkote, Sreenivas 1903c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1904c4a3e0a5SBagalkote, Sreenivas 1905c4a3e0a5SBagalkote, Sreenivas struct { 1906c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1907c4a3e0a5SBagalkote, Sreenivas u32 err; 1908c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err; 1909c4a3e0a5SBagalkote, Sreenivas 1910c4a3e0a5SBagalkote, Sreenivas struct { 1911c4a3e0a5SBagalkote, Sreenivas u64 lba; 1912c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1913c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba; 1914c4a3e0a5SBagalkote, Sreenivas 1915c4a3e0a5SBagalkote, Sreenivas struct { 1916c4a3e0a5SBagalkote, Sreenivas u64 lba; 1917c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1918c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld; 1919c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld; 1920c4a3e0a5SBagalkote, Sreenivas 1921c4a3e0a5SBagalkote, Sreenivas struct { 1922c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1923c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog; 1924c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog; 1925c4a3e0a5SBagalkote, Sreenivas 1926c4a3e0a5SBagalkote, Sreenivas struct { 1927c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd; 1928c4a3e0a5SBagalkote, Sreenivas u32 prevState; 1929c4a3e0a5SBagalkote, Sreenivas u32 newState; 1930c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state; 1931c4a3e0a5SBagalkote, Sreenivas 1932c4a3e0a5SBagalkote, Sreenivas struct { 1933c4a3e0a5SBagalkote, Sreenivas u16 vendorId; 19349ab9ed38SChristoph Hellwig __le16 deviceId; 1935c4a3e0a5SBagalkote, Sreenivas u16 subVendorId; 1936c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId; 1937c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci; 1938c4a3e0a5SBagalkote, Sreenivas 1939c4a3e0a5SBagalkote, Sreenivas u32 rate; 1940c4a3e0a5SBagalkote, Sreenivas char str[96]; 1941c4a3e0a5SBagalkote, Sreenivas 1942c4a3e0a5SBagalkote, Sreenivas struct { 1943c4a3e0a5SBagalkote, Sreenivas u32 rtc; 1944c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds; 1945c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time; 1946c4a3e0a5SBagalkote, Sreenivas 1947c4a3e0a5SBagalkote, Sreenivas struct { 1948c4a3e0a5SBagalkote, Sreenivas u32 ecar; 1949c4a3e0a5SBagalkote, Sreenivas u32 elog; 1950c4a3e0a5SBagalkote, Sreenivas char str[64]; 1951c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc; 1952c4a3e0a5SBagalkote, Sreenivas 1953c4a3e0a5SBagalkote, Sreenivas u8 b[96]; 19549ab9ed38SChristoph Hellwig __le16 s[48]; 19559ab9ed38SChristoph Hellwig __le32 w[24]; 19569ab9ed38SChristoph Hellwig __le64 d[12]; 1957c4a3e0a5SBagalkote, Sreenivas } args; 1958c4a3e0a5SBagalkote, Sreenivas 1959c4a3e0a5SBagalkote, Sreenivas char description[128]; 1960c4a3e0a5SBagalkote, Sreenivas 1961c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 1962c4a3e0a5SBagalkote, Sreenivas 19637e8a75f4SYang, Bo struct megasas_aen_event { 1964c1d390d8SXiaotian Feng struct delayed_work hotplug_work; 19657e8a75f4SYang, Bo struct megasas_instance *instance; 19667e8a75f4SYang, Bo }; 19677e8a75f4SYang, Bo 1968c8e858feSadam radford struct megasas_irq_context { 1969c8e858feSadam radford struct megasas_instance *instance; 1970c8e858feSadam radford u32 MSIxIndex; 1971c8e858feSadam radford }; 1972c8e858feSadam radford 19735765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO { 19745765c5b8SSumit.Saxena@avagotech.com u8 infoVersion; 19755765c5b8SSumit.Saxena@avagotech.com u8 systemIdLength; 19765765c5b8SSumit.Saxena@avagotech.com u16 reserved0; 19775765c5b8SSumit.Saxena@avagotech.com u8 systemId[64]; 19785765c5b8SSumit.Saxena@avagotech.com u8 reserved[1980]; 19795765c5b8SSumit.Saxena@avagotech.com }; 19805765c5b8SSumit.Saxena@avagotech.com 19812216c305SSumit Saxena enum MR_PD_TYPE { 19822216c305SSumit Saxena UNKNOWN_DRIVE = 0, 19832216c305SSumit Saxena PARALLEL_SCSI = 1, 19842216c305SSumit Saxena SAS_PD = 2, 19852216c305SSumit Saxena SATA_PD = 3, 19862216c305SSumit Saxena FC_PD = 4, 19872216c305SSumit Saxena }; 19882216c305SSumit Saxena 19892216c305SSumit Saxena /* JBOD Queue depth definitions */ 19902216c305SSumit Saxena #define MEGASAS_SATA_QD 32 19912216c305SSumit Saxena #define MEGASAS_SAS_QD 64 19922216c305SSumit Saxena #define MEGASAS_DEFAULT_PD_QD 64 19932216c305SSumit Saxena 1994c4a3e0a5SBagalkote, Sreenivas struct megasas_instance { 1995c4a3e0a5SBagalkote, Sreenivas 19969ab9ed38SChristoph Hellwig __le32 *producer; 1997c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h; 19989ab9ed38SChristoph Hellwig __le32 *consumer; 1999c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h; 20005765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO *system_info_buf; 20015765c5b8SSumit.Saxena@avagotech.com dma_addr_t system_info_h; 2002229fe47cSadam radford struct MR_LD_VF_AFFILIATION *vf_affiliation; 2003229fe47cSadam radford dma_addr_t vf_affiliation_h; 2004229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2005229fe47cSadam radford dma_addr_t vf_affiliation_111_h; 2006229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2007229fe47cSadam radford dma_addr_t hb_host_mem_h; 20082216c305SSumit Saxena struct MR_PD_INFO *pd_info; 20092216c305SSumit Saxena dma_addr_t pd_info_h; 2010c4a3e0a5SBagalkote, Sreenivas 20119ab9ed38SChristoph Hellwig __le32 *reply_queue; 2012c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h; 2013c4a3e0a5SBagalkote, Sreenivas 2014fc62b3fcSSumit.Saxena@avagotech.com u32 *crash_dump_buf; 2015fc62b3fcSSumit.Saxena@avagotech.com dma_addr_t crash_dump_h; 2016fc62b3fcSSumit.Saxena@avagotech.com void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2017fc62b3fcSSumit.Saxena@avagotech.com u32 crash_buf_pages; 2018fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_size; 2019fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_state; 2020fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_offset; 2021fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_index; 2022fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_alloc; 2023fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_fw_support; 2024fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_drv_support; 2025fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_app_support; 20267497cde8SSumit.Saxena@avagotech.com u32 secure_jbod_support; 20273761cb4cSsumit.saxena@avagotech.com bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2028fc62b3fcSSumit.Saxena@avagotech.com spinlock_t crashdump_lock; 2029fc62b3fcSSumit.Saxena@avagotech.com 2030c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set; 20318a232bb3SChristoph Hellwig u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 203281e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2033999ece0aSSumit.Saxena@lsi.com struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2034bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2035c4a3e0a5SBagalkote, Sreenivas s8 init_id; 2036c4a3e0a5SBagalkote, Sreenivas 2037c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge; 2038c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds; 20399c915a8cSadam radford u16 max_mfi_cmds; 2040ae09a6c1SSumit.Saxena@avagotech.com u16 max_scsi_cmds; 2041c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req; 20427e8a75f4SYang, Bo struct megasas_aen_event *ev; 2043c4a3e0a5SBagalkote, Sreenivas 2044c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list; 2045c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool; 204639a98554Sbo yang /* used to sync fire the cmd to fw */ 204790dc9d98SSumit.Saxena@avagotech.com spinlock_t mfi_pool_lock; 204839a98554Sbo yang /* used to sync fire the cmd to fw */ 204939a98554Sbo yang spinlock_t hba_lock; 20507343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */ 20517343eb65Sbo yang spinlock_t completion_lock; 2052c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool; 2053c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool; 2054c4a3e0a5SBagalkote, Sreenivas 2055c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail; 2056c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h; 2057c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd; 20582216c305SSumit Saxena struct mutex hba_mutex; 2059c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem; 2060c4a3e0a5SBagalkote, Sreenivas 2061c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host; 2062c4a3e0a5SBagalkote, Sreenivas 2063c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q; 2064c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q; 2065c4a3e0a5SBagalkote, Sreenivas 2066c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev; 2067c4a3e0a5SBagalkote, Sreenivas u32 unique_id; 206839a98554Sbo yang u32 fw_support_ieee; 2069c4a3e0a5SBagalkote, Sreenivas 2070e4a082c7SSumant Patro atomic_t fw_outstanding; 207139a98554Sbo yang atomic_t fw_reset_no_pci_access; 20721341c939SSumant Patro 20731341c939SSumant Patro struct megasas_instance_template *instancet; 20745d018ad0SSumant Patro struct tasklet_struct isr_tasklet; 207539a98554Sbo yang struct work_struct work_init; 2076fc62b3fcSSumit.Saxena@avagotech.com struct work_struct crash_init; 207705e9ebbeSSumant Patro 207805e9ebbeSSumant Patro u8 flag; 2079c3518837SYang, Bo u8 unload; 2080f4c9a131SYang, Bo u8 flag_ieee; 208139a98554Sbo yang u8 issuepend_done; 208239a98554Sbo yang u8 disableOnlineCtrlReset; 2083bc93d425SSumit.Saxena@lsi.com u8 UnevenSpanSupport; 208451087a86SSumit.Saxena@avagotech.com 208551087a86SSumit.Saxena@avagotech.com u8 supportmax256vd; 2086aed335eeSSumit Saxena u8 allow_fw_scan; 208751087a86SSumit.Saxena@avagotech.com u16 fw_supported_vd_count; 208851087a86SSumit.Saxena@avagotech.com u16 fw_supported_pd_count; 208951087a86SSumit.Saxena@avagotech.com 209051087a86SSumit.Saxena@avagotech.com u16 drv_supported_vd_count; 209151087a86SSumit.Saxena@avagotech.com u16 drv_supported_pd_count; 209251087a86SSumit.Saxena@avagotech.com 209339a98554Sbo yang u8 adprecovery; 209405e9ebbeSSumant Patro unsigned long last_time; 209539a98554Sbo yang u32 mfiStatus; 209639a98554Sbo yang u32 last_seq_num; 2097ad84db2eSbo yang 209839a98554Sbo yang struct list_head internal_reset_pending_q; 209980d9da98Sadam radford 210025985edcSLucas De Marchi /* Ptr to hba specific information */ 21019c915a8cSadam radford void *ctrl_context; 210251087a86SSumit.Saxena@avagotech.com u32 ctrl_context_pages; 210351087a86SSumit.Saxena@avagotech.com struct megasas_ctrl_info *ctrl_info; 2104c8e858feSadam radford unsigned int msix_vectors; 2105c8e858feSadam radford struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 2106c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 21079c915a8cSadam radford u64 map_id; 21083761cb4cSsumit.saxena@avagotech.com u64 pd_seq_map_id; 21099c915a8cSadam radford struct megasas_cmd *map_update_cmd; 21103761cb4cSsumit.saxena@avagotech.com struct megasas_cmd *jbod_seq_cmd; 2111b6d5d880Sadam radford unsigned long bar; 21129c915a8cSadam radford long reset_flags; 21139c915a8cSadam radford struct mutex reset_mutex; 2114229fe47cSadam radford struct timer_list sriov_heartbeat_timer; 2115229fe47cSadam radford char skip_heartbeat_timer_del; 2116229fe47cSadam radford u8 requestorId; 2117229fe47cSadam radford char PlasmaFW111; 2118229fe47cSadam radford char mpio; 2119ae09a6c1SSumit.Saxena@avagotech.com u16 throttlequeuedepth; 2120d46a3ad6SSumit.Saxena@lsi.com u8 mask_interrupts; 2121bd5f9484Ssumit.saxena@avagotech.com u16 max_chain_frame_sz; 2122404a8a1aSSumit.Saxena@lsi.com u8 is_imr; 2123179ac142SSumit Saxena u8 is_rdpq; 21245765c5b8SSumit.Saxena@avagotech.com bool dev_handle; 212539a98554Sbo yang }; 2126229fe47cSadam radford struct MR_LD_VF_MAP { 2127229fe47cSadam radford u32 size; 2128229fe47cSadam radford union MR_LD_REF ref; 2129229fe47cSadam radford u8 ldVfCount; 2130229fe47cSadam radford u8 reserved[6]; 2131229fe47cSadam radford u8 policy[1]; 2132229fe47cSadam radford }; 2133229fe47cSadam radford 2134229fe47cSadam radford struct MR_LD_VF_AFFILIATION { 2135229fe47cSadam radford u32 size; 2136229fe47cSadam radford u8 ldCount; 2137229fe47cSadam radford u8 vfCount; 2138229fe47cSadam radford u8 thisVf; 2139229fe47cSadam radford u8 reserved[9]; 2140229fe47cSadam radford struct MR_LD_VF_MAP map[1]; 2141229fe47cSadam radford }; 2142229fe47cSadam radford 2143229fe47cSadam radford /* Plasma 1.11 FW backward compatibility structures */ 2144229fe47cSadam radford #define IOV_111_OFFSET 0x7CE 2145229fe47cSadam radford #define MAX_VIRTUAL_FUNCTIONS 8 21464cbfea88SAdam Radford #define MR_LD_ACCESS_HIDDEN 15 2147229fe47cSadam radford 2148229fe47cSadam radford struct IOV_111 { 2149229fe47cSadam radford u8 maxVFsSupported; 2150229fe47cSadam radford u8 numVFsEnabled; 2151229fe47cSadam radford u8 requestorId; 2152229fe47cSadam radford u8 reserved[5]; 2153229fe47cSadam radford }; 2154229fe47cSadam radford 2155229fe47cSadam radford struct MR_LD_VF_MAP_111 { 2156229fe47cSadam radford u8 targetId; 2157229fe47cSadam radford u8 reserved[3]; 2158229fe47cSadam radford u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2159229fe47cSadam radford }; 2160229fe47cSadam radford 2161229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 { 2162229fe47cSadam radford u8 vdCount; 2163229fe47cSadam radford u8 vfCount; 2164229fe47cSadam radford u8 thisVf; 2165229fe47cSadam radford u8 reserved[5]; 2166229fe47cSadam radford struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2167229fe47cSadam radford }; 2168229fe47cSadam radford 2169229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM { 2170229fe47cSadam radford struct { 2171229fe47cSadam radford u32 fwCounter; /* Firmware heart beat counter */ 2172229fe47cSadam radford struct { 2173229fe47cSadam radford u32 debugmode:1; /* 1=Firmware is in debug mode. 2174229fe47cSadam radford Heart beat will not be updated. */ 2175229fe47cSadam radford u32 reserved:31; 2176229fe47cSadam radford } debug; 2177229fe47cSadam radford u32 reserved_fw[6]; 2178229fe47cSadam radford u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2179229fe47cSadam radford u32 reserved_driver[7]; 2180229fe47cSadam radford } HB; 2181229fe47cSadam radford u8 pad[0x400-0x40]; 2182229fe47cSadam radford }; 218339a98554Sbo yang 218439a98554Sbo yang enum { 218539a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0, 218639a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1, 218739a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 218839a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 218939a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4, 2190229fe47cSadam radford MEGASAS_ADPRESET_SM_POLLING = 5, 219139a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2192c4a3e0a5SBagalkote, Sreenivas }; 2193c4a3e0a5SBagalkote, Sreenivas 21940c79e681SYang, Bo struct megasas_instance_template { 21950c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 21960c79e681SYang, Bo u32, struct megasas_register_set __iomem *); 21970c79e681SYang, Bo 2198d46a3ad6SSumit.Saxena@lsi.com void (*enable_intr)(struct megasas_instance *); 2199d46a3ad6SSumit.Saxena@lsi.com void (*disable_intr)(struct megasas_instance *); 22000c79e681SYang, Bo 22010c79e681SYang, Bo int (*clear_intr)(struct megasas_register_set __iomem *); 22020c79e681SYang, Bo 22030c79e681SYang, Bo u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 220439a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \ 220539a98554Sbo yang struct megasas_register_set __iomem *); 220639a98554Sbo yang int (*check_reset)(struct megasas_instance *, \ 220739a98554Sbo yang struct megasas_register_set __iomem *); 2208cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp); 2209cd50ba8eSadam radford void (*tasklet)(unsigned long); 2210cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *); 2211cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *, 2212cd50ba8eSadam radford struct scsi_cmnd *); 22136d40afbcSSumit Saxena int (*issue_dcmd)(struct megasas_instance *instance, 2214cd50ba8eSadam radford struct megasas_cmd *cmd); 22150c79e681SYang, Bo }; 22160c79e681SYang, Bo 2217c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IS_LOGICAL(scp) \ 2218c4a3e0a5SBagalkote, Sreenivas (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 2219c4a3e0a5SBagalkote, Sreenivas 22204a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_DEV_INDEX(scp) \ 22214a5c814dSSumit.Saxena@avagotech.com (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 22224a5c814dSSumit.Saxena@avagotech.com scp->device->id) 22234a5c814dSSumit.Saxena@avagotech.com 22244a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_PD_INDEX(scp) \ 22254a5c814dSSumit.Saxena@avagotech.com ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 22264a5c814dSSumit.Saxena@avagotech.com scp->device->id) 2227c4a3e0a5SBagalkote, Sreenivas 2228c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd { 2229c4a3e0a5SBagalkote, Sreenivas 2230c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame; 2231c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr; 2232c4a3e0a5SBagalkote, Sreenivas u8 *sense; 2233c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr; 2234c4a3e0a5SBagalkote, Sreenivas 2235c4a3e0a5SBagalkote, Sreenivas u32 index; 2236c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd; 22372be2a988SSumit.Saxena@avagotech.com u8 cmd_status_drv; 223839a98554Sbo yang u8 abort_aen; 223939a98554Sbo yang u8 retry_for_fw_reset; 224039a98554Sbo yang 2241c4a3e0a5SBagalkote, Sreenivas 2242c4a3e0a5SBagalkote, Sreenivas struct list_head list; 2243c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd; 22444026e9aaSSumit.Saxena@avagotech.com u8 flags; 224590dc9d98SSumit.Saxena@avagotech.com 2246c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance; 22479c915a8cSadam radford union { 22489c915a8cSadam radford struct { 22499c915a8cSadam radford u16 smid; 22509c915a8cSadam radford u16 resvd; 22519c915a8cSadam radford } context; 2252c4a3e0a5SBagalkote, Sreenivas u32 frame_count; 2253c4a3e0a5SBagalkote, Sreenivas }; 22549c915a8cSadam radford }; 2255c4a3e0a5SBagalkote, Sreenivas 2256c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024 2257c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16 2258c4a3e0a5SBagalkote, Sreenivas 2259c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket { 2260c4a3e0a5SBagalkote, Sreenivas 2261c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2262c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2263c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 2264c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 2265c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 2266c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 2267c4a3e0a5SBagalkote, Sreenivas union { 2268c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 2269c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 2270c4a3e0a5SBagalkote, Sreenivas } frame; 2271c4a3e0a5SBagalkote, Sreenivas 2272c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE]; 2273c4a3e0a5SBagalkote, Sreenivas 2274c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2275c4a3e0a5SBagalkote, Sreenivas 2276c4a3e0a5SBagalkote, Sreenivas struct megasas_aen { 2277c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2278c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2279c4a3e0a5SBagalkote, Sreenivas u32 seq_num; 2280c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word; 2281c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2282c4a3e0a5SBagalkote, Sreenivas 2283c4a3e0a5SBagalkote, Sreenivas #ifdef CONFIG_COMPAT 2284c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket { 2285c4a3e0a5SBagalkote, Sreenivas u16 host_no; 2286c4a3e0a5SBagalkote, Sreenivas u16 __pad1; 2287c4a3e0a5SBagalkote, Sreenivas u32 sgl_off; 2288c4a3e0a5SBagalkote, Sreenivas u32 sge_count; 2289c4a3e0a5SBagalkote, Sreenivas u32 sense_off; 2290c4a3e0a5SBagalkote, Sreenivas u32 sense_len; 2291c4a3e0a5SBagalkote, Sreenivas union { 2292c4a3e0a5SBagalkote, Sreenivas u8 raw[128]; 2293c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr; 2294c4a3e0a5SBagalkote, Sreenivas } frame; 2295c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE]; 2296c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)); 2297c4a3e0a5SBagalkote, Sreenivas 22980e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2299c4a3e0a5SBagalkote, Sreenivas #endif 2300c4a3e0a5SBagalkote, Sreenivas 2301cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2302c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2303c4a3e0a5SBagalkote, Sreenivas 2304c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info { 2305c4a3e0a5SBagalkote, Sreenivas 2306c4a3e0a5SBagalkote, Sreenivas u16 count; 2307c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2308c4a3e0a5SBagalkote, Sreenivas int max_index; 2309c4a3e0a5SBagalkote, Sreenivas }; 2310c4a3e0a5SBagalkote, Sreenivas 23116d40afbcSSumit Saxena enum MEGASAS_OCR_CAUSE { 23126d40afbcSSumit Saxena FW_FAULT_OCR = 0, 23136d40afbcSSumit Saxena SCSIIO_TIMEOUT_OCR = 1, 23146d40afbcSSumit Saxena MFI_IO_TIMEOUT_OCR = 2, 23156d40afbcSSumit Saxena }; 23166d40afbcSSumit Saxena 23176d40afbcSSumit Saxena enum DCMD_RETURN_STATUS { 23186d40afbcSSumit Saxena DCMD_SUCCESS = 0, 23196d40afbcSSumit Saxena DCMD_TIMEOUT = 1, 23206d40afbcSSumit Saxena DCMD_FAILED = 2, 23216d40afbcSSumit Saxena DCMD_NOT_FIRED = 3, 23226d40afbcSSumit Saxena }; 23236d40afbcSSumit Saxena 232421c9e160Sadam radford u8 232521c9e160Sadam radford MR_BuildRaidContext(struct megasas_instance *instance, 232621c9e160Sadam radford struct IO_REQUEST_INFO *io_info, 232721c9e160Sadam radford struct RAID_CONTEXT *pRAID_Context, 232851087a86SSumit.Saxena@avagotech.com struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 232951087a86SSumit.Saxena@avagotech.com u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 233051087a86SSumit.Saxena@avagotech.com struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 233151087a86SSumit.Saxena@avagotech.com u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 233251087a86SSumit.Saxena@avagotech.com u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 23339ab9ed38SChristoph Hellwig __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 233451087a86SSumit.Saxena@avagotech.com u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 233521c9e160Sadam radford 23369ab9ed38SChristoph Hellwig __le16 get_updated_dev_handle(struct megasas_instance *instance, 2337d2552ebeSSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info); 233851087a86SSumit.Saxena@avagotech.com void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 233951087a86SSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo); 2340d009b576SSumit.Saxena@avagotech.com int megasas_get_ctrl_info(struct megasas_instance *instance); 23413761cb4cSsumit.saxena@avagotech.com /* PD sequence */ 23423761cb4cSsumit.saxena@avagotech.com int 23433761cb4cSsumit.saxena@avagotech.com megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2344fc62b3fcSSumit.Saxena@avagotech.com int megasas_set_crash_dump_params(struct megasas_instance *instance, 2345fc62b3fcSSumit.Saxena@avagotech.com u8 crash_buf_state); 2346fc62b3fcSSumit.Saxena@avagotech.com void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2347fc62b3fcSSumit.Saxena@avagotech.com void megasas_fusion_crash_dump_wq(struct work_struct *work); 234851087a86SSumit.Saxena@avagotech.com 234990dc9d98SSumit.Saxena@avagotech.com void megasas_return_cmd_fusion(struct megasas_instance *instance, 235090dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd_fusion *cmd); 235190dc9d98SSumit.Saxena@avagotech.com int megasas_issue_blocked_cmd(struct megasas_instance *instance, 235290dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd, int timeout); 235390dc9d98SSumit.Saxena@avagotech.com void __megasas_return_cmd(struct megasas_instance *instance, 235490dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd); 235590dc9d98SSumit.Saxena@avagotech.com 235690dc9d98SSumit.Saxena@avagotech.com void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 235790dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 23587497cde8SSumit.Saxena@avagotech.com int megasas_cmd_type(struct scsi_cmnd *cmd); 23593761cb4cSsumit.saxena@avagotech.com void megasas_setup_jbod_map(struct megasas_instance *instance); 236090dc9d98SSumit.Saxena@avagotech.com 236118365b13SSumit Saxena void megasas_update_sdev_properties(struct scsi_device *sdev); 236218365b13SSumit Saxena int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 236318365b13SSumit Saxena int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 236418365b13SSumit Saxena int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2365c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */ 2366