11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2c4a3e0a5SBagalkote, Sreenivas /*
3c4a3e0a5SBagalkote, Sreenivas * Linux MegaRAID driver for SAS based RAID controllers
4c4a3e0a5SBagalkote, Sreenivas *
5e399065bSSumit.Saxena@avagotech.com * Copyright (c) 2003-2013 LSI Corporation
6365597cfSShivasharan S * Copyright (c) 2013-2016 Avago Technologies
7365597cfSShivasharan S * Copyright (c) 2016-2018 Broadcom Inc.
8c4a3e0a5SBagalkote, Sreenivas *
9c4a3e0a5SBagalkote, Sreenivas * FILE: megaraid_sas.h
103f1530c1Sadam radford *
11365597cfSShivasharan S * Authors: Broadcom Inc.
12365597cfSShivasharan S * Kashyap Desai <kashyap.desai@broadcom.com>
13365597cfSShivasharan S * Sumit Saxena <sumit.saxena@broadcom.com>
143f1530c1Sadam radford *
15365597cfSShivasharan S * Send feedback to: megaraidlinux.pdl@broadcom.com
16c4a3e0a5SBagalkote, Sreenivas */
17c4a3e0a5SBagalkote, Sreenivas
18c4a3e0a5SBagalkote, Sreenivas #ifndef LSI_MEGARAID_SAS_H
19c4a3e0a5SBagalkote, Sreenivas #define LSI_MEGARAID_SAS_H
20c4a3e0a5SBagalkote, Sreenivas
2196e77a27SBart Van Assche #include <scsi/scsi_cmnd.h>
2296e77a27SBart Van Assche
23a69b74d3SRandy Dunlap /*
24c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS Driver meta data
25c4a3e0a5SBagalkote, Sreenivas */
26a2033f9fSChandrakanth Patil #define MEGASAS_VERSION "07.725.01.00-rc1"
27a2033f9fSChandrakanth Patil #define MEGASAS_RELDATE "Mar 2, 2023"
280e98936cSSumant Patro
29ff7ca7fdSChandrakanth Patil #define MEGASAS_MSIX_NAME_LEN 32
30ff7ca7fdSChandrakanth Patil
310e98936cSSumant Patro /*
320e98936cSSumant Patro * Device IDs
330e98936cSSumant Patro */
340e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
35af7a5647Sbo yang #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
360e98936cSSumant Patro #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
376610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
386610a6b3SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
3987911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
4087911122SYang, Bo #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
419c915a8cSadam radford #define PCI_DEVICE_ID_LSI_FUSION 0x005b
42229fe47cSadam radford #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
4336807e67Sadam radford #define PCI_DEVICE_ID_LSI_INVADER 0x005d
4421d3c710SSumit.Saxena@lsi.com #define PCI_DEVICE_ID_LSI_FURY 0x005f
4590c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
4690c204bcSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
477364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
487364d34bSsumit.saxena@avagotech.com #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
4945f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
50754f1baeSShivasharan S #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
5145f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
5245f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
5345f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
5445f4f2ebSSasikumar Chandrasekaran #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
55469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
56469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
57469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
58469f72ddSShivasharan S #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
59dd807699SChandrakanth Patil #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
60dd807699SChandrakanth Patil #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
61dd807699SChandrakanth Patil #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
62dd807699SChandrakanth Patil #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
630e98936cSSumant Patro
64c4a3e0a5SBagalkote, Sreenivas /*
6539b72c3cSSumit.Saxena@lsi.com * Intel HBA SSDIDs
6639b72c3cSSumit.Saxena@lsi.com */
6739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
6839b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
6939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
7039b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
7139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
7239b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
737364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
7439b72c3cSSumit.Saxena@lsi.com
7539b72c3cSSumit.Saxena@lsi.com /*
7690c204bcSsumit.saxena@avagotech.com * Intruder HBA SSDIDs
7790c204bcSsumit.saxena@avagotech.com */
7890c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID1 0x9371
7990c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID2 0x9390
8090c204bcSsumit.saxena@avagotech.com #define MEGARAID_INTRUDER_SSDID3 0x9370
8190c204bcSsumit.saxena@avagotech.com
8290c204bcSsumit.saxena@avagotech.com /*
8339b72c3cSSumit.Saxena@lsi.com * Intel HBA branding
8439b72c3cSSumit.Saxena@lsi.com */
8539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC080_BRANDING \
8639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC080"
8739b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3DC040_BRANDING \
8839b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3DC040"
8939b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3SC008_BRANDING \
9039b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3SC008"
9139b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3MC044_BRANDING \
9239b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3MC044"
9339b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC080_BRANDING \
9439b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC080"
9539b72c3cSSumit.Saxena@lsi.com #define MEGARAID_INTEL_RS3WC040_BRANDING \
9639b72c3cSSumit.Saxena@lsi.com "Intel(R) RAID Controller RS3WC040"
977364d34bSsumit.saxena@avagotech.com #define MEGARAID_INTEL_RMS3BC160_BRANDING \
987364d34bSsumit.saxena@avagotech.com "Intel(R) Integrated RAID Module RMS3BC160"
9939b72c3cSSumit.Saxena@lsi.com
10039b72c3cSSumit.Saxena@lsi.com /*
101c4a3e0a5SBagalkote, Sreenivas * =====================================
102c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS MFI firmware definitions
103c4a3e0a5SBagalkote, Sreenivas * =====================================
104c4a3e0a5SBagalkote, Sreenivas */
105c4a3e0a5SBagalkote, Sreenivas
106c4a3e0a5SBagalkote, Sreenivas /*
107c4a3e0a5SBagalkote, Sreenivas * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
108c4a3e0a5SBagalkote, Sreenivas * protocol between the software and firmware. Commands are issued using
109c4a3e0a5SBagalkote, Sreenivas * "message frames"
110c4a3e0a5SBagalkote, Sreenivas */
111c4a3e0a5SBagalkote, Sreenivas
112a69b74d3SRandy Dunlap /*
113c4a3e0a5SBagalkote, Sreenivas * FW posts its state in upper 4 bits of outbound_msg_0 register
114c4a3e0a5SBagalkote, Sreenivas */
115c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_MASK 0xF0000000
116c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_UNDEFINED 0x00000000
117c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_BB_INIT 0x10000000
118c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT 0x40000000
119c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
120c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FW_INIT_2 0x70000000
121c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_DEVICE_SCAN 0x80000000
122e3bbff9fSSumant Patro #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
123c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FLUSH_CACHE 0xA0000000
124c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_READY 0xB0000000
125c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_OPERATIONAL 0xC0000000
126c4a3e0a5SBagalkote, Sreenivas #define MFI_STATE_FAULT 0xF0000000
127fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_FORCE_OCR 0x00000080
128fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_DMADONE 0x00000008
129fc62b3fcSSumit.Saxena@avagotech.com #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
13039a98554Sbo yang #define MFI_RESET_REQUIRED 0x00000001
1317e70e733Sadam radford #define MFI_RESET_ADAPTER 0x00000002
132c4a3e0a5SBagalkote, Sreenivas #define MEGAMFI_FRAME_SIZE 64
133c4a3e0a5SBagalkote, Sreenivas
134b6661342SShivasharan S #define MFI_STATE_FAULT_CODE 0x0FFF0000
135b6661342SShivasharan S #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
136a69b74d3SRandy Dunlap /*
137c4a3e0a5SBagalkote, Sreenivas * During FW init, clear pending cmds & reset state using inbound_msg_0
138c4a3e0a5SBagalkote, Sreenivas *
139c4a3e0a5SBagalkote, Sreenivas * ABORT : Abort all pending cmds
140c4a3e0a5SBagalkote, Sreenivas * READY : Move from OPERATIONAL to READY state; discard queue info
141c4a3e0a5SBagalkote, Sreenivas * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
142c4a3e0a5SBagalkote, Sreenivas * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
143e3bbff9fSSumant Patro * HOTPLUG : Resume from Hotplug
144e3bbff9fSSumant Patro * MFI_STOP_ADP : Send signal to FW to stop processing
145f0c21df6SShivasharan S * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
146c4a3e0a5SBagalkote, Sreenivas */
14739a98554Sbo yang #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
14839a98554Sbo yang #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
14939a98554Sbo yang #define DIAG_WRITE_ENABLE (0x00000080)
15039a98554Sbo yang #define DIAG_RESET_ADAPTER (0x00000004)
15139a98554Sbo yang
15239a98554Sbo yang #define MFI_ADP_RESET 0x00000040
153e3bbff9fSSumant Patro #define MFI_INIT_ABORT 0x00000001
154c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_READY 0x00000002
155c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_MFIMODE 0x00000004
156c4a3e0a5SBagalkote, Sreenivas #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
157e3bbff9fSSumant Patro #define MFI_INIT_HOTPLUG 0x00000010
158e3bbff9fSSumant Patro #define MFI_STOP_ADP 0x00000020
159e3bbff9fSSumant Patro #define MFI_RESET_FLAGS MFI_INIT_READY| \
160e3bbff9fSSumant Patro MFI_INIT_MFIMODE| \
161e3bbff9fSSumant Patro MFI_INIT_ABORT
162f0c21df6SShivasharan S #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
163179ac142SSumit Saxena #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
164c4a3e0a5SBagalkote, Sreenivas
165a69b74d3SRandy Dunlap /*
166c4a3e0a5SBagalkote, Sreenivas * MFI frame flags
167c4a3e0a5SBagalkote, Sreenivas */
168c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
169c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
170c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL32 0x0000
171c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SGL64 0x0002
172c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE32 0x0000
173c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_SENSE64 0x0004
174c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_NONE 0x0000
175c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_WRITE 0x0008
176c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_READ 0x0010
177c4a3e0a5SBagalkote, Sreenivas #define MFI_FRAME_DIR_BOTH 0x0018
178f4c9a131SYang, Bo #define MFI_FRAME_IEEE 0x0020
179c4a3e0a5SBagalkote, Sreenivas
1804026e9aaSSumit.Saxena@avagotech.com /* Driver internal */
1814026e9aaSSumit.Saxena@avagotech.com #define DRV_DCMD_POLLED_MODE 0x1
1826d40afbcSSumit Saxena #define DRV_DCMD_SKIP_REFIRE 0x2
1834026e9aaSSumit.Saxena@avagotech.com
184a69b74d3SRandy Dunlap /*
185c4a3e0a5SBagalkote, Sreenivas * Definition for cmd_status
186c4a3e0a5SBagalkote, Sreenivas */
187c4a3e0a5SBagalkote, Sreenivas #define MFI_CMD_STATUS_POLL_MODE 0xFF
188c4a3e0a5SBagalkote, Sreenivas
189a69b74d3SRandy Dunlap /*
190c4a3e0a5SBagalkote, Sreenivas * MFI command opcodes
191c4a3e0a5SBagalkote, Sreenivas */
19282add4e1SShivasharan S enum MFI_CMD_OP {
19382add4e1SShivasharan S MFI_CMD_INIT = 0x0,
19482add4e1SShivasharan S MFI_CMD_LD_READ = 0x1,
19582add4e1SShivasharan S MFI_CMD_LD_WRITE = 0x2,
19682add4e1SShivasharan S MFI_CMD_LD_SCSI_IO = 0x3,
19782add4e1SShivasharan S MFI_CMD_PD_SCSI_IO = 0x4,
19882add4e1SShivasharan S MFI_CMD_DCMD = 0x5,
19982add4e1SShivasharan S MFI_CMD_ABORT = 0x6,
20082add4e1SShivasharan S MFI_CMD_SMP = 0x7,
20182add4e1SShivasharan S MFI_CMD_STP = 0x8,
202f870bcbeSShivasharan S MFI_CMD_NVME = 0x9,
20358136856SChandrakanth Patil MFI_CMD_TOOLBOX = 0xa,
20482add4e1SShivasharan S MFI_CMD_OP_COUNT,
20582add4e1SShivasharan S MFI_CMD_INVALID = 0xff
20682add4e1SShivasharan S };
207c4a3e0a5SBagalkote, Sreenivas
208c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_GET_INFO 0x01010000
209bdc6fb8dSYang, Bo #define MR_DCMD_LD_GET_LIST 0x03010000
21021c9e160Sadam radford #define MR_DCMD_LD_LIST_QUERY 0x03010100
211c4a3e0a5SBagalkote, Sreenivas
212c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
213c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_CTRL_CACHE 0x01
214c4a3e0a5SBagalkote, Sreenivas #define MR_FLUSH_DISK_CACHE 0x02
215c4a3e0a5SBagalkote, Sreenivas
216c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
21731ea7088Sbo yang #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
218c4a3e0a5SBagalkote, Sreenivas #define MR_ENABLE_DRIVE_SPINDOWN 0x01
219c4a3e0a5SBagalkote, Sreenivas
220c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
221c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_GET 0x01040300
222c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
223c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
224c4a3e0a5SBagalkote, Sreenivas
225c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER 0x08000000
226c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
227c4a3e0a5SBagalkote, Sreenivas #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
22881e403ceSYang, Bo #define MR_DCMD_PD_LIST_QUERY 0x02010100
229c4a3e0a5SBagalkote, Sreenivas
230fc62b3fcSSumit.Saxena@avagotech.com #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
231fc62b3fcSSumit.Saxena@avagotech.com #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
2322216c305SSumit Saxena #define MR_DCMD_PD_GET_INFO 0x02020000
233fc62b3fcSSumit.Saxena@avagotech.com
234a69b74d3SRandy Dunlap /*
235bc93d425SSumit.Saxena@lsi.com * Global functions
236bc93d425SSumit.Saxena@lsi.com */
2375f19f7c8SShivasharan S extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
238bc93d425SSumit.Saxena@lsi.com
239bc93d425SSumit.Saxena@lsi.com
240bc93d425SSumit.Saxena@lsi.com /*
241c4a3e0a5SBagalkote, Sreenivas * MFI command completion codes
242c4a3e0a5SBagalkote, Sreenivas */
243c4a3e0a5SBagalkote, Sreenivas enum MFI_STAT {
244c4a3e0a5SBagalkote, Sreenivas MFI_STAT_OK = 0x00,
245c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_CMD = 0x01,
246c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_DCMD = 0x02,
247c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_PARAMETER = 0x03,
248c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
249c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
250c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
251c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_IN_USE = 0x07,
252c4a3e0a5SBagalkote, Sreenivas MFI_STAT_APP_NOT_INITIALIZED = 0x08,
253c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
254c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
255c4a3e0a5SBagalkote, Sreenivas MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
256c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
257c4a3e0a5SBagalkote, Sreenivas MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
258c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
259c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_BUSY = 0x0f,
260c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_ERROR = 0x10,
261c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_BAD = 0x11,
262c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
263c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_OPEN = 0x13,
264c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLASH_NOT_STARTED = 0x14,
265c4a3e0a5SBagalkote, Sreenivas MFI_STAT_FLUSH_FAILED = 0x15,
266c4a3e0a5SBagalkote, Sreenivas MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
267c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
268c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
269c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
270c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
271c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
272c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
273c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
274c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
275c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
276c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
277c4a3e0a5SBagalkote, Sreenivas MFI_STAT_MFC_HW_ERROR = 0x21,
278c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NO_HW_PRESENT = 0x22,
279c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_FOUND = 0x23,
280c4a3e0a5SBagalkote, Sreenivas MFI_STAT_NOT_IN_ENCL = 0x24,
281c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
282c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PD_TYPE_WRONG = 0x26,
283c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PR_DISABLED = 0x27,
284c4a3e0a5SBagalkote, Sreenivas MFI_STAT_ROW_INDEX_INVALID = 0x28,
285c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
286c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
287c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
288c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
289c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
290c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_IO_FAILED = 0x2e,
291c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
292c4a3e0a5SBagalkote, Sreenivas MFI_STAT_SHUTDOWN_FAILED = 0x30,
293c4a3e0a5SBagalkote, Sreenivas MFI_STAT_TIME_NOT_SET = 0x31,
294c4a3e0a5SBagalkote, Sreenivas MFI_STAT_WRONG_STATE = 0x32,
295c4a3e0a5SBagalkote, Sreenivas MFI_STAT_LD_OFFLINE = 0x33,
296c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
297c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
298c4a3e0a5SBagalkote, Sreenivas MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
299c4a3e0a5SBagalkote, Sreenivas MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
300c4a3e0a5SBagalkote, Sreenivas MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
30136807e67Sadam radford MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
302c4a3e0a5SBagalkote, Sreenivas
303c4a3e0a5SBagalkote, Sreenivas MFI_STAT_INVALID_STATUS = 0xFF
304c4a3e0a5SBagalkote, Sreenivas };
305c4a3e0a5SBagalkote, Sreenivas
306714f5177Ssumit.saxena@avagotech.com enum mfi_evt_class {
307714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEBUG = -2,
308714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_PROGRESS = -1,
309714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_INFO = 0,
310714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_WARNING = 1,
311714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_CRITICAL = 2,
312714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_FATAL = 3,
313714f5177Ssumit.saxena@avagotech.com MFI_EVT_CLASS_DEAD = 4
314714f5177Ssumit.saxena@avagotech.com };
315714f5177Ssumit.saxena@avagotech.com
316c4a3e0a5SBagalkote, Sreenivas /*
317fc62b3fcSSumit.Saxena@avagotech.com * Crash dump related defines
318fc62b3fcSSumit.Saxena@avagotech.com */
319fc62b3fcSSumit.Saxena@avagotech.com #define MAX_CRASH_DUMP_SIZE 512
320fc62b3fcSSumit.Saxena@avagotech.com #define CRASH_DMA_BUF_SIZE (1024 * 1024)
321fc62b3fcSSumit.Saxena@avagotech.com
322fc62b3fcSSumit.Saxena@avagotech.com enum MR_FW_CRASH_DUMP_STATE {
323fc62b3fcSSumit.Saxena@avagotech.com UNAVAILABLE = 0,
324fc62b3fcSSumit.Saxena@avagotech.com AVAILABLE = 1,
325fc62b3fcSSumit.Saxena@avagotech.com COPYING = 2,
326fc62b3fcSSumit.Saxena@avagotech.com COPIED = 3,
327fc62b3fcSSumit.Saxena@avagotech.com COPY_ERROR = 4,
328fc62b3fcSSumit.Saxena@avagotech.com };
329fc62b3fcSSumit.Saxena@avagotech.com
330fc62b3fcSSumit.Saxena@avagotech.com enum _MR_CRASH_BUF_STATUS {
331fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_OFF = 0,
332fc62b3fcSSumit.Saxena@avagotech.com MR_CRASH_BUF_TURN_ON = 1,
333fc62b3fcSSumit.Saxena@avagotech.com };
334fc62b3fcSSumit.Saxena@avagotech.com
335fc62b3fcSSumit.Saxena@avagotech.com /*
336c4a3e0a5SBagalkote, Sreenivas * Number of mailbox bytes in DCMD message frame
337c4a3e0a5SBagalkote, Sreenivas */
338c4a3e0a5SBagalkote, Sreenivas #define MFI_MBOX_SIZE 12
339c4a3e0a5SBagalkote, Sreenivas
340c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_CLASS {
341c4a3e0a5SBagalkote, Sreenivas
342c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEBUG = -2,
343c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_PROGRESS = -1,
344c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_INFO = 0,
345c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_WARNING = 1,
346c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_CRITICAL = 2,
347c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_FATAL = 3,
348c4a3e0a5SBagalkote, Sreenivas MR_EVT_CLASS_DEAD = 4,
349c4a3e0a5SBagalkote, Sreenivas
350c4a3e0a5SBagalkote, Sreenivas };
351c4a3e0a5SBagalkote, Sreenivas
352c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_LOCALE {
353c4a3e0a5SBagalkote, Sreenivas
354c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_LD = 0x0001,
355c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_PD = 0x0002,
356c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ENCL = 0x0004,
357c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_BBU = 0x0008,
358c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_SAS = 0x0010,
359c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CTRL = 0x0020,
360c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CONFIG = 0x0040,
361c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_CLUSTER = 0x0080,
362c4a3e0a5SBagalkote, Sreenivas MR_EVT_LOCALE_ALL = 0xffff,
363c4a3e0a5SBagalkote, Sreenivas
364c4a3e0a5SBagalkote, Sreenivas };
365c4a3e0a5SBagalkote, Sreenivas
366c4a3e0a5SBagalkote, Sreenivas enum MR_EVT_ARGS {
367c4a3e0a5SBagalkote, Sreenivas
368c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_NONE,
369c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_CDB_SENSE,
370c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD,
371c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_COUNT,
372c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA,
373c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_OWNER,
374c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_LBA_PD_LBA,
375c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_PROG,
376c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STATE,
377c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_LD_STRIP,
378c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD,
379c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_ERR,
380c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA,
381c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_LBA_LD,
382c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_PROG,
383c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PD_STATE,
384c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_PCI,
385c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_RATE,
386c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_STR,
387c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_TIME,
388c4a3e0a5SBagalkote, Sreenivas MR_EVT_ARGS_ECC,
38981e403ceSYang, Bo MR_EVT_ARGS_LD_PROP,
39081e403ceSYang, Bo MR_EVT_ARGS_PD_SPARE,
39181e403ceSYang, Bo MR_EVT_ARGS_PD_INDEX,
39281e403ceSYang, Bo MR_EVT_ARGS_DIAG_PASS,
39381e403ceSYang, Bo MR_EVT_ARGS_DIAG_FAIL,
39481e403ceSYang, Bo MR_EVT_ARGS_PD_LBA_LBA,
39581e403ceSYang, Bo MR_EVT_ARGS_PORT_PHY,
39681e403ceSYang, Bo MR_EVT_ARGS_PD_MISSING,
39781e403ceSYang, Bo MR_EVT_ARGS_PD_ADDRESS,
39881e403ceSYang, Bo MR_EVT_ARGS_BITMAP,
39981e403ceSYang, Bo MR_EVT_ARGS_CONNECTOR,
40081e403ceSYang, Bo MR_EVT_ARGS_PD_PD,
40181e403ceSYang, Bo MR_EVT_ARGS_PD_FRU,
40281e403ceSYang, Bo MR_EVT_ARGS_PD_PATHINFO,
40381e403ceSYang, Bo MR_EVT_ARGS_PD_POWER_STATE,
40481e403ceSYang, Bo MR_EVT_ARGS_GENERIC,
405c4a3e0a5SBagalkote, Sreenivas };
406c4a3e0a5SBagalkote, Sreenivas
407357ae967Ssumit.saxena@avagotech.com
408357ae967Ssumit.saxena@avagotech.com #define SGE_BUFFER_SIZE 4096
4098f67c8c5SSumit Saxena #define MEGASAS_CLUSTER_ID_SIZE 16
410c4a3e0a5SBagalkote, Sreenivas /*
41181e403ceSYang, Bo * define constants for device list query options
41281e403ceSYang, Bo */
41381e403ceSYang, Bo enum MR_PD_QUERY_TYPE {
41481e403ceSYang, Bo MR_PD_QUERY_TYPE_ALL = 0,
41581e403ceSYang, Bo MR_PD_QUERY_TYPE_STATE = 1,
41681e403ceSYang, Bo MR_PD_QUERY_TYPE_POWER_STATE = 2,
41781e403ceSYang, Bo MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
41881e403ceSYang, Bo MR_PD_QUERY_TYPE_SPEED = 4,
41981e403ceSYang, Bo MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
42081e403ceSYang, Bo };
42181e403ceSYang, Bo
42221c9e160Sadam radford enum MR_LD_QUERY_TYPE {
42321c9e160Sadam radford MR_LD_QUERY_TYPE_ALL = 0,
42421c9e160Sadam radford MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
42521c9e160Sadam radford MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
42621c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
42721c9e160Sadam radford MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
42821c9e160Sadam radford };
42921c9e160Sadam radford
43021c9e160Sadam radford
4317e8a75f4SYang, Bo #define MR_EVT_CFG_CLEARED 0x0004
4327e8a75f4SYang, Bo #define MR_EVT_LD_STATE_CHANGE 0x0051
4337e8a75f4SYang, Bo #define MR_EVT_PD_INSERTED 0x005b
4347e8a75f4SYang, Bo #define MR_EVT_PD_REMOVED 0x0070
4357e8a75f4SYang, Bo #define MR_EVT_LD_CREATED 0x008a
4367e8a75f4SYang, Bo #define MR_EVT_LD_DELETED 0x008b
4377e8a75f4SYang, Bo #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
4387e8a75f4SYang, Bo #define MR_EVT_LD_OFFLINE 0x00fc
4397e8a75f4SYang, Bo #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
440c4bd2654Ssumit.saxena@avagotech.com #define MR_EVT_CTRL_PROP_CHANGED 0x012f
4417e8a75f4SYang, Bo
44281e403ceSYang, Bo enum MR_PD_STATE {
44381e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
44481e403ceSYang, Bo MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
44581e403ceSYang, Bo MR_PD_STATE_HOT_SPARE = 0x02,
44681e403ceSYang, Bo MR_PD_STATE_OFFLINE = 0x10,
44781e403ceSYang, Bo MR_PD_STATE_FAILED = 0x11,
44881e403ceSYang, Bo MR_PD_STATE_REBUILD = 0x14,
44981e403ceSYang, Bo MR_PD_STATE_ONLINE = 0x18,
45081e403ceSYang, Bo MR_PD_STATE_COPYBACK = 0x20,
45181e403ceSYang, Bo MR_PD_STATE_SYSTEM = 0x40,
45281e403ceSYang, Bo };
45381e403ceSYang, Bo
4542216c305SSumit Saxena union MR_PD_REF {
4552216c305SSumit Saxena struct {
4562216c305SSumit Saxena u16 deviceId;
4572216c305SSumit Saxena u16 seqNum;
4582216c305SSumit Saxena } mrPdRef;
4592216c305SSumit Saxena u32 ref;
4602216c305SSumit Saxena };
4612216c305SSumit Saxena
4622216c305SSumit Saxena /*
4632216c305SSumit Saxena * define the DDF Type bit structure
4642216c305SSumit Saxena */
4652216c305SSumit Saxena union MR_PD_DDF_TYPE {
4662216c305SSumit Saxena struct {
4672216c305SSumit Saxena union {
4682216c305SSumit Saxena struct {
4692216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD
4702216c305SSumit Saxena u16 forcedPDGUID:1;
4712216c305SSumit Saxena u16 inVD:1;
4722216c305SSumit Saxena u16 isGlobalSpare:1;
4732216c305SSumit Saxena u16 isSpare:1;
4742216c305SSumit Saxena u16 isForeign:1;
4752216c305SSumit Saxena u16 reserved:7;
4762216c305SSumit Saxena u16 intf:4;
4772216c305SSumit Saxena #else
4782216c305SSumit Saxena u16 intf:4;
4792216c305SSumit Saxena u16 reserved:7;
4802216c305SSumit Saxena u16 isForeign:1;
4812216c305SSumit Saxena u16 isSpare:1;
4822216c305SSumit Saxena u16 isGlobalSpare:1;
4832216c305SSumit Saxena u16 inVD:1;
4842216c305SSumit Saxena u16 forcedPDGUID:1;
4852216c305SSumit Saxena #endif
4862216c305SSumit Saxena } pdType;
4872216c305SSumit Saxena u16 type;
4882216c305SSumit Saxena };
4892216c305SSumit Saxena u16 reserved;
4902216c305SSumit Saxena } ddf;
4912216c305SSumit Saxena struct {
4922216c305SSumit Saxena u32 reserved;
4932216c305SSumit Saxena } nonDisk;
4942216c305SSumit Saxena u32 type;
4952216c305SSumit Saxena } __packed;
4962216c305SSumit Saxena
4972216c305SSumit Saxena /*
4982216c305SSumit Saxena * defines the progress structure
4992216c305SSumit Saxena */
5002216c305SSumit Saxena union MR_PROGRESS {
5012216c305SSumit Saxena struct {
5022216c305SSumit Saxena u16 progress;
5032216c305SSumit Saxena union {
5042216c305SSumit Saxena u16 elapsedSecs;
5052216c305SSumit Saxena u16 elapsedSecsForLastPercent;
5062216c305SSumit Saxena };
5072216c305SSumit Saxena } mrProgress;
5082216c305SSumit Saxena u32 w;
5092216c305SSumit Saxena } __packed;
5102216c305SSumit Saxena
5112216c305SSumit Saxena /*
5122216c305SSumit Saxena * defines the physical drive progress structure
5132216c305SSumit Saxena */
5142216c305SSumit Saxena struct MR_PD_PROGRESS {
5152216c305SSumit Saxena struct {
516b9d5e3e7SShivasharan S #ifndef __BIG_ENDIAN_BITFIELD
5172216c305SSumit Saxena u32 rbld:1;
5182216c305SSumit Saxena u32 patrol:1;
5192216c305SSumit Saxena u32 clear:1;
5202216c305SSumit Saxena u32 copyBack:1;
5212216c305SSumit Saxena u32 erase:1;
5222216c305SSumit Saxena u32 locate:1;
5232216c305SSumit Saxena u32 reserved:26;
5242216c305SSumit Saxena #else
5252216c305SSumit Saxena u32 reserved:26;
5262216c305SSumit Saxena u32 locate:1;
5272216c305SSumit Saxena u32 erase:1;
5282216c305SSumit Saxena u32 copyBack:1;
5292216c305SSumit Saxena u32 clear:1;
5302216c305SSumit Saxena u32 patrol:1;
5312216c305SSumit Saxena u32 rbld:1;
5322216c305SSumit Saxena #endif
5332216c305SSumit Saxena } active;
5342216c305SSumit Saxena union MR_PROGRESS rbld;
5352216c305SSumit Saxena union MR_PROGRESS patrol;
5362216c305SSumit Saxena union {
5372216c305SSumit Saxena union MR_PROGRESS clear;
5382216c305SSumit Saxena union MR_PROGRESS erase;
5392216c305SSumit Saxena };
5402216c305SSumit Saxena
5412216c305SSumit Saxena struct {
542b9d5e3e7SShivasharan S #ifndef __BIG_ENDIAN_BITFIELD
5432216c305SSumit Saxena u32 rbld:1;
5442216c305SSumit Saxena u32 patrol:1;
5452216c305SSumit Saxena u32 clear:1;
5462216c305SSumit Saxena u32 copyBack:1;
5472216c305SSumit Saxena u32 erase:1;
5482216c305SSumit Saxena u32 reserved:27;
5492216c305SSumit Saxena #else
5502216c305SSumit Saxena u32 reserved:27;
5512216c305SSumit Saxena u32 erase:1;
5522216c305SSumit Saxena u32 copyBack:1;
5532216c305SSumit Saxena u32 clear:1;
5542216c305SSumit Saxena u32 patrol:1;
5552216c305SSumit Saxena u32 rbld:1;
5562216c305SSumit Saxena #endif
5572216c305SSumit Saxena } pause;
5582216c305SSumit Saxena
5592216c305SSumit Saxena union MR_PROGRESS reserved[3];
5602216c305SSumit Saxena } __packed;
5612216c305SSumit Saxena
5622216c305SSumit Saxena struct MR_PD_INFO {
5632216c305SSumit Saxena union MR_PD_REF ref;
5642216c305SSumit Saxena u8 inquiryData[96];
5652216c305SSumit Saxena u8 vpdPage83[64];
5662216c305SSumit Saxena u8 notSupported;
5672216c305SSumit Saxena u8 scsiDevType;
5682216c305SSumit Saxena
5692216c305SSumit Saxena union {
5702216c305SSumit Saxena u8 connectedPortBitmap;
5712216c305SSumit Saxena u8 connectedPortNumbers;
5722216c305SSumit Saxena };
5732216c305SSumit Saxena
5742216c305SSumit Saxena u8 deviceSpeed;
5752216c305SSumit Saxena u32 mediaErrCount;
5762216c305SSumit Saxena u32 otherErrCount;
5772216c305SSumit Saxena u32 predFailCount;
5782216c305SSumit Saxena u32 lastPredFailEventSeqNum;
5792216c305SSumit Saxena
5802216c305SSumit Saxena u16 fwState;
5812216c305SSumit Saxena u8 disabledForRemoval;
5822216c305SSumit Saxena u8 linkSpeed;
5832216c305SSumit Saxena union MR_PD_DDF_TYPE state;
5842216c305SSumit Saxena
5852216c305SSumit Saxena struct {
5862216c305SSumit Saxena u8 count;
5872216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD
5882216c305SSumit Saxena u8 isPathBroken:4;
5892216c305SSumit Saxena u8 reserved3:3;
5902216c305SSumit Saxena u8 widePortCapable:1;
5912216c305SSumit Saxena #else
5922216c305SSumit Saxena u8 widePortCapable:1;
5932216c305SSumit Saxena u8 reserved3:3;
5942216c305SSumit Saxena u8 isPathBroken:4;
5952216c305SSumit Saxena #endif
5962216c305SSumit Saxena
5972216c305SSumit Saxena u8 connectorIndex[2];
5982216c305SSumit Saxena u8 reserved[4];
5992216c305SSumit Saxena u64 sasAddr[2];
6002216c305SSumit Saxena u8 reserved2[16];
6012216c305SSumit Saxena } pathInfo;
6022216c305SSumit Saxena
6032216c305SSumit Saxena u64 rawSize;
6042216c305SSumit Saxena u64 nonCoercedSize;
6052216c305SSumit Saxena u64 coercedSize;
6062216c305SSumit Saxena u16 enclDeviceId;
6072216c305SSumit Saxena u8 enclIndex;
6082216c305SSumit Saxena
6092216c305SSumit Saxena union {
6102216c305SSumit Saxena u8 slotNumber;
6112216c305SSumit Saxena u8 enclConnectorIndex;
6122216c305SSumit Saxena };
6132216c305SSumit Saxena
6142216c305SSumit Saxena struct MR_PD_PROGRESS progInfo;
6152216c305SSumit Saxena u8 badBlockTableFull;
6162216c305SSumit Saxena u8 unusableInCurrentConfig;
6172216c305SSumit Saxena u8 vpdPage83Ext[64];
6182216c305SSumit Saxena u8 powerState;
6192216c305SSumit Saxena u8 enclPosition;
6202216c305SSumit Saxena u32 allowedOps;
6212216c305SSumit Saxena u16 copyBackPartnerId;
6222216c305SSumit Saxena u16 enclPartnerDeviceId;
6232216c305SSumit Saxena struct {
6242216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD
6252216c305SSumit Saxena u16 fdeCapable:1;
6262216c305SSumit Saxena u16 fdeEnabled:1;
6272216c305SSumit Saxena u16 secured:1;
6282216c305SSumit Saxena u16 locked:1;
6292216c305SSumit Saxena u16 foreign:1;
6302216c305SSumit Saxena u16 needsEKM:1;
6312216c305SSumit Saxena u16 reserved:10;
6322216c305SSumit Saxena #else
6332216c305SSumit Saxena u16 reserved:10;
6342216c305SSumit Saxena u16 needsEKM:1;
6352216c305SSumit Saxena u16 foreign:1;
6362216c305SSumit Saxena u16 locked:1;
6372216c305SSumit Saxena u16 secured:1;
6382216c305SSumit Saxena u16 fdeEnabled:1;
6392216c305SSumit Saxena u16 fdeCapable:1;
6402216c305SSumit Saxena #endif
6412216c305SSumit Saxena } security;
6422216c305SSumit Saxena u8 mediaType;
6432216c305SSumit Saxena u8 notCertified;
6442216c305SSumit Saxena u8 bridgeVendor[8];
6452216c305SSumit Saxena u8 bridgeProductIdentification[16];
6462216c305SSumit Saxena u8 bridgeProductRevisionLevel[4];
6472216c305SSumit Saxena u8 satBridgeExists;
6482216c305SSumit Saxena
6492216c305SSumit Saxena u8 interfaceType;
6502216c305SSumit Saxena u8 temperature;
6512216c305SSumit Saxena u8 emulatedBlockSize;
6522216c305SSumit Saxena u16 userDataBlockSize;
6532216c305SSumit Saxena u16 reserved2;
6542216c305SSumit Saxena
6552216c305SSumit Saxena struct {
6562216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD
6572216c305SSumit Saxena u32 piType:3;
6582216c305SSumit Saxena u32 piFormatted:1;
6592216c305SSumit Saxena u32 piEligible:1;
6602216c305SSumit Saxena u32 NCQ:1;
6612216c305SSumit Saxena u32 WCE:1;
6622216c305SSumit Saxena u32 commissionedSpare:1;
6632216c305SSumit Saxena u32 emergencySpare:1;
6642216c305SSumit Saxena u32 ineligibleForSSCD:1;
6652216c305SSumit Saxena u32 ineligibleForLd:1;
6662216c305SSumit Saxena u32 useSSEraseType:1;
6672216c305SSumit Saxena u32 wceUnchanged:1;
6682216c305SSumit Saxena u32 supportScsiUnmap:1;
6692216c305SSumit Saxena u32 reserved:18;
6702216c305SSumit Saxena #else
6712216c305SSumit Saxena u32 reserved:18;
6722216c305SSumit Saxena u32 supportScsiUnmap:1;
6732216c305SSumit Saxena u32 wceUnchanged:1;
6742216c305SSumit Saxena u32 useSSEraseType:1;
6752216c305SSumit Saxena u32 ineligibleForLd:1;
6762216c305SSumit Saxena u32 ineligibleForSSCD:1;
6772216c305SSumit Saxena u32 emergencySpare:1;
6782216c305SSumit Saxena u32 commissionedSpare:1;
6792216c305SSumit Saxena u32 WCE:1;
6802216c305SSumit Saxena u32 NCQ:1;
6812216c305SSumit Saxena u32 piEligible:1;
6822216c305SSumit Saxena u32 piFormatted:1;
6832216c305SSumit Saxena u32 piType:3;
6842216c305SSumit Saxena #endif
6852216c305SSumit Saxena } properties;
6862216c305SSumit Saxena
6872216c305SSumit Saxena u64 shieldDiagCompletionTime;
6882216c305SSumit Saxena u8 shieldCounter;
6892216c305SSumit Saxena
6902216c305SSumit Saxena u8 linkSpeedOther;
6912216c305SSumit Saxena u8 reserved4[2];
6922216c305SSumit Saxena
6932216c305SSumit Saxena struct {
6942216c305SSumit Saxena #ifndef __BIG_ENDIAN_BITFIELD
6952216c305SSumit Saxena u32 bbmErrCountSupported:1;
6962216c305SSumit Saxena u32 bbmErrCount:31;
6972216c305SSumit Saxena #else
6982216c305SSumit Saxena u32 bbmErrCount:31;
6992216c305SSumit Saxena u32 bbmErrCountSupported:1;
7002216c305SSumit Saxena #endif
7012216c305SSumit Saxena } bbmErr;
7022216c305SSumit Saxena
7032216c305SSumit Saxena u8 reserved1[512-428];
7042216c305SSumit Saxena } __packed;
70581e403ceSYang, Bo
70681e403ceSYang, Bo /*
70796188a89SShivasharan S * Definition of structure used to expose attributes of VD or JBOD
70896188a89SShivasharan S * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
70996188a89SShivasharan S * is fired by driver)
71096188a89SShivasharan S */
71196188a89SShivasharan S struct MR_TARGET_PROPERTIES {
71296188a89SShivasharan S u32 max_io_size_kb;
71396188a89SShivasharan S u32 device_qdepth;
71496188a89SShivasharan S u32 sector_size;
715e9495e2dSShivasharan S u8 reset_tmo;
716e9495e2dSShivasharan S u8 reserved[499];
71796188a89SShivasharan S } __packed;
71896188a89SShivasharan S
71996188a89SShivasharan S /*
72081e403ceSYang, Bo * defines the physical drive address structure
72181e403ceSYang, Bo */
72281e403ceSYang, Bo struct MR_PD_ADDRESS {
7239ab9ed38SChristoph Hellwig __le16 deviceId;
72481e403ceSYang, Bo u16 enclDeviceId;
72581e403ceSYang, Bo
72681e403ceSYang, Bo union {
72781e403ceSYang, Bo struct {
72881e403ceSYang, Bo u8 enclIndex;
72981e403ceSYang, Bo u8 slotNumber;
73081e403ceSYang, Bo } mrPdAddress;
73181e403ceSYang, Bo struct {
73281e403ceSYang, Bo u8 enclPosition;
73381e403ceSYang, Bo u8 enclConnectorIndex;
73481e403ceSYang, Bo } mrEnclAddress;
73581e403ceSYang, Bo };
73681e403ceSYang, Bo u8 scsiDevType;
73781e403ceSYang, Bo union {
73881e403ceSYang, Bo u8 connectedPortBitmap;
73981e403ceSYang, Bo u8 connectedPortNumbers;
74081e403ceSYang, Bo };
74181e403ceSYang, Bo u64 sasAddr[2];
74281e403ceSYang, Bo } __packed;
74381e403ceSYang, Bo
74481e403ceSYang, Bo /*
74581e403ceSYang, Bo * defines the physical drive list structure
74681e403ceSYang, Bo */
74781e403ceSYang, Bo struct MR_PD_LIST {
7489ab9ed38SChristoph Hellwig __le32 size;
7499ab9ed38SChristoph Hellwig __le32 count;
75081e403ceSYang, Bo struct MR_PD_ADDRESS addr[1];
75181e403ceSYang, Bo } __packed;
75281e403ceSYang, Bo
75381e403ceSYang, Bo struct megasas_pd_list {
75481e403ceSYang, Bo u16 tid;
75581e403ceSYang, Bo u8 driveType;
75681e403ceSYang, Bo u8 driveState;
75781e403ceSYang, Bo } __packed;
75881e403ceSYang, Bo
75981e403ceSYang, Bo /*
760bdc6fb8dSYang, Bo * defines the logical drive reference structure
761bdc6fb8dSYang, Bo */
762bdc6fb8dSYang, Bo union MR_LD_REF {
763bdc6fb8dSYang, Bo struct {
764bdc6fb8dSYang, Bo u8 targetId;
765bdc6fb8dSYang, Bo u8 reserved;
7669ab9ed38SChristoph Hellwig __le16 seqNum;
767bdc6fb8dSYang, Bo };
7689ab9ed38SChristoph Hellwig __le32 ref;
769bdc6fb8dSYang, Bo } __packed;
770bdc6fb8dSYang, Bo
771bdc6fb8dSYang, Bo /*
772bdc6fb8dSYang, Bo * defines the logical drive list structure
773bdc6fb8dSYang, Bo */
774bdc6fb8dSYang, Bo struct MR_LD_LIST {
7759ab9ed38SChristoph Hellwig __le32 ldCount;
7769ab9ed38SChristoph Hellwig __le32 reserved;
777bdc6fb8dSYang, Bo struct {
778bdc6fb8dSYang, Bo union MR_LD_REF ref;
779bdc6fb8dSYang, Bo u8 state;
780bdc6fb8dSYang, Bo u8 reserved[3];
7819ab9ed38SChristoph Hellwig __le64 size;
78251087a86SSumit.Saxena@avagotech.com } ldList[MAX_LOGICAL_DRIVES_EXT];
783bdc6fb8dSYang, Bo } __packed;
784bdc6fb8dSYang, Bo
78521c9e160Sadam radford struct MR_LD_TARGETID_LIST {
7869ab9ed38SChristoph Hellwig __le32 size;
7879ab9ed38SChristoph Hellwig __le32 count;
78821c9e160Sadam radford u8 pad[3];
78951087a86SSumit.Saxena@avagotech.com u8 targetId[MAX_LOGICAL_DRIVES_EXT];
79021c9e160Sadam radford };
79121c9e160Sadam radford
792f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST_ENTRY {
793f6fe5731SShivasharan S struct {
794f6fe5731SShivasharan S union {
795f6fe5731SShivasharan S struct {
796f6fe5731SShivasharan S #if defined(__BIG_ENDIAN_BITFIELD)
797f6fe5731SShivasharan S u8 reserved:7;
798f6fe5731SShivasharan S u8 is_sys_pd:1;
799f6fe5731SShivasharan S #else
800f6fe5731SShivasharan S u8 is_sys_pd:1;
801f6fe5731SShivasharan S u8 reserved:7;
802f6fe5731SShivasharan S #endif
803f6fe5731SShivasharan S } bits;
804f6fe5731SShivasharan S u8 byte;
805f6fe5731SShivasharan S } u;
806f6fe5731SShivasharan S } flags;
807f6fe5731SShivasharan S u8 scsi_type;
808f6fe5731SShivasharan S __le16 target_id;
809a3742d68SShivasharan S u8 reserved[4];
810f6fe5731SShivasharan S __le64 sas_addr[2];
811f6fe5731SShivasharan S } __packed;
812f6fe5731SShivasharan S
813f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST {
814f6fe5731SShivasharan S __le32 size;
815f6fe5731SShivasharan S __le32 count;
816a3742d68SShivasharan S __le32 reserved[2];
817f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST_ENTRY host_device_list[1];
818f6fe5731SShivasharan S } __packed;
819f6fe5731SShivasharan S
820f6fe5731SShivasharan S #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \
821f6fe5731SShivasharan S (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \
822f6fe5731SShivasharan S (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
823f6fe5731SShivasharan S
82421c9e160Sadam radford
825bdc6fb8dSYang, Bo /*
826c4a3e0a5SBagalkote, Sreenivas * SAS controller properties
827c4a3e0a5SBagalkote, Sreenivas */
828c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop {
829c4a3e0a5SBagalkote, Sreenivas
830c4a3e0a5SBagalkote, Sreenivas u16 seq_num;
831c4a3e0a5SBagalkote, Sreenivas u16 pred_fail_poll_interval;
832c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_count;
833c4a3e0a5SBagalkote, Sreenivas u16 intr_throttle_timeouts;
834c4a3e0a5SBagalkote, Sreenivas u8 rebuild_rate;
835c4a3e0a5SBagalkote, Sreenivas u8 patrol_read_rate;
836c4a3e0a5SBagalkote, Sreenivas u8 bgi_rate;
837c4a3e0a5SBagalkote, Sreenivas u8 cc_rate;
838c4a3e0a5SBagalkote, Sreenivas u8 recon_rate;
839c4a3e0a5SBagalkote, Sreenivas u8 cache_flush_interval;
840c4a3e0a5SBagalkote, Sreenivas u8 spinup_drv_count;
841c4a3e0a5SBagalkote, Sreenivas u8 spinup_delay;
842c4a3e0a5SBagalkote, Sreenivas u8 cluster_enable;
843c4a3e0a5SBagalkote, Sreenivas u8 coercion_mode;
844c4a3e0a5SBagalkote, Sreenivas u8 alarm_enable;
845c4a3e0a5SBagalkote, Sreenivas u8 disable_auto_rebuild;
846c4a3e0a5SBagalkote, Sreenivas u8 disable_battery_warn;
847c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_size;
848c4a3e0a5SBagalkote, Sreenivas u16 ecc_bucket_leak_rate;
849c4a3e0a5SBagalkote, Sreenivas u8 restore_hotspare_on_insertion;
850c4a3e0a5SBagalkote, Sreenivas u8 expose_encl_devices;
85139a98554Sbo yang u8 maintainPdFailHistory;
85239a98554Sbo yang u8 disallowHostRequestReordering;
85339a98554Sbo yang u8 abortCCOnError;
85439a98554Sbo yang u8 loadBalanceMode;
85539a98554Sbo yang u8 disableAutoDetectBackplane;
856c4a3e0a5SBagalkote, Sreenivas
85739a98554Sbo yang u8 snapVDSpace;
85839a98554Sbo yang
85939a98554Sbo yang /*
86039a98554Sbo yang * Add properties that can be controlled by
86139a98554Sbo yang * a bit in the following structure.
86239a98554Sbo yang */
86339a98554Sbo yang struct {
86494cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD)
86594cd65ddSSumit.Saxena@lsi.com u32 reserved:18;
86694cd65ddSSumit.Saxena@lsi.com u32 enableJBOD:1;
86794cd65ddSSumit.Saxena@lsi.com u32 disableSpinDownHS:1;
86894cd65ddSSumit.Saxena@lsi.com u32 allowBootWithPinnedCache:1;
86994cd65ddSSumit.Saxena@lsi.com u32 disableOnlineCtrlReset:1;
87094cd65ddSSumit.Saxena@lsi.com u32 enableSecretKeyControl:1;
87194cd65ddSSumit.Saxena@lsi.com u32 autoEnhancedImport:1;
87294cd65ddSSumit.Saxena@lsi.com u32 enableSpinDownUnconfigured:1;
87394cd65ddSSumit.Saxena@lsi.com u32 SSDPatrolReadEnabled:1;
87494cd65ddSSumit.Saxena@lsi.com u32 SSDSMARTerEnabled:1;
87594cd65ddSSumit.Saxena@lsi.com u32 disableNCQ:1;
87694cd65ddSSumit.Saxena@lsi.com u32 useFdeOnly:1;
87794cd65ddSSumit.Saxena@lsi.com u32 prCorrectUnconfiguredAreas:1;
87894cd65ddSSumit.Saxena@lsi.com u32 SMARTerEnabled:1;
87994cd65ddSSumit.Saxena@lsi.com u32 copyBackDisabled:1;
88094cd65ddSSumit.Saxena@lsi.com #else
88139a98554Sbo yang u32 copyBackDisabled:1;
88239a98554Sbo yang u32 SMARTerEnabled:1;
88339a98554Sbo yang u32 prCorrectUnconfiguredAreas:1;
88439a98554Sbo yang u32 useFdeOnly:1;
88539a98554Sbo yang u32 disableNCQ:1;
88639a98554Sbo yang u32 SSDSMARTerEnabled:1;
88739a98554Sbo yang u32 SSDPatrolReadEnabled:1;
88839a98554Sbo yang u32 enableSpinDownUnconfigured:1;
88939a98554Sbo yang u32 autoEnhancedImport:1;
89039a98554Sbo yang u32 enableSecretKeyControl:1;
89139a98554Sbo yang u32 disableOnlineCtrlReset:1;
89239a98554Sbo yang u32 allowBootWithPinnedCache:1;
89339a98554Sbo yang u32 disableSpinDownHS:1;
89439a98554Sbo yang u32 enableJBOD:1;
89539a98554Sbo yang u32 reserved:18;
89694cd65ddSSumit.Saxena@lsi.com #endif
89739a98554Sbo yang } OnOffProperties;
898f0c21df6SShivasharan S
899f0c21df6SShivasharan S union {
90039a98554Sbo yang u8 autoSnapVDSpace;
90139a98554Sbo yang u8 viewSpace;
902f0c21df6SShivasharan S struct {
903f0c21df6SShivasharan S #if defined(__BIG_ENDIAN_BITFIELD)
904f6fe5731SShivasharan S u16 reserved3:9;
905f6fe5731SShivasharan S u16 enable_fw_dev_list:1;
906f6fe5731SShivasharan S u16 reserved2:1;
907f0c21df6SShivasharan S u16 enable_snap_dump:1;
908f0c21df6SShivasharan S u16 reserved1:4;
909f0c21df6SShivasharan S #else
910f0c21df6SShivasharan S u16 reserved1:4;
911f0c21df6SShivasharan S u16 enable_snap_dump:1;
912f6fe5731SShivasharan S u16 reserved2:1;
913f6fe5731SShivasharan S u16 enable_fw_dev_list:1;
914f6fe5731SShivasharan S u16 reserved3:9;
915f0c21df6SShivasharan S #endif
916f0c21df6SShivasharan S } on_off_properties2;
917f0c21df6SShivasharan S };
9189ab9ed38SChristoph Hellwig __le16 spinDownTime;
91939a98554Sbo yang u8 reserved[24];
92081e403ceSYang, Bo } __packed;
921c4a3e0a5SBagalkote, Sreenivas
922c4a3e0a5SBagalkote, Sreenivas /*
923c4a3e0a5SBagalkote, Sreenivas * SAS controller information
924c4a3e0a5SBagalkote, Sreenivas */
925c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_info {
926c4a3e0a5SBagalkote, Sreenivas
927c4a3e0a5SBagalkote, Sreenivas /*
928c4a3e0a5SBagalkote, Sreenivas * PCI device information
929c4a3e0a5SBagalkote, Sreenivas */
930c4a3e0a5SBagalkote, Sreenivas struct {
931c4a3e0a5SBagalkote, Sreenivas
9329ab9ed38SChristoph Hellwig __le16 vendor_id;
9339ab9ed38SChristoph Hellwig __le16 device_id;
9349ab9ed38SChristoph Hellwig __le16 sub_vendor_id;
9359ab9ed38SChristoph Hellwig __le16 sub_device_id;
936c4a3e0a5SBagalkote, Sreenivas u8 reserved[24];
937c4a3e0a5SBagalkote, Sreenivas
938c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci;
939c4a3e0a5SBagalkote, Sreenivas
940c4a3e0a5SBagalkote, Sreenivas /*
941c4a3e0a5SBagalkote, Sreenivas * Host interface information
942c4a3e0a5SBagalkote, Sreenivas */
943c4a3e0a5SBagalkote, Sreenivas struct {
944c4a3e0a5SBagalkote, Sreenivas
945c4a3e0a5SBagalkote, Sreenivas u8 PCIX:1;
946c4a3e0a5SBagalkote, Sreenivas u8 PCIE:1;
947c4a3e0a5SBagalkote, Sreenivas u8 iSCSI:1;
948c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1;
949229fe47cSadam radford u8 SRIOV:1;
950229fe47cSadam radford u8 reserved_0:3;
951c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6];
952c4a3e0a5SBagalkote, Sreenivas u8 port_count;
953c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8];
954c4a3e0a5SBagalkote, Sreenivas
955c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) host_interface;
956c4a3e0a5SBagalkote, Sreenivas
957c4a3e0a5SBagalkote, Sreenivas /*
958c4a3e0a5SBagalkote, Sreenivas * Device (backend) interface information
959c4a3e0a5SBagalkote, Sreenivas */
960c4a3e0a5SBagalkote, Sreenivas struct {
961c4a3e0a5SBagalkote, Sreenivas
962c4a3e0a5SBagalkote, Sreenivas u8 SPI:1;
963c4a3e0a5SBagalkote, Sreenivas u8 SAS_3G:1;
964c4a3e0a5SBagalkote, Sreenivas u8 SATA_1_5G:1;
965c4a3e0a5SBagalkote, Sreenivas u8 SATA_3G:1;
966c4a3e0a5SBagalkote, Sreenivas u8 reserved_0:4;
967c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[6];
968c4a3e0a5SBagalkote, Sreenivas u8 port_count;
969c4a3e0a5SBagalkote, Sreenivas u64 port_addr[8];
970c4a3e0a5SBagalkote, Sreenivas
971c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) device_interface;
972c4a3e0a5SBagalkote, Sreenivas
973c4a3e0a5SBagalkote, Sreenivas /*
974c4a3e0a5SBagalkote, Sreenivas * List of components residing in flash. All str are null terminated
975c4a3e0a5SBagalkote, Sreenivas */
9769ab9ed38SChristoph Hellwig __le32 image_check_word;
9779ab9ed38SChristoph Hellwig __le32 image_component_count;
978c4a3e0a5SBagalkote, Sreenivas
979c4a3e0a5SBagalkote, Sreenivas struct {
980c4a3e0a5SBagalkote, Sreenivas
981c4a3e0a5SBagalkote, Sreenivas char name[8];
982c4a3e0a5SBagalkote, Sreenivas char version[32];
983c4a3e0a5SBagalkote, Sreenivas char build_date[16];
984c4a3e0a5SBagalkote, Sreenivas char built_time[16];
985c4a3e0a5SBagalkote, Sreenivas
986c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) image_component[8];
987c4a3e0a5SBagalkote, Sreenivas
988c4a3e0a5SBagalkote, Sreenivas /*
989c4a3e0a5SBagalkote, Sreenivas * List of flash components that have been flashed on the card, but
990c4a3e0a5SBagalkote, Sreenivas * are not in use, pending reset of the adapter. This list will be
991c4a3e0a5SBagalkote, Sreenivas * empty if a flash operation has not occurred. All stings are null
992c4a3e0a5SBagalkote, Sreenivas * terminated
993c4a3e0a5SBagalkote, Sreenivas */
9949ab9ed38SChristoph Hellwig __le32 pending_image_component_count;
995c4a3e0a5SBagalkote, Sreenivas
996c4a3e0a5SBagalkote, Sreenivas struct {
997c4a3e0a5SBagalkote, Sreenivas
998c4a3e0a5SBagalkote, Sreenivas char name[8];
999c4a3e0a5SBagalkote, Sreenivas char version[32];
1000c4a3e0a5SBagalkote, Sreenivas char build_date[16];
1001c4a3e0a5SBagalkote, Sreenivas char build_time[16];
1002c4a3e0a5SBagalkote, Sreenivas
1003c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pending_image_component[8];
1004c4a3e0a5SBagalkote, Sreenivas
1005c4a3e0a5SBagalkote, Sreenivas u8 max_arms;
1006c4a3e0a5SBagalkote, Sreenivas u8 max_spans;
1007c4a3e0a5SBagalkote, Sreenivas u8 max_arrays;
1008c4a3e0a5SBagalkote, Sreenivas u8 max_lds;
1009c4a3e0a5SBagalkote, Sreenivas
1010c4a3e0a5SBagalkote, Sreenivas char product_name[80];
1011c4a3e0a5SBagalkote, Sreenivas char serial_no[32];
1012c4a3e0a5SBagalkote, Sreenivas
1013c4a3e0a5SBagalkote, Sreenivas /*
1014c4a3e0a5SBagalkote, Sreenivas * Other physical/controller/operation information. Indicates the
1015c4a3e0a5SBagalkote, Sreenivas * presence of the hardware
1016c4a3e0a5SBagalkote, Sreenivas */
1017c4a3e0a5SBagalkote, Sreenivas struct {
1018c4a3e0a5SBagalkote, Sreenivas
1019c4a3e0a5SBagalkote, Sreenivas u32 bbu:1;
1020c4a3e0a5SBagalkote, Sreenivas u32 alarm:1;
1021c4a3e0a5SBagalkote, Sreenivas u32 nvram:1;
1022c4a3e0a5SBagalkote, Sreenivas u32 uart:1;
1023c4a3e0a5SBagalkote, Sreenivas u32 reserved:28;
1024c4a3e0a5SBagalkote, Sreenivas
1025c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) hw_present;
1026c4a3e0a5SBagalkote, Sreenivas
10279ab9ed38SChristoph Hellwig __le32 current_fw_time;
1028c4a3e0a5SBagalkote, Sreenivas
1029c4a3e0a5SBagalkote, Sreenivas /*
1030c4a3e0a5SBagalkote, Sreenivas * Maximum data transfer sizes
1031c4a3e0a5SBagalkote, Sreenivas */
10329ab9ed38SChristoph Hellwig __le16 max_concurrent_cmds;
10339ab9ed38SChristoph Hellwig __le16 max_sge_count;
10349ab9ed38SChristoph Hellwig __le32 max_request_size;
1035c4a3e0a5SBagalkote, Sreenivas
1036c4a3e0a5SBagalkote, Sreenivas /*
1037c4a3e0a5SBagalkote, Sreenivas * Logical and physical device counts
1038c4a3e0a5SBagalkote, Sreenivas */
10399ab9ed38SChristoph Hellwig __le16 ld_present_count;
10409ab9ed38SChristoph Hellwig __le16 ld_degraded_count;
10419ab9ed38SChristoph Hellwig __le16 ld_offline_count;
1042c4a3e0a5SBagalkote, Sreenivas
10439ab9ed38SChristoph Hellwig __le16 pd_present_count;
10449ab9ed38SChristoph Hellwig __le16 pd_disk_present_count;
10459ab9ed38SChristoph Hellwig __le16 pd_disk_pred_failure_count;
10469ab9ed38SChristoph Hellwig __le16 pd_disk_failed_count;
1047c4a3e0a5SBagalkote, Sreenivas
1048c4a3e0a5SBagalkote, Sreenivas /*
1049c4a3e0a5SBagalkote, Sreenivas * Memory size information
1050c4a3e0a5SBagalkote, Sreenivas */
10519ab9ed38SChristoph Hellwig __le16 nvram_size;
10529ab9ed38SChristoph Hellwig __le16 memory_size;
10539ab9ed38SChristoph Hellwig __le16 flash_size;
1054c4a3e0a5SBagalkote, Sreenivas
1055c4a3e0a5SBagalkote, Sreenivas /*
1056c4a3e0a5SBagalkote, Sreenivas * Error counters
1057c4a3e0a5SBagalkote, Sreenivas */
10589ab9ed38SChristoph Hellwig __le16 mem_correctable_error_count;
10599ab9ed38SChristoph Hellwig __le16 mem_uncorrectable_error_count;
1060c4a3e0a5SBagalkote, Sreenivas
1061c4a3e0a5SBagalkote, Sreenivas /*
1062c4a3e0a5SBagalkote, Sreenivas * Cluster information
1063c4a3e0a5SBagalkote, Sreenivas */
1064c4a3e0a5SBagalkote, Sreenivas u8 cluster_permitted;
1065c4a3e0a5SBagalkote, Sreenivas u8 cluster_active;
1066c4a3e0a5SBagalkote, Sreenivas
1067c4a3e0a5SBagalkote, Sreenivas /*
1068c4a3e0a5SBagalkote, Sreenivas * Additional max data transfer sizes
1069c4a3e0a5SBagalkote, Sreenivas */
10709ab9ed38SChristoph Hellwig __le16 max_strips_per_io;
1071c4a3e0a5SBagalkote, Sreenivas
1072c4a3e0a5SBagalkote, Sreenivas /*
1073c4a3e0a5SBagalkote, Sreenivas * Controller capabilities structures
1074c4a3e0a5SBagalkote, Sreenivas */
1075c4a3e0a5SBagalkote, Sreenivas struct {
1076c4a3e0a5SBagalkote, Sreenivas
1077c4a3e0a5SBagalkote, Sreenivas u32 raid_level_0:1;
1078c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1:1;
1079c4a3e0a5SBagalkote, Sreenivas u32 raid_level_5:1;
1080c4a3e0a5SBagalkote, Sreenivas u32 raid_level_1E:1;
1081c4a3e0a5SBagalkote, Sreenivas u32 raid_level_6:1;
1082c4a3e0a5SBagalkote, Sreenivas u32 reserved:27;
1083c4a3e0a5SBagalkote, Sreenivas
1084c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) raid_levels;
1085c4a3e0a5SBagalkote, Sreenivas
1086c4a3e0a5SBagalkote, Sreenivas struct {
1087c4a3e0a5SBagalkote, Sreenivas
1088c4a3e0a5SBagalkote, Sreenivas u32 rbld_rate:1;
1089c4a3e0a5SBagalkote, Sreenivas u32 cc_rate:1;
1090c4a3e0a5SBagalkote, Sreenivas u32 bgi_rate:1;
1091c4a3e0a5SBagalkote, Sreenivas u32 recon_rate:1;
1092c4a3e0a5SBagalkote, Sreenivas u32 patrol_rate:1;
1093c4a3e0a5SBagalkote, Sreenivas u32 alarm_control:1;
1094c4a3e0a5SBagalkote, Sreenivas u32 cluster_supported:1;
1095c4a3e0a5SBagalkote, Sreenivas u32 bbu:1;
1096c4a3e0a5SBagalkote, Sreenivas u32 spanning_allowed:1;
1097c4a3e0a5SBagalkote, Sreenivas u32 dedicated_hotspares:1;
1098c4a3e0a5SBagalkote, Sreenivas u32 revertible_hotspares:1;
1099c4a3e0a5SBagalkote, Sreenivas u32 foreign_config_import:1;
1100c4a3e0a5SBagalkote, Sreenivas u32 self_diagnostic:1;
1101c4a3e0a5SBagalkote, Sreenivas u32 mixed_redundancy_arr:1;
1102c4a3e0a5SBagalkote, Sreenivas u32 global_hot_spares:1;
1103c4a3e0a5SBagalkote, Sreenivas u32 reserved:17;
1104c4a3e0a5SBagalkote, Sreenivas
1105c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) adapter_operations;
1106c4a3e0a5SBagalkote, Sreenivas
1107c4a3e0a5SBagalkote, Sreenivas struct {
1108c4a3e0a5SBagalkote, Sreenivas
1109c4a3e0a5SBagalkote, Sreenivas u32 read_policy:1;
1110c4a3e0a5SBagalkote, Sreenivas u32 write_policy:1;
1111c4a3e0a5SBagalkote, Sreenivas u32 io_policy:1;
1112c4a3e0a5SBagalkote, Sreenivas u32 access_policy:1;
1113c4a3e0a5SBagalkote, Sreenivas u32 disk_cache_policy:1;
1114c4a3e0a5SBagalkote, Sreenivas u32 reserved:27;
1115c4a3e0a5SBagalkote, Sreenivas
1116c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_operations;
1117c4a3e0a5SBagalkote, Sreenivas
1118c4a3e0a5SBagalkote, Sreenivas struct {
1119c4a3e0a5SBagalkote, Sreenivas
1120c4a3e0a5SBagalkote, Sreenivas u8 min;
1121c4a3e0a5SBagalkote, Sreenivas u8 max;
1122c4a3e0a5SBagalkote, Sreenivas u8 reserved[2];
1123c4a3e0a5SBagalkote, Sreenivas
1124c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) stripe_sz_ops;
1125c4a3e0a5SBagalkote, Sreenivas
1126c4a3e0a5SBagalkote, Sreenivas struct {
1127c4a3e0a5SBagalkote, Sreenivas
1128c4a3e0a5SBagalkote, Sreenivas u32 force_online:1;
1129c4a3e0a5SBagalkote, Sreenivas u32 force_offline:1;
1130c4a3e0a5SBagalkote, Sreenivas u32 force_rebuild:1;
1131c4a3e0a5SBagalkote, Sreenivas u32 reserved:29;
1132c4a3e0a5SBagalkote, Sreenivas
1133c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_operations;
1134c4a3e0a5SBagalkote, Sreenivas
1135c4a3e0a5SBagalkote, Sreenivas struct {
1136c4a3e0a5SBagalkote, Sreenivas
1137c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sas:1;
1138c4a3e0a5SBagalkote, Sreenivas u32 ctrl_supports_sata:1;
1139c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_encl:1;
1140c4a3e0a5SBagalkote, Sreenivas u32 allow_mix_in_ld:1;
1141c4a3e0a5SBagalkote, Sreenivas u32 allow_sata_in_cluster:1;
1142c4a3e0a5SBagalkote, Sreenivas u32 reserved:27;
1143c4a3e0a5SBagalkote, Sreenivas
1144c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_mix_support;
1145c4a3e0a5SBagalkote, Sreenivas
1146c4a3e0a5SBagalkote, Sreenivas /*
1147c4a3e0a5SBagalkote, Sreenivas * Define ECC single-bit-error bucket information
1148c4a3e0a5SBagalkote, Sreenivas */
1149c4a3e0a5SBagalkote, Sreenivas u8 ecc_bucket_count;
1150c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[11];
1151c4a3e0a5SBagalkote, Sreenivas
1152c4a3e0a5SBagalkote, Sreenivas /*
1153c4a3e0a5SBagalkote, Sreenivas * Include the controller properties (changeable items)
1154c4a3e0a5SBagalkote, Sreenivas */
1155c4a3e0a5SBagalkote, Sreenivas struct megasas_ctrl_prop properties;
1156c4a3e0a5SBagalkote, Sreenivas
1157c4a3e0a5SBagalkote, Sreenivas /*
1158c4a3e0a5SBagalkote, Sreenivas * Define FW pkg version (set in envt v'bles on OEM basis)
1159c4a3e0a5SBagalkote, Sreenivas */
1160c4a3e0a5SBagalkote, Sreenivas char package_version[0x60];
1161c4a3e0a5SBagalkote, Sreenivas
1162c4a3e0a5SBagalkote, Sreenivas
1163bc93d425SSumit.Saxena@lsi.com /*
1164bc93d425SSumit.Saxena@lsi.com * If adapterOperations.supportMoreThan8Phys is set,
1165bc93d425SSumit.Saxena@lsi.com * and deviceInterface.portCount is greater than 8,
1166bc93d425SSumit.Saxena@lsi.com * SAS Addrs for first 8 ports shall be populated in
1167bc93d425SSumit.Saxena@lsi.com * deviceInterface.portAddr, and the rest shall be
1168bc93d425SSumit.Saxena@lsi.com * populated in deviceInterfacePortAddr2.
1169bc93d425SSumit.Saxena@lsi.com */
11709ab9ed38SChristoph Hellwig __le64 deviceInterfacePortAddr2[8]; /*6a0h */
1171bc93d425SSumit.Saxena@lsi.com u8 reserved3[128]; /*6e0h */
1172bc93d425SSumit.Saxena@lsi.com
1173bc93d425SSumit.Saxena@lsi.com struct { /*760h */
1174bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_0:4;
1175bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_0:12;
1176bc93d425SSumit.Saxena@lsi.com
1177bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1:4;
1178bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1:12;
1179bc93d425SSumit.Saxena@lsi.com
1180bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_5:4;
1181bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_5:12;
1182bc93d425SSumit.Saxena@lsi.com
1183bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E:4;
1184bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E:12;
1185bc93d425SSumit.Saxena@lsi.com
1186bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_6:4;
1187bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_6:12;
1188bc93d425SSumit.Saxena@lsi.com
1189bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_10:4;
1190bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_10:12;
1191bc93d425SSumit.Saxena@lsi.com
1192bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_50:4;
1193bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_50:12;
1194bc93d425SSumit.Saxena@lsi.com
1195bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_60:4;
1196bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_60:12;
1197bc93d425SSumit.Saxena@lsi.com
1198bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E_RLQ0:4;
1199bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E_RLQ0:12;
1200bc93d425SSumit.Saxena@lsi.com
1201bc93d425SSumit.Saxena@lsi.com u16 minPdRaidLevel_1E0_RLQ0:4;
1202bc93d425SSumit.Saxena@lsi.com u16 maxPdRaidLevel_1E0_RLQ0:12;
1203bc93d425SSumit.Saxena@lsi.com
1204bc93d425SSumit.Saxena@lsi.com u16 reserved[6];
1205bc93d425SSumit.Saxena@lsi.com } pdsForRaidLevels;
1206bc93d425SSumit.Saxena@lsi.com
12079ab9ed38SChristoph Hellwig __le16 maxPds; /*780h */
12089ab9ed38SChristoph Hellwig __le16 maxDedHSPs; /*782h */
12099ab9ed38SChristoph Hellwig __le16 maxGlobalHSP; /*784h */
12109ab9ed38SChristoph Hellwig __le16 ddfSize; /*786h */
1211bc93d425SSumit.Saxena@lsi.com u8 maxLdsPerArray; /*788h */
1212bc93d425SSumit.Saxena@lsi.com u8 partitionsInDDF; /*789h */
1213bc93d425SSumit.Saxena@lsi.com u8 lockKeyBinding; /*78ah */
1214bc93d425SSumit.Saxena@lsi.com u8 maxPITsPerLd; /*78bh */
1215bc93d425SSumit.Saxena@lsi.com u8 maxViewsPerLd; /*78ch */
1216bc93d425SSumit.Saxena@lsi.com u8 maxTargetId; /*78dh */
12179ab9ed38SChristoph Hellwig __le16 maxBvlVdSize; /*78eh */
1218bc93d425SSumit.Saxena@lsi.com
12199ab9ed38SChristoph Hellwig __le16 maxConfigurableSSCSize; /*790h */
12209ab9ed38SChristoph Hellwig __le16 currentSSCsize; /*792h */
1221bc93d425SSumit.Saxena@lsi.com
1222bc93d425SSumit.Saxena@lsi.com char expanderFwVersion[12]; /*794h */
1223bc93d425SSumit.Saxena@lsi.com
12249ab9ed38SChristoph Hellwig __le16 PFKTrialTimeRemaining; /*7A0h */
1225bc93d425SSumit.Saxena@lsi.com
12269ab9ed38SChristoph Hellwig __le16 cacheMemorySize; /*7A2h */
1227bc93d425SSumit.Saxena@lsi.com
1228bc93d425SSumit.Saxena@lsi.com struct { /*7A4h */
122994cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD)
1230229fe47cSadam radford u32 reserved:5;
1231229fe47cSadam radford u32 activePassive:2;
1232229fe47cSadam radford u32 supportConfigAutoBalance:1;
1233229fe47cSadam radford u32 mpio:1;
1234229fe47cSadam radford u32 supportDataLDonSSCArray:1;
1235229fe47cSadam radford u32 supportPointInTimeProgress:1;
123694cd65ddSSumit.Saxena@lsi.com u32 supportUnevenSpans:1;
123794cd65ddSSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1;
123894cd65ddSSumit.Saxena@lsi.com u32 headlessMode:1;
123994cd65ddSSumit.Saxena@lsi.com u32 supportEmulatedDrives:1;
124094cd65ddSSumit.Saxena@lsi.com u32 supportResetNow:1;
124194cd65ddSSumit.Saxena@lsi.com u32 realTimeScheduler:1;
124294cd65ddSSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1;
124394cd65ddSSumit.Saxena@lsi.com u32 supportPerfTuning:1;
124494cd65ddSSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1;
124594cd65ddSSumit.Saxena@lsi.com u32 supportJBOD:1;
124694cd65ddSSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1;
124794cd65ddSSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1;
124894cd65ddSSumit.Saxena@lsi.com u32 supportEmergencySpares:1;
124994cd65ddSSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1;
125094cd65ddSSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1;
125194cd65ddSSumit.Saxena@lsi.com u32 supportShieldState:1;
125294cd65ddSSumit.Saxena@lsi.com u32 supportLdBBMInfo:1;
125394cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType3:1;
125494cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType2:1;
125594cd65ddSSumit.Saxena@lsi.com u32 supportLdPIType1:1;
125694cd65ddSSumit.Saxena@lsi.com u32 supportPIcontroller:1;
125794cd65ddSSumit.Saxena@lsi.com #else
1258bc93d425SSumit.Saxena@lsi.com u32 supportPIcontroller:1;
1259bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType1:1;
1260bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType2:1;
1261bc93d425SSumit.Saxena@lsi.com u32 supportLdPIType3:1;
1262bc93d425SSumit.Saxena@lsi.com u32 supportLdBBMInfo:1;
1263bc93d425SSumit.Saxena@lsi.com u32 supportShieldState:1;
1264bc93d425SSumit.Saxena@lsi.com u32 blockSSDWriteCacheChange:1;
1265bc93d425SSumit.Saxena@lsi.com u32 supportSuspendResumeBGops:1;
1266bc93d425SSumit.Saxena@lsi.com u32 supportEmergencySpares:1;
1267bc93d425SSumit.Saxena@lsi.com u32 supportSetLinkSpeed:1;
1268bc93d425SSumit.Saxena@lsi.com u32 supportBootTimePFKChange:1;
1269bc93d425SSumit.Saxena@lsi.com u32 supportJBOD:1;
1270bc93d425SSumit.Saxena@lsi.com u32 disableOnlinePFKChange:1;
1271bc93d425SSumit.Saxena@lsi.com u32 supportPerfTuning:1;
1272bc93d425SSumit.Saxena@lsi.com u32 supportSSDPatrolRead:1;
1273bc93d425SSumit.Saxena@lsi.com u32 realTimeScheduler:1;
1274bc93d425SSumit.Saxena@lsi.com
1275bc93d425SSumit.Saxena@lsi.com u32 supportResetNow:1;
1276bc93d425SSumit.Saxena@lsi.com u32 supportEmulatedDrives:1;
1277bc93d425SSumit.Saxena@lsi.com u32 headlessMode:1;
1278bc93d425SSumit.Saxena@lsi.com u32 dedicatedHotSparesLimited:1;
1279bc93d425SSumit.Saxena@lsi.com
1280bc93d425SSumit.Saxena@lsi.com
1281bc93d425SSumit.Saxena@lsi.com u32 supportUnevenSpans:1;
1282229fe47cSadam radford u32 supportPointInTimeProgress:1;
1283229fe47cSadam radford u32 supportDataLDonSSCArray:1;
1284229fe47cSadam radford u32 mpio:1;
1285229fe47cSadam radford u32 supportConfigAutoBalance:1;
1286229fe47cSadam radford u32 activePassive:2;
1287229fe47cSadam radford u32 reserved:5;
128894cd65ddSSumit.Saxena@lsi.com #endif
1289bc93d425SSumit.Saxena@lsi.com } adapterOperations2;
1290bc93d425SSumit.Saxena@lsi.com
1291bc93d425SSumit.Saxena@lsi.com u8 driverVersion[32]; /*7A8h */
1292bc93d425SSumit.Saxena@lsi.com u8 maxDAPdCountSpinup60; /*7C8h */
1293bc93d425SSumit.Saxena@lsi.com u8 temperatureROC; /*7C9h */
1294bc93d425SSumit.Saxena@lsi.com u8 temperatureCtrl; /*7CAh */
1295bc93d425SSumit.Saxena@lsi.com u8 reserved4; /*7CBh */
12969ab9ed38SChristoph Hellwig __le16 maxConfigurablePds; /*7CCh */
1297bc93d425SSumit.Saxena@lsi.com
1298bc93d425SSumit.Saxena@lsi.com
1299bc93d425SSumit.Saxena@lsi.com u8 reserved5[2]; /*0x7CDh */
1300bc93d425SSumit.Saxena@lsi.com
1301bc93d425SSumit.Saxena@lsi.com /*
1302bc93d425SSumit.Saxena@lsi.com * HA cluster information
1303bc93d425SSumit.Saxena@lsi.com */
1304bc93d425SSumit.Saxena@lsi.com struct {
130551087a86SSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD)
13068f67c8c5SSumit Saxena u32 reserved:25;
13078f67c8c5SSumit Saxena u32 passive:1;
130851087a86SSumit.Saxena@avagotech.com u32 premiumFeatureMismatch:1;
130951087a86SSumit.Saxena@avagotech.com u32 ctrlPropIncompatible:1;
131051087a86SSumit.Saxena@avagotech.com u32 fwVersionMismatch:1;
131151087a86SSumit.Saxena@avagotech.com u32 hwIncompatible:1;
131251087a86SSumit.Saxena@avagotech.com u32 peerIsIncompatible:1;
131351087a86SSumit.Saxena@avagotech.com u32 peerIsPresent:1;
131451087a86SSumit.Saxena@avagotech.com #else
1315bc93d425SSumit.Saxena@lsi.com u32 peerIsPresent:1;
1316bc93d425SSumit.Saxena@lsi.com u32 peerIsIncompatible:1;
1317bc93d425SSumit.Saxena@lsi.com u32 hwIncompatible:1;
1318bc93d425SSumit.Saxena@lsi.com u32 fwVersionMismatch:1;
1319bc93d425SSumit.Saxena@lsi.com u32 ctrlPropIncompatible:1;
1320bc93d425SSumit.Saxena@lsi.com u32 premiumFeatureMismatch:1;
13218f67c8c5SSumit Saxena u32 passive:1;
13228f67c8c5SSumit Saxena u32 reserved:25;
132351087a86SSumit.Saxena@avagotech.com #endif
1324bc93d425SSumit.Saxena@lsi.com } cluster;
1325bc93d425SSumit.Saxena@lsi.com
13268f67c8c5SSumit Saxena char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1327229fe47cSadam radford struct {
1328229fe47cSadam radford u8 maxVFsSupported; /*0x7E4*/
1329229fe47cSadam radford u8 numVFsEnabled; /*0x7E5*/
1330229fe47cSadam radford u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1331229fe47cSadam radford u8 reserved; /*0x7E7*/
1332229fe47cSadam radford } iov;
1333bc93d425SSumit.Saxena@lsi.com
1334fc62b3fcSSumit.Saxena@avagotech.com struct {
1335fc62b3fcSSumit.Saxena@avagotech.com #if defined(__BIG_ENDIAN_BITFIELD)
13363761cb4cSsumit.saxena@avagotech.com u32 reserved:7;
13373761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1;
13380be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1;
13390be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1;
13400be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1;
13410be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1;
13427497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1;
13437497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1;
13447497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1;
13457497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1;
13467497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1;
13477497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1;
13487497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1;
13497497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1;
13507497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1;
13517497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1;
13527497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1;
13537497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1;
13547497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1;
1355fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1;
135651087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1;
135751087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1;
135851087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1;
135951087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1;
136051087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2;
1361fc62b3fcSSumit.Saxena@avagotech.com #else
136251087a86SSumit.Saxena@avagotech.com u32 supportPersonalityChange:2;
136351087a86SSumit.Saxena@avagotech.com u32 supportThermalPollInterval:1;
136451087a86SSumit.Saxena@avagotech.com u32 supportDisableImmediateIO:1;
136551087a86SSumit.Saxena@avagotech.com u32 supportT10RebuildAssist:1;
136651087a86SSumit.Saxena@avagotech.com u32 supportMaxExtLDs:1;
1367fc62b3fcSSumit.Saxena@avagotech.com u32 supportCrashDump:1;
13687497cde8SSumit.Saxena@avagotech.com u32 supportSwZone:1;
13697497cde8SSumit.Saxena@avagotech.com u32 supportDebugQueue:1;
13707497cde8SSumit.Saxena@avagotech.com u32 supportNVCacheErase:1;
13717497cde8SSumit.Saxena@avagotech.com u32 supportForceTo512e:1;
13727497cde8SSumit.Saxena@avagotech.com u32 supportHOQRebuild:1;
13737497cde8SSumit.Saxena@avagotech.com u32 supportAllowedOpsforDrvRemoval:1;
13747497cde8SSumit.Saxena@avagotech.com u32 supportDrvActivityLEDSetting:1;
13757497cde8SSumit.Saxena@avagotech.com u32 supportNVDRAM:1;
13767497cde8SSumit.Saxena@avagotech.com u32 supportForceFlash:1;
13777497cde8SSumit.Saxena@avagotech.com u32 supportDisableSESMonitoring:1;
13787497cde8SSumit.Saxena@avagotech.com u32 supportCacheBypassModes:1;
13797497cde8SSumit.Saxena@avagotech.com u32 supportSecurityonJBOD:1;
13807497cde8SSumit.Saxena@avagotech.com u32 discardCacheDuringLDDelete:1;
13810be3f4c9Ssumit.saxena@avagotech.com u32 supportTTYLogCompression:1;
13820be3f4c9Ssumit.saxena@avagotech.com u32 supportCPLDUpdate:1;
13830be3f4c9Ssumit.saxena@avagotech.com u32 supportDiskCacheSettingForSysPDs:1;
13840be3f4c9Ssumit.saxena@avagotech.com u32 supportExtendedSSCSize:1;
13853761cb4cSsumit.saxena@avagotech.com u32 useSeqNumJbodFP:1;
13863761cb4cSsumit.saxena@avagotech.com u32 reserved:7;
1387fc62b3fcSSumit.Saxena@avagotech.com #endif
1388fc62b3fcSSumit.Saxena@avagotech.com } adapterOperations3;
1389fc62b3fcSSumit.Saxena@avagotech.com
1390ede7c3ceSSasikumar Chandrasekaran struct {
1391ede7c3ceSSasikumar Chandrasekaran #if defined(__BIG_ENDIAN_BITFIELD)
1392ede7c3ceSSasikumar Chandrasekaran u8 reserved:7;
1393ede7c3ceSSasikumar Chandrasekaran /* Indicates whether the CPLD image is part of
1394ede7c3ceSSasikumar Chandrasekaran * the package and stored in flash
1395ede7c3ceSSasikumar Chandrasekaran */
1396ede7c3ceSSasikumar Chandrasekaran u8 cpld_in_flash:1;
1397ede7c3ceSSasikumar Chandrasekaran #else
1398ede7c3ceSSasikumar Chandrasekaran u8 cpld_in_flash:1;
1399ede7c3ceSSasikumar Chandrasekaran u8 reserved:7;
1400ede7c3ceSSasikumar Chandrasekaran #endif
1401ede7c3ceSSasikumar Chandrasekaran u8 reserved1[3];
1402ede7c3ceSSasikumar Chandrasekaran /* Null terminated string. Has the version
1403ede7c3ceSSasikumar Chandrasekaran * information if cpld_in_flash = FALSE
1404ede7c3ceSSasikumar Chandrasekaran */
1405ede7c3ceSSasikumar Chandrasekaran u8 userCodeDefinition[12];
1406ede7c3ceSSasikumar Chandrasekaran } cpld; /* Valid only if upgradableCPLD is TRUE */
1407ede7c3ceSSasikumar Chandrasekaran
1408ede7c3ceSSasikumar Chandrasekaran struct {
1409ede7c3ceSSasikumar Chandrasekaran #if defined(__BIG_ENDIAN_BITFIELD)
1410f870bcbeSShivasharan S u16 reserved:2;
1411f870bcbeSShivasharan S u16 support_nvme_passthru:1;
1412f870bcbeSShivasharan S u16 support_pl_debug_info:1;
1413f870bcbeSShivasharan S u16 support_flash_comp_info:1;
1414f870bcbeSShivasharan S u16 support_host_info:1;
1415f870bcbeSShivasharan S u16 support_dual_fw_update:1;
1416f870bcbeSShivasharan S u16 support_ssc_rev3:1;
1417ede7c3ceSSasikumar Chandrasekaran u16 fw_swaps_bbu_vpd_info:1;
1418ede7c3ceSSasikumar Chandrasekaran u16 support_pd_map_target_id:1;
1419ede7c3ceSSasikumar Chandrasekaran u16 support_ses_ctrl_in_multipathcfg:1;
1420ede7c3ceSSasikumar Chandrasekaran u16 image_upload_supported:1;
1421ede7c3ceSSasikumar Chandrasekaran u16 support_encrypted_mfc:1;
1422ede7c3ceSSasikumar Chandrasekaran u16 supported_enc_algo:1;
1423ede7c3ceSSasikumar Chandrasekaran u16 support_ibutton_less:1;
1424ede7c3ceSSasikumar Chandrasekaran u16 ctrl_info_ext_supported:1;
1425ede7c3ceSSasikumar Chandrasekaran #else
1426ede7c3ceSSasikumar Chandrasekaran
1427ede7c3ceSSasikumar Chandrasekaran u16 ctrl_info_ext_supported:1;
1428ede7c3ceSSasikumar Chandrasekaran u16 support_ibutton_less:1;
1429ede7c3ceSSasikumar Chandrasekaran u16 supported_enc_algo:1;
1430ede7c3ceSSasikumar Chandrasekaran u16 support_encrypted_mfc:1;
1431ede7c3ceSSasikumar Chandrasekaran u16 image_upload_supported:1;
1432ede7c3ceSSasikumar Chandrasekaran /* FW supports LUN based association and target port based */
1433ede7c3ceSSasikumar Chandrasekaran u16 support_ses_ctrl_in_multipathcfg:1;
1434ede7c3ceSSasikumar Chandrasekaran /* association for the SES device connected in multipath mode */
1435ede7c3ceSSasikumar Chandrasekaran /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1436ede7c3ceSSasikumar Chandrasekaran u16 support_pd_map_target_id:1;
1437ede7c3ceSSasikumar Chandrasekaran /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1438ede7c3ceSSasikumar Chandrasekaran * provide the data in little endian order
1439ede7c3ceSSasikumar Chandrasekaran */
1440ede7c3ceSSasikumar Chandrasekaran u16 fw_swaps_bbu_vpd_info:1;
1441f870bcbeSShivasharan S u16 support_ssc_rev3:1;
1442f870bcbeSShivasharan S /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1443f870bcbeSShivasharan S u16 support_dual_fw_update:1;
1444f870bcbeSShivasharan S /* FW supports dual firmware update feature */
1445f870bcbeSShivasharan S u16 support_host_info:1;
1446f870bcbeSShivasharan S /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1447f870bcbeSShivasharan S u16 support_flash_comp_info:1;
1448f870bcbeSShivasharan S /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1449f870bcbeSShivasharan S u16 support_pl_debug_info:1;
1450f870bcbeSShivasharan S /* FW supports retrieval of PL debug information through apps */
1451f870bcbeSShivasharan S u16 support_nvme_passthru:1;
1452f870bcbeSShivasharan S /* FW supports NVMe passthru commands */
1453f870bcbeSShivasharan S u16 reserved:2;
1454ede7c3ceSSasikumar Chandrasekaran #endif
1455ede7c3ceSSasikumar Chandrasekaran } adapter_operations4;
1456ede7c3ceSSasikumar Chandrasekaran u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1457e9495e2dSShivasharan S
1458e9495e2dSShivasharan S u32 size;
1459e9495e2dSShivasharan S u32 pad1;
1460e9495e2dSShivasharan S
1461e9495e2dSShivasharan S u8 reserved6[64];
1462e9495e2dSShivasharan S
146358136856SChandrakanth Patil struct {
146458136856SChandrakanth Patil #if defined(__BIG_ENDIAN_BITFIELD)
146558136856SChandrakanth Patil u32 reserved:19;
146658136856SChandrakanth Patil u32 support_pci_lane_margining: 1;
146758136856SChandrakanth Patil u32 support_psoc_update:1;
146858136856SChandrakanth Patil u32 support_force_personality_change:1;
146958136856SChandrakanth Patil u32 support_fde_type_mix:1;
147058136856SChandrakanth Patil u32 support_snap_dump:1;
147158136856SChandrakanth Patil u32 support_nvme_tm:1;
147258136856SChandrakanth Patil u32 support_oce_only:1;
147358136856SChandrakanth Patil u32 support_ext_mfg_vpd:1;
147458136856SChandrakanth Patil u32 support_pcie:1;
147558136856SChandrakanth Patil u32 support_cvhealth_info:1;
147658136856SChandrakanth Patil u32 support_profile_change:2;
147758136856SChandrakanth Patil u32 mr_config_ext2_supported:1;
147858136856SChandrakanth Patil #else
147958136856SChandrakanth Patil u32 mr_config_ext2_supported:1;
148058136856SChandrakanth Patil u32 support_profile_change:2;
148158136856SChandrakanth Patil u32 support_cvhealth_info:1;
148258136856SChandrakanth Patil u32 support_pcie:1;
148358136856SChandrakanth Patil u32 support_ext_mfg_vpd:1;
148458136856SChandrakanth Patil u32 support_oce_only:1;
148558136856SChandrakanth Patil u32 support_nvme_tm:1;
148658136856SChandrakanth Patil u32 support_snap_dump:1;
148758136856SChandrakanth Patil u32 support_fde_type_mix:1;
148858136856SChandrakanth Patil u32 support_force_personality_change:1;
148958136856SChandrakanth Patil u32 support_psoc_update:1;
149058136856SChandrakanth Patil u32 support_pci_lane_margining: 1;
149158136856SChandrakanth Patil u32 reserved:19;
149258136856SChandrakanth Patil #endif
149358136856SChandrakanth Patil } adapter_operations5;
149458136856SChandrakanth Patil
149558136856SChandrakanth Patil u32 rsvdForAdptOp[63];
1496e9495e2dSShivasharan S
1497e9495e2dSShivasharan S u8 reserved7[3];
1498e9495e2dSShivasharan S
1499e9495e2dSShivasharan S u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1500e9495e2dSShivasharan S u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */
1501e9495e2dSShivasharan S u8 reserved8[3];
150281e403ceSYang, Bo } __packed;
1503c4a3e0a5SBagalkote, Sreenivas
1504c4a3e0a5SBagalkote, Sreenivas /*
1505c4a3e0a5SBagalkote, Sreenivas * ===============================
1506c4a3e0a5SBagalkote, Sreenivas * MegaRAID SAS driver definitions
1507c4a3e0a5SBagalkote, Sreenivas * ===============================
1508c4a3e0a5SBagalkote, Sreenivas */
1509c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_PD_CHANNELS 2
151051087a86SSumit.Saxena@avagotech.com #define MEGASAS_MAX_LD_CHANNELS 2
1511c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1512c4a3e0a5SBagalkote, Sreenivas MEGASAS_MAX_LD_CHANNELS)
1513c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1514c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_DEFAULT_INIT_ID -1
1515c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_MAX_LUN 8
15166bf579a3Sadam radford #define MEGASAS_DEFAULT_CMD_PER_LUN 256
151781e403ceSYang, Bo #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
151881e403ceSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL)
1519bdc6fb8dSYang, Bo #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1520bdc6fb8dSYang, Bo MEGASAS_MAX_DEV_PER_CHANNEL)
1521c4a3e0a5SBagalkote, Sreenivas
1522bfa65917SChandrakanth Patil #define MEGASAS_MAX_SUPPORTED_LD_IDS 240
1523bfa65917SChandrakanth Patil
15241fd10685SYang, Bo #define MEGASAS_MAX_SECTORS (2*1024)
152542a8d2b3Sadam radford #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1526658dcedbSSumant Patro #define MEGASAS_DBG_LVL 1
1527658dcedbSSumant Patro
152805e9ebbeSSumant Patro #define MEGASAS_FW_BUSY 1
152905e9ebbeSSumant Patro
1530def0eab3SShivasharan S /* Driver's internal Logging levels*/
153196c9603cSShivasharan S #define OCR_DEBUG (1 << 0)
153296c9603cSShivasharan S #define TM_DEBUG (1 << 1)
15330a11c0b0SShivasharan S #define LD_PD_DEBUG (1 << 2)
1534def0eab3SShivasharan S
153511c71cb4SSumit Saxena #define SCAN_PD_CHANNEL 0x1
153611c71cb4SSumit Saxena #define SCAN_VD_CHANNEL 0x2
153790dc9d98SSumit.Saxena@avagotech.com
1538c3e385a1SSumit Saxena #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1539a48ba0ecSShivasharan S #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1540a48ba0ecSShivasharan S #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1541c3e385a1SSumit Saxena
15427497cde8SSumit.Saxena@avagotech.com enum MR_SCSI_CMD_TYPE {
15437497cde8SSumit.Saxena@avagotech.com READ_WRITE_LDIO = 0,
15447497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_LDIO = 1,
15457497cde8SSumit.Saxena@avagotech.com READ_WRITE_SYSPDIO = 2,
15467497cde8SSumit.Saxena@avagotech.com NON_READ_WRITE_SYSPDIO = 3,
15477497cde8SSumit.Saxena@avagotech.com };
15487497cde8SSumit.Saxena@avagotech.com
15496d40afbcSSumit Saxena enum DCMD_TIMEOUT_ACTION {
15506d40afbcSSumit Saxena INITIATE_OCR = 0,
15516d40afbcSSumit Saxena KILL_ADAPTER = 1,
15526d40afbcSSumit Saxena IGNORE_TIMEOUT = 2,
15536d40afbcSSumit Saxena };
1554308ec459SSumit Saxena
1555308ec459SSumit Saxena enum FW_BOOT_CONTEXT {
1556308ec459SSumit Saxena PROBE_CONTEXT = 0,
1557308ec459SSumit Saxena OCR_CONTEXT = 1,
1558308ec459SSumit Saxena };
1559308ec459SSumit Saxena
1560d532dbe2Sbo yang /* Frame Type */
1561d532dbe2Sbo yang #define IO_FRAME 0
1562d532dbe2Sbo yang #define PTHRU_FRAME 1
1563d532dbe2Sbo yang
1564c4a3e0a5SBagalkote, Sreenivas /*
1565c4a3e0a5SBagalkote, Sreenivas * When SCSI mid-layer calls driver's reset routine, driver waits for
1566c4a3e0a5SBagalkote, Sreenivas * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1567c4a3e0a5SBagalkote, Sreenivas * that the driver cannot _actually_ abort or reset pending commands. While
1568c4a3e0a5SBagalkote, Sreenivas * it is waiting for the commands to complete, it prints a diagnostic message
1569c4a3e0a5SBagalkote, Sreenivas * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1570c4a3e0a5SBagalkote, Sreenivas */
1571c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_WAIT_TIME 180
15722a3681e5SSumant Patro #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1573c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_RESET_NOTICE_INTERVAL 5
1574c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOCTL_CMD 0
157505e9ebbeSSumant Patro #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1576c5daa6a9Sadam radford #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1577e9495e2dSShivasharan S #define MEGASAS_DEFAULT_TM_TIMEOUT 50
1578c4a3e0a5SBagalkote, Sreenivas /*
1579c4a3e0a5SBagalkote, Sreenivas * FW reports the maximum of number of commands that it can accept (maximum
1580c4a3e0a5SBagalkote, Sreenivas * commands that can be outstanding) at any time. The driver must report a
1581c4a3e0a5SBagalkote, Sreenivas * lower number to the mid layer because it can issue a few internal commands
1582c4a3e0a5SBagalkote, Sreenivas * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1583c4a3e0a5SBagalkote, Sreenivas * is shown below
1584c4a3e0a5SBagalkote, Sreenivas */
1585c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_INT_CMDS 32
15867bebf5c7SYang, Bo #define MEGASAS_SKINNY_INT_CMDS 5
1587ec779595SShivasharan S #define MEGASAS_FUSION_INTERNAL_CMDS 8
1588ae09a6c1SSumit.Saxena@avagotech.com #define MEGASAS_FUSION_IOCTL_CMDS 3
1589f26ac3a1SSumit.Saxena@avagotech.com #define MEGASAS_MFI_IOCTL_CMDS 27
1590c4a3e0a5SBagalkote, Sreenivas
1591d46a3ad6SSumit.Saxena@lsi.com #define MEGASAS_MAX_MSIX_QUEUES 128
1592c4a3e0a5SBagalkote, Sreenivas /*
1593c4a3e0a5SBagalkote, Sreenivas * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1594c4a3e0a5SBagalkote, Sreenivas * SGLs based on the size of dma_addr_t
1595c4a3e0a5SBagalkote, Sreenivas */
1596c4a3e0a5SBagalkote, Sreenivas #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1597c4a3e0a5SBagalkote, Sreenivas
159839a98554Sbo yang #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
159939a98554Sbo yang
160039a98554Sbo yang #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
160139a98554Sbo yang #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
160239a98554Sbo yang #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
160339a98554Sbo yang
1604c4a3e0a5SBagalkote, Sreenivas #define MFI_OB_INTR_STATUS_MASK 0x00000002
160514faea9fSbo yang #define MFI_POLL_TIMEOUT_SECS 60
16066d40afbcSSumit Saxena #define MFI_IO_TIMEOUT_SECS 180
1607229fe47cSadam radford #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1608229fe47cSadam radford #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
160944e8d693SShivasharan S #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF 1
1610229fe47cSadam radford #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1611f9876f0bSSumant Patro #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
16126610a6b3SYang, Bo #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
16136610a6b3SYang, Bo #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
161487911122SYang, Bo #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
161587911122SYang, Bo #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
16160e98936cSSumant Patro
161739a98554Sbo yang #define MFI_1068_PCSR_OFFSET 0x84
161839a98554Sbo yang #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
161939a98554Sbo yang #define MFI_1068_FW_READY 0xDDDD0000
1620d46a3ad6SSumit.Saxena@lsi.com
1621d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1622d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1623d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1624d46a3ad6SSumit.Saxena@lsi.com #define MR_MAX_MSIX_REG_ARRAY 16
1625179ac142SSumit Saxena #define MR_RDPQ_MODE_OFFSET 0X00800000
1626d889344eSSasikumar Chandrasekaran
1627d889344eSSasikumar Chandrasekaran #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1628d889344eSSasikumar Chandrasekaran #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1629d889344eSSasikumar Chandrasekaran #define MR_MIN_MAP_SIZE 0x10000
1630d889344eSSasikumar Chandrasekaran /* 64k */
1631d889344eSSasikumar Chandrasekaran
1632d0fc91d6SKashyap Desai #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1633d0fc91d6SKashyap Desai
16345885571dSChandrakanth Patil #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
16355885571dSChandrakanth Patil
1636107a60ddSShivasharan S #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25)
1637132147d7SChandrakanth Patil #define MR_INTR_COALESCING_SUPPORT_OFFSET (1 << 26)
1638107a60ddSShivasharan S
16393f6194afSShivasharan S #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000
16403f6194afSShivasharan S #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20
16413f6194afSShivasharan S #define MEGASAS_WATCHDOG_WAIT_COUNT 50
16423f6194afSShivasharan S
1643c365178fSShivasharan S enum MR_ADAPTER_TYPE {
1644c365178fSShivasharan S MFI_SERIES = 1,
1645c365178fSShivasharan S THUNDERBOLT_SERIES = 2,
1646c365178fSShivasharan S INVADER_SERIES = 3,
1647c365178fSShivasharan S VENTURA_SERIES = 4,
1648154a7cdeSShivasharan S AERO_SERIES = 5,
1649c365178fSShivasharan S };
1650c365178fSShivasharan S
16510e98936cSSumant Patro /*
16520e98936cSSumant Patro * register set for both 1068 and 1078 controllers
16530e98936cSSumant Patro * structure extended for 1078 registers
16540e98936cSSumant Patro */
1655c4a3e0a5SBagalkote, Sreenivas
1656f9876f0bSSumant Patro struct megasas_register_set {
16579c915a8cSadam radford u32 doorbell; /*0000h*/
16589c915a8cSadam radford u32 fusion_seq_offset; /*0004h*/
16599c915a8cSadam radford u32 fusion_host_diag; /*0008h*/
16609c915a8cSadam radford u32 reserved_01; /*000Ch*/
1661c4a3e0a5SBagalkote, Sreenivas
1662c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_0; /*0010h*/
1663c4a3e0a5SBagalkote, Sreenivas u32 inbound_msg_1; /*0014h*/
1664c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_0; /*0018h*/
1665c4a3e0a5SBagalkote, Sreenivas u32 outbound_msg_1; /*001Ch*/
1666c4a3e0a5SBagalkote, Sreenivas
1667c4a3e0a5SBagalkote, Sreenivas u32 inbound_doorbell; /*0020h*/
1668c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_status; /*0024h*/
1669c4a3e0a5SBagalkote, Sreenivas u32 inbound_intr_mask; /*0028h*/
1670c4a3e0a5SBagalkote, Sreenivas
1671c4a3e0a5SBagalkote, Sreenivas u32 outbound_doorbell; /*002Ch*/
1672c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_status; /*0030h*/
1673c4a3e0a5SBagalkote, Sreenivas u32 outbound_intr_mask; /*0034h*/
1674c4a3e0a5SBagalkote, Sreenivas
1675c4a3e0a5SBagalkote, Sreenivas u32 reserved_1[2]; /*0038h*/
1676c4a3e0a5SBagalkote, Sreenivas
1677c4a3e0a5SBagalkote, Sreenivas u32 inbound_queue_port; /*0040h*/
1678c4a3e0a5SBagalkote, Sreenivas u32 outbound_queue_port; /*0044h*/
1679c4a3e0a5SBagalkote, Sreenivas
16809c915a8cSadam radford u32 reserved_2[9]; /*0048h*/
16819c915a8cSadam radford u32 reply_post_host_index; /*006Ch*/
16829c915a8cSadam radford u32 reserved_2_2[12]; /*0070h*/
1683c4a3e0a5SBagalkote, Sreenivas
1684f9876f0bSSumant Patro u32 outbound_doorbell_clear; /*00A0h*/
1685f9876f0bSSumant Patro
1686f9876f0bSSumant Patro u32 reserved_3[3]; /*00A4h*/
1687f9876f0bSSumant Patro
168881b76452SShivasharan S u32 outbound_scratch_pad_0; /*00B0h*/
168981b76452SShivasharan S u32 outbound_scratch_pad_1; /*00B4h*/
169081b76452SShivasharan S u32 outbound_scratch_pad_2; /*00B8h*/
169181b76452SShivasharan S u32 outbound_scratch_pad_3; /*00BCh*/
1692f9876f0bSSumant Patro
1693f9876f0bSSumant Patro u32 inbound_low_queue_port ; /*00C0h*/
1694f9876f0bSSumant Patro
1695f9876f0bSSumant Patro u32 inbound_high_queue_port ; /*00C4h*/
1696f9876f0bSSumant Patro
169745f4f2ebSSasikumar Chandrasekaran u32 inbound_single_queue_port; /*00C8h*/
169839a98554Sbo yang u32 res_6[11]; /*CCh*/
169939a98554Sbo yang u32 host_diag;
170039a98554Sbo yang u32 seq_offset;
170139a98554Sbo yang u32 index_registers[807]; /*00CCh*/
1702c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1703c4a3e0a5SBagalkote, Sreenivas
1704c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 {
1705c4a3e0a5SBagalkote, Sreenivas
17069ab9ed38SChristoph Hellwig __le32 phys_addr;
17079ab9ed38SChristoph Hellwig __le32 length;
1708c4a3e0a5SBagalkote, Sreenivas
1709c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1710c4a3e0a5SBagalkote, Sreenivas
1711c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 {
1712c4a3e0a5SBagalkote, Sreenivas
17139ab9ed38SChristoph Hellwig __le64 phys_addr;
17149ab9ed38SChristoph Hellwig __le32 length;
1715c4a3e0a5SBagalkote, Sreenivas
1716c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1717c4a3e0a5SBagalkote, Sreenivas
1718f4c9a131SYang, Bo struct megasas_sge_skinny {
17199ab9ed38SChristoph Hellwig __le64 phys_addr;
17209ab9ed38SChristoph Hellwig __le32 length;
17219ab9ed38SChristoph Hellwig __le32 flag;
1722f4c9a131SYang, Bo } __packed;
1723f4c9a131SYang, Bo
1724c4a3e0a5SBagalkote, Sreenivas union megasas_sgl {
1725aa673800SKees Cook DECLARE_FLEX_ARRAY(struct megasas_sge32, sge32);
1726aa673800SKees Cook DECLARE_FLEX_ARRAY(struct megasas_sge64, sge64);
1727aa673800SKees Cook DECLARE_FLEX_ARRAY(struct megasas_sge_skinny, sge_skinny);
1728c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1729c4a3e0a5SBagalkote, Sreenivas
1730c4a3e0a5SBagalkote, Sreenivas struct megasas_header {
1731c4a3e0a5SBagalkote, Sreenivas
1732c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1733c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */
1734c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1735c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */
1736c4a3e0a5SBagalkote, Sreenivas
1737c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */
1738c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */
1739c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */
1740c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1741c4a3e0a5SBagalkote, Sreenivas
17429ab9ed38SChristoph Hellwig __le32 context; /*08h */
17439ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1744c4a3e0a5SBagalkote, Sreenivas
17459ab9ed38SChristoph Hellwig __le16 flags; /*10h */
17469ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
17479ab9ed38SChristoph Hellwig __le32 data_xferlen; /*14h */
1748c4a3e0a5SBagalkote, Sreenivas
1749c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1750c4a3e0a5SBagalkote, Sreenivas
1751c4a3e0a5SBagalkote, Sreenivas union megasas_sgl_frame {
1752c4a3e0a5SBagalkote, Sreenivas
1753c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[8];
1754c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[5];
1755c4a3e0a5SBagalkote, Sreenivas
1756c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1757c4a3e0a5SBagalkote, Sreenivas
1758d46a3ad6SSumit.Saxena@lsi.com typedef union _MFI_CAPABILITIES {
1759d46a3ad6SSumit.Saxena@lsi.com struct {
176094cd65ddSSumit.Saxena@lsi.com #if defined(__BIG_ENDIAN_BITFIELD)
17619bcb1d5aSChandrakanth Patil u32 reserved:15;
17629bcb1d5aSChandrakanth Patil u32 support_memdump:1;
1763f6fe5731SShivasharan S u32 support_fw_exposed_dev_list:1;
1764f870bcbeSShivasharan S u32 support_nvme_passthru:1;
1765107a60ddSShivasharan S u32 support_64bit_mode:1;
1766ede7c3ceSSasikumar Chandrasekaran u32 support_pd_map_target_id:1;
176752b62ac7SSumit Saxena u32 support_qd_throttling:1;
17688f05024cSSumit Saxena u32 support_fp_rlbypass:1;
17698f05024cSSumit Saxena u32 support_vfid_in_ioframe:1;
1770bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1;
17710be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1;
17727497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1;
17737497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1;
1774d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1;
177551087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1;
17767497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1;
177794cd65ddSSumit.Saxena@lsi.com u32 support_additional_msix:1;
177894cd65ddSSumit.Saxena@lsi.com u32 support_fp_remote_lun:1;
177994cd65ddSSumit.Saxena@lsi.com #else
1780d46a3ad6SSumit.Saxena@lsi.com u32 support_fp_remote_lun:1;
1781d46a3ad6SSumit.Saxena@lsi.com u32 support_additional_msix:1;
17827497cde8SSumit.Saxena@avagotech.com u32 support_fastpath_wb:1;
178351087a86SSumit.Saxena@avagotech.com u32 support_max_255lds:1;
1784d2552ebeSSumit.Saxena@avagotech.com u32 support_ndrive_r1_lb:1;
17857497cde8SSumit.Saxena@avagotech.com u32 support_core_affinity:1;
17867497cde8SSumit.Saxena@avagotech.com u32 security_protocol_cmds_fw:1;
17870be3f4c9Ssumit.saxena@avagotech.com u32 support_ext_queue_depth:1;
1788bd5f9484Ssumit.saxena@avagotech.com u32 support_ext_io_size:1;
17898f05024cSSumit Saxena u32 support_vfid_in_ioframe:1;
17908f05024cSSumit Saxena u32 support_fp_rlbypass:1;
179152b62ac7SSumit Saxena u32 support_qd_throttling:1;
1792ede7c3ceSSasikumar Chandrasekaran u32 support_pd_map_target_id:1;
1793107a60ddSShivasharan S u32 support_64bit_mode:1;
1794f870bcbeSShivasharan S u32 support_nvme_passthru:1;
1795f6fe5731SShivasharan S u32 support_fw_exposed_dev_list:1;
17969bcb1d5aSChandrakanth Patil u32 support_memdump:1;
17979bcb1d5aSChandrakanth Patil u32 reserved:15;
179894cd65ddSSumit.Saxena@lsi.com #endif
1799d46a3ad6SSumit.Saxena@lsi.com } mfi_capabilities;
18009ab9ed38SChristoph Hellwig __le32 reg;
1801d46a3ad6SSumit.Saxena@lsi.com } MFI_CAPABILITIES;
1802d46a3ad6SSumit.Saxena@lsi.com
1803c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame {
1804c4a3e0a5SBagalkote, Sreenivas
1805c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1806c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */
1807c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1808c4a3e0a5SBagalkote, Sreenivas
1809c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */
1810d46a3ad6SSumit.Saxena@lsi.com MFI_CAPABILITIES driver_operations; /*04h*/
1811c4a3e0a5SBagalkote, Sreenivas
18129ab9ed38SChristoph Hellwig __le32 context; /*08h */
18139ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1814c4a3e0a5SBagalkote, Sreenivas
18159ab9ed38SChristoph Hellwig __le16 flags; /*10h */
1816ea836f40SChandrakanth Patil __le16 replyqueue_mask; /*12h */
18179ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */
1818c4a3e0a5SBagalkote, Sreenivas
18199ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_lo; /*18h */
18209ab9ed38SChristoph Hellwig __le32 queue_info_new_phys_addr_hi; /*1Ch */
18219ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_lo; /*20h */
18229ab9ed38SChristoph Hellwig __le32 queue_info_old_phys_addr_hi; /*24h */
18239ab9ed38SChristoph Hellwig __le32 reserved_4[2]; /*28h */
18249ab9ed38SChristoph Hellwig __le32 system_info_lo; /*30h */
18259ab9ed38SChristoph Hellwig __le32 system_info_hi; /*34h */
18269ab9ed38SChristoph Hellwig __le32 reserved_5[2]; /*38h */
1827c4a3e0a5SBagalkote, Sreenivas
1828c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1829c4a3e0a5SBagalkote, Sreenivas
1830c4a3e0a5SBagalkote, Sreenivas struct megasas_init_queue_info {
1831c4a3e0a5SBagalkote, Sreenivas
18329ab9ed38SChristoph Hellwig __le32 init_flags; /*00h */
18339ab9ed38SChristoph Hellwig __le32 reply_queue_entries; /*04h */
1834c4a3e0a5SBagalkote, Sreenivas
18359ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_lo; /*08h */
18369ab9ed38SChristoph Hellwig __le32 reply_queue_start_phys_addr_hi; /*0Ch */
18379ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_lo; /*10h */
18389ab9ed38SChristoph Hellwig __le32 producer_index_phys_addr_hi; /*14h */
18399ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_lo; /*18h */
18409ab9ed38SChristoph Hellwig __le32 consumer_index_phys_addr_hi; /*1Ch */
1841c4a3e0a5SBagalkote, Sreenivas
1842c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1843c4a3e0a5SBagalkote, Sreenivas
1844c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame {
1845c4a3e0a5SBagalkote, Sreenivas
1846c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1847c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */
1848c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1849c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */
1850c4a3e0a5SBagalkote, Sreenivas
1851c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */
1852c4a3e0a5SBagalkote, Sreenivas u8 access_byte; /*05h */
1853c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*06h */
1854c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1855c4a3e0a5SBagalkote, Sreenivas
18569ab9ed38SChristoph Hellwig __le32 context; /*08h */
18579ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1858c4a3e0a5SBagalkote, Sreenivas
18599ab9ed38SChristoph Hellwig __le16 flags; /*10h */
18609ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
18619ab9ed38SChristoph Hellwig __le32 lba_count; /*14h */
1862c4a3e0a5SBagalkote, Sreenivas
18639ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */
18649ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */
1865c4a3e0a5SBagalkote, Sreenivas
18669ab9ed38SChristoph Hellwig __le32 start_lba_lo; /*20h */
18679ab9ed38SChristoph Hellwig __le32 start_lba_hi; /*24h */
1868c4a3e0a5SBagalkote, Sreenivas
1869c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */
1870c4a3e0a5SBagalkote, Sreenivas
1871c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1872c4a3e0a5SBagalkote, Sreenivas
1873c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame {
1874c4a3e0a5SBagalkote, Sreenivas
1875c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1876c4a3e0a5SBagalkote, Sreenivas u8 sense_len; /*01h */
1877c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1878c4a3e0a5SBagalkote, Sreenivas u8 scsi_status; /*03h */
1879c4a3e0a5SBagalkote, Sreenivas
1880c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */
1881c4a3e0a5SBagalkote, Sreenivas u8 lun; /*05h */
1882c4a3e0a5SBagalkote, Sreenivas u8 cdb_len; /*06h */
1883c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1884c4a3e0a5SBagalkote, Sreenivas
18859ab9ed38SChristoph Hellwig __le32 context; /*08h */
18869ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1887c4a3e0a5SBagalkote, Sreenivas
18889ab9ed38SChristoph Hellwig __le16 flags; /*10h */
18899ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
18909ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */
1891c4a3e0a5SBagalkote, Sreenivas
18929ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_lo; /*18h */
18939ab9ed38SChristoph Hellwig __le32 sense_buf_phys_addr_hi; /*1Ch */
1894c4a3e0a5SBagalkote, Sreenivas
1895c4a3e0a5SBagalkote, Sreenivas u8 cdb[16]; /*20h */
1896c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*30h */
1897c4a3e0a5SBagalkote, Sreenivas
1898c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1899c4a3e0a5SBagalkote, Sreenivas
1900c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame {
1901c4a3e0a5SBagalkote, Sreenivas
1902c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1903c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */
1904c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1905c4a3e0a5SBagalkote, Sreenivas u8 reserved_1[4]; /*03h */
1906c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1907c4a3e0a5SBagalkote, Sreenivas
19089ab9ed38SChristoph Hellwig __le32 context; /*08h */
19099ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1910c4a3e0a5SBagalkote, Sreenivas
19119ab9ed38SChristoph Hellwig __le16 flags; /*10h */
19129ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
1913c4a3e0a5SBagalkote, Sreenivas
19149ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */
19159ab9ed38SChristoph Hellwig __le32 opcode; /*18h */
1916c4a3e0a5SBagalkote, Sreenivas
1917c4a3e0a5SBagalkote, Sreenivas union { /*1Ch */
1918c4a3e0a5SBagalkote, Sreenivas u8 b[12];
19199ab9ed38SChristoph Hellwig __le16 s[6];
19209ab9ed38SChristoph Hellwig __le32 w[3];
1921c4a3e0a5SBagalkote, Sreenivas } mbox;
1922c4a3e0a5SBagalkote, Sreenivas
1923c4a3e0a5SBagalkote, Sreenivas union megasas_sgl sgl; /*28h */
1924c4a3e0a5SBagalkote, Sreenivas
1925c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1926c4a3e0a5SBagalkote, Sreenivas
1927c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame {
1928c4a3e0a5SBagalkote, Sreenivas
1929c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1930c4a3e0a5SBagalkote, Sreenivas u8 reserved_0; /*01h */
1931c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1932c4a3e0a5SBagalkote, Sreenivas
1933c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*03h */
19349ab9ed38SChristoph Hellwig __le32 reserved_2; /*04h */
1935c4a3e0a5SBagalkote, Sreenivas
19369ab9ed38SChristoph Hellwig __le32 context; /*08h */
19379ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1938c4a3e0a5SBagalkote, Sreenivas
19399ab9ed38SChristoph Hellwig __le16 flags; /*10h */
19409ab9ed38SChristoph Hellwig __le16 reserved_3; /*12h */
19419ab9ed38SChristoph Hellwig __le32 reserved_4; /*14h */
1942c4a3e0a5SBagalkote, Sreenivas
19439ab9ed38SChristoph Hellwig __le32 abort_context; /*18h */
19449ab9ed38SChristoph Hellwig __le32 pad_1; /*1Ch */
1945c4a3e0a5SBagalkote, Sreenivas
19469ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_lo; /*20h */
19479ab9ed38SChristoph Hellwig __le32 abort_mfi_phys_addr_hi; /*24h */
1948c4a3e0a5SBagalkote, Sreenivas
19499ab9ed38SChristoph Hellwig __le32 reserved_5[6]; /*28h */
1950c4a3e0a5SBagalkote, Sreenivas
1951c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1952c4a3e0a5SBagalkote, Sreenivas
1953c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame {
1954c4a3e0a5SBagalkote, Sreenivas
1955c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1956c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */
1957c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1958c4a3e0a5SBagalkote, Sreenivas u8 connection_status; /*03h */
1959c4a3e0a5SBagalkote, Sreenivas
1960c4a3e0a5SBagalkote, Sreenivas u8 reserved_2[3]; /*04h */
1961c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1962c4a3e0a5SBagalkote, Sreenivas
19639ab9ed38SChristoph Hellwig __le32 context; /*08h */
19649ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1965c4a3e0a5SBagalkote, Sreenivas
19669ab9ed38SChristoph Hellwig __le16 flags; /*10h */
19679ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
1968c4a3e0a5SBagalkote, Sreenivas
19699ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */
19709ab9ed38SChristoph Hellwig __le64 sas_addr; /*18h */
1971c4a3e0a5SBagalkote, Sreenivas
1972c4a3e0a5SBagalkote, Sreenivas union {
1973c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1974c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1975c4a3e0a5SBagalkote, Sreenivas } sgl;
1976c4a3e0a5SBagalkote, Sreenivas
1977c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
1978c4a3e0a5SBagalkote, Sreenivas
1979c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame {
1980c4a3e0a5SBagalkote, Sreenivas
1981c4a3e0a5SBagalkote, Sreenivas u8 cmd; /*00h */
1982c4a3e0a5SBagalkote, Sreenivas u8 reserved_1; /*01h */
1983c4a3e0a5SBagalkote, Sreenivas u8 cmd_status; /*02h */
1984c4a3e0a5SBagalkote, Sreenivas u8 reserved_2; /*03h */
1985c4a3e0a5SBagalkote, Sreenivas
1986c4a3e0a5SBagalkote, Sreenivas u8 target_id; /*04h */
1987c4a3e0a5SBagalkote, Sreenivas u8 reserved_3[2]; /*05h */
1988c4a3e0a5SBagalkote, Sreenivas u8 sge_count; /*07h */
1989c4a3e0a5SBagalkote, Sreenivas
19909ab9ed38SChristoph Hellwig __le32 context; /*08h */
19919ab9ed38SChristoph Hellwig __le32 pad_0; /*0Ch */
1992c4a3e0a5SBagalkote, Sreenivas
19939ab9ed38SChristoph Hellwig __le16 flags; /*10h */
19949ab9ed38SChristoph Hellwig __le16 timeout; /*12h */
1995c4a3e0a5SBagalkote, Sreenivas
19969ab9ed38SChristoph Hellwig __le32 data_xfer_len; /*14h */
1997c4a3e0a5SBagalkote, Sreenivas
19989ab9ed38SChristoph Hellwig __le16 fis[10]; /*18h */
19999ab9ed38SChristoph Hellwig __le32 stp_flags;
2000c4a3e0a5SBagalkote, Sreenivas
2001c4a3e0a5SBagalkote, Sreenivas union {
2002c4a3e0a5SBagalkote, Sreenivas struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
2003c4a3e0a5SBagalkote, Sreenivas struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
2004c4a3e0a5SBagalkote, Sreenivas } sgl;
2005c4a3e0a5SBagalkote, Sreenivas
2006c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2007c4a3e0a5SBagalkote, Sreenivas
2008c4a3e0a5SBagalkote, Sreenivas union megasas_frame {
2009c4a3e0a5SBagalkote, Sreenivas
2010c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr;
2011c4a3e0a5SBagalkote, Sreenivas struct megasas_init_frame init;
2012c4a3e0a5SBagalkote, Sreenivas struct megasas_io_frame io;
2013c4a3e0a5SBagalkote, Sreenivas struct megasas_pthru_frame pthru;
2014c4a3e0a5SBagalkote, Sreenivas struct megasas_dcmd_frame dcmd;
2015c4a3e0a5SBagalkote, Sreenivas struct megasas_abort_frame abort;
2016c4a3e0a5SBagalkote, Sreenivas struct megasas_smp_frame smp;
2017c4a3e0a5SBagalkote, Sreenivas struct megasas_stp_frame stp;
2018c4a3e0a5SBagalkote, Sreenivas
2019c4a3e0a5SBagalkote, Sreenivas u8 raw_bytes[64];
2020c4a3e0a5SBagalkote, Sreenivas };
2021c4a3e0a5SBagalkote, Sreenivas
202218365b13SSumit Saxena /**
202318365b13SSumit Saxena * struct MR_PRIV_DEVICE - sdev private hostdata
202418365b13SSumit Saxena * @is_tm_capable: firmware managed tm_capable flag
202518365b13SSumit Saxena * @tm_busy: TM request is in progress
20266cb9b152SKashyap Desai * @sdev_priv_busy: pending command per sdev
202718365b13SSumit Saxena */
202818365b13SSumit Saxena struct MR_PRIV_DEVICE {
202918365b13SSumit Saxena bool is_tm_capable;
203018365b13SSumit Saxena bool tm_busy;
20316cb9b152SKashyap Desai atomic_t sdev_priv_busy;
2032a48ba0ecSShivasharan S atomic_t r1_ldio_hint;
203315dd0381SShivasharan S u8 interface_type;
2034e9495e2dSShivasharan S u8 task_abort_tmo;
2035e9495e2dSShivasharan S u8 target_reset_tmo;
203618365b13SSumit Saxena };
2037c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd;
2038c4a3e0a5SBagalkote, Sreenivas
2039c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale {
2040c4a3e0a5SBagalkote, Sreenivas
2041c4a3e0a5SBagalkote, Sreenivas struct {
2042be26374bSSumit.Saxena@lsi.com #ifndef __BIG_ENDIAN_BITFIELD
2043c4a3e0a5SBagalkote, Sreenivas u16 locale;
2044c4a3e0a5SBagalkote, Sreenivas u8 reserved;
2045c4a3e0a5SBagalkote, Sreenivas s8 class;
2046be26374bSSumit.Saxena@lsi.com #else
2047be26374bSSumit.Saxena@lsi.com s8 class;
2048be26374bSSumit.Saxena@lsi.com u8 reserved;
2049be26374bSSumit.Saxena@lsi.com u16 locale;
2050be26374bSSumit.Saxena@lsi.com #endif
2051c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) members;
2052c4a3e0a5SBagalkote, Sreenivas
2053c4a3e0a5SBagalkote, Sreenivas u32 word;
2054c4a3e0a5SBagalkote, Sreenivas
2055c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2056c4a3e0a5SBagalkote, Sreenivas
2057c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_log_info {
20589ab9ed38SChristoph Hellwig __le32 newest_seq_num;
20599ab9ed38SChristoph Hellwig __le32 oldest_seq_num;
20609ab9ed38SChristoph Hellwig __le32 clear_seq_num;
20619ab9ed38SChristoph Hellwig __le32 shutdown_seq_num;
20629ab9ed38SChristoph Hellwig __le32 boot_seq_num;
2063c4a3e0a5SBagalkote, Sreenivas
2064c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2065c4a3e0a5SBagalkote, Sreenivas
2066c4a3e0a5SBagalkote, Sreenivas struct megasas_progress {
2067c4a3e0a5SBagalkote, Sreenivas
20689ab9ed38SChristoph Hellwig __le16 progress;
20699ab9ed38SChristoph Hellwig __le16 elapsed_seconds;
2070c4a3e0a5SBagalkote, Sreenivas
2071c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2072c4a3e0a5SBagalkote, Sreenivas
2073c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld {
2074c4a3e0a5SBagalkote, Sreenivas
2075c4a3e0a5SBagalkote, Sreenivas u16 target_id;
2076c4a3e0a5SBagalkote, Sreenivas u8 ld_index;
2077c4a3e0a5SBagalkote, Sreenivas u8 reserved;
2078c4a3e0a5SBagalkote, Sreenivas
2079c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2080c4a3e0a5SBagalkote, Sreenivas
2081c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd {
2082c4a3e0a5SBagalkote, Sreenivas u16 device_id;
2083c4a3e0a5SBagalkote, Sreenivas u8 encl_index;
2084c4a3e0a5SBagalkote, Sreenivas u8 slot_number;
2085c4a3e0a5SBagalkote, Sreenivas
2086c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2087c4a3e0a5SBagalkote, Sreenivas
2088c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail {
2089c4a3e0a5SBagalkote, Sreenivas
20909ab9ed38SChristoph Hellwig __le32 seq_num;
20919ab9ed38SChristoph Hellwig __le32 time_stamp;
20929ab9ed38SChristoph Hellwig __le32 code;
2093c4a3e0a5SBagalkote, Sreenivas union megasas_evt_class_locale cl;
2094c4a3e0a5SBagalkote, Sreenivas u8 arg_type;
2095c4a3e0a5SBagalkote, Sreenivas u8 reserved1[15];
2096c4a3e0a5SBagalkote, Sreenivas
2097c4a3e0a5SBagalkote, Sreenivas union {
2098c4a3e0a5SBagalkote, Sreenivas struct {
2099c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2100c4a3e0a5SBagalkote, Sreenivas u8 cdb_length;
2101c4a3e0a5SBagalkote, Sreenivas u8 sense_length;
2102c4a3e0a5SBagalkote, Sreenivas u8 reserved[2];
2103c4a3e0a5SBagalkote, Sreenivas u8 cdb[16];
2104c4a3e0a5SBagalkote, Sreenivas u8 sense[64];
2105c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) cdbSense;
2106c4a3e0a5SBagalkote, Sreenivas
2107c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2108c4a3e0a5SBagalkote, Sreenivas
2109c4a3e0a5SBagalkote, Sreenivas struct {
2110c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
21119ab9ed38SChristoph Hellwig __le64 count;
2112c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_count;
2113c4a3e0a5SBagalkote, Sreenivas
2114c4a3e0a5SBagalkote, Sreenivas struct {
21159ab9ed38SChristoph Hellwig __le64 lba;
2116c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2117c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba;
2118c4a3e0a5SBagalkote, Sreenivas
2119c4a3e0a5SBagalkote, Sreenivas struct {
2120c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
21219ab9ed38SChristoph Hellwig __le32 prevOwner;
21229ab9ed38SChristoph Hellwig __le32 newOwner;
2123c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_owner;
2124c4a3e0a5SBagalkote, Sreenivas
2125c4a3e0a5SBagalkote, Sreenivas struct {
2126c4a3e0a5SBagalkote, Sreenivas u64 ld_lba;
2127c4a3e0a5SBagalkote, Sreenivas u64 pd_lba;
2128c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2129c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2130c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_lba_pd_lba;
2131c4a3e0a5SBagalkote, Sreenivas
2132c4a3e0a5SBagalkote, Sreenivas struct {
2133c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2134c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog;
2135c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_prog;
2136c4a3e0a5SBagalkote, Sreenivas
2137c4a3e0a5SBagalkote, Sreenivas struct {
2138c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2139c4a3e0a5SBagalkote, Sreenivas u32 prev_state;
2140c4a3e0a5SBagalkote, Sreenivas u32 new_state;
2141c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_state;
2142c4a3e0a5SBagalkote, Sreenivas
2143c4a3e0a5SBagalkote, Sreenivas struct {
2144c4a3e0a5SBagalkote, Sreenivas u64 strip;
2145c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2146c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ld_strip;
2147c4a3e0a5SBagalkote, Sreenivas
2148c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2149c4a3e0a5SBagalkote, Sreenivas
2150c4a3e0a5SBagalkote, Sreenivas struct {
2151c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2152c4a3e0a5SBagalkote, Sreenivas u32 err;
2153c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_err;
2154c4a3e0a5SBagalkote, Sreenivas
2155c4a3e0a5SBagalkote, Sreenivas struct {
2156c4a3e0a5SBagalkote, Sreenivas u64 lba;
2157c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2158c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba;
2159c4a3e0a5SBagalkote, Sreenivas
2160c4a3e0a5SBagalkote, Sreenivas struct {
2161c4a3e0a5SBagalkote, Sreenivas u64 lba;
2162c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2163c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_ld ld;
2164c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_lba_ld;
2165c4a3e0a5SBagalkote, Sreenivas
2166c4a3e0a5SBagalkote, Sreenivas struct {
2167c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2168c4a3e0a5SBagalkote, Sreenivas struct megasas_progress prog;
2169c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_prog;
2170c4a3e0a5SBagalkote, Sreenivas
2171c4a3e0a5SBagalkote, Sreenivas struct {
2172c4a3e0a5SBagalkote, Sreenivas struct megasas_evtarg_pd pd;
2173c4a3e0a5SBagalkote, Sreenivas u32 prevState;
2174c4a3e0a5SBagalkote, Sreenivas u32 newState;
2175c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pd_state;
2176c4a3e0a5SBagalkote, Sreenivas
2177c4a3e0a5SBagalkote, Sreenivas struct {
2178c4a3e0a5SBagalkote, Sreenivas u16 vendorId;
21799ab9ed38SChristoph Hellwig __le16 deviceId;
2180c4a3e0a5SBagalkote, Sreenivas u16 subVendorId;
2181c4a3e0a5SBagalkote, Sreenivas u16 subDeviceId;
2182c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) pci;
2183c4a3e0a5SBagalkote, Sreenivas
2184c4a3e0a5SBagalkote, Sreenivas u32 rate;
2185c4a3e0a5SBagalkote, Sreenivas char str[96];
2186c4a3e0a5SBagalkote, Sreenivas
2187c4a3e0a5SBagalkote, Sreenivas struct {
2188c4a3e0a5SBagalkote, Sreenivas u32 rtc;
2189c4a3e0a5SBagalkote, Sreenivas u32 elapsedSeconds;
2190c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) time;
2191c4a3e0a5SBagalkote, Sreenivas
2192c4a3e0a5SBagalkote, Sreenivas struct {
2193c4a3e0a5SBagalkote, Sreenivas u32 ecar;
2194c4a3e0a5SBagalkote, Sreenivas u32 elog;
2195c4a3e0a5SBagalkote, Sreenivas char str[64];
2196c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed)) ecc;
2197c4a3e0a5SBagalkote, Sreenivas
2198c4a3e0a5SBagalkote, Sreenivas u8 b[96];
21999ab9ed38SChristoph Hellwig __le16 s[48];
22009ab9ed38SChristoph Hellwig __le32 w[24];
22019ab9ed38SChristoph Hellwig __le64 d[12];
2202c4a3e0a5SBagalkote, Sreenivas } args;
2203c4a3e0a5SBagalkote, Sreenivas
2204c4a3e0a5SBagalkote, Sreenivas char description[128];
2205c4a3e0a5SBagalkote, Sreenivas
2206c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2207c4a3e0a5SBagalkote, Sreenivas
22087e8a75f4SYang, Bo struct megasas_aen_event {
2209c1d390d8SXiaotian Feng struct delayed_work hotplug_work;
22107e8a75f4SYang, Bo struct megasas_instance *instance;
22117e8a75f4SYang, Bo };
22127e8a75f4SYang, Bo
2213c8e858feSadam radford struct megasas_irq_context {
2214ff7ca7fdSChandrakanth Patil char name[MEGASAS_MSIX_NAME_LEN];
2215c8e858feSadam radford struct megasas_instance *instance;
2216c8e858feSadam radford u32 MSIxIndex;
221762a04f81SShivasharan S u32 os_irq;
221862a04f81SShivasharan S struct irq_poll irqpoll;
221962a04f81SShivasharan S bool irq_poll_scheduled;
2220a6ffd5bfSChandrakanth Patil bool irq_line_enable;
22219e4bec5bSKashyap Desai atomic_t in_used;
2222c8e858feSadam radford };
2223c8e858feSadam radford
22245765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO {
22255765c5b8SSumit.Saxena@avagotech.com u8 infoVersion;
22265765c5b8SSumit.Saxena@avagotech.com u8 systemIdLength;
22275765c5b8SSumit.Saxena@avagotech.com u16 reserved0;
22285765c5b8SSumit.Saxena@avagotech.com u8 systemId[64];
22295765c5b8SSumit.Saxena@avagotech.com u8 reserved[1980];
22305765c5b8SSumit.Saxena@avagotech.com };
22315765c5b8SSumit.Saxena@avagotech.com
22322216c305SSumit Saxena enum MR_PD_TYPE {
22332216c305SSumit Saxena UNKNOWN_DRIVE = 0,
22342216c305SSumit Saxena PARALLEL_SCSI = 1,
22352216c305SSumit Saxena SAS_PD = 2,
22362216c305SSumit Saxena SATA_PD = 3,
22372216c305SSumit Saxena FC_PD = 4,
223815dd0381SShivasharan S NVME_PD = 5,
22392216c305SSumit Saxena };
22402216c305SSumit Saxena
22412216c305SSumit Saxena /* JBOD Queue depth definitions */
22422216c305SSumit Saxena #define MEGASAS_SATA_QD 32
22436e735506SAnand Lodnoor #define MEGASAS_SAS_QD 256
22442216c305SSumit Saxena #define MEGASAS_DEFAULT_PD_QD 64
22456e735506SAnand Lodnoor #define MEGASAS_NVME_QD 64
224615dd0381SShivasharan S
224715dd0381SShivasharan S #define MR_DEFAULT_NVME_PAGE_SIZE 4096
224815dd0381SShivasharan S #define MR_DEFAULT_NVME_PAGE_SHIFT 12
224915dd0381SShivasharan S #define MR_DEFAULT_NVME_MDTS_KB 128
225015dd0381SShivasharan S #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
22512216c305SSumit Saxena
2252132147d7SChandrakanth Patil /*Aero performance parameters*/
2253132147d7SChandrakanth Patil #define MR_HIGH_IOPS_QUEUE_COUNT 8
2254f39e5e52SChandrakanth Patil #define MR_DEVICE_HIGH_IOPS_DEPTH 8
2255f39e5e52SChandrakanth Patil #define MR_HIGH_IOPS_BATCH_COUNT 16
2256132147d7SChandrakanth Patil
2257299ee426SChandrakanth Patil enum MR_PERF_MODE {
2258299ee426SChandrakanth Patil MR_BALANCED_PERF_MODE = 0,
2259299ee426SChandrakanth Patil MR_IOPS_PERF_MODE = 1,
2260299ee426SChandrakanth Patil MR_LATENCY_PERF_MODE = 2,
2261299ee426SChandrakanth Patil };
2262299ee426SChandrakanth Patil
2263299ee426SChandrakanth Patil #define MEGASAS_PERF_MODE_2STR(mode) \
2264299ee426SChandrakanth Patil ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2265299ee426SChandrakanth Patil (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2266299ee426SChandrakanth Patil (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2267299ee426SChandrakanth Patil "Unknown")
2268299ee426SChandrakanth Patil
2269ae6874baSKashyap Desai enum MEGASAS_LD_TARGET_ID_STATUS {
2270ae6874baSKashyap Desai LD_TARGET_ID_INITIAL,
2271ae6874baSKashyap Desai LD_TARGET_ID_ACTIVE,
2272ae6874baSKashyap Desai LD_TARGET_ID_DELETED,
2273ae6874baSKashyap Desai };
2274ae6874baSKashyap Desai
2275ae6874baSKashyap Desai #define MEGASAS_TARGET_ID(sdev) \
2276ae6874baSKashyap Desai (((sdev->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id)
2277ae6874baSKashyap Desai
2278c4a3e0a5SBagalkote, Sreenivas struct megasas_instance {
2279c4a3e0a5SBagalkote, Sreenivas
2280adbe5523SMing Lei unsigned int *reply_map;
22819ab9ed38SChristoph Hellwig __le32 *producer;
2282c4a3e0a5SBagalkote, Sreenivas dma_addr_t producer_h;
22839ab9ed38SChristoph Hellwig __le32 *consumer;
2284c4a3e0a5SBagalkote, Sreenivas dma_addr_t consumer_h;
22855765c5b8SSumit.Saxena@avagotech.com struct MR_DRV_SYSTEM_INFO *system_info_buf;
22865765c5b8SSumit.Saxena@avagotech.com dma_addr_t system_info_h;
2287229fe47cSadam radford struct MR_LD_VF_AFFILIATION *vf_affiliation;
2288229fe47cSadam radford dma_addr_t vf_affiliation_h;
2289229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2290229fe47cSadam radford dma_addr_t vf_affiliation_111_h;
2291229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2292229fe47cSadam radford dma_addr_t hb_host_mem_h;
22932216c305SSumit Saxena struct MR_PD_INFO *pd_info;
22942216c305SSumit Saxena dma_addr_t pd_info_h;
229596188a89SShivasharan S struct MR_TARGET_PROPERTIES *tgt_prop;
229696188a89SShivasharan S dma_addr_t tgt_prop_h;
2297c4a3e0a5SBagalkote, Sreenivas
22989ab9ed38SChristoph Hellwig __le32 *reply_queue;
2299c4a3e0a5SBagalkote, Sreenivas dma_addr_t reply_queue_h;
2300c4a3e0a5SBagalkote, Sreenivas
2301fc62b3fcSSumit.Saxena@avagotech.com u32 *crash_dump_buf;
2302fc62b3fcSSumit.Saxena@avagotech.com dma_addr_t crash_dump_h;
23039b3d028fSShivasharan S
23049b3d028fSShivasharan S struct MR_PD_LIST *pd_list_buf;
23059b3d028fSShivasharan S dma_addr_t pd_list_buf_h;
23069b3d028fSShivasharan S
23079b3d028fSShivasharan S struct megasas_ctrl_info *ctrl_info_buf;
23089b3d028fSShivasharan S dma_addr_t ctrl_info_buf_h;
23099b3d028fSShivasharan S
23109b3d028fSShivasharan S struct MR_LD_LIST *ld_list_buf;
23119b3d028fSShivasharan S dma_addr_t ld_list_buf_h;
23129b3d028fSShivasharan S
23139b3d028fSShivasharan S struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
23149b3d028fSShivasharan S dma_addr_t ld_targetid_list_buf_h;
23159b3d028fSShivasharan S
2316f6fe5731SShivasharan S struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2317f6fe5731SShivasharan S dma_addr_t host_device_list_buf_h;
2318f6fe5731SShivasharan S
2319f0c21df6SShivasharan S struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2320f0c21df6SShivasharan S dma_addr_t snapdump_prop_h;
2321f0c21df6SShivasharan S
2322fc62b3fcSSumit.Saxena@avagotech.com void *crash_buf[MAX_CRASH_DUMP_SIZE];
2323fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_size;
2324fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_state;
2325fc62b3fcSSumit.Saxena@avagotech.com unsigned int fw_crash_buffer_offset;
2326fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_index;
2327fc62b3fcSSumit.Saxena@avagotech.com u32 drv_buf_alloc;
2328fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_fw_support;
2329fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_drv_support;
2330fc62b3fcSSumit.Saxena@avagotech.com u32 crash_dump_app_support;
23317497cde8SSumit.Saxena@avagotech.com u32 secure_jbod_support;
2332ede7c3ceSSasikumar Chandrasekaran u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
23333761cb4cSsumit.saxena@avagotech.com bool use_seqnum_jbod_fp; /* Added for PD sequence */
23341d15d909SShivasharan S bool smp_affinity_enable;
2335*0b0747d5SJunxiao Bi struct mutex crashdump_lock;
2336fc62b3fcSSumit.Saxena@avagotech.com
2337c4a3e0a5SBagalkote, Sreenivas struct megasas_register_set __iomem *reg_set;
23388a232bb3SChristoph Hellwig u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
233981e403ceSYang, Bo struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
2340999ece0aSSumit.Saxena@lsi.com struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
2341bdc6fb8dSYang, Bo u8 ld_ids[MEGASAS_MAX_LD_IDS];
2342ae6874baSKashyap Desai u8 ld_tgtid_status[MEGASAS_MAX_LD_IDS];
2343ae6874baSKashyap Desai u8 ld_ids_prev[MEGASAS_MAX_LD_IDS];
2344ae6874baSKashyap Desai u8 ld_ids_from_raidmap[MEGASAS_MAX_LD_IDS];
2345c4a3e0a5SBagalkote, Sreenivas s8 init_id;
2346c4a3e0a5SBagalkote, Sreenivas
2347c4a3e0a5SBagalkote, Sreenivas u16 max_num_sge;
2348c4a3e0a5SBagalkote, Sreenivas u16 max_fw_cmds;
234969c337c0SSasikumar Chandrasekaran u16 max_mpt_cmds;
23509c915a8cSadam radford u16 max_mfi_cmds;
2351ae09a6c1SSumit.Saxena@avagotech.com u16 max_scsi_cmds;
2352308ec459SSumit Saxena u16 ldio_threshold;
2353308ec459SSumit Saxena u16 cur_can_queue;
2354c4a3e0a5SBagalkote, Sreenivas u32 max_sectors_per_req;
23551d15d909SShivasharan S bool msix_load_balance;
23567e8a75f4SYang, Bo struct megasas_aen_event *ev;
2357c4a3e0a5SBagalkote, Sreenivas
2358c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd **cmd_list;
2359c4a3e0a5SBagalkote, Sreenivas struct list_head cmd_pool;
236039a98554Sbo yang /* used to sync fire the cmd to fw */
236190dc9d98SSumit.Saxena@avagotech.com spinlock_t mfi_pool_lock;
236239a98554Sbo yang /* used to sync fire the cmd to fw */
236339a98554Sbo yang spinlock_t hba_lock;
23647343eb65Sbo yang /* used to synch producer, consumer ptrs in dpc */
2365fdd84e25SSasikumar Chandrasekaran spinlock_t stream_lock;
23667343eb65Sbo yang spinlock_t completion_lock;
2367c4a3e0a5SBagalkote, Sreenivas struct dma_pool *frame_dma_pool;
2368c4a3e0a5SBagalkote, Sreenivas struct dma_pool *sense_dma_pool;
2369c4a3e0a5SBagalkote, Sreenivas
2370c4a3e0a5SBagalkote, Sreenivas struct megasas_evt_detail *evt_detail;
2371c4a3e0a5SBagalkote, Sreenivas dma_addr_t evt_detail_h;
2372c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd *aen_cmd;
2373c4a3e0a5SBagalkote, Sreenivas struct semaphore ioctl_sem;
2374c4a3e0a5SBagalkote, Sreenivas
2375c4a3e0a5SBagalkote, Sreenivas struct Scsi_Host *host;
2376c4a3e0a5SBagalkote, Sreenivas
2377c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t int_cmd_wait_q;
2378c4a3e0a5SBagalkote, Sreenivas wait_queue_head_t abort_cmd_wait_q;
2379c4a3e0a5SBagalkote, Sreenivas
2380c4a3e0a5SBagalkote, Sreenivas struct pci_dev *pdev;
2381c4a3e0a5SBagalkote, Sreenivas u32 unique_id;
238239a98554Sbo yang u32 fw_support_ieee;
238362a04f81SShivasharan S u32 threshold_reply_count;
2384c4a3e0a5SBagalkote, Sreenivas
2385e4a082c7SSumant Patro atomic_t fw_outstanding;
2386308ec459SSumit Saxena atomic_t ldio_outstanding;
238739a98554Sbo yang atomic_t fw_reset_no_pci_access;
23881d15d909SShivasharan S atomic64_t total_io_count;
2389f39e5e52SChandrakanth Patil atomic64_t high_iops_outstanding;
23901341c939SSumant Patro
23911341c939SSumant Patro struct megasas_instance_template *instancet;
23925d018ad0SSumant Patro struct tasklet_struct isr_tasklet;
239339a98554Sbo yang struct work_struct work_init;
23943f6194afSShivasharan S struct delayed_work fw_fault_work;
23953f6194afSShivasharan S struct workqueue_struct *fw_fault_work_q;
23963f6194afSShivasharan S char fault_handler_work_q_name[48];
239705e9ebbeSSumant Patro
239805e9ebbeSSumant Patro u8 flag;
2399c3518837SYang, Bo u8 unload;
2400f4c9a131SYang, Bo u8 flag_ieee;
240139a98554Sbo yang u8 issuepend_done;
240239a98554Sbo yang u8 disableOnlineCtrlReset;
2403bc93d425SSumit.Saxena@lsi.com u8 UnevenSpanSupport;
240451087a86SSumit.Saxena@avagotech.com
240551087a86SSumit.Saxena@avagotech.com u8 supportmax256vd;
240630845586SSumit Saxena u8 pd_list_not_supported;
240751087a86SSumit.Saxena@avagotech.com u16 fw_supported_vd_count;
240851087a86SSumit.Saxena@avagotech.com u16 fw_supported_pd_count;
240951087a86SSumit.Saxena@avagotech.com
241051087a86SSumit.Saxena@avagotech.com u16 drv_supported_vd_count;
241151087a86SSumit.Saxena@avagotech.com u16 drv_supported_pd_count;
241251087a86SSumit.Saxena@avagotech.com
24138a01a41dSSumit Saxena atomic_t adprecovery;
241405e9ebbeSSumant Patro unsigned long last_time;
241539a98554Sbo yang u32 mfiStatus;
241639a98554Sbo yang u32 last_seq_num;
2417ad84db2eSbo yang
241839a98554Sbo yang struct list_head internal_reset_pending_q;
241980d9da98Sadam radford
242025985edcSLucas De Marchi /* Ptr to hba specific information */
24219c915a8cSadam radford void *ctrl_context;
2422c8e858feSadam radford unsigned int msix_vectors;
2423c8e858feSadam radford struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
24249c915a8cSadam radford u64 map_id;
24253761cb4cSsumit.saxena@avagotech.com u64 pd_seq_map_id;
24269c915a8cSadam radford struct megasas_cmd *map_update_cmd;
24273761cb4cSsumit.saxena@avagotech.com struct megasas_cmd *jbod_seq_cmd;
2428b6d5d880Sadam radford unsigned long bar;
24299c915a8cSadam radford long reset_flags;
24309c915a8cSadam radford struct mutex reset_mutex;
2431229fe47cSadam radford struct timer_list sriov_heartbeat_timer;
2432229fe47cSadam radford char skip_heartbeat_timer_del;
2433229fe47cSadam radford u8 requestorId;
2434229fe47cSadam radford char PlasmaFW111;
24358f67c8c5SSumit Saxena char clusterId[MEGASAS_CLUSTER_ID_SIZE];
24368f67c8c5SSumit Saxena u8 peerIsPresent;
24378f67c8c5SSumit Saxena u8 passive;
2438ae09a6c1SSumit.Saxena@avagotech.com u16 throttlequeuedepth;
2439d46a3ad6SSumit.Saxena@lsi.com u8 mask_interrupts;
2440bd5f9484Ssumit.saxena@avagotech.com u16 max_chain_frame_sz;
2441404a8a1aSSumit.Saxena@lsi.com u8 is_imr;
2442179ac142SSumit Saxena u8 is_rdpq;
24435765c5b8SSumit.Saxena@avagotech.com bool dev_handle;
2444d0fc91d6SKashyap Desai bool fw_sync_cache_support;
244521c34006SShivasharan S u32 mfi_frame_size;
24462493c67eSSasikumar Chandrasekaran bool msix_combined;
2447d889344eSSasikumar Chandrasekaran u16 max_raid_mapsize;
2448a48ba0ecSShivasharan S /* preffered count to send as LDIO irrspective of FP capable.*/
2449a48ba0ecSShivasharan S u8 r1_ldio_hint_default;
245015dd0381SShivasharan S u32 nvme_page_size;
2451c365178fSShivasharan S u8 adapter_type;
2452107a60ddSShivasharan S bool consistent_mask_64bit;
2453f870bcbeSShivasharan S bool support_nvme_passthru;
24549ab089d3SChandrakanth Patil bool enable_sdev_max_qd;
2455e9495e2dSShivasharan S u8 task_abort_tmo;
2456e9495e2dSShivasharan S u8 max_reset_tmo;
2457f0c21df6SShivasharan S u8 snapdump_wait_time;
2458ba53572bSShivasharan S #ifdef CONFIG_DEBUG_FS
2459ba53572bSShivasharan S struct dentry *debugfs_root;
2460ba53572bSShivasharan S struct dentry *raidmap_dump;
2461ba53572bSShivasharan S #endif
2462f6fe5731SShivasharan S u8 enable_fw_dev_list;
24635885571dSChandrakanth Patil bool atomic_desc_support;
246459db5a93SChandrakanth Patil bool support_seqnum_jbod_fp;
246558136856SChandrakanth Patil bool support_pci_lane_margining;
2466132147d7SChandrakanth Patil u8 low_latency_index_start;
2467299ee426SChandrakanth Patil int perf_mode;
24689e4bec5bSKashyap Desai int iopoll_q_count;
246939a98554Sbo yang };
247059db5a93SChandrakanth Patil
2471229fe47cSadam radford struct MR_LD_VF_MAP {
2472229fe47cSadam radford u32 size;
2473229fe47cSadam radford union MR_LD_REF ref;
2474229fe47cSadam radford u8 ldVfCount;
2475229fe47cSadam radford u8 reserved[6];
2476229fe47cSadam radford u8 policy[1];
2477229fe47cSadam radford };
2478229fe47cSadam radford
2479229fe47cSadam radford struct MR_LD_VF_AFFILIATION {
2480229fe47cSadam radford u32 size;
2481229fe47cSadam radford u8 ldCount;
2482229fe47cSadam radford u8 vfCount;
2483229fe47cSadam radford u8 thisVf;
2484229fe47cSadam radford u8 reserved[9];
2485229fe47cSadam radford struct MR_LD_VF_MAP map[1];
2486229fe47cSadam radford };
2487229fe47cSadam radford
2488229fe47cSadam radford /* Plasma 1.11 FW backward compatibility structures */
2489229fe47cSadam radford #define IOV_111_OFFSET 0x7CE
2490229fe47cSadam radford #define MAX_VIRTUAL_FUNCTIONS 8
24914cbfea88SAdam Radford #define MR_LD_ACCESS_HIDDEN 15
2492229fe47cSadam radford
2493229fe47cSadam radford struct IOV_111 {
2494229fe47cSadam radford u8 maxVFsSupported;
2495229fe47cSadam radford u8 numVFsEnabled;
2496229fe47cSadam radford u8 requestorId;
2497229fe47cSadam radford u8 reserved[5];
2498229fe47cSadam radford };
2499229fe47cSadam radford
2500229fe47cSadam radford struct MR_LD_VF_MAP_111 {
2501229fe47cSadam radford u8 targetId;
2502229fe47cSadam radford u8 reserved[3];
2503229fe47cSadam radford u8 policy[MAX_VIRTUAL_FUNCTIONS];
2504229fe47cSadam radford };
2505229fe47cSadam radford
2506229fe47cSadam radford struct MR_LD_VF_AFFILIATION_111 {
2507229fe47cSadam radford u8 vdCount;
2508229fe47cSadam radford u8 vfCount;
2509229fe47cSadam radford u8 thisVf;
2510229fe47cSadam radford u8 reserved[5];
2511229fe47cSadam radford struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2512229fe47cSadam radford };
2513229fe47cSadam radford
2514229fe47cSadam radford struct MR_CTRL_HB_HOST_MEM {
2515229fe47cSadam radford struct {
2516229fe47cSadam radford u32 fwCounter; /* Firmware heart beat counter */
2517229fe47cSadam radford struct {
2518229fe47cSadam radford u32 debugmode:1; /* 1=Firmware is in debug mode.
2519229fe47cSadam radford Heart beat will not be updated. */
2520229fe47cSadam radford u32 reserved:31;
2521229fe47cSadam radford } debug;
2522229fe47cSadam radford u32 reserved_fw[6];
2523229fe47cSadam radford u32 driverCounter; /* Driver heart beat counter. 0x20 */
2524229fe47cSadam radford u32 reserved_driver[7];
2525229fe47cSadam radford } HB;
2526229fe47cSadam radford u8 pad[0x400-0x40];
2527229fe47cSadam radford };
252839a98554Sbo yang
252939a98554Sbo yang enum {
253039a98554Sbo yang MEGASAS_HBA_OPERATIONAL = 0,
253139a98554Sbo yang MEGASAS_ADPRESET_SM_INFAULT = 1,
253239a98554Sbo yang MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
253339a98554Sbo yang MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
253439a98554Sbo yang MEGASAS_HW_CRITICAL_ERROR = 4,
2535229fe47cSadam radford MEGASAS_ADPRESET_SM_POLLING = 5,
253639a98554Sbo yang MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2537c4a3e0a5SBagalkote, Sreenivas };
2538c4a3e0a5SBagalkote, Sreenivas
25390c79e681SYang, Bo struct megasas_instance_template {
25400c79e681SYang, Bo void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
25410c79e681SYang, Bo u32, struct megasas_register_set __iomem *);
25420c79e681SYang, Bo
2543d46a3ad6SSumit.Saxena@lsi.com void (*enable_intr)(struct megasas_instance *);
2544d46a3ad6SSumit.Saxena@lsi.com void (*disable_intr)(struct megasas_instance *);
25450c79e681SYang, Bo
2546de516379SShivasharan S int (*clear_intr)(struct megasas_instance *);
25470c79e681SYang, Bo
2548de516379SShivasharan S u32 (*read_fw_status_reg)(struct megasas_instance *);
254939a98554Sbo yang int (*adp_reset)(struct megasas_instance *, \
255039a98554Sbo yang struct megasas_register_set __iomem *);
255139a98554Sbo yang int (*check_reset)(struct megasas_instance *, \
255239a98554Sbo yang struct megasas_register_set __iomem *);
2553cd50ba8eSadam radford irqreturn_t (*service_isr)(int irq, void *devp);
2554cd50ba8eSadam radford void (*tasklet)(unsigned long);
2555cd50ba8eSadam radford u32 (*init_adapter)(struct megasas_instance *);
2556cd50ba8eSadam radford u32 (*build_and_issue_cmd) (struct megasas_instance *,
2557cd50ba8eSadam radford struct scsi_cmnd *);
2558f4fc2093SShivasharan S void (*issue_dcmd)(struct megasas_instance *instance,
2559cd50ba8eSadam radford struct megasas_cmd *cmd);
25600c79e681SYang, Bo };
25610c79e681SYang, Bo
25623cabd162SShivasharan S #define MEGASAS_IS_LOGICAL(sdev) \
25633cabd162SShivasharan S ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2564c4a3e0a5SBagalkote, Sreenivas
256556495f29SChandrakanth patil #define MEGASAS_IS_LUN_VALID(sdev) \
256656495f29SChandrakanth patil (((sdev)->lun == 0) ? 1 : 0)
256756495f29SChandrakanth patil
25684a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_DEV_INDEX(scp) \
25694a5c814dSSumit.Saxena@avagotech.com (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
25704a5c814dSSumit.Saxena@avagotech.com scp->device->id)
25714a5c814dSSumit.Saxena@avagotech.com
25724a5c814dSSumit.Saxena@avagotech.com #define MEGASAS_PD_INDEX(scp) \
25734a5c814dSSumit.Saxena@avagotech.com ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
25744a5c814dSSumit.Saxena@avagotech.com scp->device->id)
2575c4a3e0a5SBagalkote, Sreenivas
2576c4a3e0a5SBagalkote, Sreenivas struct megasas_cmd {
2577c4a3e0a5SBagalkote, Sreenivas
2578c4a3e0a5SBagalkote, Sreenivas union megasas_frame *frame;
2579c4a3e0a5SBagalkote, Sreenivas dma_addr_t frame_phys_addr;
2580c4a3e0a5SBagalkote, Sreenivas u8 *sense;
2581c4a3e0a5SBagalkote, Sreenivas dma_addr_t sense_phys_addr;
2582c4a3e0a5SBagalkote, Sreenivas
2583c4a3e0a5SBagalkote, Sreenivas u32 index;
2584c4a3e0a5SBagalkote, Sreenivas u8 sync_cmd;
25852be2a988SSumit.Saxena@avagotech.com u8 cmd_status_drv;
258639a98554Sbo yang u8 abort_aen;
258739a98554Sbo yang u8 retry_for_fw_reset;
258839a98554Sbo yang
2589c4a3e0a5SBagalkote, Sreenivas
2590c4a3e0a5SBagalkote, Sreenivas struct list_head list;
2591c4a3e0a5SBagalkote, Sreenivas struct scsi_cmnd *scmd;
25924026e9aaSSumit.Saxena@avagotech.com u8 flags;
259390dc9d98SSumit.Saxena@avagotech.com
2594c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance;
25959c915a8cSadam radford union {
25969c915a8cSadam radford struct {
25979c915a8cSadam radford u16 smid;
25989c915a8cSadam radford u16 resvd;
25999c915a8cSadam radford } context;
2600c4a3e0a5SBagalkote, Sreenivas u32 frame_count;
2601c4a3e0a5SBagalkote, Sreenivas };
26029c915a8cSadam radford };
2603c4a3e0a5SBagalkote, Sreenivas
260496e77a27SBart Van Assche struct megasas_cmd_priv {
260596e77a27SBart Van Assche void *cmd_priv;
260696e77a27SBart Van Assche u8 status;
260796e77a27SBart Van Assche };
260896e77a27SBart Van Assche
megasas_priv(struct scsi_cmnd * cmd)260996e77a27SBart Van Assche static inline struct megasas_cmd_priv *megasas_priv(struct scsi_cmnd *cmd)
261096e77a27SBart Van Assche {
261196e77a27SBart Van Assche return scsi_cmd_priv(cmd);
261296e77a27SBart Van Assche }
261396e77a27SBart Van Assche
2614c4a3e0a5SBagalkote, Sreenivas #define MAX_MGMT_ADAPTERS 1024
2615c4a3e0a5SBagalkote, Sreenivas #define MAX_IOCTL_SGE 16
2616c4a3e0a5SBagalkote, Sreenivas
2617c4a3e0a5SBagalkote, Sreenivas struct megasas_iocpacket {
2618c4a3e0a5SBagalkote, Sreenivas
2619c4a3e0a5SBagalkote, Sreenivas u16 host_no;
2620c4a3e0a5SBagalkote, Sreenivas u16 __pad1;
2621c4a3e0a5SBagalkote, Sreenivas u32 sgl_off;
2622c4a3e0a5SBagalkote, Sreenivas u32 sge_count;
2623c4a3e0a5SBagalkote, Sreenivas u32 sense_off;
2624c4a3e0a5SBagalkote, Sreenivas u32 sense_len;
2625c4a3e0a5SBagalkote, Sreenivas union {
2626c4a3e0a5SBagalkote, Sreenivas u8 raw[128];
2627c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr;
2628c4a3e0a5SBagalkote, Sreenivas } frame;
2629c4a3e0a5SBagalkote, Sreenivas
2630c4a3e0a5SBagalkote, Sreenivas struct iovec sgl[MAX_IOCTL_SGE];
2631c4a3e0a5SBagalkote, Sreenivas
2632c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2633c4a3e0a5SBagalkote, Sreenivas
2634c4a3e0a5SBagalkote, Sreenivas struct megasas_aen {
2635c4a3e0a5SBagalkote, Sreenivas u16 host_no;
2636c4a3e0a5SBagalkote, Sreenivas u16 __pad1;
2637c4a3e0a5SBagalkote, Sreenivas u32 seq_num;
2638c4a3e0a5SBagalkote, Sreenivas u32 class_locale_word;
2639c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2640c4a3e0a5SBagalkote, Sreenivas
2641c4a3e0a5SBagalkote, Sreenivas struct compat_megasas_iocpacket {
2642c4a3e0a5SBagalkote, Sreenivas u16 host_no;
2643c4a3e0a5SBagalkote, Sreenivas u16 __pad1;
2644c4a3e0a5SBagalkote, Sreenivas u32 sgl_off;
2645c4a3e0a5SBagalkote, Sreenivas u32 sge_count;
2646c4a3e0a5SBagalkote, Sreenivas u32 sense_off;
2647c4a3e0a5SBagalkote, Sreenivas u32 sense_len;
2648c4a3e0a5SBagalkote, Sreenivas union {
2649c4a3e0a5SBagalkote, Sreenivas u8 raw[128];
2650c4a3e0a5SBagalkote, Sreenivas struct megasas_header hdr;
2651c4a3e0a5SBagalkote, Sreenivas } frame;
2652c4a3e0a5SBagalkote, Sreenivas struct compat_iovec sgl[MAX_IOCTL_SGE];
2653c4a3e0a5SBagalkote, Sreenivas } __attribute__ ((packed));
2654c4a3e0a5SBagalkote, Sreenivas
26550e98936cSSumant Patro #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2656c4a3e0a5SBagalkote, Sreenivas
2657cb59aa6aSSumant Patro #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2658c4a3e0a5SBagalkote, Sreenivas #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2659c4a3e0a5SBagalkote, Sreenivas
2660c4a3e0a5SBagalkote, Sreenivas struct megasas_mgmt_info {
2661c4a3e0a5SBagalkote, Sreenivas
2662c4a3e0a5SBagalkote, Sreenivas u16 count;
2663c4a3e0a5SBagalkote, Sreenivas struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2664c4a3e0a5SBagalkote, Sreenivas int max_index;
2665c4a3e0a5SBagalkote, Sreenivas };
2666c4a3e0a5SBagalkote, Sreenivas
26676d40afbcSSumit Saxena enum MEGASAS_OCR_CAUSE {
26686d40afbcSSumit Saxena FW_FAULT_OCR = 0,
26696d40afbcSSumit Saxena SCSIIO_TIMEOUT_OCR = 1,
26706d40afbcSSumit Saxena MFI_IO_TIMEOUT_OCR = 2,
26716d40afbcSSumit Saxena };
26726d40afbcSSumit Saxena
26736d40afbcSSumit Saxena enum DCMD_RETURN_STATUS {
2674201a810cSAnand Lodnoor DCMD_SUCCESS = 0x00,
2675201a810cSAnand Lodnoor DCMD_TIMEOUT = 0x01,
2676201a810cSAnand Lodnoor DCMD_FAILED = 0x02,
2677201a810cSAnand Lodnoor DCMD_BUSY = 0x03,
2678201a810cSAnand Lodnoor DCMD_INIT = 0xff,
26796d40afbcSSumit Saxena };
26806d40afbcSSumit Saxena
268121c9e160Sadam radford u8
268221c9e160Sadam radford MR_BuildRaidContext(struct megasas_instance *instance,
268321c9e160Sadam radford struct IO_REQUEST_INFO *io_info,
268421c9e160Sadam radford struct RAID_CONTEXT *pRAID_Context,
268551087a86SSumit.Saxena@avagotech.com struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2686d2d0358bSShivasharan S u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
268751087a86SSumit.Saxena@avagotech.com struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
268851087a86SSumit.Saxena@avagotech.com u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
268951087a86SSumit.Saxena@avagotech.com u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
26909ab9ed38SChristoph Hellwig __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
269151087a86SSumit.Saxena@avagotech.com u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
269221c9e160Sadam radford
26939ab9ed38SChristoph Hellwig __le16 get_updated_dev_handle(struct megasas_instance *instance,
269433203bc4SShivasharan S struct LD_LOAD_BALANCE_INFO *lbInfo,
269533203bc4SShivasharan S struct IO_REQUEST_INFO *in_info,
269633203bc4SShivasharan S struct MR_DRV_RAID_MAP_ALL *drv_map);
269751087a86SSumit.Saxena@avagotech.com void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
269851087a86SSumit.Saxena@avagotech.com struct LD_LOAD_BALANCE_INFO *lbInfo);
2699d009b576SSumit.Saxena@avagotech.com int megasas_get_ctrl_info(struct megasas_instance *instance);
27003761cb4cSsumit.saxena@avagotech.com /* PD sequence */
27013761cb4cSsumit.saxena@avagotech.com int
27023761cb4cSsumit.saxena@avagotech.com megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2703e9495e2dSShivasharan S void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2704e9495e2dSShivasharan S bool is_target_prop);
2705e9495e2dSShivasharan S int megasas_get_target_prop(struct megasas_instance *instance,
2706e9495e2dSShivasharan S struct scsi_device *sdev);
2707f0c21df6SShivasharan S void megasas_get_snapdump_properties(struct megasas_instance *instance);
2708e9495e2dSShivasharan S
2709fc62b3fcSSumit.Saxena@avagotech.com int megasas_set_crash_dump_params(struct megasas_instance *instance,
2710fc62b3fcSSumit.Saxena@avagotech.com u8 crash_buf_state);
2711fc62b3fcSSumit.Saxena@avagotech.com void megasas_free_host_crash_buffer(struct megasas_instance *instance);
271251087a86SSumit.Saxena@avagotech.com
271390dc9d98SSumit.Saxena@avagotech.com void megasas_return_cmd_fusion(struct megasas_instance *instance,
271490dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd_fusion *cmd);
271590dc9d98SSumit.Saxena@avagotech.com int megasas_issue_blocked_cmd(struct megasas_instance *instance,
271690dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd, int timeout);
271790dc9d98SSumit.Saxena@avagotech.com void __megasas_return_cmd(struct megasas_instance *instance,
271890dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd);
271990dc9d98SSumit.Saxena@avagotech.com
272090dc9d98SSumit.Saxena@avagotech.com void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
272190dc9d98SSumit.Saxena@avagotech.com struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
27227497cde8SSumit.Saxena@avagotech.com int megasas_cmd_type(struct scsi_cmnd *cmd);
27233761cb4cSsumit.saxena@avagotech.com void megasas_setup_jbod_map(struct megasas_instance *instance);
272490dc9d98SSumit.Saxena@avagotech.com
272518365b13SSumit Saxena void megasas_update_sdev_properties(struct scsi_device *sdev);
272618365b13SSumit Saxena int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
272718365b13SSumit Saxena int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
272818365b13SSumit Saxena int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
272933203bc4SShivasharan S u32 mega_mod64(u64 dividend, u32 divisor);
27305fc499b6SShivasharan S int megasas_alloc_fusion_context(struct megasas_instance *instance);
27315fc499b6SShivasharan S void megasas_free_fusion_context(struct megasas_instance *instance);
27323f6194afSShivasharan S int megasas_fusion_start_watchdog(struct megasas_instance *instance);
27333f6194afSShivasharan S void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
27343f6194afSShivasharan S
2735107a60ddSShivasharan S void megasas_set_dma_settings(struct megasas_instance *instance,
2736107a60ddSShivasharan S struct megasas_dcmd_frame *dcmd,
2737107a60ddSShivasharan S dma_addr_t dma_addr, u32 dma_len);
273878409d4bSShivasharan S int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
273978409d4bSShivasharan S bool do_adp_reset,
274078409d4bSShivasharan S int ocr_context);
274162a04f81SShivasharan S int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
274296c9603cSShivasharan S void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
27437b3c1035SDamien Le Moal u32 megasas_readl(struct megasas_instance *instance,
27447b3c1035SDamien Le Moal const volatile void __iomem *addr);
27457b3c1035SDamien Le Moal struct megasas_cmd *megasas_get_cmd(struct megasas_instance *instance);
27467b3c1035SDamien Le Moal void megasas_return_cmd(struct megasas_instance *instance,
27477b3c1035SDamien Le Moal struct megasas_cmd *cmd);
27487b3c1035SDamien Le Moal int megasas_issue_polled(struct megasas_instance *instance,
27497b3c1035SDamien Le Moal struct megasas_cmd *cmd);
27507b3c1035SDamien Le Moal void megaraid_sas_kill_hba(struct megasas_instance *instance);
27517b3c1035SDamien Le Moal void megasas_check_and_restore_queue_depth(struct megasas_instance *instance);
27527b3c1035SDamien Le Moal void megasas_start_timer(struct megasas_instance *instance);
27537b3c1035SDamien Le Moal int megasas_sriov_start_heartbeat(struct megasas_instance *instance,
27547b3c1035SDamien Le Moal int initial);
27557b3c1035SDamien Le Moal int megasas_alloc_cmds(struct megasas_instance *instance);
27567b3c1035SDamien Le Moal void megasas_free_cmds(struct megasas_instance *instance);
27577b3c1035SDamien Le Moal
27587b3c1035SDamien Le Moal void megasas_init_debugfs(void);
27597b3c1035SDamien Le Moal void megasas_exit_debugfs(void);
27607b3c1035SDamien Le Moal void megasas_setup_debugfs(struct megasas_instance *instance);
27617b3c1035SDamien Le Moal void megasas_destroy_debugfs(struct megasas_instance *instance);
27629e4bec5bSKashyap Desai int megasas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
27637b3c1035SDamien Le Moal
2764c4a3e0a5SBagalkote, Sreenivas #endif /*LSI_MEGARAID_SAS_H */
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