1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor 4 * found on Power Macintosh computers, controlling the external SCSI chain. 5 * 6 * Copyright (C) 1996 Paul Mackerras. 7 */ 8 #ifndef _MAC53C94_H 9 #define _MAC53C94_H 10 11 /* 12 * Registers in the 53C94 controller. 13 */ 14 15 struct mac53c94_regs { 16 unsigned char count_lo; 17 char pad0[15]; 18 unsigned char count_mid; 19 char pad1[15]; 20 unsigned char fifo; 21 char pad2[15]; 22 unsigned char command; 23 char pad3[15]; 24 unsigned char status; 25 char pad4[15]; 26 unsigned char interrupt; 27 char pad5[15]; 28 unsigned char seqstep; 29 char pad6[15]; 30 unsigned char flags; 31 char pad7[15]; 32 unsigned char config1; 33 char pad8[15]; 34 unsigned char clk_factor; 35 char pad9[15]; 36 unsigned char test; 37 char pad10[15]; 38 unsigned char config2; 39 char pad11[15]; 40 unsigned char config3; 41 char pad12[15]; 42 unsigned char config4; 43 char pad13[15]; 44 unsigned char count_hi; 45 char pad14[15]; 46 unsigned char fifo_res; 47 char pad15[15]; 48 }; 49 50 /* 51 * Alternate functions for some registers. 52 */ 53 #define dest_id status 54 #define sel_timeout interrupt 55 #define sync_period seqstep 56 #define sync_offset flags 57 58 /* 59 * Bits in command register. 60 */ 61 #define CMD_DMA_MODE 0x80 62 #define CMD_MODE_MASK 0x70 63 #define CMD_MODE_INIT 0x10 64 #define CMD_MODE_TARG 0x20 65 #define CMD_MODE_DISC 0x40 66 67 #define CMD_NOP 0 68 #define CMD_FLUSH 1 69 #define CMD_RESET 2 70 #define CMD_SCSI_RESET 3 71 72 #define CMD_XFER_DATA 0x10 73 #define CMD_I_COMPLETE 0x11 74 #define CMD_ACCEPT_MSG 0x12 75 #define CMD_XFER_PAD 0x18 76 #define CMD_SET_ATN 0x1a 77 #define CMD_CLR_ATN 0x1b 78 79 #define CMD_SEND_MSG 0x20 80 #define CMD_SEND_STATUS 0x21 81 #define CMD_SEND_DATA 0x22 82 #define CMD_DISC_SEQ 0x23 83 #define CMD_TERMINATE 0x24 84 #define CMD_T_COMPLETE 0x25 85 #define CMD_DISCONNECT 0x27 86 #define CMD_RECV_MSG 0x28 87 #define CMD_RECV_CDB 0x29 88 #define CMD_RECV_DATA 0x2a 89 #define CMD_RECV_CMD 0x2b 90 #define CMD_ABORT_DMA 0x04 91 92 #define CMD_RESELECT 0x40 93 #define CMD_SELECT 0x41 94 #define CMD_SELECT_ATN 0x42 95 #define CMD_SELATN_STOP 0x43 96 #define CMD_ENABLE_SEL 0x44 97 #define CMD_DISABLE_SEL 0x45 98 #define CMD_SEL_ATN3 0x46 99 #define CMD_RESEL_ATN3 0x47 100 101 /* 102 * Bits in status register. 103 */ 104 #define STAT_IRQ 0x80 105 #define STAT_ERROR 0x40 106 #define STAT_PARITY 0x20 107 #define STAT_TC_ZERO 0x10 108 #define STAT_DONE 0x08 109 #define STAT_PHASE 0x07 110 #define STAT_MSG 0x04 111 #define STAT_CD 0x02 112 #define STAT_IO 0x01 113 114 /* 115 * Bits in interrupt register. 116 */ 117 #define INTR_RESET 0x80 /* SCSI bus was reset */ 118 #define INTR_ILL_CMD 0x40 /* illegal command */ 119 #define INTR_DISCONNECT 0x20 /* we got disconnected */ 120 #define INTR_BUS_SERV 0x10 /* bus service requested */ 121 #define INTR_DONE 0x08 /* function completed */ 122 #define INTR_RESELECTED 0x04 /* we were reselected */ 123 #define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */ 124 #define INTR_SELECT 0x01 /* we were selected, ATN negated */ 125 126 /* 127 * Encoding for the select timeout. 128 */ 129 #define TIMO_VAL(x) ((x) * 5000 / 7682) 130 131 /* 132 * Bits in sequence step register. 133 */ 134 #define SS_MASK 7 135 #define SS_ARB_SEL 0 /* Selection & arbitration complete */ 136 #define SS_MSG_SENT 1 /* One message byte sent */ 137 #define SS_NOT_CMD 2 /* Not in command phase */ 138 #define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */ 139 #define SS_DONE 4 /* Command was sent OK */ 140 141 /* 142 * Encoding for sync transfer period. 143 */ 144 #define SYNCP_MASK 0x1f 145 #define SYNCP_MIN 4 146 #define SYNCP_MAX 31 147 148 /* 149 * Bits in flags register. 150 */ 151 #define FLAGS_FIFO_LEV 0x1f 152 #define FLAGS_SEQ_STEP 0xe0 153 154 /* 155 * Encoding for sync offset. 156 */ 157 #define SYNCO_MASK 0x0f 158 #define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */ 159 #define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */ 160 161 /* 162 * Bits in config1 register. 163 */ 164 #define CF1_SLOW_CABLE 0x80 /* Slow cable mode */ 165 #define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */ 166 #define CF1_PAR_TEST 0x20 /* Parity test mode enable */ 167 #define CF1_PAR_ENABLE 0x10 /* Enable parity checks */ 168 #define CF1_TEST 0x08 /* Chip tests */ 169 #define CF1_MY_ID 0x07 /* Controller's address on bus */ 170 171 /* 172 * Encoding for clk_factor register. 173 */ 174 #define CLKF_MASK 7 175 #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK) 176 177 /* 178 * Bits in test mode register. 179 */ 180 #define TEST_TARGET 1 /* target test mode */ 181 #define TEST_INITIATOR 2 /* initiator test mode */ 182 #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */ 183 184 /* 185 * Bits in config2 register. 186 */ 187 #define CF2_RFB 0x80 188 #define CF2_FEATURE_EN 0x40 /* enable features / phase latch */ 189 #define CF2_BYTECTRL 0x20 190 #define CF2_DREQ_HIZ 0x10 191 #define CF2_SCSI2 0x08 192 #define CF2_PAR_ABORT 0x04 /* bad parity target abort */ 193 #define CF2_REG_PARERR 0x02 /* register parity error */ 194 #define CF2_DMA_PARERR 0x01 /* DMA parity error */ 195 196 /* 197 * Bits in the config3 register. 198 */ 199 #define CF3_ID_MSG_CHK 0x80 200 #define CF3_3B_MSGS 0x40 201 #define CF3_CDB10 0x20 202 #define CF3_FASTSCSI 0x10 /* enable fast SCSI support */ 203 #define CF3_FASTCLOCK 0x08 204 #define CF3_SAVERESID 0x04 205 #define CF3_ALT_DMA 0x02 206 #define CF3_THRESH_8 0x01 207 208 /* 209 * Bits in the config4 register. 210 */ 211 #define CF4_EAN 0x04 212 #define CF4_TEST 0x02 213 #define CF4_BBTE 0x01 214 215 #endif /* _MAC53C94_H */ 216