1dea3101eS /******************************************************************* 2dea3101eS * This file is part of the Emulex Linux Device Driver for * 3c44ce173SJames.Smart@Emulex.Com * Fibre Channel Host Bus Adapters. * 441415862SJamie Wellnitz * Copyright (C) 2004-2006 Emulex. All rights reserved. * 5c44ce173SJames.Smart@Emulex.Com * EMULEX and SLI are trademarks of Emulex. * 6dea3101eS * www.emulex.com * 7c44ce173SJames.Smart@Emulex.Com * Portions Copyright (C) 2004-2005 Christoph Hellwig * 8dea3101eS * * 9dea3101eS * This program is free software; you can redistribute it and/or * 10c44ce173SJames.Smart@Emulex.Com * modify it under the terms of version 2 of the GNU General * 11c44ce173SJames.Smart@Emulex.Com * Public License as published by the Free Software Foundation. * 12c44ce173SJames.Smart@Emulex.Com * This program is distributed in the hope that it will be useful. * 13c44ce173SJames.Smart@Emulex.Com * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 14c44ce173SJames.Smart@Emulex.Com * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 15c44ce173SJames.Smart@Emulex.Com * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 16c44ce173SJames.Smart@Emulex.Com * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 17c44ce173SJames.Smart@Emulex.Com * TO BE LEGALLY INVALID. See the GNU General Public License for * 18c44ce173SJames.Smart@Emulex.Com * more details, a copy of which can be found in the file COPYING * 19c44ce173SJames.Smart@Emulex.Com * included with this package. * 20dea3101eS *******************************************************************/ 21dea3101eS 22dea3101eS #include <linux/blkdev.h> 23dea3101eS #include <linux/pci.h> 24dea3101eS #include <linux/interrupt.h> 25dea3101eS 26f888ba3cSJames.Smart@Emulex.Com #include <scsi/scsi_device.h> 27f888ba3cSJames.Smart@Emulex.Com #include <scsi/scsi_transport_fc.h> 28f888ba3cSJames.Smart@Emulex.Com 2991886523SJames.Smart@Emulex.Com #include <scsi/scsi.h> 3091886523SJames.Smart@Emulex.Com 31dea3101eS #include "lpfc_hw.h" 32dea3101eS #include "lpfc_sli.h" 33dea3101eS #include "lpfc_disc.h" 34dea3101eS #include "lpfc_scsi.h" 35dea3101eS #include "lpfc.h" 36dea3101eS #include "lpfc_logmsg.h" 37dea3101eS #include "lpfc_crtn.h" 38dea3101eS #include "lpfc_compat.h" 39dea3101eS 40dea3101eS /**********************************************/ 41dea3101eS 42dea3101eS /* mailbox command */ 43dea3101eS /**********************************************/ 44dea3101eS void 45dea3101eS lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset) 46dea3101eS { 47dea3101eS MAILBOX_t *mb; 48dea3101eS void *ctx; 49dea3101eS 50dea3101eS mb = &pmb->mb; 51dea3101eS ctx = pmb->context2; 52dea3101eS 53dea3101eS /* Setup to dump VPD region */ 54dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 55dea3101eS mb->mbxCommand = MBX_DUMP_MEMORY; 56dea3101eS mb->un.varDmp.cv = 1; 57dea3101eS mb->un.varDmp.type = DMP_NV_PARAMS; 58dea3101eS mb->un.varDmp.entry_index = offset; 59dea3101eS mb->un.varDmp.region_id = DMP_REGION_VPD; 60dea3101eS mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t)); 61dea3101eS mb->un.varDmp.co = 0; 62dea3101eS mb->un.varDmp.resp_offset = 0; 63dea3101eS pmb->context2 = ctx; 64dea3101eS mb->mbxOwner = OWN_HOST; 65dea3101eS return; 66dea3101eS } 67dea3101eS 68dea3101eS /**********************************************/ 69dea3101eS /* lpfc_read_nv Issue a READ NVPARAM */ 70dea3101eS /* mailbox command */ 71dea3101eS /**********************************************/ 72dea3101eS void 73dea3101eS lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 74dea3101eS { 75dea3101eS MAILBOX_t *mb; 76dea3101eS 77dea3101eS mb = &pmb->mb; 78dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 79dea3101eS mb->mbxCommand = MBX_READ_NV; 80dea3101eS mb->mbxOwner = OWN_HOST; 81dea3101eS return; 82dea3101eS } 83dea3101eS 84dea3101eS /**********************************************/ 85dea3101eS /* lpfc_read_la Issue a READ LA */ 86dea3101eS /* mailbox command */ 87dea3101eS /**********************************************/ 88dea3101eS int 89dea3101eS lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp) 90dea3101eS { 91dea3101eS MAILBOX_t *mb; 92dea3101eS struct lpfc_sli *psli; 93dea3101eS 94dea3101eS psli = &phba->sli; 95dea3101eS mb = &pmb->mb; 96dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 97dea3101eS 98dea3101eS INIT_LIST_HEAD(&mp->list); 99dea3101eS mb->mbxCommand = MBX_READ_LA64; 100dea3101eS mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128; 101dea3101eS mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys); 102dea3101eS mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys); 103dea3101eS 104dea3101eS /* Save address for later completion and set the owner to host so that 105dea3101eS * the FW knows this mailbox is available for processing. 106dea3101eS */ 107dea3101eS pmb->context1 = (uint8_t *) mp; 108dea3101eS mb->mbxOwner = OWN_HOST; 109dea3101eS return (0); 110dea3101eS } 111dea3101eS 112dea3101eS /**********************************************/ 113dea3101eS /* lpfc_clear_la Issue a CLEAR LA */ 114dea3101eS /* mailbox command */ 115dea3101eS /**********************************************/ 116dea3101eS void 117dea3101eS lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 118dea3101eS { 119dea3101eS MAILBOX_t *mb; 120dea3101eS 121dea3101eS mb = &pmb->mb; 122dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 123dea3101eS 124dea3101eS mb->un.varClearLA.eventTag = phba->fc_eventTag; 125dea3101eS mb->mbxCommand = MBX_CLEAR_LA; 126dea3101eS mb->mbxOwner = OWN_HOST; 127dea3101eS return; 128dea3101eS } 129dea3101eS 130dea3101eS /**************************************************/ 131dea3101eS /* lpfc_config_link Issue a CONFIG LINK */ 132dea3101eS /* mailbox command */ 133dea3101eS /**************************************************/ 134dea3101eS void 135dea3101eS lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 136dea3101eS { 137dea3101eS MAILBOX_t *mb = &pmb->mb; 138dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 139dea3101eS 140dea3101eS /* NEW_FEATURE 141dea3101eS * SLI-2, Coalescing Response Feature. 142dea3101eS */ 143dea3101eS if (phba->cfg_cr_delay) { 144dea3101eS mb->un.varCfgLnk.cr = 1; 145dea3101eS mb->un.varCfgLnk.ci = 1; 146dea3101eS mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay; 147dea3101eS mb->un.varCfgLnk.cr_count = phba->cfg_cr_count; 148dea3101eS } 149dea3101eS 150dea3101eS mb->un.varCfgLnk.myId = phba->fc_myDID; 151dea3101eS mb->un.varCfgLnk.edtov = phba->fc_edtov; 152dea3101eS mb->un.varCfgLnk.arbtov = phba->fc_arbtov; 153dea3101eS mb->un.varCfgLnk.ratov = phba->fc_ratov; 154dea3101eS mb->un.varCfgLnk.rttov = phba->fc_rttov; 155dea3101eS mb->un.varCfgLnk.altov = phba->fc_altov; 156dea3101eS mb->un.varCfgLnk.crtov = phba->fc_crtov; 157dea3101eS mb->un.varCfgLnk.citov = phba->fc_citov; 158dea3101eS 159dea3101eS if (phba->cfg_ack0) 160dea3101eS mb->un.varCfgLnk.ack0_enable = 1; 161dea3101eS 162dea3101eS mb->mbxCommand = MBX_CONFIG_LINK; 163dea3101eS mb->mbxOwner = OWN_HOST; 164dea3101eS return; 165dea3101eS } 166dea3101eS 167dea3101eS /**********************************************/ 168dea3101eS /* lpfc_init_link Issue an INIT LINK */ 169dea3101eS /* mailbox command */ 170dea3101eS /**********************************************/ 171dea3101eS void 172dea3101eS lpfc_init_link(struct lpfc_hba * phba, 173dea3101eS LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed) 174dea3101eS { 175dea3101eS lpfc_vpd_t *vpd; 176dea3101eS struct lpfc_sli *psli; 177dea3101eS MAILBOX_t *mb; 178dea3101eS 179dea3101eS mb = &pmb->mb; 180dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 181dea3101eS 182dea3101eS psli = &phba->sli; 183dea3101eS switch (topology) { 184dea3101eS case FLAGS_TOPOLOGY_MODE_LOOP_PT: 185dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; 186dea3101eS mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; 187dea3101eS break; 188dea3101eS case FLAGS_TOPOLOGY_MODE_PT_PT: 189dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; 190dea3101eS break; 191dea3101eS case FLAGS_TOPOLOGY_MODE_LOOP: 192dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; 193dea3101eS break; 194dea3101eS case FLAGS_TOPOLOGY_MODE_PT_LOOP: 195dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; 196dea3101eS mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; 197dea3101eS break; 198367c2713SJamie Wellnitz case FLAGS_LOCAL_LB: 199367c2713SJamie Wellnitz mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB; 200367c2713SJamie Wellnitz break; 201dea3101eS } 202dea3101eS 2034b0b91d4SJames Smart /* Enable asynchronous ABTS responses from firmware */ 2044b0b91d4SJames Smart mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT; 2054b0b91d4SJames Smart 206dea3101eS /* NEW_FEATURE 207dea3101eS * Setting up the link speed 208dea3101eS */ 209dea3101eS vpd = &phba->vpd; 210dea3101eS if (vpd->rev.feaLevelHigh >= 0x02){ 211dea3101eS switch(linkspeed){ 212dea3101eS case LINK_SPEED_1G: 213dea3101eS case LINK_SPEED_2G: 214dea3101eS case LINK_SPEED_4G: 215b87eab38SJames Smart case LINK_SPEED_8G: 216dea3101eS mb->un.varInitLnk.link_flags |= 217dea3101eS FLAGS_LINK_SPEED; 218dea3101eS mb->un.varInitLnk.link_speed = linkspeed; 219dea3101eS break; 220dea3101eS case LINK_SPEED_AUTO: 221dea3101eS default: 222dea3101eS mb->un.varInitLnk.link_speed = 223dea3101eS LINK_SPEED_AUTO; 224dea3101eS break; 225dea3101eS } 226dea3101eS 227dea3101eS } 228dea3101eS else 229dea3101eS mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO; 230dea3101eS 231dea3101eS mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK; 232dea3101eS mb->mbxOwner = OWN_HOST; 233dea3101eS mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA; 234dea3101eS return; 235dea3101eS } 236dea3101eS 237dea3101eS /**********************************************/ 238dea3101eS /* lpfc_read_sparam Issue a READ SPARAM */ 239dea3101eS /* mailbox command */ 240dea3101eS /**********************************************/ 241dea3101eS int 242dea3101eS lpfc_read_sparam(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 243dea3101eS { 244dea3101eS struct lpfc_dmabuf *mp; 245dea3101eS MAILBOX_t *mb; 246dea3101eS struct lpfc_sli *psli; 247dea3101eS 248dea3101eS psli = &phba->sli; 249dea3101eS mb = &pmb->mb; 250dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 251dea3101eS 252dea3101eS mb->mbxOwner = OWN_HOST; 253dea3101eS 254dea3101eS /* Get a buffer to hold the HBAs Service Parameters */ 255dea3101eS 256dea3101eS if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) || 257dea3101eS ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { 258dea3101eS kfree(mp); 259dea3101eS mb->mbxCommand = MBX_READ_SPARM64; 260dea3101eS /* READ_SPARAM: no buffers */ 261dea3101eS lpfc_printf_log(phba, 262dea3101eS KERN_WARNING, 263dea3101eS LOG_MBOX, 264dea3101eS "%d:0301 READ_SPARAM: no buffers\n", 265dea3101eS phba->brd_no); 266dea3101eS return (1); 267dea3101eS } 268dea3101eS INIT_LIST_HEAD(&mp->list); 269dea3101eS mb->mbxCommand = MBX_READ_SPARM64; 270dea3101eS mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); 271dea3101eS mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys); 272dea3101eS mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys); 273dea3101eS 274dea3101eS /* save address for completion */ 275dea3101eS pmb->context1 = mp; 276dea3101eS 277dea3101eS return (0); 278dea3101eS } 279dea3101eS 280dea3101eS /********************************************/ 281dea3101eS /* lpfc_unreg_did Issue a UNREG_DID */ 282dea3101eS /* mailbox command */ 283dea3101eS /********************************************/ 284dea3101eS void 285dea3101eS lpfc_unreg_did(struct lpfc_hba * phba, uint32_t did, LPFC_MBOXQ_t * pmb) 286dea3101eS { 287dea3101eS MAILBOX_t *mb; 288dea3101eS 289dea3101eS mb = &pmb->mb; 290dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 291dea3101eS 292dea3101eS mb->un.varUnregDID.did = did; 293dea3101eS 294dea3101eS mb->mbxCommand = MBX_UNREG_D_ID; 295dea3101eS mb->mbxOwner = OWN_HOST; 296dea3101eS return; 297dea3101eS } 298dea3101eS 299dea3101eS /**********************************************/ 300dea3101eS /* lpfc_read_nv Issue a READ CONFIG */ 301dea3101eS /* mailbox command */ 302dea3101eS /**********************************************/ 303dea3101eS void 304dea3101eS lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 305dea3101eS { 306dea3101eS MAILBOX_t *mb; 307dea3101eS 308dea3101eS mb = &pmb->mb; 309dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 310dea3101eS 311dea3101eS mb->mbxCommand = MBX_READ_CONFIG; 312dea3101eS mb->mbxOwner = OWN_HOST; 313dea3101eS return; 314dea3101eS } 315dea3101eS 3167bb3b137SJamie Wellnitz /*************************************************/ 3177bb3b137SJamie Wellnitz /* lpfc_read_lnk_stat Issue a READ LINK STATUS */ 3187bb3b137SJamie Wellnitz /* mailbox command */ 3197bb3b137SJamie Wellnitz /*************************************************/ 3207bb3b137SJamie Wellnitz void 3217bb3b137SJamie Wellnitz lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 3227bb3b137SJamie Wellnitz { 3237bb3b137SJamie Wellnitz MAILBOX_t *mb; 3247bb3b137SJamie Wellnitz 3257bb3b137SJamie Wellnitz mb = &pmb->mb; 3267bb3b137SJamie Wellnitz memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 3277bb3b137SJamie Wellnitz 3287bb3b137SJamie Wellnitz mb->mbxCommand = MBX_READ_LNK_STAT; 3297bb3b137SJamie Wellnitz mb->mbxOwner = OWN_HOST; 3307bb3b137SJamie Wellnitz return; 3317bb3b137SJamie Wellnitz } 3327bb3b137SJamie Wellnitz 333dea3101eS /********************************************/ 334dea3101eS /* lpfc_reg_login Issue a REG_LOGIN */ 335dea3101eS /* mailbox command */ 336dea3101eS /********************************************/ 337dea3101eS int 338dea3101eS lpfc_reg_login(struct lpfc_hba * phba, 339dea3101eS uint32_t did, uint8_t * param, LPFC_MBOXQ_t * pmb, uint32_t flag) 340dea3101eS { 341dea3101eS uint8_t *sparam; 342dea3101eS struct lpfc_dmabuf *mp; 343dea3101eS MAILBOX_t *mb; 344dea3101eS struct lpfc_sli *psli; 345dea3101eS 346dea3101eS psli = &phba->sli; 347dea3101eS mb = &pmb->mb; 348dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 349dea3101eS 350dea3101eS mb->un.varRegLogin.rpi = 0; 351dea3101eS mb->un.varRegLogin.did = did; 352dea3101eS mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */ 353dea3101eS 354dea3101eS mb->mbxOwner = OWN_HOST; 355dea3101eS 356dea3101eS /* Get a buffer to hold NPorts Service Parameters */ 357dea3101eS if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) || 358dea3101eS ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { 359dea3101eS kfree(mp); 360dea3101eS mb->mbxCommand = MBX_REG_LOGIN64; 361dea3101eS /* REG_LOGIN: no buffers */ 362dea3101eS lpfc_printf_log(phba, 363dea3101eS KERN_WARNING, 364dea3101eS LOG_MBOX, 365dea3101eS "%d:0302 REG_LOGIN: no buffers Data x%x x%x\n", 366dea3101eS phba->brd_no, 367dea3101eS (uint32_t) did, (uint32_t) flag); 368dea3101eS return (1); 369dea3101eS } 370dea3101eS INIT_LIST_HEAD(&mp->list); 371dea3101eS sparam = mp->virt; 372dea3101eS 373dea3101eS /* Copy param's into a new buffer */ 374dea3101eS memcpy(sparam, param, sizeof (struct serv_parm)); 375dea3101eS 376dea3101eS /* save address for completion */ 377dea3101eS pmb->context1 = (uint8_t *) mp; 378dea3101eS 379dea3101eS mb->mbxCommand = MBX_REG_LOGIN64; 380dea3101eS mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); 381dea3101eS mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys); 382dea3101eS mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys); 383dea3101eS 384dea3101eS return (0); 385dea3101eS } 386dea3101eS 387dea3101eS /**********************************************/ 388dea3101eS /* lpfc_unreg_login Issue a UNREG_LOGIN */ 389dea3101eS /* mailbox command */ 390dea3101eS /**********************************************/ 391dea3101eS void 392dea3101eS lpfc_unreg_login(struct lpfc_hba * phba, uint32_t rpi, LPFC_MBOXQ_t * pmb) 393dea3101eS { 394dea3101eS MAILBOX_t *mb; 395dea3101eS 396dea3101eS mb = &pmb->mb; 397dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 398dea3101eS 399dea3101eS mb->un.varUnregLogin.rpi = (uint16_t) rpi; 400dea3101eS mb->un.varUnregLogin.rsvd1 = 0; 401dea3101eS 402dea3101eS mb->mbxCommand = MBX_UNREG_LOGIN; 403dea3101eS mb->mbxOwner = OWN_HOST; 404dea3101eS return; 405dea3101eS } 406dea3101eS 407dea3101eS static void 408dea3101eS lpfc_config_pcb_setup(struct lpfc_hba * phba) 409dea3101eS { 410dea3101eS struct lpfc_sli *psli = &phba->sli; 411dea3101eS struct lpfc_sli_ring *pring; 412dea3101eS PCB_t *pcbp = &phba->slim2p->pcb; 413dea3101eS dma_addr_t pdma_addr; 414dea3101eS uint32_t offset; 415dea3101eS uint32_t iocbCnt; 416dea3101eS int i; 417dea3101eS 418dea3101eS pcbp->maxRing = (psli->num_rings - 1); 419dea3101eS 420dea3101eS iocbCnt = 0; 421dea3101eS for (i = 0; i < psli->num_rings; i++) { 422dea3101eS pring = &psli->ring[i]; 423dea3101eS /* A ring MUST have both cmd and rsp entries defined to be 424dea3101eS valid */ 425dea3101eS if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) { 426dea3101eS pcbp->rdsc[i].cmdEntries = 0; 427dea3101eS pcbp->rdsc[i].rspEntries = 0; 428dea3101eS pcbp->rdsc[i].cmdAddrHigh = 0; 429dea3101eS pcbp->rdsc[i].rspAddrHigh = 0; 430dea3101eS pcbp->rdsc[i].cmdAddrLow = 0; 431dea3101eS pcbp->rdsc[i].rspAddrLow = 0; 432dea3101eS pring->cmdringaddr = NULL; 433dea3101eS pring->rspringaddr = NULL; 434dea3101eS continue; 435dea3101eS } 436dea3101eS /* Command ring setup for ring */ 437dea3101eS pring->cmdringaddr = 438dea3101eS (void *)&phba->slim2p->IOCBs[iocbCnt]; 439dea3101eS pcbp->rdsc[i].cmdEntries = pring->numCiocb; 440dea3101eS 441dea3101eS offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - 442dea3101eS (uint8_t *)phba->slim2p; 443dea3101eS pdma_addr = phba->slim2p_mapping + offset; 444dea3101eS pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr); 445dea3101eS pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr); 446dea3101eS iocbCnt += pring->numCiocb; 447dea3101eS 448dea3101eS /* Response ring setup for ring */ 449dea3101eS pring->rspringaddr = 450dea3101eS (void *)&phba->slim2p->IOCBs[iocbCnt]; 451dea3101eS 452dea3101eS pcbp->rdsc[i].rspEntries = pring->numRiocb; 453dea3101eS offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - 454dea3101eS (uint8_t *)phba->slim2p; 455dea3101eS pdma_addr = phba->slim2p_mapping + offset; 456dea3101eS pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr); 457dea3101eS pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr); 458dea3101eS iocbCnt += pring->numRiocb; 459dea3101eS } 460dea3101eS } 461dea3101eS 462dea3101eS void 463dea3101eS lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 464dea3101eS { 465dea3101eS MAILBOX_t *mb; 466dea3101eS 467dea3101eS mb = &pmb->mb; 468dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 469dea3101eS mb->un.varRdRev.cv = 1; 470dea3101eS mb->mbxCommand = MBX_READ_REV; 471dea3101eS mb->mbxOwner = OWN_HOST; 472dea3101eS return; 473dea3101eS } 474dea3101eS 475dea3101eS void 476dea3101eS lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb) 477dea3101eS { 478dea3101eS int i; 479dea3101eS MAILBOX_t *mb = &pmb->mb; 480dea3101eS struct lpfc_sli *psli; 481dea3101eS struct lpfc_sli_ring *pring; 482dea3101eS 483dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 484dea3101eS 485dea3101eS mb->un.varCfgRing.ring = ring; 486dea3101eS mb->un.varCfgRing.maxOrigXchg = 0; 487dea3101eS mb->un.varCfgRing.maxRespXchg = 0; 488dea3101eS mb->un.varCfgRing.recvNotify = 1; 489dea3101eS 490dea3101eS psli = &phba->sli; 491dea3101eS pring = &psli->ring[ring]; 492dea3101eS mb->un.varCfgRing.numMask = pring->num_mask; 493dea3101eS mb->mbxCommand = MBX_CONFIG_RING; 494dea3101eS mb->mbxOwner = OWN_HOST; 495dea3101eS 496dea3101eS /* Is this ring configured for a specific profile */ 497dea3101eS if (pring->prt[0].profile) { 498dea3101eS mb->un.varCfgRing.profile = pring->prt[0].profile; 499dea3101eS return; 500dea3101eS } 501dea3101eS 502dea3101eS /* Otherwise we setup specific rctl / type masks for this ring */ 503dea3101eS for (i = 0; i < pring->num_mask; i++) { 504dea3101eS mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl; 505dea3101eS if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ) 506dea3101eS mb->un.varCfgRing.rrRegs[i].rmask = 0xff; 507dea3101eS else 508dea3101eS mb->un.varCfgRing.rrRegs[i].rmask = 0xfe; 509dea3101eS mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type; 510dea3101eS mb->un.varCfgRing.rrRegs[i].tmask = 0xff; 511dea3101eS } 512dea3101eS 513dea3101eS return; 514dea3101eS } 515dea3101eS 516dea3101eS void 517dea3101eS lpfc_config_port(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 518dea3101eS { 519dea3101eS MAILBOX_t *mb = &pmb->mb; 520dea3101eS dma_addr_t pdma_addr; 521dea3101eS uint32_t bar_low, bar_high; 522dea3101eS size_t offset; 5234cc2da1dSJames.Smart@Emulex.Com struct lpfc_hgp hgp; 524dea3101eS void __iomem *to_slim; 525f91b392cSJames.Smart@Emulex.Com int i; 526dea3101eS 527dea3101eS memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); 528dea3101eS mb->mbxCommand = MBX_CONFIG_PORT; 529dea3101eS mb->mbxOwner = OWN_HOST; 530dea3101eS 531dea3101eS mb->un.varCfgPort.pcbLen = sizeof(PCB_t); 532dea3101eS 533dea3101eS offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p; 534dea3101eS pdma_addr = phba->slim2p_mapping + offset; 535dea3101eS mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr); 536dea3101eS mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr); 537dea3101eS 538dea3101eS /* Now setup pcb */ 539dea3101eS phba->slim2p->pcb.type = TYPE_NATIVE_SLI2; 540dea3101eS phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2; 541dea3101eS 542dea3101eS /* Setup Mailbox pointers */ 543dea3101eS phba->slim2p->pcb.mailBoxSize = sizeof(MAILBOX_t); 544dea3101eS offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p; 545dea3101eS pdma_addr = phba->slim2p_mapping + offset; 546dea3101eS phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr); 547dea3101eS phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr); 548dea3101eS 549dea3101eS /* 550dea3101eS * Setup Host Group ring pointer. 551dea3101eS * 552dea3101eS * For efficiency reasons, the ring get/put pointers can be 553dea3101eS * placed in adapter memory (SLIM) rather than in host memory. 554dea3101eS * This allows firmware to avoid PCI reads/writes when updating 555dea3101eS * and checking pointers. 556dea3101eS * 557dea3101eS * The firmware recognizes the use of SLIM memory by comparing 558dea3101eS * the address of the get/put pointers structure with that of 559dea3101eS * the SLIM BAR (BAR0). 560dea3101eS * 561dea3101eS * Caution: be sure to use the PCI config space value of BAR0/BAR1 562dea3101eS * (the hardware's view of the base address), not the OS's 563dea3101eS * value of pci_resource_start() as the OS value may be a cookie 564dea3101eS * for ioremap/iomap. 565dea3101eS */ 566dea3101eS 567dea3101eS 568dea3101eS pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low); 569dea3101eS pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high); 570dea3101eS 571dea3101eS 572dea3101eS /* mask off BAR0's flag bits 0 - 3 */ 573dea3101eS phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) + 574dea3101eS (SLIMOFF*sizeof(uint32_t)); 575dea3101eS if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64) 576dea3101eS phba->slim2p->pcb.hgpAddrHigh = bar_high; 577dea3101eS else 578dea3101eS phba->slim2p->pcb.hgpAddrHigh = 0; 579dea3101eS /* write HGP data to SLIM at the required longword offset */ 5804cc2da1dSJames.Smart@Emulex.Com memset(&hgp, 0, sizeof(struct lpfc_hgp)); 581dea3101eS to_slim = phba->MBslimaddr + (SLIMOFF*sizeof (uint32_t)); 582f91b392cSJames.Smart@Emulex.Com 583f91b392cSJames.Smart@Emulex.Com for (i=0; i < phba->sli.num_rings; i++) { 5844cc2da1dSJames.Smart@Emulex.Com lpfc_memcpy_to_slim(to_slim, &hgp, sizeof(struct lpfc_hgp)); 585f91b392cSJames.Smart@Emulex.Com to_slim += sizeof (struct lpfc_hgp); 586f91b392cSJames.Smart@Emulex.Com } 587dea3101eS 588dea3101eS /* Setup Port Group ring pointer */ 589dea3101eS offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port - 590dea3101eS (uint8_t *)phba->slim2p; 591dea3101eS pdma_addr = phba->slim2p_mapping + offset; 592dea3101eS phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr); 593dea3101eS phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr); 594dea3101eS 595dea3101eS /* Use callback routine to setp rings in the pcb */ 596dea3101eS lpfc_config_pcb_setup(phba); 597dea3101eS 598dea3101eS /* special handling for LC HBAs */ 599dea3101eS if (lpfc_is_LC_HBA(phba->pcidev->device)) { 600dea3101eS uint32_t hbainit[5]; 601dea3101eS 602dea3101eS lpfc_hba_init(phba, hbainit); 603dea3101eS 604dea3101eS memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20); 605dea3101eS } 606dea3101eS 607dea3101eS /* Swap PCB if needed */ 608dea3101eS lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb, 609dea3101eS sizeof (PCB_t)); 610dea3101eS 611dea3101eS lpfc_printf_log(phba, KERN_INFO, LOG_INIT, 612dea3101eS "%d:0405 Service Level Interface (SLI) 2 selected\n", 613dea3101eS phba->brd_no); 614dea3101eS } 615dea3101eS 616dea3101eS void 61741415862SJamie Wellnitz lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 61841415862SJamie Wellnitz { 61941415862SJamie Wellnitz MAILBOX_t *mb = &pmb->mb; 62041415862SJamie Wellnitz 62141415862SJamie Wellnitz memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); 62241415862SJamie Wellnitz mb->mbxCommand = MBX_KILL_BOARD; 62341415862SJamie Wellnitz mb->mbxOwner = OWN_HOST; 62441415862SJamie Wellnitz return; 62541415862SJamie Wellnitz } 62641415862SJamie Wellnitz 62741415862SJamie Wellnitz void 628dea3101eS lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) 629dea3101eS { 630dea3101eS struct lpfc_sli *psli; 631dea3101eS 632dea3101eS psli = &phba->sli; 633dea3101eS 634dea3101eS list_add_tail(&mbq->list, &psli->mboxq); 635dea3101eS 636dea3101eS psli->mboxq_cnt++; 637dea3101eS 638dea3101eS return; 639dea3101eS } 640dea3101eS 641dea3101eS LPFC_MBOXQ_t * 642dea3101eS lpfc_mbox_get(struct lpfc_hba * phba) 643dea3101eS { 644dea3101eS LPFC_MBOXQ_t *mbq = NULL; 645dea3101eS struct lpfc_sli *psli = &phba->sli; 646dea3101eS 647dea3101eS list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, 648dea3101eS list); 649dea3101eS if (mbq) { 650dea3101eS psli->mboxq_cnt--; 651dea3101eS } 652dea3101eS 653dea3101eS return mbq; 654dea3101eS } 655a309a6b6SJames Smart 656a309a6b6SJames Smart int 657a309a6b6SJames Smart lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd) 658a309a6b6SJames Smart { 659a309a6b6SJames Smart switch (cmd) { 660a309a6b6SJames Smart case MBX_WRITE_NV: /* 0x03 */ 661a309a6b6SJames Smart case MBX_UPDATE_CFG: /* 0x1B */ 662a309a6b6SJames Smart case MBX_DOWN_LOAD: /* 0x1C */ 663a309a6b6SJames Smart case MBX_DEL_LD_ENTRY: /* 0x1D */ 664a309a6b6SJames Smart case MBX_LOAD_AREA: /* 0x81 */ 665a309a6b6SJames Smart case MBX_FLASH_WR_ULA: /* 0x98 */ 666a309a6b6SJames Smart case MBX_LOAD_EXP_ROM: /* 0x9C */ 667a309a6b6SJames Smart return LPFC_MBOX_TMO_FLASH_CMD; 668a309a6b6SJames Smart } 669a309a6b6SJames Smart return LPFC_MBOX_TMO; 670a309a6b6SJames Smart } 671