1dea3101eS /******************************************************************* 2dea3101eS * This file is part of the Emulex Linux Device Driver for * 3c44ce173SJames.Smart@Emulex.Com * Fibre Channel Host Bus Adapters. * 49413afffSJames Smart * Copyright (C) 2004-2007 Emulex. All rights reserved. * 5c44ce173SJames.Smart@Emulex.Com * EMULEX and SLI are trademarks of Emulex. * 6dea3101eS * www.emulex.com * 7c44ce173SJames.Smart@Emulex.Com * Portions Copyright (C) 2004-2005 Christoph Hellwig * 8dea3101eS * * 9dea3101eS * This program is free software; you can redistribute it and/or * 10c44ce173SJames.Smart@Emulex.Com * modify it under the terms of version 2 of the GNU General * 11c44ce173SJames.Smart@Emulex.Com * Public License as published by the Free Software Foundation. * 12c44ce173SJames.Smart@Emulex.Com * This program is distributed in the hope that it will be useful. * 13c44ce173SJames.Smart@Emulex.Com * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 14c44ce173SJames.Smart@Emulex.Com * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 15c44ce173SJames.Smart@Emulex.Com * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 16c44ce173SJames.Smart@Emulex.Com * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 17c44ce173SJames.Smart@Emulex.Com * TO BE LEGALLY INVALID. See the GNU General Public License for * 18c44ce173SJames.Smart@Emulex.Com * more details, a copy of which can be found in the file COPYING * 19c44ce173SJames.Smart@Emulex.Com * included with this package. * 20dea3101eS *******************************************************************/ 21dea3101eS 22dea3101eS #include <linux/blkdev.h> 23dea3101eS #include <linux/pci.h> 24dea3101eS #include <linux/interrupt.h> 25dea3101eS 26f888ba3cSJames.Smart@Emulex.Com #include <scsi/scsi_device.h> 27f888ba3cSJames.Smart@Emulex.Com #include <scsi/scsi_transport_fc.h> 28f888ba3cSJames.Smart@Emulex.Com 2991886523SJames.Smart@Emulex.Com #include <scsi/scsi.h> 3091886523SJames.Smart@Emulex.Com 31dea3101eS #include "lpfc_hw.h" 32dea3101eS #include "lpfc_sli.h" 33dea3101eS #include "lpfc_disc.h" 34dea3101eS #include "lpfc_scsi.h" 35dea3101eS #include "lpfc.h" 36dea3101eS #include "lpfc_logmsg.h" 37dea3101eS #include "lpfc_crtn.h" 38dea3101eS #include "lpfc_compat.h" 39dea3101eS 40dea3101eS /**********************************************/ 41dea3101eS 42dea3101eS /* mailbox command */ 43dea3101eS /**********************************************/ 44dea3101eS void 45dea3101eS lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset) 46dea3101eS { 47dea3101eS MAILBOX_t *mb; 48dea3101eS void *ctx; 49dea3101eS 50dea3101eS mb = &pmb->mb; 51dea3101eS ctx = pmb->context2; 52dea3101eS 53dea3101eS /* Setup to dump VPD region */ 54dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 55dea3101eS mb->mbxCommand = MBX_DUMP_MEMORY; 56dea3101eS mb->un.varDmp.cv = 1; 57dea3101eS mb->un.varDmp.type = DMP_NV_PARAMS; 58dea3101eS mb->un.varDmp.entry_index = offset; 59dea3101eS mb->un.varDmp.region_id = DMP_REGION_VPD; 60dea3101eS mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t)); 61dea3101eS mb->un.varDmp.co = 0; 62dea3101eS mb->un.varDmp.resp_offset = 0; 63dea3101eS pmb->context2 = ctx; 64dea3101eS mb->mbxOwner = OWN_HOST; 65dea3101eS return; 66dea3101eS } 67dea3101eS 68dea3101eS /**********************************************/ 69dea3101eS /* lpfc_read_nv Issue a READ NVPARAM */ 70dea3101eS /* mailbox command */ 71dea3101eS /**********************************************/ 72dea3101eS void 73dea3101eS lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 74dea3101eS { 75dea3101eS MAILBOX_t *mb; 76dea3101eS 77dea3101eS mb = &pmb->mb; 78dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 79dea3101eS mb->mbxCommand = MBX_READ_NV; 80dea3101eS mb->mbxOwner = OWN_HOST; 81dea3101eS return; 82dea3101eS } 83dea3101eS 84dea3101eS /**********************************************/ 85dea3101eS /* lpfc_read_la Issue a READ LA */ 86dea3101eS /* mailbox command */ 87dea3101eS /**********************************************/ 88dea3101eS int 89dea3101eS lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp) 90dea3101eS { 91dea3101eS MAILBOX_t *mb; 92dea3101eS struct lpfc_sli *psli; 93dea3101eS 94dea3101eS psli = &phba->sli; 95dea3101eS mb = &pmb->mb; 96dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 97dea3101eS 98dea3101eS INIT_LIST_HEAD(&mp->list); 99dea3101eS mb->mbxCommand = MBX_READ_LA64; 100dea3101eS mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128; 101dea3101eS mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys); 102dea3101eS mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys); 103dea3101eS 104dea3101eS /* Save address for later completion and set the owner to host so that 105dea3101eS * the FW knows this mailbox is available for processing. 106dea3101eS */ 107dea3101eS pmb->context1 = (uint8_t *) mp; 108dea3101eS mb->mbxOwner = OWN_HOST; 10992d7f7b0SJames Smart return (0); 110dea3101eS } 111dea3101eS 112dea3101eS /**********************************************/ 113dea3101eS /* lpfc_clear_la Issue a CLEAR LA */ 114dea3101eS /* mailbox command */ 115dea3101eS /**********************************************/ 116dea3101eS void 117dea3101eS lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 118dea3101eS { 119dea3101eS MAILBOX_t *mb; 120dea3101eS 121dea3101eS mb = &pmb->mb; 122dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 123dea3101eS 124dea3101eS mb->un.varClearLA.eventTag = phba->fc_eventTag; 125dea3101eS mb->mbxCommand = MBX_CLEAR_LA; 126dea3101eS mb->mbxOwner = OWN_HOST; 127dea3101eS return; 128dea3101eS } 129dea3101eS 130dea3101eS /**************************************************/ 131dea3101eS /* lpfc_config_link Issue a CONFIG LINK */ 132dea3101eS /* mailbox command */ 133dea3101eS /**************************************************/ 134dea3101eS void 135dea3101eS lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 136dea3101eS { 1372e0fef85SJames Smart struct lpfc_vport *vport = phba->pport; 138dea3101eS MAILBOX_t *mb = &pmb->mb; 139dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 140dea3101eS 141dea3101eS /* NEW_FEATURE 142dea3101eS * SLI-2, Coalescing Response Feature. 143dea3101eS */ 144dea3101eS if (phba->cfg_cr_delay) { 145dea3101eS mb->un.varCfgLnk.cr = 1; 146dea3101eS mb->un.varCfgLnk.ci = 1; 147dea3101eS mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay; 148dea3101eS mb->un.varCfgLnk.cr_count = phba->cfg_cr_count; 149dea3101eS } 150dea3101eS 1512e0fef85SJames Smart mb->un.varCfgLnk.myId = vport->fc_myDID; 152dea3101eS mb->un.varCfgLnk.edtov = phba->fc_edtov; 153dea3101eS mb->un.varCfgLnk.arbtov = phba->fc_arbtov; 154dea3101eS mb->un.varCfgLnk.ratov = phba->fc_ratov; 155dea3101eS mb->un.varCfgLnk.rttov = phba->fc_rttov; 156dea3101eS mb->un.varCfgLnk.altov = phba->fc_altov; 157dea3101eS mb->un.varCfgLnk.crtov = phba->fc_crtov; 158dea3101eS mb->un.varCfgLnk.citov = phba->fc_citov; 159dea3101eS 160dea3101eS if (phba->cfg_ack0) 161dea3101eS mb->un.varCfgLnk.ack0_enable = 1; 162dea3101eS 163dea3101eS mb->mbxCommand = MBX_CONFIG_LINK; 164dea3101eS mb->mbxOwner = OWN_HOST; 165dea3101eS return; 166dea3101eS } 167dea3101eS 168dea3101eS /**********************************************/ 169dea3101eS /* lpfc_init_link Issue an INIT LINK */ 170dea3101eS /* mailbox command */ 171dea3101eS /**********************************************/ 172dea3101eS void 173dea3101eS lpfc_init_link(struct lpfc_hba * phba, 174dea3101eS LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed) 175dea3101eS { 176dea3101eS lpfc_vpd_t *vpd; 177dea3101eS struct lpfc_sli *psli; 178dea3101eS MAILBOX_t *mb; 179dea3101eS 180dea3101eS mb = &pmb->mb; 181dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 182dea3101eS 183dea3101eS psli = &phba->sli; 184dea3101eS switch (topology) { 185dea3101eS case FLAGS_TOPOLOGY_MODE_LOOP_PT: 186dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; 187dea3101eS mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; 188dea3101eS break; 189dea3101eS case FLAGS_TOPOLOGY_MODE_PT_PT: 190dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; 191dea3101eS break; 192dea3101eS case FLAGS_TOPOLOGY_MODE_LOOP: 193dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; 194dea3101eS break; 195dea3101eS case FLAGS_TOPOLOGY_MODE_PT_LOOP: 196dea3101eS mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; 197dea3101eS mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; 198dea3101eS break; 199367c2713SJamie Wellnitz case FLAGS_LOCAL_LB: 200367c2713SJamie Wellnitz mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB; 201367c2713SJamie Wellnitz break; 202dea3101eS } 203dea3101eS 2044b0b91d4SJames Smart /* Enable asynchronous ABTS responses from firmware */ 2054b0b91d4SJames Smart mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT; 2064b0b91d4SJames Smart 207dea3101eS /* NEW_FEATURE 208dea3101eS * Setting up the link speed 209dea3101eS */ 210dea3101eS vpd = &phba->vpd; 211dea3101eS if (vpd->rev.feaLevelHigh >= 0x02){ 212dea3101eS switch(linkspeed){ 213dea3101eS case LINK_SPEED_1G: 214dea3101eS case LINK_SPEED_2G: 215dea3101eS case LINK_SPEED_4G: 216b87eab38SJames Smart case LINK_SPEED_8G: 217dea3101eS mb->un.varInitLnk.link_flags |= 218dea3101eS FLAGS_LINK_SPEED; 219dea3101eS mb->un.varInitLnk.link_speed = linkspeed; 220dea3101eS break; 221dea3101eS case LINK_SPEED_AUTO: 222dea3101eS default: 223dea3101eS mb->un.varInitLnk.link_speed = 224dea3101eS LINK_SPEED_AUTO; 225dea3101eS break; 226dea3101eS } 227dea3101eS 228dea3101eS } 229dea3101eS else 230dea3101eS mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO; 231dea3101eS 232dea3101eS mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK; 233dea3101eS mb->mbxOwner = OWN_HOST; 234dea3101eS mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA; 235dea3101eS return; 236dea3101eS } 237dea3101eS 238dea3101eS /**********************************************/ 239dea3101eS /* lpfc_read_sparam Issue a READ SPARAM */ 240dea3101eS /* mailbox command */ 241dea3101eS /**********************************************/ 242dea3101eS int 24392d7f7b0SJames Smart lpfc_read_sparam(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb, int vpi) 244dea3101eS { 245dea3101eS struct lpfc_dmabuf *mp; 246dea3101eS MAILBOX_t *mb; 247dea3101eS struct lpfc_sli *psli; 248dea3101eS 249dea3101eS psli = &phba->sli; 250dea3101eS mb = &pmb->mb; 251dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 252dea3101eS 253dea3101eS mb->mbxOwner = OWN_HOST; 254dea3101eS 255dea3101eS /* Get a buffer to hold the HBAs Service Parameters */ 256dea3101eS 257dea3101eS if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) || 258dea3101eS ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { 259dea3101eS kfree(mp); 260dea3101eS mb->mbxCommand = MBX_READ_SPARM64; 261dea3101eS /* READ_SPARAM: no buffers */ 262dea3101eS lpfc_printf_log(phba, 263dea3101eS KERN_WARNING, 264dea3101eS LOG_MBOX, 265dea3101eS "%d:0301 READ_SPARAM: no buffers\n", 266dea3101eS phba->brd_no); 26792d7f7b0SJames Smart return (1); 268dea3101eS } 269dea3101eS INIT_LIST_HEAD(&mp->list); 270dea3101eS mb->mbxCommand = MBX_READ_SPARM64; 271dea3101eS mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); 272dea3101eS mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys); 273dea3101eS mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys); 27492d7f7b0SJames Smart mb->un.varRdSparm.vpi = vpi; 275dea3101eS 276dea3101eS /* save address for completion */ 277dea3101eS pmb->context1 = mp; 278dea3101eS 27992d7f7b0SJames Smart return (0); 280dea3101eS } 281dea3101eS 282dea3101eS /********************************************/ 283dea3101eS /* lpfc_unreg_did Issue a UNREG_DID */ 284dea3101eS /* mailbox command */ 285dea3101eS /********************************************/ 286dea3101eS void 28792d7f7b0SJames Smart lpfc_unreg_did(struct lpfc_hba * phba, uint16_t vpi, uint32_t did, 28892d7f7b0SJames Smart LPFC_MBOXQ_t * pmb) 289dea3101eS { 290dea3101eS MAILBOX_t *mb; 291dea3101eS 292dea3101eS mb = &pmb->mb; 293dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 294dea3101eS 295dea3101eS mb->un.varUnregDID.did = did; 29692d7f7b0SJames Smart mb->un.varUnregDID.vpi = vpi; 297dea3101eS 298dea3101eS mb->mbxCommand = MBX_UNREG_D_ID; 299dea3101eS mb->mbxOwner = OWN_HOST; 300dea3101eS return; 301dea3101eS } 302dea3101eS 303dea3101eS /**********************************************/ 304dea3101eS /* lpfc_read_nv Issue a READ CONFIG */ 305dea3101eS /* mailbox command */ 306dea3101eS /**********************************************/ 307dea3101eS void 308dea3101eS lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 309dea3101eS { 310dea3101eS MAILBOX_t *mb; 311dea3101eS 312dea3101eS mb = &pmb->mb; 313dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 314dea3101eS 315dea3101eS mb->mbxCommand = MBX_READ_CONFIG; 316dea3101eS mb->mbxOwner = OWN_HOST; 317dea3101eS return; 318dea3101eS } 319dea3101eS 3207bb3b137SJamie Wellnitz /*************************************************/ 3217bb3b137SJamie Wellnitz /* lpfc_read_lnk_stat Issue a READ LINK STATUS */ 3227bb3b137SJamie Wellnitz /* mailbox command */ 3237bb3b137SJamie Wellnitz /*************************************************/ 3247bb3b137SJamie Wellnitz void 3257bb3b137SJamie Wellnitz lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 3267bb3b137SJamie Wellnitz { 3277bb3b137SJamie Wellnitz MAILBOX_t *mb; 3287bb3b137SJamie Wellnitz 3297bb3b137SJamie Wellnitz mb = &pmb->mb; 3307bb3b137SJamie Wellnitz memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 3317bb3b137SJamie Wellnitz 3327bb3b137SJamie Wellnitz mb->mbxCommand = MBX_READ_LNK_STAT; 3337bb3b137SJamie Wellnitz mb->mbxOwner = OWN_HOST; 3347bb3b137SJamie Wellnitz return; 3357bb3b137SJamie Wellnitz } 3367bb3b137SJamie Wellnitz 337dea3101eS /********************************************/ 338dea3101eS /* lpfc_reg_login Issue a REG_LOGIN */ 339dea3101eS /* mailbox command */ 340dea3101eS /********************************************/ 341dea3101eS int 34292d7f7b0SJames Smart lpfc_reg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t did, 34392d7f7b0SJames Smart uint8_t *param, LPFC_MBOXQ_t *pmb, uint32_t flag) 344dea3101eS { 3452e0fef85SJames Smart MAILBOX_t *mb = &pmb->mb; 346dea3101eS uint8_t *sparam; 347dea3101eS struct lpfc_dmabuf *mp; 348dea3101eS 349dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 350dea3101eS 351dea3101eS mb->un.varRegLogin.rpi = 0; 35292d7f7b0SJames Smart mb->un.varRegLogin.vpi = vpi; 353dea3101eS mb->un.varRegLogin.did = did; 354dea3101eS mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */ 355dea3101eS 356dea3101eS mb->mbxOwner = OWN_HOST; 357dea3101eS 358dea3101eS /* Get a buffer to hold NPorts Service Parameters */ 359dea3101eS if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) || 360dea3101eS ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { 361dea3101eS kfree(mp); 362dea3101eS mb->mbxCommand = MBX_REG_LOGIN64; 363dea3101eS /* REG_LOGIN: no buffers */ 36492d7f7b0SJames Smart lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX, 36592d7f7b0SJames Smart "%d (%d):0302 REG_LOGIN: no buffers, DID x%x, " 36692d7f7b0SJames Smart "flag x%x\n", 36792d7f7b0SJames Smart phba->brd_no, vpi, did, flag); 36892d7f7b0SJames Smart return (1); 369dea3101eS } 370dea3101eS INIT_LIST_HEAD(&mp->list); 371dea3101eS sparam = mp->virt; 372dea3101eS 373dea3101eS /* Copy param's into a new buffer */ 374dea3101eS memcpy(sparam, param, sizeof (struct serv_parm)); 375dea3101eS 376dea3101eS /* save address for completion */ 377dea3101eS pmb->context1 = (uint8_t *) mp; 378dea3101eS 379dea3101eS mb->mbxCommand = MBX_REG_LOGIN64; 380dea3101eS mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); 381dea3101eS mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys); 382dea3101eS mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys); 383dea3101eS 38492d7f7b0SJames Smart return (0); 385dea3101eS } 386dea3101eS 387dea3101eS /**********************************************/ 388dea3101eS /* lpfc_unreg_login Issue a UNREG_LOGIN */ 389dea3101eS /* mailbox command */ 390dea3101eS /**********************************************/ 391dea3101eS void 39292d7f7b0SJames Smart lpfc_unreg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t rpi, 39392d7f7b0SJames Smart LPFC_MBOXQ_t * pmb) 394dea3101eS { 395dea3101eS MAILBOX_t *mb; 396dea3101eS 397dea3101eS mb = &pmb->mb; 398dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 399dea3101eS 400dea3101eS mb->un.varUnregLogin.rpi = (uint16_t) rpi; 401dea3101eS mb->un.varUnregLogin.rsvd1 = 0; 40292d7f7b0SJames Smart mb->un.varUnregLogin.vpi = vpi; 403dea3101eS 404dea3101eS mb->mbxCommand = MBX_UNREG_LOGIN; 405dea3101eS mb->mbxOwner = OWN_HOST; 406dea3101eS return; 407dea3101eS } 408dea3101eS 40992d7f7b0SJames Smart /**************************************************/ 41092d7f7b0SJames Smart /* lpfc_reg_vpi Issue a REG_VPI */ 41192d7f7b0SJames Smart /* mailbox command */ 41292d7f7b0SJames Smart /**************************************************/ 41392d7f7b0SJames Smart void 41492d7f7b0SJames Smart lpfc_reg_vpi(struct lpfc_hba *phba, uint16_t vpi, uint32_t sid, 41592d7f7b0SJames Smart LPFC_MBOXQ_t *pmb) 41692d7f7b0SJames Smart { 41792d7f7b0SJames Smart MAILBOX_t *mb = &pmb->mb; 41892d7f7b0SJames Smart 41992d7f7b0SJames Smart memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 42092d7f7b0SJames Smart 42192d7f7b0SJames Smart mb->un.varRegVpi.vpi = vpi; 42292d7f7b0SJames Smart mb->un.varRegVpi.sid = sid; 42392d7f7b0SJames Smart 42492d7f7b0SJames Smart mb->mbxCommand = MBX_REG_VPI; 42592d7f7b0SJames Smart mb->mbxOwner = OWN_HOST; 42692d7f7b0SJames Smart return; 42792d7f7b0SJames Smart 42892d7f7b0SJames Smart } 42992d7f7b0SJames Smart 43092d7f7b0SJames Smart /**************************************************/ 43192d7f7b0SJames Smart /* lpfc_unreg_vpi Issue a UNREG_VNPI */ 43292d7f7b0SJames Smart /* mailbox command */ 43392d7f7b0SJames Smart /**************************************************/ 43492d7f7b0SJames Smart void 43592d7f7b0SJames Smart lpfc_unreg_vpi(struct lpfc_hba *phba, uint16_t vpi, LPFC_MBOXQ_t *pmb) 43692d7f7b0SJames Smart { 43792d7f7b0SJames Smart MAILBOX_t *mb = &pmb->mb; 43892d7f7b0SJames Smart memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 43992d7f7b0SJames Smart 44092d7f7b0SJames Smart mb->un.varUnregVpi.vpi = vpi; 44192d7f7b0SJames Smart 44292d7f7b0SJames Smart mb->mbxCommand = MBX_UNREG_VPI; 44392d7f7b0SJames Smart mb->mbxOwner = OWN_HOST; 44492d7f7b0SJames Smart return; 44592d7f7b0SJames Smart 44692d7f7b0SJames Smart } 44792d7f7b0SJames Smart 448dea3101eS static void 449dea3101eS lpfc_config_pcb_setup(struct lpfc_hba * phba) 450dea3101eS { 451dea3101eS struct lpfc_sli *psli = &phba->sli; 452dea3101eS struct lpfc_sli_ring *pring; 453dea3101eS PCB_t *pcbp = &phba->slim2p->pcb; 454dea3101eS dma_addr_t pdma_addr; 455dea3101eS uint32_t offset; 4562e0fef85SJames Smart uint32_t iocbCnt = 0; 457dea3101eS int i; 458dea3101eS 459dea3101eS pcbp->maxRing = (psli->num_rings - 1); 460dea3101eS 461dea3101eS for (i = 0; i < psli->num_rings; i++) { 462dea3101eS pring = &psli->ring[i]; 4632e0fef85SJames Smart 464ed957684SJames Smart pring->sizeCiocb = phba->sli_rev == 3 ? SLI3_IOCB_CMD_SIZE: 465ed957684SJames Smart SLI2_IOCB_CMD_SIZE; 466ed957684SJames Smart pring->sizeRiocb = phba->sli_rev == 3 ? SLI3_IOCB_RSP_SIZE: 467ed957684SJames Smart SLI2_IOCB_RSP_SIZE; 468dea3101eS /* A ring MUST have both cmd and rsp entries defined to be 469dea3101eS valid */ 470dea3101eS if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) { 471dea3101eS pcbp->rdsc[i].cmdEntries = 0; 472dea3101eS pcbp->rdsc[i].rspEntries = 0; 473dea3101eS pcbp->rdsc[i].cmdAddrHigh = 0; 474dea3101eS pcbp->rdsc[i].rspAddrHigh = 0; 475dea3101eS pcbp->rdsc[i].cmdAddrLow = 0; 476dea3101eS pcbp->rdsc[i].rspAddrLow = 0; 477dea3101eS pring->cmdringaddr = NULL; 478dea3101eS pring->rspringaddr = NULL; 479dea3101eS continue; 480dea3101eS } 481dea3101eS /* Command ring setup for ring */ 482ed957684SJames Smart pring->cmdringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt]; 483dea3101eS pcbp->rdsc[i].cmdEntries = pring->numCiocb; 484dea3101eS 485dea3101eS offset = (uint8_t *) &phba->slim2p->IOCBs[iocbCnt] - 486dea3101eS (uint8_t *) phba->slim2p; 487dea3101eS pdma_addr = phba->slim2p_mapping + offset; 488dea3101eS pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr); 489dea3101eS pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr); 490dea3101eS iocbCnt += pring->numCiocb; 491dea3101eS 492dea3101eS /* Response ring setup for ring */ 493ed957684SJames Smart pring->rspringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt]; 494dea3101eS 495dea3101eS pcbp->rdsc[i].rspEntries = pring->numRiocb; 496dea3101eS offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - 497dea3101eS (uint8_t *)phba->slim2p; 498dea3101eS pdma_addr = phba->slim2p_mapping + offset; 499dea3101eS pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr); 500dea3101eS pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr); 501dea3101eS iocbCnt += pring->numRiocb; 502dea3101eS } 503dea3101eS } 504dea3101eS 505dea3101eS void 506dea3101eS lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 507dea3101eS { 5082e0fef85SJames Smart MAILBOX_t *mb = &pmb->mb; 509dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 510dea3101eS mb->un.varRdRev.cv = 1; 511ed957684SJames Smart mb->un.varRdRev.v3req = 1; /* Request SLI3 info */ 512dea3101eS mb->mbxCommand = MBX_READ_REV; 513dea3101eS mb->mbxOwner = OWN_HOST; 514dea3101eS return; 515dea3101eS } 516dea3101eS 517ed957684SJames Smart static void 518ed957684SJames Smart lpfc_build_hbq_profile2(struct config_hbq_var *hbqmb, 519ed957684SJames Smart struct lpfc_hbq_init *hbq_desc) 520ed957684SJames Smart { 521ed957684SJames Smart hbqmb->profiles.profile2.seqlenbcnt = hbq_desc->seqlenbcnt; 522ed957684SJames Smart hbqmb->profiles.profile2.maxlen = hbq_desc->maxlen; 523ed957684SJames Smart hbqmb->profiles.profile2.seqlenoff = hbq_desc->seqlenoff; 524ed957684SJames Smart } 525ed957684SJames Smart 526ed957684SJames Smart static void 527ed957684SJames Smart lpfc_build_hbq_profile3(struct config_hbq_var *hbqmb, 528ed957684SJames Smart struct lpfc_hbq_init *hbq_desc) 529ed957684SJames Smart { 530ed957684SJames Smart hbqmb->profiles.profile3.seqlenbcnt = hbq_desc->seqlenbcnt; 531ed957684SJames Smart hbqmb->profiles.profile3.maxlen = hbq_desc->maxlen; 532ed957684SJames Smart hbqmb->profiles.profile3.cmdcodeoff = hbq_desc->cmdcodeoff; 533ed957684SJames Smart hbqmb->profiles.profile3.seqlenoff = hbq_desc->seqlenoff; 534ed957684SJames Smart memcpy(&hbqmb->profiles.profile3.cmdmatch, hbq_desc->cmdmatch, 535ed957684SJames Smart sizeof(hbqmb->profiles.profile3.cmdmatch)); 536ed957684SJames Smart } 537ed957684SJames Smart 538ed957684SJames Smart static void 539ed957684SJames Smart lpfc_build_hbq_profile5(struct config_hbq_var *hbqmb, 540ed957684SJames Smart struct lpfc_hbq_init *hbq_desc) 541ed957684SJames Smart { 542ed957684SJames Smart hbqmb->profiles.profile5.seqlenbcnt = hbq_desc->seqlenbcnt; 543ed957684SJames Smart hbqmb->profiles.profile5.maxlen = hbq_desc->maxlen; 544ed957684SJames Smart hbqmb->profiles.profile5.cmdcodeoff = hbq_desc->cmdcodeoff; 545ed957684SJames Smart hbqmb->profiles.profile5.seqlenoff = hbq_desc->seqlenoff; 546ed957684SJames Smart memcpy(&hbqmb->profiles.profile5.cmdmatch, hbq_desc->cmdmatch, 547ed957684SJames Smart sizeof(hbqmb->profiles.profile5.cmdmatch)); 548ed957684SJames Smart } 549ed957684SJames Smart 550ed957684SJames Smart void 551ed957684SJames Smart lpfc_config_hbq(struct lpfc_hba *phba, struct lpfc_hbq_init *hbq_desc, 552ed957684SJames Smart uint32_t hbq_entry_index, LPFC_MBOXQ_t *pmb) 553ed957684SJames Smart { 554ed957684SJames Smart int i; 555ed957684SJames Smart MAILBOX_t *mb = &pmb->mb; 556ed957684SJames Smart struct config_hbq_var *hbqmb = &mb->un.varCfgHbq; 557ed957684SJames Smart 558ed957684SJames Smart memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 559ed957684SJames Smart hbqmb->entry_count = hbq_desc->entry_count; /* # entries in HBQ */ 560ed957684SJames Smart hbqmb->recvNotify = hbq_desc->rn; /* Receive 561ed957684SJames Smart * Notification */ 562ed957684SJames Smart hbqmb->numMask = hbq_desc->mask_count; /* # R_CTL/TYPE masks 563ed957684SJames Smart * # in words 0-19 */ 564ed957684SJames Smart hbqmb->profile = hbq_desc->profile; /* Selection profile: 565ed957684SJames Smart * 0 = all, 566ed957684SJames Smart * 7 = logentry */ 567ed957684SJames Smart hbqmb->ringMask = hbq_desc->ring_mask; /* Binds HBQ to a ring 568ed957684SJames Smart * e.g. Ring0=b0001, 569ed957684SJames Smart * ring2=b0100 */ 570ed957684SJames Smart hbqmb->headerLen = hbq_desc->headerLen; /* 0 if not profile 4 571ed957684SJames Smart * or 5 */ 572ed957684SJames Smart hbqmb->logEntry = hbq_desc->logEntry; /* Set to 1 if this 573ed957684SJames Smart * HBQ will be used 574ed957684SJames Smart * for LogEntry 575ed957684SJames Smart * buffers */ 576ed957684SJames Smart hbqmb->hbqaddrLow = putPaddrLow(phba->hbqslimp.phys) + 577ed957684SJames Smart hbq_entry_index * sizeof(struct lpfc_hbq_entry); 578ed957684SJames Smart hbqmb->hbqaddrHigh = putPaddrHigh(phba->hbqslimp.phys); 579ed957684SJames Smart 580ed957684SJames Smart mb->mbxCommand = MBX_CONFIG_HBQ; 581ed957684SJames Smart mb->mbxOwner = OWN_HOST; 582ed957684SJames Smart 583ed957684SJames Smart /* Copy info for profiles 2,3,5. Other 584ed957684SJames Smart * profiles this area is reserved 585ed957684SJames Smart */ 586ed957684SJames Smart if (hbq_desc->profile == 2) 587ed957684SJames Smart lpfc_build_hbq_profile2(hbqmb, hbq_desc); 588ed957684SJames Smart else if (hbq_desc->profile == 3) 589ed957684SJames Smart lpfc_build_hbq_profile3(hbqmb, hbq_desc); 590ed957684SJames Smart else if (hbq_desc->profile == 5) 591ed957684SJames Smart lpfc_build_hbq_profile5(hbqmb, hbq_desc); 592ed957684SJames Smart 593ed957684SJames Smart /* Return if no rctl / type masks for this HBQ */ 594ed957684SJames Smart if (!hbq_desc->mask_count) 595ed957684SJames Smart return; 596ed957684SJames Smart 597ed957684SJames Smart /* Otherwise we setup specific rctl / type masks for this HBQ */ 598ed957684SJames Smart for (i = 0; i < hbq_desc->mask_count; i++) { 599ed957684SJames Smart hbqmb->hbqMasks[i].tmatch = hbq_desc->hbqMasks[i].tmatch; 600ed957684SJames Smart hbqmb->hbqMasks[i].tmask = hbq_desc->hbqMasks[i].tmask; 601ed957684SJames Smart hbqmb->hbqMasks[i].rctlmatch = hbq_desc->hbqMasks[i].rctlmatch; 602ed957684SJames Smart hbqmb->hbqMasks[i].rctlmask = hbq_desc->hbqMasks[i].rctlmask; 603ed957684SJames Smart } 604ed957684SJames Smart 605ed957684SJames Smart return; 606ed957684SJames Smart } 607ed957684SJames Smart 60892d7f7b0SJames Smart 60992d7f7b0SJames Smart 610dea3101eS void 611dea3101eS lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb) 612dea3101eS { 613dea3101eS int i; 614dea3101eS MAILBOX_t *mb = &pmb->mb; 615dea3101eS struct lpfc_sli *psli; 616dea3101eS struct lpfc_sli_ring *pring; 617dea3101eS 618dea3101eS memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); 619dea3101eS 620dea3101eS mb->un.varCfgRing.ring = ring; 621dea3101eS mb->un.varCfgRing.maxOrigXchg = 0; 622dea3101eS mb->un.varCfgRing.maxRespXchg = 0; 623dea3101eS mb->un.varCfgRing.recvNotify = 1; 624dea3101eS 625dea3101eS psli = &phba->sli; 626dea3101eS pring = &psli->ring[ring]; 627dea3101eS mb->un.varCfgRing.numMask = pring->num_mask; 628dea3101eS mb->mbxCommand = MBX_CONFIG_RING; 629dea3101eS mb->mbxOwner = OWN_HOST; 630dea3101eS 631dea3101eS /* Is this ring configured for a specific profile */ 632dea3101eS if (pring->prt[0].profile) { 633dea3101eS mb->un.varCfgRing.profile = pring->prt[0].profile; 634dea3101eS return; 635dea3101eS } 636dea3101eS 637dea3101eS /* Otherwise we setup specific rctl / type masks for this ring */ 638dea3101eS for (i = 0; i < pring->num_mask; i++) { 639dea3101eS mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl; 640dea3101eS if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ) 641dea3101eS mb->un.varCfgRing.rrRegs[i].rmask = 0xff; 642dea3101eS else 643dea3101eS mb->un.varCfgRing.rrRegs[i].rmask = 0xfe; 644dea3101eS mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type; 645dea3101eS mb->un.varCfgRing.rrRegs[i].tmask = 0xff; 646dea3101eS } 647dea3101eS 648dea3101eS return; 649dea3101eS } 650dea3101eS 651dea3101eS void 652dea3101eS lpfc_config_port(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb) 653dea3101eS { 654ed957684SJames Smart MAILBOX_t __iomem *mb_slim = (MAILBOX_t __iomem *) phba->MBslimaddr; 655dea3101eS MAILBOX_t *mb = &pmb->mb; 656dea3101eS dma_addr_t pdma_addr; 657dea3101eS uint32_t bar_low, bar_high; 658dea3101eS size_t offset; 6594cc2da1dSJames.Smart@Emulex.Com struct lpfc_hgp hgp; 660f91b392cSJames.Smart@Emulex.Com int i; 661ed957684SJames Smart uint32_t pgp_offset; 662dea3101eS 663dea3101eS memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); 664dea3101eS mb->mbxCommand = MBX_CONFIG_PORT; 665dea3101eS mb->mbxOwner = OWN_HOST; 666dea3101eS 667dea3101eS mb->un.varCfgPort.pcbLen = sizeof(PCB_t); 668dea3101eS 669dea3101eS offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p; 670dea3101eS pdma_addr = phba->slim2p_mapping + offset; 671dea3101eS mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr); 672dea3101eS mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr); 673dea3101eS 674ed957684SJames Smart /* If HBA supports SLI=3 ask for it */ 675ed957684SJames Smart 67692d7f7b0SJames Smart if (phba->sli_rev == 3 && phba->vpd.sli3Feat.cerbm) { 677ed957684SJames Smart mb->un.varCfgPort.cerbm = 1; /* Request HBQs */ 678ed957684SJames Smart mb->un.varCfgPort.max_hbq = 1; /* Requesting 2 HBQs */ 67992d7f7b0SJames Smart if (phba->max_vpi && lpfc_npiv_enable && 68092d7f7b0SJames Smart phba->vpd.sli3Feat.cmv) { 68192d7f7b0SJames Smart mb->un.varCfgPort.max_vpi = phba->max_vpi; 68292d7f7b0SJames Smart mb->un.varCfgPort.cmv = 1; 68392d7f7b0SJames Smart phba->sli3_options |= LPFC_SLI3_NPIV_ENABLED; 68492d7f7b0SJames Smart } else 68592d7f7b0SJames Smart mb->un.varCfgPort.max_vpi = phba->max_vpi = 0; 68692d7f7b0SJames Smart } else 68792d7f7b0SJames Smart phba->sli_rev = 2; 68892d7f7b0SJames Smart mb->un.varCfgPort.sli_mode = phba->sli_rev; 689ed957684SJames Smart 690dea3101eS /* Now setup pcb */ 691dea3101eS phba->slim2p->pcb.type = TYPE_NATIVE_SLI2; 692dea3101eS phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2; 693dea3101eS 694dea3101eS /* Setup Mailbox pointers */ 695ed957684SJames Smart phba->slim2p->pcb.mailBoxSize = offsetof(MAILBOX_t, us) + 696ed957684SJames Smart sizeof(struct sli2_desc); 697dea3101eS offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p; 698dea3101eS pdma_addr = phba->slim2p_mapping + offset; 699dea3101eS phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr); 700dea3101eS phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr); 701dea3101eS 702dea3101eS /* 703dea3101eS * Setup Host Group ring pointer. 704dea3101eS * 705dea3101eS * For efficiency reasons, the ring get/put pointers can be 706dea3101eS * placed in adapter memory (SLIM) rather than in host memory. 707dea3101eS * This allows firmware to avoid PCI reads/writes when updating 708dea3101eS * and checking pointers. 709dea3101eS * 710dea3101eS * The firmware recognizes the use of SLIM memory by comparing 711dea3101eS * the address of the get/put pointers structure with that of 712dea3101eS * the SLIM BAR (BAR0). 713dea3101eS * 714dea3101eS * Caution: be sure to use the PCI config space value of BAR0/BAR1 715dea3101eS * (the hardware's view of the base address), not the OS's 716dea3101eS * value of pci_resource_start() as the OS value may be a cookie 717dea3101eS * for ioremap/iomap. 718dea3101eS */ 719dea3101eS 720dea3101eS 721dea3101eS pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low); 722dea3101eS pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high); 723dea3101eS 724ed957684SJames Smart /* 725ed957684SJames Smart * Set up HGP - Port Memory 726ed957684SJames Smart * 727ed957684SJames Smart * The port expects the host get/put pointers to reside in memory 728ed957684SJames Smart * following the "non-diagnostic" mode mailbox (32 words, 0x80 bytes) 729ed957684SJames Smart * area of SLIM. In SLI-2 mode, there's an additional 16 reserved 730ed957684SJames Smart * words (0x40 bytes). This area is not reserved if HBQs are 731ed957684SJames Smart * configured in SLI-3. 732ed957684SJames Smart * 733ed957684SJames Smart * CR0Put - SLI2(no HBQs) = 0xc0, With HBQs = 0x80 734ed957684SJames Smart * RR0Get 0xc4 0x84 735ed957684SJames Smart * CR1Put 0xc8 0x88 736ed957684SJames Smart * RR1Get 0xcc 0x8c 737ed957684SJames Smart * CR2Put 0xd0 0x90 738ed957684SJames Smart * RR2Get 0xd4 0x94 739ed957684SJames Smart * CR3Put 0xd8 0x98 740ed957684SJames Smart * RR3Get 0xdc 0x9c 741ed957684SJames Smart * 742ed957684SJames Smart * Reserved 0xa0-0xbf 743ed957684SJames Smart * If HBQs configured: 744ed957684SJames Smart * HBQ 0 Put ptr 0xc0 745ed957684SJames Smart * HBQ 1 Put ptr 0xc4 746ed957684SJames Smart * HBQ 2 Put ptr 0xc8 747ed957684SJames Smart * ...... 748ed957684SJames Smart * HBQ(M-1)Put Pointer 0xc0+(M-1)*4 749ed957684SJames Smart * 750ed957684SJames Smart */ 751ed957684SJames Smart 752ed957684SJames Smart if (phba->sli_rev == 3) { 753ed957684SJames Smart phba->host_gp = &mb_slim->us.s3.host[0]; 754ed957684SJames Smart phba->hbq_put = &mb_slim->us.s3.hbq_put[0]; 755ed957684SJames Smart } else { 756ed957684SJames Smart phba->host_gp = &mb_slim->us.s2.host[0]; 757ed957684SJames Smart phba->hbq_put = NULL; 758ed957684SJames Smart } 759dea3101eS 760dea3101eS /* mask off BAR0's flag bits 0 - 3 */ 761dea3101eS phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) + 762ed957684SJames Smart (void __iomem *) phba->host_gp - 763ed957684SJames Smart (void __iomem *)phba->MBslimaddr; 764dea3101eS if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64) 765dea3101eS phba->slim2p->pcb.hgpAddrHigh = bar_high; 766dea3101eS else 767dea3101eS phba->slim2p->pcb.hgpAddrHigh = 0; 768dea3101eS /* write HGP data to SLIM at the required longword offset */ 7694cc2da1dSJames.Smart@Emulex.Com memset(&hgp, 0, sizeof(struct lpfc_hgp)); 770f91b392cSJames.Smart@Emulex.Com 771f91b392cSJames.Smart@Emulex.Com for (i=0; i < phba->sli.num_rings; i++) { 772ed957684SJames Smart lpfc_memcpy_to_slim(phba->host_gp + i, &hgp, 773ed957684SJames Smart sizeof(*phba->host_gp)); 774f91b392cSJames.Smart@Emulex.Com } 775dea3101eS 776dea3101eS /* Setup Port Group ring pointer */ 777ed957684SJames Smart if (phba->sli_rev == 3) 778ed957684SJames Smart pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s3_pgp.port - 779dea3101eS (uint8_t *)phba->slim2p; 780ed957684SJames Smart else 781ed957684SJames Smart pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port - 782ed957684SJames Smart (uint8_t *)phba->slim2p; 783ed957684SJames Smart 784ed957684SJames Smart pdma_addr = phba->slim2p_mapping + pgp_offset; 785dea3101eS phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr); 786dea3101eS phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr); 787ed957684SJames Smart phba->hbq_get = &phba->slim2p->mbx.us.s3_pgp.hbq_get[0]; 788dea3101eS 789dea3101eS /* Use callback routine to setp rings in the pcb */ 790dea3101eS lpfc_config_pcb_setup(phba); 791dea3101eS 792dea3101eS /* special handling for LC HBAs */ 793dea3101eS if (lpfc_is_LC_HBA(phba->pcidev->device)) { 794dea3101eS uint32_t hbainit[5]; 795dea3101eS 796dea3101eS lpfc_hba_init(phba, hbainit); 797dea3101eS 798dea3101eS memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20); 799dea3101eS } 800dea3101eS 801dea3101eS /* Swap PCB if needed */ 802dea3101eS lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb, 803dea3101eS sizeof(PCB_t)); 804dea3101eS } 805dea3101eS 806dea3101eS void 80741415862SJamie Wellnitz lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) 80841415862SJamie Wellnitz { 80941415862SJamie Wellnitz MAILBOX_t *mb = &pmb->mb; 81041415862SJamie Wellnitz 81141415862SJamie Wellnitz memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); 81241415862SJamie Wellnitz mb->mbxCommand = MBX_KILL_BOARD; 81341415862SJamie Wellnitz mb->mbxOwner = OWN_HOST; 81441415862SJamie Wellnitz return; 81541415862SJamie Wellnitz } 81641415862SJamie Wellnitz 81741415862SJamie Wellnitz void 818dea3101eS lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) 819dea3101eS { 820dea3101eS struct lpfc_sli *psli; 821dea3101eS 822dea3101eS psli = &phba->sli; 823dea3101eS 824dea3101eS list_add_tail(&mbq->list, &psli->mboxq); 825dea3101eS 826dea3101eS psli->mboxq_cnt++; 827dea3101eS 828dea3101eS return; 829dea3101eS } 830dea3101eS 831dea3101eS LPFC_MBOXQ_t * 832dea3101eS lpfc_mbox_get(struct lpfc_hba * phba) 833dea3101eS { 834dea3101eS LPFC_MBOXQ_t *mbq = NULL; 835dea3101eS struct lpfc_sli *psli = &phba->sli; 836dea3101eS 8372e0fef85SJames Smart list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, list); 83892d7f7b0SJames Smart if (mbq) 839dea3101eS psli->mboxq_cnt--; 840dea3101eS 841dea3101eS return mbq; 842dea3101eS } 843a309a6b6SJames Smart 84492d7f7b0SJames Smart void 84592d7f7b0SJames Smart lpfc_mbox_cmpl_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) 84692d7f7b0SJames Smart { 84792d7f7b0SJames Smart /* This function expects to be called from interupt context */ 84892d7f7b0SJames Smart spin_lock(&phba->hbalock); 84992d7f7b0SJames Smart list_add_tail(&mbq->list, &phba->sli.mboxq_cmpl); 85092d7f7b0SJames Smart spin_unlock(&phba->hbalock); 85192d7f7b0SJames Smart return; 85292d7f7b0SJames Smart } 85392d7f7b0SJames Smart 854a309a6b6SJames Smart int 855a309a6b6SJames Smart lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd) 856a309a6b6SJames Smart { 857a309a6b6SJames Smart switch (cmd) { 858a309a6b6SJames Smart case MBX_WRITE_NV: /* 0x03 */ 859a309a6b6SJames Smart case MBX_UPDATE_CFG: /* 0x1B */ 860a309a6b6SJames Smart case MBX_DOWN_LOAD: /* 0x1C */ 861a309a6b6SJames Smart case MBX_DEL_LD_ENTRY: /* 0x1D */ 862a309a6b6SJames Smart case MBX_LOAD_AREA: /* 0x81 */ 863a309a6b6SJames Smart case MBX_FLASH_WR_ULA: /* 0x98 */ 864a309a6b6SJames Smart case MBX_LOAD_EXP_ROM: /* 0x9C */ 865a309a6b6SJames Smart return LPFC_MBOX_TMO_FLASH_CMD; 866a309a6b6SJames Smart } 867a309a6b6SJames Smart return LPFC_MBOX_TMO; 868a309a6b6SJames Smart } 869