1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 /* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46 #define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52 #define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56 #define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60 struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63 }; 64 65 struct lpfc_sli_intf { 66 uint32_t word0; 67 #define lpfc_sli_intf_valid_SHIFT 29 68 #define lpfc_sli_intf_valid_MASK 0x00000007 69 #define lpfc_sli_intf_valid_WORD word0 70 #define LPFC_SLI_INTF_VALID 6 71 #define lpfc_sli_intf_sli_hint2_SHIFT 24 72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73 #define lpfc_sli_intf_sli_hint2_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75 #define lpfc_sli_intf_sli_hint1_SHIFT 16 76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77 #define lpfc_sli_intf_sli_hint1_WORD word0 78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79 #define LPFC_SLI_INTF_SLI_HINT1_1 1 80 #define LPFC_SLI_INTF_SLI_HINT1_2 2 81 #define lpfc_sli_intf_if_type_SHIFT 12 82 #define lpfc_sli_intf_if_type_MASK 0x0000000F 83 #define lpfc_sli_intf_if_type_WORD word0 84 #define LPFC_SLI_INTF_IF_TYPE_0 0 85 #define LPFC_SLI_INTF_IF_TYPE_1 1 86 #define LPFC_SLI_INTF_IF_TYPE_2 2 87 #define lpfc_sli_intf_sli_family_SHIFT 8 88 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 89 #define lpfc_sli_intf_sli_family_WORD word0 90 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 91 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 92 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 93 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 94 #define lpfc_sli_intf_slirev_SHIFT 4 95 #define lpfc_sli_intf_slirev_MASK 0x0000000F 96 #define lpfc_sli_intf_slirev_WORD word0 97 #define LPFC_SLI_INTF_REV_SLI3 3 98 #define LPFC_SLI_INTF_REV_SLI4 4 99 #define lpfc_sli_intf_func_type_SHIFT 0 100 #define lpfc_sli_intf_func_type_MASK 0x00000001 101 #define lpfc_sli_intf_func_type_WORD word0 102 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 103 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 104 }; 105 106 #define LPFC_SLI4_MBX_EMBED true 107 #define LPFC_SLI4_MBX_NEMBED false 108 109 #define LPFC_SLI4_MB_WORD_COUNT 64 110 #define LPFC_MAX_MQ_PAGE 8 111 #define LPFC_MAX_WQ_PAGE_V0 4 112 #define LPFC_MAX_WQ_PAGE 8 113 #define LPFC_MAX_RQ_PAGE 8 114 #define LPFC_MAX_CQ_PAGE 4 115 #define LPFC_MAX_EQ_PAGE 8 116 117 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 118 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 119 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 120 121 /* Define SLI4 Alignment requirements. */ 122 #define LPFC_ALIGN_16_BYTE 16 123 #define LPFC_ALIGN_64_BYTE 64 124 125 /* Define SLI4 specific definitions. */ 126 #define LPFC_MQ_CQE_BYTE_OFFSET 256 127 #define LPFC_MBX_CMD_HDR_LENGTH 16 128 #define LPFC_MBX_ERROR_RANGE 0x4000 129 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 130 #define LPFC_BMBX_BIT1_ADDR_LO 0 131 #define LPFC_RPI_HDR_COUNT 64 132 #define LPFC_HDR_TEMPLATE_SIZE 4096 133 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 134 #define LPFC_FCF_RECORD_WD_CNT 132 135 #define LPFC_ENTIRE_FCF_DATABASE 0 136 #define LPFC_DFLT_FCF_INDEX 0 137 138 /* Virtual function numbers */ 139 #define LPFC_VF0 0 140 #define LPFC_VF1 1 141 #define LPFC_VF2 2 142 #define LPFC_VF3 3 143 #define LPFC_VF4 4 144 #define LPFC_VF5 5 145 #define LPFC_VF6 6 146 #define LPFC_VF7 7 147 #define LPFC_VF8 8 148 #define LPFC_VF9 9 149 #define LPFC_VF10 10 150 #define LPFC_VF11 11 151 #define LPFC_VF12 12 152 #define LPFC_VF13 13 153 #define LPFC_VF14 14 154 #define LPFC_VF15 15 155 #define LPFC_VF16 16 156 #define LPFC_VF17 17 157 #define LPFC_VF18 18 158 #define LPFC_VF19 19 159 #define LPFC_VF20 20 160 #define LPFC_VF21 21 161 #define LPFC_VF22 22 162 #define LPFC_VF23 23 163 #define LPFC_VF24 24 164 #define LPFC_VF25 25 165 #define LPFC_VF26 26 166 #define LPFC_VF27 27 167 #define LPFC_VF28 28 168 #define LPFC_VF29 29 169 #define LPFC_VF30 30 170 #define LPFC_VF31 31 171 172 /* PCI function numbers */ 173 #define LPFC_PCI_FUNC0 0 174 #define LPFC_PCI_FUNC1 1 175 #define LPFC_PCI_FUNC2 2 176 #define LPFC_PCI_FUNC3 3 177 #define LPFC_PCI_FUNC4 4 178 179 /* SLI4 interface type-2 PDEV_CTL register */ 180 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 181 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 182 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 183 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 184 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 185 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 186 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 187 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 188 189 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 190 191 /* Active interrupt test count */ 192 #define LPFC_ACT_INTR_CNT 4 193 194 /* Algrithmns for scheduling FCP commands to WQs */ 195 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 196 #define LPFC_FCP_SCHED_BY_CPU 1 197 198 /* Delay Multiplier constant */ 199 #define LPFC_DMULT_CONST 651042 200 201 /* Configuration of Interrupts / sec for entire HBA port */ 202 #define LPFC_MIN_IMAX 5000 203 #define LPFC_MAX_IMAX 5000000 204 #define LPFC_DEF_IMAX 150000 205 206 #define LPFC_MIN_CPU_MAP 0 207 #define LPFC_MAX_CPU_MAP 2 208 #define LPFC_HBA_CPU_MAP 1 209 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 210 211 /* PORT_CAPABILITIES constants. */ 212 #define LPFC_MAX_SUPPORTED_PAGES 8 213 214 struct ulp_bde64 { 215 union ULP_BDE_TUS { 216 uint32_t w; 217 struct { 218 #ifdef __BIG_ENDIAN_BITFIELD 219 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 220 VALUE !! */ 221 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 222 #else /* __LITTLE_ENDIAN_BITFIELD */ 223 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 224 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 225 VALUE !! */ 226 #endif 227 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 228 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 229 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 230 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 231 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 232 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 233 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 234 } f; 235 } tus; 236 uint32_t addrLow; 237 uint32_t addrHigh; 238 }; 239 240 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 241 #define LPFC_MAX_BDE_IMM_SIZE 64 242 243 struct lpfc_sli4_flags { 244 uint32_t word0; 245 #define lpfc_idx_rsrc_rdy_SHIFT 0 246 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 247 #define lpfc_idx_rsrc_rdy_WORD word0 248 #define LPFC_IDX_RSRC_RDY 1 249 #define lpfc_rpi_rsrc_rdy_SHIFT 1 250 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 251 #define lpfc_rpi_rsrc_rdy_WORD word0 252 #define LPFC_RPI_RSRC_RDY 1 253 #define lpfc_vpi_rsrc_rdy_SHIFT 2 254 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 255 #define lpfc_vpi_rsrc_rdy_WORD word0 256 #define LPFC_VPI_RSRC_RDY 1 257 #define lpfc_vfi_rsrc_rdy_SHIFT 3 258 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 259 #define lpfc_vfi_rsrc_rdy_WORD word0 260 #define LPFC_VFI_RSRC_RDY 1 261 }; 262 263 struct sli4_bls_rsp { 264 uint32_t word0_rsvd; /* Word0 must be reserved */ 265 uint32_t word1; 266 #define lpfc_abts_orig_SHIFT 0 267 #define lpfc_abts_orig_MASK 0x00000001 268 #define lpfc_abts_orig_WORD word1 269 #define LPFC_ABTS_UNSOL_RSP 1 270 #define LPFC_ABTS_UNSOL_INT 0 271 uint32_t word2; 272 #define lpfc_abts_rxid_SHIFT 0 273 #define lpfc_abts_rxid_MASK 0x0000FFFF 274 #define lpfc_abts_rxid_WORD word2 275 #define lpfc_abts_oxid_SHIFT 16 276 #define lpfc_abts_oxid_MASK 0x0000FFFF 277 #define lpfc_abts_oxid_WORD word2 278 uint32_t word3; 279 #define lpfc_vndr_code_SHIFT 0 280 #define lpfc_vndr_code_MASK 0x000000FF 281 #define lpfc_vndr_code_WORD word3 282 #define lpfc_rsn_expln_SHIFT 8 283 #define lpfc_rsn_expln_MASK 0x000000FF 284 #define lpfc_rsn_expln_WORD word3 285 #define lpfc_rsn_code_SHIFT 16 286 #define lpfc_rsn_code_MASK 0x000000FF 287 #define lpfc_rsn_code_WORD word3 288 289 uint32_t word4; 290 uint32_t word5_rsvd; /* Word5 must be reserved */ 291 }; 292 293 /* event queue entry structure */ 294 struct lpfc_eqe { 295 uint32_t word0; 296 #define lpfc_eqe_resource_id_SHIFT 16 297 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 298 #define lpfc_eqe_resource_id_WORD word0 299 #define lpfc_eqe_minor_code_SHIFT 4 300 #define lpfc_eqe_minor_code_MASK 0x00000FFF 301 #define lpfc_eqe_minor_code_WORD word0 302 #define lpfc_eqe_major_code_SHIFT 1 303 #define lpfc_eqe_major_code_MASK 0x00000007 304 #define lpfc_eqe_major_code_WORD word0 305 #define lpfc_eqe_valid_SHIFT 0 306 #define lpfc_eqe_valid_MASK 0x00000001 307 #define lpfc_eqe_valid_WORD word0 308 }; 309 310 /* completion queue entry structure (common fields for all cqe types) */ 311 struct lpfc_cqe { 312 uint32_t reserved0; 313 uint32_t reserved1; 314 uint32_t reserved2; 315 uint32_t word3; 316 #define lpfc_cqe_valid_SHIFT 31 317 #define lpfc_cqe_valid_MASK 0x00000001 318 #define lpfc_cqe_valid_WORD word3 319 #define lpfc_cqe_code_SHIFT 16 320 #define lpfc_cqe_code_MASK 0x000000FF 321 #define lpfc_cqe_code_WORD word3 322 }; 323 324 /* Completion Queue Entry Status Codes */ 325 #define CQE_STATUS_SUCCESS 0x0 326 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 327 #define CQE_STATUS_REMOTE_STOP 0x2 328 #define CQE_STATUS_LOCAL_REJECT 0x3 329 #define CQE_STATUS_NPORT_RJT 0x4 330 #define CQE_STATUS_FABRIC_RJT 0x5 331 #define CQE_STATUS_NPORT_BSY 0x6 332 #define CQE_STATUS_FABRIC_BSY 0x7 333 #define CQE_STATUS_INTERMED_RSP 0x8 334 #define CQE_STATUS_LS_RJT 0x9 335 #define CQE_STATUS_CMD_REJECT 0xb 336 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 337 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 338 #define CQE_STATUS_DI_ERROR 0x16 339 340 /* Used when mapping CQE status to IOCB */ 341 #define LPFC_IOCB_STATUS_MASK 0xf 342 343 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 344 #define CQE_HW_STATUS_NO_ERR 0x0 345 #define CQE_HW_STATUS_UNDERRUN 0x1 346 #define CQE_HW_STATUS_OVERRUN 0x2 347 348 /* Completion Queue Entry Codes */ 349 #define CQE_CODE_COMPL_WQE 0x1 350 #define CQE_CODE_RELEASE_WQE 0x2 351 #define CQE_CODE_RECEIVE 0x4 352 #define CQE_CODE_XRI_ABORTED 0x5 353 #define CQE_CODE_RECEIVE_V1 0x9 354 #define CQE_CODE_NVME_ERSP 0xd 355 356 /* 357 * Define mask value for xri_aborted and wcqe completed CQE extended status. 358 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 359 */ 360 #define WCQE_PARAM_MASK 0x1FF 361 362 /* completion queue entry for wqe completions */ 363 struct lpfc_wcqe_complete { 364 uint32_t word0; 365 #define lpfc_wcqe_c_request_tag_SHIFT 16 366 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 367 #define lpfc_wcqe_c_request_tag_WORD word0 368 #define lpfc_wcqe_c_status_SHIFT 8 369 #define lpfc_wcqe_c_status_MASK 0x000000FF 370 #define lpfc_wcqe_c_status_WORD word0 371 #define lpfc_wcqe_c_hw_status_SHIFT 0 372 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 373 #define lpfc_wcqe_c_hw_status_WORD word0 374 #define lpfc_wcqe_c_ersp0_SHIFT 0 375 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 376 #define lpfc_wcqe_c_ersp0_WORD word0 377 uint32_t total_data_placed; 378 uint32_t parameter; 379 #define lpfc_wcqe_c_bg_edir_SHIFT 5 380 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 381 #define lpfc_wcqe_c_bg_edir_WORD parameter 382 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 383 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 384 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 385 #define lpfc_wcqe_c_bg_re_SHIFT 2 386 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 387 #define lpfc_wcqe_c_bg_re_WORD parameter 388 #define lpfc_wcqe_c_bg_ae_SHIFT 1 389 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 390 #define lpfc_wcqe_c_bg_ae_WORD parameter 391 #define lpfc_wcqe_c_bg_ge_SHIFT 0 392 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 393 #define lpfc_wcqe_c_bg_ge_WORD parameter 394 uint32_t word3; 395 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 396 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 397 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 398 #define lpfc_wcqe_c_xb_SHIFT 28 399 #define lpfc_wcqe_c_xb_MASK 0x00000001 400 #define lpfc_wcqe_c_xb_WORD word3 401 #define lpfc_wcqe_c_pv_SHIFT 27 402 #define lpfc_wcqe_c_pv_MASK 0x00000001 403 #define lpfc_wcqe_c_pv_WORD word3 404 #define lpfc_wcqe_c_priority_SHIFT 24 405 #define lpfc_wcqe_c_priority_MASK 0x00000007 406 #define lpfc_wcqe_c_priority_WORD word3 407 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 408 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 409 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 410 #define lpfc_wcqe_c_sqhead_SHIFT 0 411 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 412 #define lpfc_wcqe_c_sqhead_WORD word3 413 }; 414 415 /* completion queue entry for wqe release */ 416 struct lpfc_wcqe_release { 417 uint32_t reserved0; 418 uint32_t reserved1; 419 uint32_t word2; 420 #define lpfc_wcqe_r_wq_id_SHIFT 16 421 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 422 #define lpfc_wcqe_r_wq_id_WORD word2 423 #define lpfc_wcqe_r_wqe_index_SHIFT 0 424 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 425 #define lpfc_wcqe_r_wqe_index_WORD word2 426 uint32_t word3; 427 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 428 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 429 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 430 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 431 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 432 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 433 }; 434 435 struct sli4_wcqe_xri_aborted { 436 uint32_t word0; 437 #define lpfc_wcqe_xa_status_SHIFT 8 438 #define lpfc_wcqe_xa_status_MASK 0x000000FF 439 #define lpfc_wcqe_xa_status_WORD word0 440 uint32_t parameter; 441 uint32_t word2; 442 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 443 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 444 #define lpfc_wcqe_xa_remote_xid_WORD word2 445 #define lpfc_wcqe_xa_xri_SHIFT 0 446 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 447 #define lpfc_wcqe_xa_xri_WORD word2 448 uint32_t word3; 449 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 450 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 451 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 452 #define lpfc_wcqe_xa_ia_SHIFT 30 453 #define lpfc_wcqe_xa_ia_MASK 0x00000001 454 #define lpfc_wcqe_xa_ia_WORD word3 455 #define CQE_XRI_ABORTED_IA_REMOTE 0 456 #define CQE_XRI_ABORTED_IA_LOCAL 1 457 #define lpfc_wcqe_xa_br_SHIFT 29 458 #define lpfc_wcqe_xa_br_MASK 0x00000001 459 #define lpfc_wcqe_xa_br_WORD word3 460 #define CQE_XRI_ABORTED_BR_BA_ACC 0 461 #define CQE_XRI_ABORTED_BR_BA_RJT 1 462 #define lpfc_wcqe_xa_eo_SHIFT 28 463 #define lpfc_wcqe_xa_eo_MASK 0x00000001 464 #define lpfc_wcqe_xa_eo_WORD word3 465 #define CQE_XRI_ABORTED_EO_REMOTE 0 466 #define CQE_XRI_ABORTED_EO_LOCAL 1 467 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 468 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 469 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 470 }; 471 472 /* completion queue entry structure for rqe completion */ 473 struct lpfc_rcqe { 474 uint32_t word0; 475 #define lpfc_rcqe_bindex_SHIFT 16 476 #define lpfc_rcqe_bindex_MASK 0x0000FFF 477 #define lpfc_rcqe_bindex_WORD word0 478 #define lpfc_rcqe_status_SHIFT 8 479 #define lpfc_rcqe_status_MASK 0x000000FF 480 #define lpfc_rcqe_status_WORD word0 481 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 482 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 483 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 484 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 485 uint32_t word1; 486 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 487 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 488 #define lpfc_rcqe_fcf_id_v1_WORD word1 489 uint32_t word2; 490 #define lpfc_rcqe_length_SHIFT 16 491 #define lpfc_rcqe_length_MASK 0x0000FFFF 492 #define lpfc_rcqe_length_WORD word2 493 #define lpfc_rcqe_rq_id_SHIFT 6 494 #define lpfc_rcqe_rq_id_MASK 0x000003FF 495 #define lpfc_rcqe_rq_id_WORD word2 496 #define lpfc_rcqe_fcf_id_SHIFT 0 497 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 498 #define lpfc_rcqe_fcf_id_WORD word2 499 #define lpfc_rcqe_rq_id_v1_SHIFT 0 500 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 501 #define lpfc_rcqe_rq_id_v1_WORD word2 502 uint32_t word3; 503 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 504 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 505 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 506 #define lpfc_rcqe_port_SHIFT 30 507 #define lpfc_rcqe_port_MASK 0x00000001 508 #define lpfc_rcqe_port_WORD word3 509 #define lpfc_rcqe_hdr_length_SHIFT 24 510 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 511 #define lpfc_rcqe_hdr_length_WORD word3 512 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 513 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 514 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 515 #define lpfc_rcqe_eof_SHIFT 8 516 #define lpfc_rcqe_eof_MASK 0x000000FF 517 #define lpfc_rcqe_eof_WORD word3 518 #define FCOE_EOFn 0x41 519 #define FCOE_EOFt 0x42 520 #define FCOE_EOFni 0x49 521 #define FCOE_EOFa 0x50 522 #define lpfc_rcqe_sof_SHIFT 0 523 #define lpfc_rcqe_sof_MASK 0x000000FF 524 #define lpfc_rcqe_sof_WORD word3 525 #define FCOE_SOFi2 0x2d 526 #define FCOE_SOFi3 0x2e 527 #define FCOE_SOFn2 0x35 528 #define FCOE_SOFn3 0x36 529 }; 530 531 struct lpfc_rqe { 532 uint32_t address_hi; 533 uint32_t address_lo; 534 }; 535 536 /* buffer descriptors */ 537 struct lpfc_bde4 { 538 uint32_t addr_hi; 539 uint32_t addr_lo; 540 uint32_t word2; 541 #define lpfc_bde4_last_SHIFT 31 542 #define lpfc_bde4_last_MASK 0x00000001 543 #define lpfc_bde4_last_WORD word2 544 #define lpfc_bde4_sge_offset_SHIFT 0 545 #define lpfc_bde4_sge_offset_MASK 0x000003FF 546 #define lpfc_bde4_sge_offset_WORD word2 547 uint32_t word3; 548 #define lpfc_bde4_length_SHIFT 0 549 #define lpfc_bde4_length_MASK 0x000000FF 550 #define lpfc_bde4_length_WORD word3 551 }; 552 553 struct lpfc_register { 554 uint32_t word0; 555 }; 556 557 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 558 #define LPFC_PORT_SEM_MASK 0xF000 559 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 560 #define LPFC_UERR_STATUS_HI 0x00A4 561 #define LPFC_UERR_STATUS_LO 0x00A0 562 #define LPFC_UE_MASK_HI 0x00AC 563 #define LPFC_UE_MASK_LO 0x00A8 564 565 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 566 #define LPFC_SLI_INTF 0x0058 567 568 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 569 #define lpfc_port_smphr_perr_SHIFT 31 570 #define lpfc_port_smphr_perr_MASK 0x1 571 #define lpfc_port_smphr_perr_WORD word0 572 #define lpfc_port_smphr_sfi_SHIFT 30 573 #define lpfc_port_smphr_sfi_MASK 0x1 574 #define lpfc_port_smphr_sfi_WORD word0 575 #define lpfc_port_smphr_nip_SHIFT 29 576 #define lpfc_port_smphr_nip_MASK 0x1 577 #define lpfc_port_smphr_nip_WORD word0 578 #define lpfc_port_smphr_ipc_SHIFT 28 579 #define lpfc_port_smphr_ipc_MASK 0x1 580 #define lpfc_port_smphr_ipc_WORD word0 581 #define lpfc_port_smphr_scr1_SHIFT 27 582 #define lpfc_port_smphr_scr1_MASK 0x1 583 #define lpfc_port_smphr_scr1_WORD word0 584 #define lpfc_port_smphr_scr2_SHIFT 26 585 #define lpfc_port_smphr_scr2_MASK 0x1 586 #define lpfc_port_smphr_scr2_WORD word0 587 #define lpfc_port_smphr_host_scratch_SHIFT 16 588 #define lpfc_port_smphr_host_scratch_MASK 0xFF 589 #define lpfc_port_smphr_host_scratch_WORD word0 590 #define lpfc_port_smphr_port_status_SHIFT 0 591 #define lpfc_port_smphr_port_status_MASK 0xFFFF 592 #define lpfc_port_smphr_port_status_WORD word0 593 594 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 595 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 596 #define LPFC_POST_STAGE_HOST_RDY 0x0002 597 #define LPFC_POST_STAGE_BE_RESET 0x0003 598 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 599 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 600 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 601 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 602 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 603 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 604 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 605 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 606 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 607 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 608 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 609 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 610 #define LPFC_POST_STAGE_ARMFW_START 0x0800 611 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 612 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 613 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 614 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 615 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 616 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 617 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 618 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 619 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 620 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 621 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 622 #define LPFC_POST_STAGE_RC_DONE 0x0B07 623 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 624 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 625 #define LPFC_POST_STAGE_PORT_READY 0xC000 626 #define LPFC_POST_STAGE_PORT_UE 0xF000 627 628 #define LPFC_CTL_PORT_STA_OFFSET 0x404 629 #define lpfc_sliport_status_err_SHIFT 31 630 #define lpfc_sliport_status_err_MASK 0x1 631 #define lpfc_sliport_status_err_WORD word0 632 #define lpfc_sliport_status_end_SHIFT 30 633 #define lpfc_sliport_status_end_MASK 0x1 634 #define lpfc_sliport_status_end_WORD word0 635 #define lpfc_sliport_status_oti_SHIFT 29 636 #define lpfc_sliport_status_oti_MASK 0x1 637 #define lpfc_sliport_status_oti_WORD word0 638 #define lpfc_sliport_status_rn_SHIFT 24 639 #define lpfc_sliport_status_rn_MASK 0x1 640 #define lpfc_sliport_status_rn_WORD word0 641 #define lpfc_sliport_status_rdy_SHIFT 23 642 #define lpfc_sliport_status_rdy_MASK 0x1 643 #define lpfc_sliport_status_rdy_WORD word0 644 #define MAX_IF_TYPE_2_RESETS 6 645 646 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 647 #define lpfc_sliport_ctrl_end_SHIFT 30 648 #define lpfc_sliport_ctrl_end_MASK 0x1 649 #define lpfc_sliport_ctrl_end_WORD word0 650 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 651 #define LPFC_SLIPORT_BIG_ENDIAN 1 652 #define lpfc_sliport_ctrl_ip_SHIFT 27 653 #define lpfc_sliport_ctrl_ip_MASK 0x1 654 #define lpfc_sliport_ctrl_ip_WORD word0 655 #define LPFC_SLIPORT_INIT_PORT 1 656 657 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 658 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 659 660 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 661 * reside in BAR 2. 662 */ 663 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 664 665 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 666 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 667 668 #define LPFC_HST_ISR0 0x0C18 669 #define LPFC_HST_ISR1 0x0C1C 670 #define LPFC_HST_ISR2 0x0C20 671 #define LPFC_HST_ISR3 0x0C24 672 #define LPFC_HST_ISR4 0x0C28 673 674 #define LPFC_HST_IMR0 0x0C48 675 #define LPFC_HST_IMR1 0x0C4C 676 #define LPFC_HST_IMR2 0x0C50 677 #define LPFC_HST_IMR3 0x0C54 678 #define LPFC_HST_IMR4 0x0C58 679 680 #define LPFC_HST_ISCR0 0x0C78 681 #define LPFC_HST_ISCR1 0x0C7C 682 #define LPFC_HST_ISCR2 0x0C80 683 #define LPFC_HST_ISCR3 0x0C84 684 #define LPFC_HST_ISCR4 0x0C88 685 686 #define LPFC_SLI4_INTR0 BIT0 687 #define LPFC_SLI4_INTR1 BIT1 688 #define LPFC_SLI4_INTR2 BIT2 689 #define LPFC_SLI4_INTR3 BIT3 690 #define LPFC_SLI4_INTR4 BIT4 691 #define LPFC_SLI4_INTR5 BIT5 692 #define LPFC_SLI4_INTR6 BIT6 693 #define LPFC_SLI4_INTR7 BIT7 694 #define LPFC_SLI4_INTR8 BIT8 695 #define LPFC_SLI4_INTR9 BIT9 696 #define LPFC_SLI4_INTR10 BIT10 697 #define LPFC_SLI4_INTR11 BIT11 698 #define LPFC_SLI4_INTR12 BIT12 699 #define LPFC_SLI4_INTR13 BIT13 700 #define LPFC_SLI4_INTR14 BIT14 701 #define LPFC_SLI4_INTR15 BIT15 702 #define LPFC_SLI4_INTR16 BIT16 703 #define LPFC_SLI4_INTR17 BIT17 704 #define LPFC_SLI4_INTR18 BIT18 705 #define LPFC_SLI4_INTR19 BIT19 706 #define LPFC_SLI4_INTR20 BIT20 707 #define LPFC_SLI4_INTR21 BIT21 708 #define LPFC_SLI4_INTR22 BIT22 709 #define LPFC_SLI4_INTR23 BIT23 710 #define LPFC_SLI4_INTR24 BIT24 711 #define LPFC_SLI4_INTR25 BIT25 712 #define LPFC_SLI4_INTR26 BIT26 713 #define LPFC_SLI4_INTR27 BIT27 714 #define LPFC_SLI4_INTR28 BIT28 715 #define LPFC_SLI4_INTR29 BIT29 716 #define LPFC_SLI4_INTR30 BIT30 717 #define LPFC_SLI4_INTR31 BIT31 718 719 /* 720 * The Doorbell registers defined here exist in different BAR 721 * register sets depending on the UCNA Port's reported if_type 722 * value. For UCNA ports running SLI4 and if_type 0, they reside in 723 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 724 * BAR0. The offsets are the same so the driver must account for 725 * any base address difference. 726 */ 727 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 728 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 729 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 730 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 731 #define lpfc_rq_db_list_fm_num_posted_WORD word0 732 #define lpfc_rq_db_list_fm_index_SHIFT 16 733 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 734 #define lpfc_rq_db_list_fm_index_WORD word0 735 #define lpfc_rq_db_list_fm_id_SHIFT 0 736 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 737 #define lpfc_rq_db_list_fm_id_WORD word0 738 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 739 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 740 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 741 #define lpfc_rq_db_ring_fm_id_SHIFT 0 742 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 743 #define lpfc_rq_db_ring_fm_id_WORD word0 744 745 #define LPFC_ULP0_WQ_DOORBELL 0x0040 746 #define LPFC_ULP1_WQ_DOORBELL 0x0060 747 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 748 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 749 #define lpfc_wq_db_list_fm_num_posted_WORD word0 750 #define lpfc_wq_db_list_fm_index_SHIFT 16 751 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 752 #define lpfc_wq_db_list_fm_index_WORD word0 753 #define lpfc_wq_db_list_fm_id_SHIFT 0 754 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 755 #define lpfc_wq_db_list_fm_id_WORD word0 756 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 757 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 758 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 759 #define lpfc_wq_db_ring_fm_id_SHIFT 0 760 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 761 #define lpfc_wq_db_ring_fm_id_WORD word0 762 763 #define LPFC_EQCQ_DOORBELL 0x0120 764 #define lpfc_eqcq_doorbell_se_SHIFT 31 765 #define lpfc_eqcq_doorbell_se_MASK 0x0001 766 #define lpfc_eqcq_doorbell_se_WORD word0 767 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 768 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 769 #define lpfc_eqcq_doorbell_arm_SHIFT 29 770 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 771 #define lpfc_eqcq_doorbell_arm_WORD word0 772 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 773 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 774 #define lpfc_eqcq_doorbell_num_released_WORD word0 775 #define lpfc_eqcq_doorbell_qt_SHIFT 10 776 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 777 #define lpfc_eqcq_doorbell_qt_WORD word0 778 #define LPFC_QUEUE_TYPE_COMPLETION 0 779 #define LPFC_QUEUE_TYPE_EVENT 1 780 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 781 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 782 #define lpfc_eqcq_doorbell_eqci_WORD word0 783 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 784 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 785 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 786 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 787 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 788 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 789 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 790 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 791 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 792 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 793 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 794 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 795 #define LPFC_CQID_HI_FIELD_SHIFT 10 796 #define LPFC_EQID_HI_FIELD_SHIFT 9 797 798 #define LPFC_BMBX 0x0160 799 #define lpfc_bmbx_addr_SHIFT 2 800 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 801 #define lpfc_bmbx_addr_WORD word0 802 #define lpfc_bmbx_hi_SHIFT 1 803 #define lpfc_bmbx_hi_MASK 0x0001 804 #define lpfc_bmbx_hi_WORD word0 805 #define lpfc_bmbx_rdy_SHIFT 0 806 #define lpfc_bmbx_rdy_MASK 0x0001 807 #define lpfc_bmbx_rdy_WORD word0 808 809 #define LPFC_MQ_DOORBELL 0x0140 810 #define lpfc_mq_doorbell_num_posted_SHIFT 16 811 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 812 #define lpfc_mq_doorbell_num_posted_WORD word0 813 #define lpfc_mq_doorbell_id_SHIFT 0 814 #define lpfc_mq_doorbell_id_MASK 0xFFFF 815 #define lpfc_mq_doorbell_id_WORD word0 816 817 struct lpfc_sli4_cfg_mhdr { 818 uint32_t word1; 819 #define lpfc_mbox_hdr_emb_SHIFT 0 820 #define lpfc_mbox_hdr_emb_MASK 0x00000001 821 #define lpfc_mbox_hdr_emb_WORD word1 822 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 823 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 824 #define lpfc_mbox_hdr_sge_cnt_WORD word1 825 uint32_t payload_length; 826 uint32_t tag_lo; 827 uint32_t tag_hi; 828 uint32_t reserved5; 829 }; 830 831 union lpfc_sli4_cfg_shdr { 832 struct { 833 uint32_t word6; 834 #define lpfc_mbox_hdr_opcode_SHIFT 0 835 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 836 #define lpfc_mbox_hdr_opcode_WORD word6 837 #define lpfc_mbox_hdr_subsystem_SHIFT 8 838 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 839 #define lpfc_mbox_hdr_subsystem_WORD word6 840 #define lpfc_mbox_hdr_port_number_SHIFT 16 841 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 842 #define lpfc_mbox_hdr_port_number_WORD word6 843 #define lpfc_mbox_hdr_domain_SHIFT 24 844 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 845 #define lpfc_mbox_hdr_domain_WORD word6 846 uint32_t timeout; 847 uint32_t request_length; 848 uint32_t word9; 849 #define lpfc_mbox_hdr_version_SHIFT 0 850 #define lpfc_mbox_hdr_version_MASK 0x000000FF 851 #define lpfc_mbox_hdr_version_WORD word9 852 #define lpfc_mbox_hdr_pf_num_SHIFT 16 853 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 854 #define lpfc_mbox_hdr_pf_num_WORD word9 855 #define lpfc_mbox_hdr_vh_num_SHIFT 24 856 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 857 #define lpfc_mbox_hdr_vh_num_WORD word9 858 #define LPFC_Q_CREATE_VERSION_2 2 859 #define LPFC_Q_CREATE_VERSION_1 1 860 #define LPFC_Q_CREATE_VERSION_0 0 861 #define LPFC_OPCODE_VERSION_0 0 862 #define LPFC_OPCODE_VERSION_1 1 863 } request; 864 struct { 865 uint32_t word6; 866 #define lpfc_mbox_hdr_opcode_SHIFT 0 867 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 868 #define lpfc_mbox_hdr_opcode_WORD word6 869 #define lpfc_mbox_hdr_subsystem_SHIFT 8 870 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 871 #define lpfc_mbox_hdr_subsystem_WORD word6 872 #define lpfc_mbox_hdr_domain_SHIFT 24 873 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 874 #define lpfc_mbox_hdr_domain_WORD word6 875 uint32_t word7; 876 #define lpfc_mbox_hdr_status_SHIFT 0 877 #define lpfc_mbox_hdr_status_MASK 0x000000FF 878 #define lpfc_mbox_hdr_status_WORD word7 879 #define lpfc_mbox_hdr_add_status_SHIFT 8 880 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 881 #define lpfc_mbox_hdr_add_status_WORD word7 882 uint32_t response_length; 883 uint32_t actual_response_length; 884 } response; 885 }; 886 887 /* Mailbox Header structures. 888 * struct mbox_header is defined for first generation SLI4_CFG mailbox 889 * calls deployed for BE-based ports. 890 * 891 * struct sli4_mbox_header is defined for second generation SLI4 892 * ports that don't deploy the SLI4_CFG mechanism. 893 */ 894 struct mbox_header { 895 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 896 union lpfc_sli4_cfg_shdr cfg_shdr; 897 }; 898 899 #define LPFC_EXTENT_LOCAL 0 900 #define LPFC_TIMEOUT_DEFAULT 0 901 #define LPFC_EXTENT_VERSION_DEFAULT 0 902 903 /* Subsystem Definitions */ 904 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 905 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 906 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 907 908 /* Device Specific Definitions */ 909 910 /* The HOST ENDIAN defines are in Big Endian format. */ 911 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 912 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 913 914 /* Common Opcodes */ 915 #define LPFC_MBOX_OPCODE_NA 0x00 916 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 917 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 918 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 919 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 920 #define LPFC_MBOX_OPCODE_NOP 0x21 921 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 922 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 923 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 924 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 925 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 926 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 927 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 928 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 929 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 930 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 931 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 932 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 933 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 934 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 935 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 936 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 937 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 938 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 939 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 940 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 941 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 942 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 943 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 944 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 945 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 946 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 947 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 948 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 949 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 950 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 951 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 952 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 953 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 954 955 /* FCoE Opcodes */ 956 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 957 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 958 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 959 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 960 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 961 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 962 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 963 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 964 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 965 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 966 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 967 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 968 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 969 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 970 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 971 972 /* Mailbox command structures */ 973 struct eq_context { 974 uint32_t word0; 975 #define lpfc_eq_context_size_SHIFT 31 976 #define lpfc_eq_context_size_MASK 0x00000001 977 #define lpfc_eq_context_size_WORD word0 978 #define LPFC_EQE_SIZE_4 0x0 979 #define LPFC_EQE_SIZE_16 0x1 980 #define lpfc_eq_context_valid_SHIFT 29 981 #define lpfc_eq_context_valid_MASK 0x00000001 982 #define lpfc_eq_context_valid_WORD word0 983 uint32_t word1; 984 #define lpfc_eq_context_count_SHIFT 26 985 #define lpfc_eq_context_count_MASK 0x00000003 986 #define lpfc_eq_context_count_WORD word1 987 #define LPFC_EQ_CNT_256 0x0 988 #define LPFC_EQ_CNT_512 0x1 989 #define LPFC_EQ_CNT_1024 0x2 990 #define LPFC_EQ_CNT_2048 0x3 991 #define LPFC_EQ_CNT_4096 0x4 992 uint32_t word2; 993 #define lpfc_eq_context_delay_multi_SHIFT 13 994 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 995 #define lpfc_eq_context_delay_multi_WORD word2 996 uint32_t reserved3; 997 }; 998 999 struct eq_delay_info { 1000 uint32_t eq_id; 1001 uint32_t phase; 1002 uint32_t delay_multi; 1003 }; 1004 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1005 1006 struct sgl_page_pairs { 1007 uint32_t sgl_pg0_addr_lo; 1008 uint32_t sgl_pg0_addr_hi; 1009 uint32_t sgl_pg1_addr_lo; 1010 uint32_t sgl_pg1_addr_hi; 1011 }; 1012 1013 struct lpfc_mbx_post_sgl_pages { 1014 struct mbox_header header; 1015 uint32_t word0; 1016 #define lpfc_post_sgl_pages_xri_SHIFT 0 1017 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1018 #define lpfc_post_sgl_pages_xri_WORD word0 1019 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1020 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1021 #define lpfc_post_sgl_pages_xricnt_WORD word0 1022 struct sgl_page_pairs sgl_pg_pairs[1]; 1023 }; 1024 1025 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1026 struct lpfc_mbx_post_uembed_sgl_page1 { 1027 union lpfc_sli4_cfg_shdr cfg_shdr; 1028 uint32_t word0; 1029 struct sgl_page_pairs sgl_pg_pairs; 1030 }; 1031 1032 struct lpfc_mbx_sge { 1033 uint32_t pa_lo; 1034 uint32_t pa_hi; 1035 uint32_t length; 1036 }; 1037 1038 struct lpfc_mbx_nembed_cmd { 1039 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1040 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1041 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1042 }; 1043 1044 struct lpfc_mbx_nembed_sge_virt { 1045 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1046 }; 1047 1048 struct lpfc_mbx_eq_create { 1049 struct mbox_header header; 1050 union { 1051 struct { 1052 uint32_t word0; 1053 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1054 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1055 #define lpfc_mbx_eq_create_num_pages_WORD word0 1056 struct eq_context context; 1057 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1058 } request; 1059 struct { 1060 uint32_t word0; 1061 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1062 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1063 #define lpfc_mbx_eq_create_q_id_WORD word0 1064 } response; 1065 } u; 1066 }; 1067 1068 struct lpfc_mbx_modify_eq_delay { 1069 struct mbox_header header; 1070 union { 1071 struct { 1072 uint32_t num_eq; 1073 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1074 } request; 1075 struct { 1076 uint32_t word0; 1077 } response; 1078 } u; 1079 }; 1080 1081 struct lpfc_mbx_eq_destroy { 1082 struct mbox_header header; 1083 union { 1084 struct { 1085 uint32_t word0; 1086 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1087 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1088 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1089 } request; 1090 struct { 1091 uint32_t word0; 1092 } response; 1093 } u; 1094 }; 1095 1096 struct lpfc_mbx_nop { 1097 struct mbox_header header; 1098 uint32_t context[2]; 1099 }; 1100 1101 struct cq_context { 1102 uint32_t word0; 1103 #define lpfc_cq_context_event_SHIFT 31 1104 #define lpfc_cq_context_event_MASK 0x00000001 1105 #define lpfc_cq_context_event_WORD word0 1106 #define lpfc_cq_context_valid_SHIFT 29 1107 #define lpfc_cq_context_valid_MASK 0x00000001 1108 #define lpfc_cq_context_valid_WORD word0 1109 #define lpfc_cq_context_count_SHIFT 27 1110 #define lpfc_cq_context_count_MASK 0x00000003 1111 #define lpfc_cq_context_count_WORD word0 1112 #define LPFC_CQ_CNT_256 0x0 1113 #define LPFC_CQ_CNT_512 0x1 1114 #define LPFC_CQ_CNT_1024 0x2 1115 uint32_t word1; 1116 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1117 #define lpfc_cq_eq_id_MASK 0x000000FF 1118 #define lpfc_cq_eq_id_WORD word1 1119 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1120 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1121 #define lpfc_cq_eq_id_2_WORD word1 1122 uint32_t reserved0; 1123 uint32_t reserved1; 1124 }; 1125 1126 struct lpfc_mbx_cq_create { 1127 struct mbox_header header; 1128 union { 1129 struct { 1130 uint32_t word0; 1131 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1132 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1133 #define lpfc_mbx_cq_create_page_size_WORD word0 1134 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1135 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1136 #define lpfc_mbx_cq_create_num_pages_WORD word0 1137 struct cq_context context; 1138 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1139 } request; 1140 struct { 1141 uint32_t word0; 1142 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1143 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1144 #define lpfc_mbx_cq_create_q_id_WORD word0 1145 } response; 1146 } u; 1147 }; 1148 1149 struct lpfc_mbx_cq_create_set { 1150 union lpfc_sli4_cfg_shdr cfg_shdr; 1151 union { 1152 struct { 1153 uint32_t word0; 1154 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1155 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1156 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1157 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1158 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1159 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1160 uint32_t word1; 1161 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1162 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1163 #define lpfc_mbx_cq_create_set_evt_WORD word1 1164 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1165 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1166 #define lpfc_mbx_cq_create_set_valid_WORD word1 1167 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1168 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1169 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1170 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1171 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1172 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1173 #define lpfc_mbx_cq_create_set_auto_SHIFT 15 1174 #define lpfc_mbx_cq_create_set_auto_MASK 0x0000001 1175 #define lpfc_mbx_cq_create_set_auto_WORD word1 1176 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1177 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1178 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1179 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1180 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1181 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1182 uint32_t word2; 1183 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1184 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1185 #define lpfc_mbx_cq_create_set_arm_WORD word2 1186 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1187 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1188 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1189 uint32_t word3; 1190 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1191 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1192 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1193 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1194 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1195 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1196 uint32_t word4; 1197 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1198 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1199 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1200 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1201 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1202 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1203 uint32_t word5; 1204 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1205 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1206 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1207 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1208 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1209 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1210 uint32_t word6; 1211 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1212 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1213 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1214 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1215 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1216 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1217 uint32_t word7; 1218 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1219 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1220 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1221 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1222 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1223 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1224 uint32_t word8; 1225 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1226 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1227 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1228 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1229 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1230 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1231 uint32_t word9; 1232 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1233 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1234 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1235 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1236 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1237 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1238 uint32_t word10; 1239 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1240 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1241 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1242 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1243 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1244 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1245 struct dma_address page[1]; 1246 } request; 1247 struct { 1248 uint32_t word0; 1249 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1250 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1251 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1252 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1253 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1254 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1255 } response; 1256 } u; 1257 }; 1258 1259 struct lpfc_mbx_cq_destroy { 1260 struct mbox_header header; 1261 union { 1262 struct { 1263 uint32_t word0; 1264 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1265 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1266 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1267 } request; 1268 struct { 1269 uint32_t word0; 1270 } response; 1271 } u; 1272 }; 1273 1274 struct wq_context { 1275 uint32_t reserved0; 1276 uint32_t reserved1; 1277 uint32_t reserved2; 1278 uint32_t reserved3; 1279 }; 1280 1281 struct lpfc_mbx_wq_create { 1282 struct mbox_header header; 1283 union { 1284 struct { /* Version 0 Request */ 1285 uint32_t word0; 1286 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1287 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1288 #define lpfc_mbx_wq_create_num_pages_WORD word0 1289 #define lpfc_mbx_wq_create_dua_SHIFT 8 1290 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1291 #define lpfc_mbx_wq_create_dua_WORD word0 1292 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1293 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1294 #define lpfc_mbx_wq_create_cq_id_WORD word0 1295 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1296 uint32_t word9; 1297 #define lpfc_mbx_wq_create_bua_SHIFT 0 1298 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1299 #define lpfc_mbx_wq_create_bua_WORD word9 1300 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1301 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1302 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1303 } request; 1304 struct { /* Version 1 Request */ 1305 uint32_t word0; /* Word 0 is the same as in v0 */ 1306 uint32_t word1; 1307 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1308 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1309 #define lpfc_mbx_wq_create_page_size_WORD word1 1310 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1311 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1312 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1313 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1314 #define LPFC_WQ_WQE_SIZE_64 0x5 1315 #define LPFC_WQ_WQE_SIZE_128 0x6 1316 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1317 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1318 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1319 uint32_t word2; 1320 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1321 } request_1; 1322 struct { 1323 uint32_t word0; 1324 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1325 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1326 #define lpfc_mbx_wq_create_q_id_WORD word0 1327 uint32_t doorbell_offset; 1328 uint32_t word2; 1329 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1330 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1331 #define lpfc_mbx_wq_create_bar_set_WORD word2 1332 #define WQ_PCI_BAR_0_AND_1 0x00 1333 #define WQ_PCI_BAR_2_AND_3 0x01 1334 #define WQ_PCI_BAR_4_AND_5 0x02 1335 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1336 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1337 #define lpfc_mbx_wq_create_db_format_WORD word2 1338 } response; 1339 } u; 1340 }; 1341 1342 struct lpfc_mbx_wq_destroy { 1343 struct mbox_header header; 1344 union { 1345 struct { 1346 uint32_t word0; 1347 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1348 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1349 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1350 } request; 1351 struct { 1352 uint32_t word0; 1353 } response; 1354 } u; 1355 }; 1356 1357 #define LPFC_HDR_BUF_SIZE 128 1358 #define LPFC_DATA_BUF_SIZE 2048 1359 #define LPFC_NVMET_DATA_BUF_SIZE 128 1360 struct rq_context { 1361 uint32_t word0; 1362 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1363 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1364 #define lpfc_rq_context_rqe_count_WORD word0 1365 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1366 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1367 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1368 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1369 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1370 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1371 #define lpfc_rq_context_rqe_count_1_WORD word0 1372 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1373 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1374 #define lpfc_rq_context_rqe_size_WORD word0 1375 #define LPFC_RQE_SIZE_8 2 1376 #define LPFC_RQE_SIZE_16 3 1377 #define LPFC_RQE_SIZE_32 4 1378 #define LPFC_RQE_SIZE_64 5 1379 #define LPFC_RQE_SIZE_128 6 1380 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1381 #define lpfc_rq_context_page_size_MASK 0x000000FF 1382 #define lpfc_rq_context_page_size_WORD word0 1383 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1384 uint32_t word1; 1385 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1386 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1387 #define lpfc_rq_context_data_size_WORD word1 1388 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1389 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1390 #define lpfc_rq_context_hdr_size_WORD word1 1391 uint32_t word2; 1392 #define lpfc_rq_context_cq_id_SHIFT 16 1393 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1394 #define lpfc_rq_context_cq_id_WORD word2 1395 #define lpfc_rq_context_buf_size_SHIFT 0 1396 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1397 #define lpfc_rq_context_buf_size_WORD word2 1398 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1399 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1400 #define lpfc_rq_context_base_cq_WORD word2 1401 uint32_t buffer_size; /* Version 1 Only */ 1402 }; 1403 1404 struct lpfc_mbx_rq_create { 1405 struct mbox_header header; 1406 union { 1407 struct { 1408 uint32_t word0; 1409 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1410 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1411 #define lpfc_mbx_rq_create_num_pages_WORD word0 1412 #define lpfc_mbx_rq_create_dua_SHIFT 16 1413 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1414 #define lpfc_mbx_rq_create_dua_WORD word0 1415 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1416 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1417 #define lpfc_mbx_rq_create_bqu_WORD word0 1418 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1419 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1420 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1421 struct rq_context context; 1422 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1423 } request; 1424 struct { 1425 uint32_t word0; 1426 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1427 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1428 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1429 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1430 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1431 #define lpfc_mbx_rq_create_q_id_WORD word0 1432 uint32_t doorbell_offset; 1433 uint32_t word2; 1434 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1435 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1436 #define lpfc_mbx_rq_create_bar_set_WORD word2 1437 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1438 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1439 #define lpfc_mbx_rq_create_db_format_WORD word2 1440 } response; 1441 } u; 1442 }; 1443 1444 struct lpfc_mbx_rq_create_v2 { 1445 union lpfc_sli4_cfg_shdr cfg_shdr; 1446 union { 1447 struct { 1448 uint32_t word0; 1449 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1450 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1451 #define lpfc_mbx_rq_create_num_pages_WORD word0 1452 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1453 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1454 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1455 #define lpfc_mbx_rq_create_dua_SHIFT 16 1456 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1457 #define lpfc_mbx_rq_create_dua_WORD word0 1458 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1459 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1460 #define lpfc_mbx_rq_create_bqu_WORD word0 1461 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1462 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1463 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1464 #define lpfc_mbx_rq_create_dim_SHIFT 29 1465 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1466 #define lpfc_mbx_rq_create_dim_WORD word0 1467 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1468 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1469 #define lpfc_mbx_rq_create_dfd_WORD word0 1470 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1471 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1472 #define lpfc_mbx_rq_create_dnb_WORD word0 1473 struct rq_context context; 1474 struct dma_address page[1]; 1475 } request; 1476 struct { 1477 uint32_t word0; 1478 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1479 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1480 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1481 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1482 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1483 #define lpfc_mbx_rq_create_q_id_WORD word0 1484 uint32_t doorbell_offset; 1485 uint32_t word2; 1486 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1487 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1488 #define lpfc_mbx_rq_create_bar_set_WORD word2 1489 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1490 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1491 #define lpfc_mbx_rq_create_db_format_WORD word2 1492 } response; 1493 } u; 1494 }; 1495 1496 struct lpfc_mbx_rq_destroy { 1497 struct mbox_header header; 1498 union { 1499 struct { 1500 uint32_t word0; 1501 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1502 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1503 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1504 } request; 1505 struct { 1506 uint32_t word0; 1507 } response; 1508 } u; 1509 }; 1510 1511 struct mq_context { 1512 uint32_t word0; 1513 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1514 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1515 #define lpfc_mq_context_cq_id_WORD word0 1516 #define lpfc_mq_context_ring_size_SHIFT 16 1517 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1518 #define lpfc_mq_context_ring_size_WORD word0 1519 #define LPFC_MQ_RING_SIZE_16 0x5 1520 #define LPFC_MQ_RING_SIZE_32 0x6 1521 #define LPFC_MQ_RING_SIZE_64 0x7 1522 #define LPFC_MQ_RING_SIZE_128 0x8 1523 uint32_t word1; 1524 #define lpfc_mq_context_valid_SHIFT 31 1525 #define lpfc_mq_context_valid_MASK 0x00000001 1526 #define lpfc_mq_context_valid_WORD word1 1527 uint32_t reserved2; 1528 uint32_t reserved3; 1529 }; 1530 1531 struct lpfc_mbx_mq_create { 1532 struct mbox_header header; 1533 union { 1534 struct { 1535 uint32_t word0; 1536 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1537 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1538 #define lpfc_mbx_mq_create_num_pages_WORD word0 1539 struct mq_context context; 1540 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1541 } request; 1542 struct { 1543 uint32_t word0; 1544 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1545 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1546 #define lpfc_mbx_mq_create_q_id_WORD word0 1547 } response; 1548 } u; 1549 }; 1550 1551 struct lpfc_mbx_mq_create_ext { 1552 struct mbox_header header; 1553 union { 1554 struct { 1555 uint32_t word0; 1556 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1557 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1558 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1559 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1560 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1561 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1562 uint32_t async_evt_bmap; 1563 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1564 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1565 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1566 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1567 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1568 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1569 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1570 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1571 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1572 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1573 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1574 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1575 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1576 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1577 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1578 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1579 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1580 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1581 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1582 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1583 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1584 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1585 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1586 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1587 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1588 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1589 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1590 struct mq_context context; 1591 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1592 } request; 1593 struct { 1594 uint32_t word0; 1595 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1596 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1597 #define lpfc_mbx_mq_create_q_id_WORD word0 1598 } response; 1599 } u; 1600 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1601 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1602 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1603 }; 1604 1605 struct lpfc_mbx_mq_destroy { 1606 struct mbox_header header; 1607 union { 1608 struct { 1609 uint32_t word0; 1610 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1611 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1612 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1613 } request; 1614 struct { 1615 uint32_t word0; 1616 } response; 1617 } u; 1618 }; 1619 1620 /* Start Gen 2 SLI4 Mailbox definitions: */ 1621 1622 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1623 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1624 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1625 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1626 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1627 1628 struct lpfc_mbx_get_rsrc_extent_info { 1629 struct mbox_header header; 1630 union { 1631 struct { 1632 uint32_t word4; 1633 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1634 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1635 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1636 } req; 1637 struct { 1638 uint32_t word4; 1639 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1640 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1641 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1642 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1643 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1644 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1645 } rsp; 1646 } u; 1647 }; 1648 1649 struct lpfc_mbx_query_fw_config { 1650 struct mbox_header header; 1651 struct { 1652 uint32_t config_number; 1653 #define LPFC_FC_FCOE 0x00000007 1654 uint32_t asic_revision; 1655 uint32_t physical_port; 1656 uint32_t function_mode; 1657 #define LPFC_FCOE_INI_MODE 0x00000040 1658 #define LPFC_FCOE_TGT_MODE 0x00000080 1659 #define LPFC_DUA_MODE 0x00000800 1660 uint32_t ulp0_mode; 1661 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1662 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1663 uint32_t ulp0_nap_words[12]; 1664 uint32_t ulp1_mode; 1665 uint32_t ulp1_nap_words[12]; 1666 uint32_t function_capabilities; 1667 uint32_t cqid_base; 1668 uint32_t cqid_tot; 1669 uint32_t eqid_base; 1670 uint32_t eqid_tot; 1671 uint32_t ulp0_nap2_words[2]; 1672 uint32_t ulp1_nap2_words[2]; 1673 } rsp; 1674 }; 1675 1676 struct lpfc_mbx_set_beacon_config { 1677 struct mbox_header header; 1678 uint32_t word4; 1679 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1680 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1681 #define lpfc_mbx_set_beacon_port_num_WORD word4 1682 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1683 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1684 #define lpfc_mbx_set_beacon_port_type_WORD word4 1685 #define lpfc_mbx_set_beacon_state_SHIFT 8 1686 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1687 #define lpfc_mbx_set_beacon_state_WORD word4 1688 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1689 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1690 #define lpfc_mbx_set_beacon_duration_WORD word4 1691 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24 1692 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF 1693 #define lpfc_mbx_set_beacon_status_duration_WORD word4 1694 }; 1695 1696 struct lpfc_id_range { 1697 uint32_t word5; 1698 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1699 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1700 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1701 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1702 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1703 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1704 }; 1705 1706 struct lpfc_mbx_set_link_diag_state { 1707 struct mbox_header header; 1708 union { 1709 struct { 1710 uint32_t word0; 1711 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1712 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1713 #define lpfc_mbx_set_diag_state_diag_WORD word0 1714 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1715 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1716 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1717 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1718 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1719 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1720 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1721 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1722 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1723 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1724 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1725 } req; 1726 struct { 1727 uint32_t word0; 1728 } rsp; 1729 } u; 1730 }; 1731 1732 struct lpfc_mbx_set_link_diag_loopback { 1733 struct mbox_header header; 1734 union { 1735 struct { 1736 uint32_t word0; 1737 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1738 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1739 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1740 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1741 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1742 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1743 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1744 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1745 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1746 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1747 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1748 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1749 } req; 1750 struct { 1751 uint32_t word0; 1752 } rsp; 1753 } u; 1754 }; 1755 1756 struct lpfc_mbx_run_link_diag_test { 1757 struct mbox_header header; 1758 union { 1759 struct { 1760 uint32_t word0; 1761 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1762 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1763 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1764 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1765 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1766 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1767 uint32_t word1; 1768 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1769 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1770 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1771 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1772 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1773 #define lpfc_mbx_run_diag_test_loops_WORD word1 1774 uint32_t word2; 1775 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1776 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1777 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1778 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1779 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1780 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1781 } req; 1782 struct { 1783 uint32_t word0; 1784 } rsp; 1785 } u; 1786 }; 1787 1788 /* 1789 * struct lpfc_mbx_alloc_rsrc_extents: 1790 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1791 * 6 words of header + 4 words of shared subcommand header + 1792 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1793 * 1794 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1795 * for extents payload. 1796 * 1797 * 212/2 (bytes per extent) = 106 extents. 1798 * 106/2 (extents per word) = 53 words. 1799 * lpfc_id_range id is statically size to 53. 1800 * 1801 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1802 * extent ranges. For ALLOC, the type and cnt are required. 1803 * For GET_ALLOCATED, only the type is required. 1804 */ 1805 struct lpfc_mbx_alloc_rsrc_extents { 1806 struct mbox_header header; 1807 union { 1808 struct { 1809 uint32_t word4; 1810 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1811 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1812 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1813 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1814 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1815 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1816 } req; 1817 struct { 1818 uint32_t word4; 1819 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1820 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1821 #define lpfc_mbx_rsrc_cnt_WORD word4 1822 struct lpfc_id_range id[53]; 1823 } rsp; 1824 } u; 1825 }; 1826 1827 /* 1828 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1829 * structure shares the same SHIFT/MASK/WORD defines provided in the 1830 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1831 * the structures defined above. This non-embedded structure provides for the 1832 * maximum number of extents supported by the port. 1833 */ 1834 struct lpfc_mbx_nembed_rsrc_extent { 1835 union lpfc_sli4_cfg_shdr cfg_shdr; 1836 uint32_t word4; 1837 struct lpfc_id_range id; 1838 }; 1839 1840 struct lpfc_mbx_dealloc_rsrc_extents { 1841 struct mbox_header header; 1842 struct { 1843 uint32_t word4; 1844 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1845 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1846 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1847 } req; 1848 1849 }; 1850 1851 /* Start SLI4 FCoE specific mbox structures. */ 1852 1853 struct lpfc_mbx_post_hdr_tmpl { 1854 struct mbox_header header; 1855 uint32_t word10; 1856 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1857 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1858 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1859 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1860 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1861 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1862 uint32_t rpi_paddr_lo; 1863 uint32_t rpi_paddr_hi; 1864 }; 1865 1866 struct sli4_sge { /* SLI-4 */ 1867 uint32_t addr_hi; 1868 uint32_t addr_lo; 1869 1870 uint32_t word2; 1871 #define lpfc_sli4_sge_offset_SHIFT 0 1872 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1873 #define lpfc_sli4_sge_offset_WORD word2 1874 #define lpfc_sli4_sge_type_SHIFT 27 1875 #define lpfc_sli4_sge_type_MASK 0x0000000F 1876 #define lpfc_sli4_sge_type_WORD word2 1877 #define LPFC_SGE_TYPE_DATA 0x0 1878 #define LPFC_SGE_TYPE_DIF 0x4 1879 #define LPFC_SGE_TYPE_LSP 0x5 1880 #define LPFC_SGE_TYPE_PEDIF 0x6 1881 #define LPFC_SGE_TYPE_PESEED 0x7 1882 #define LPFC_SGE_TYPE_DISEED 0x8 1883 #define LPFC_SGE_TYPE_ENC 0x9 1884 #define LPFC_SGE_TYPE_ATM 0xA 1885 #define LPFC_SGE_TYPE_SKIP 0xC 1886 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1887 #define lpfc_sli4_sge_last_MASK 0x00000001 1888 #define lpfc_sli4_sge_last_WORD word2 1889 uint32_t sge_len; 1890 }; 1891 1892 struct sli4_sge_diseed { /* SLI-4 */ 1893 uint32_t ref_tag; 1894 uint32_t ref_tag_tran; 1895 1896 uint32_t word2; 1897 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1898 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1899 #define lpfc_sli4_sge_dif_apptran_WORD word2 1900 #define lpfc_sli4_sge_dif_af_SHIFT 24 1901 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1902 #define lpfc_sli4_sge_dif_af_WORD word2 1903 #define lpfc_sli4_sge_dif_na_SHIFT 25 1904 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1905 #define lpfc_sli4_sge_dif_na_WORD word2 1906 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1907 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1908 #define lpfc_sli4_sge_dif_hi_WORD word2 1909 #define lpfc_sli4_sge_dif_type_SHIFT 27 1910 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1911 #define lpfc_sli4_sge_dif_type_WORD word2 1912 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1913 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1914 #define lpfc_sli4_sge_dif_last_WORD word2 1915 uint32_t word3; 1916 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1917 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1918 #define lpfc_sli4_sge_dif_apptag_WORD word3 1919 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1920 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1921 #define lpfc_sli4_sge_dif_bs_WORD word3 1922 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1923 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1924 #define lpfc_sli4_sge_dif_ai_WORD word3 1925 #define lpfc_sli4_sge_dif_me_SHIFT 20 1926 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1927 #define lpfc_sli4_sge_dif_me_WORD word3 1928 #define lpfc_sli4_sge_dif_re_SHIFT 21 1929 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1930 #define lpfc_sli4_sge_dif_re_WORD word3 1931 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1932 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1933 #define lpfc_sli4_sge_dif_ce_WORD word3 1934 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1935 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1936 #define lpfc_sli4_sge_dif_nr_WORD word3 1937 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1938 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1939 #define lpfc_sli4_sge_dif_oprx_WORD word3 1940 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1941 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1942 #define lpfc_sli4_sge_dif_optx_WORD word3 1943 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1944 }; 1945 1946 struct fcf_record { 1947 uint32_t max_rcv_size; 1948 uint32_t fka_adv_period; 1949 uint32_t fip_priority; 1950 uint32_t word3; 1951 #define lpfc_fcf_record_mac_0_SHIFT 0 1952 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1953 #define lpfc_fcf_record_mac_0_WORD word3 1954 #define lpfc_fcf_record_mac_1_SHIFT 8 1955 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1956 #define lpfc_fcf_record_mac_1_WORD word3 1957 #define lpfc_fcf_record_mac_2_SHIFT 16 1958 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1959 #define lpfc_fcf_record_mac_2_WORD word3 1960 #define lpfc_fcf_record_mac_3_SHIFT 24 1961 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1962 #define lpfc_fcf_record_mac_3_WORD word3 1963 uint32_t word4; 1964 #define lpfc_fcf_record_mac_4_SHIFT 0 1965 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1966 #define lpfc_fcf_record_mac_4_WORD word4 1967 #define lpfc_fcf_record_mac_5_SHIFT 8 1968 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1969 #define lpfc_fcf_record_mac_5_WORD word4 1970 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1971 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1972 #define lpfc_fcf_record_fcf_avail_WORD word4 1973 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1974 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1975 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1976 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1977 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1978 uint32_t word5; 1979 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1980 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1981 #define lpfc_fcf_record_fab_name_0_WORD word5 1982 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1983 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1984 #define lpfc_fcf_record_fab_name_1_WORD word5 1985 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1986 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1987 #define lpfc_fcf_record_fab_name_2_WORD word5 1988 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1989 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1990 #define lpfc_fcf_record_fab_name_3_WORD word5 1991 uint32_t word6; 1992 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1993 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1994 #define lpfc_fcf_record_fab_name_4_WORD word6 1995 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1996 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1997 #define lpfc_fcf_record_fab_name_5_WORD word6 1998 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1999 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2000 #define lpfc_fcf_record_fab_name_6_WORD word6 2001 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2002 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2003 #define lpfc_fcf_record_fab_name_7_WORD word6 2004 uint32_t word7; 2005 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2006 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2007 #define lpfc_fcf_record_fc_map_0_WORD word7 2008 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2009 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2010 #define lpfc_fcf_record_fc_map_1_WORD word7 2011 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2012 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2013 #define lpfc_fcf_record_fc_map_2_WORD word7 2014 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2015 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2016 #define lpfc_fcf_record_fcf_valid_WORD word7 2017 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2018 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2019 #define lpfc_fcf_record_fcf_fc_WORD word7 2020 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2021 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2022 #define lpfc_fcf_record_fcf_sol_WORD word7 2023 uint32_t word8; 2024 #define lpfc_fcf_record_fcf_index_SHIFT 0 2025 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2026 #define lpfc_fcf_record_fcf_index_WORD word8 2027 #define lpfc_fcf_record_fcf_state_SHIFT 16 2028 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2029 #define lpfc_fcf_record_fcf_state_WORD word8 2030 uint8_t vlan_bitmap[512]; 2031 uint32_t word137; 2032 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2033 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2034 #define lpfc_fcf_record_switch_name_0_WORD word137 2035 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2036 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2037 #define lpfc_fcf_record_switch_name_1_WORD word137 2038 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2039 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2040 #define lpfc_fcf_record_switch_name_2_WORD word137 2041 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2042 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2043 #define lpfc_fcf_record_switch_name_3_WORD word137 2044 uint32_t word138; 2045 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2046 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2047 #define lpfc_fcf_record_switch_name_4_WORD word138 2048 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2049 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2050 #define lpfc_fcf_record_switch_name_5_WORD word138 2051 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2052 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2053 #define lpfc_fcf_record_switch_name_6_WORD word138 2054 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2055 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2056 #define lpfc_fcf_record_switch_name_7_WORD word138 2057 }; 2058 2059 struct lpfc_mbx_read_fcf_tbl { 2060 union lpfc_sli4_cfg_shdr cfg_shdr; 2061 union { 2062 struct { 2063 uint32_t word10; 2064 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2065 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2066 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2067 } request; 2068 struct { 2069 uint32_t eventag; 2070 } response; 2071 } u; 2072 uint32_t word11; 2073 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2074 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2075 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2076 }; 2077 2078 struct lpfc_mbx_add_fcf_tbl_entry { 2079 union lpfc_sli4_cfg_shdr cfg_shdr; 2080 uint32_t word10; 2081 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2082 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2083 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2084 struct lpfc_mbx_sge fcf_sge; 2085 }; 2086 2087 struct lpfc_mbx_del_fcf_tbl_entry { 2088 struct mbox_header header; 2089 uint32_t word10; 2090 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2091 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2092 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2093 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2094 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2095 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2096 }; 2097 2098 struct lpfc_mbx_redisc_fcf_tbl { 2099 struct mbox_header header; 2100 uint32_t word10; 2101 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2102 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2103 #define lpfc_mbx_redisc_fcf_count_WORD word10 2104 uint32_t resvd; 2105 uint32_t word12; 2106 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2107 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2108 #define lpfc_mbx_redisc_fcf_index_WORD word12 2109 }; 2110 2111 /* Status field for embedded SLI_CONFIG mailbox command */ 2112 #define STATUS_SUCCESS 0x0 2113 #define STATUS_FAILED 0x1 2114 #define STATUS_ILLEGAL_REQUEST 0x2 2115 #define STATUS_ILLEGAL_FIELD 0x3 2116 #define STATUS_INSUFFICIENT_BUFFER 0x4 2117 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2118 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2119 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2120 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2121 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2122 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2123 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2124 #define STATUS_ASSERT_FAILED 0x1e 2125 #define STATUS_INVALID_SESSION 0x1f 2126 #define STATUS_INVALID_CONNECTION 0x20 2127 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2128 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2129 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2130 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2131 #define STATUS_FLASHROM_READ_FAILED 0x27 2132 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2133 #define STATUS_ERROR_ACITMAIN 0x2a 2134 #define STATUS_REBOOT_REQUIRED 0x2c 2135 #define STATUS_FCF_IN_USE 0x3a 2136 #define STATUS_FCF_TABLE_EMPTY 0x43 2137 2138 /* 2139 * Additional status field for embedded SLI_CONFIG mailbox 2140 * command. 2141 */ 2142 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2143 2144 struct lpfc_mbx_sli4_config { 2145 struct mbox_header header; 2146 }; 2147 2148 struct lpfc_mbx_init_vfi { 2149 uint32_t word1; 2150 #define lpfc_init_vfi_vr_SHIFT 31 2151 #define lpfc_init_vfi_vr_MASK 0x00000001 2152 #define lpfc_init_vfi_vr_WORD word1 2153 #define lpfc_init_vfi_vt_SHIFT 30 2154 #define lpfc_init_vfi_vt_MASK 0x00000001 2155 #define lpfc_init_vfi_vt_WORD word1 2156 #define lpfc_init_vfi_vf_SHIFT 29 2157 #define lpfc_init_vfi_vf_MASK 0x00000001 2158 #define lpfc_init_vfi_vf_WORD word1 2159 #define lpfc_init_vfi_vp_SHIFT 28 2160 #define lpfc_init_vfi_vp_MASK 0x00000001 2161 #define lpfc_init_vfi_vp_WORD word1 2162 #define lpfc_init_vfi_vfi_SHIFT 0 2163 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2164 #define lpfc_init_vfi_vfi_WORD word1 2165 uint32_t word2; 2166 #define lpfc_init_vfi_vpi_SHIFT 16 2167 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2168 #define lpfc_init_vfi_vpi_WORD word2 2169 #define lpfc_init_vfi_fcfi_SHIFT 0 2170 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2171 #define lpfc_init_vfi_fcfi_WORD word2 2172 uint32_t word3; 2173 #define lpfc_init_vfi_pri_SHIFT 13 2174 #define lpfc_init_vfi_pri_MASK 0x00000007 2175 #define lpfc_init_vfi_pri_WORD word3 2176 #define lpfc_init_vfi_vf_id_SHIFT 1 2177 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2178 #define lpfc_init_vfi_vf_id_WORD word3 2179 uint32_t word4; 2180 #define lpfc_init_vfi_hop_count_SHIFT 24 2181 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2182 #define lpfc_init_vfi_hop_count_WORD word4 2183 }; 2184 #define MBX_VFI_IN_USE 0x9F02 2185 2186 2187 struct lpfc_mbx_reg_vfi { 2188 uint32_t word1; 2189 #define lpfc_reg_vfi_upd_SHIFT 29 2190 #define lpfc_reg_vfi_upd_MASK 0x00000001 2191 #define lpfc_reg_vfi_upd_WORD word1 2192 #define lpfc_reg_vfi_vp_SHIFT 28 2193 #define lpfc_reg_vfi_vp_MASK 0x00000001 2194 #define lpfc_reg_vfi_vp_WORD word1 2195 #define lpfc_reg_vfi_vfi_SHIFT 0 2196 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2197 #define lpfc_reg_vfi_vfi_WORD word1 2198 uint32_t word2; 2199 #define lpfc_reg_vfi_vpi_SHIFT 16 2200 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2201 #define lpfc_reg_vfi_vpi_WORD word2 2202 #define lpfc_reg_vfi_fcfi_SHIFT 0 2203 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2204 #define lpfc_reg_vfi_fcfi_WORD word2 2205 uint32_t wwn[2]; 2206 struct ulp_bde64 bde; 2207 uint32_t e_d_tov; 2208 uint32_t r_a_tov; 2209 uint32_t word10; 2210 #define lpfc_reg_vfi_nport_id_SHIFT 0 2211 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2212 #define lpfc_reg_vfi_nport_id_WORD word10 2213 }; 2214 2215 struct lpfc_mbx_init_vpi { 2216 uint32_t word1; 2217 #define lpfc_init_vpi_vfi_SHIFT 16 2218 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2219 #define lpfc_init_vpi_vfi_WORD word1 2220 #define lpfc_init_vpi_vpi_SHIFT 0 2221 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2222 #define lpfc_init_vpi_vpi_WORD word1 2223 }; 2224 2225 struct lpfc_mbx_read_vpi { 2226 uint32_t word1_rsvd; 2227 uint32_t word2; 2228 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2229 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2230 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2231 uint32_t word3_rsvd; 2232 uint32_t word4; 2233 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2234 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2235 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2236 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2237 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2238 #define lpfc_mbx_read_vpi_pb_WORD word4 2239 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2240 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2241 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2242 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2243 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2244 #define lpfc_mbx_read_vpi_ns_WORD word4 2245 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2246 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2247 #define lpfc_mbx_read_vpi_hl_WORD word4 2248 uint32_t word5_rsvd; 2249 uint32_t word6; 2250 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2251 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2252 #define lpfc_mbx_read_vpi_vpi_WORD word6 2253 uint32_t word7; 2254 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2255 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2256 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2257 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2258 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2259 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2260 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2261 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2262 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2263 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2264 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2265 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2266 uint32_t word8; 2267 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2268 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2269 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2270 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2271 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2272 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2273 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2274 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2275 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2276 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2277 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2278 #define lpfc_mbx_read_vpi_vv_WORD word8 2279 }; 2280 2281 struct lpfc_mbx_unreg_vfi { 2282 uint32_t word1_rsvd; 2283 uint32_t word2; 2284 #define lpfc_unreg_vfi_vfi_SHIFT 0 2285 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2286 #define lpfc_unreg_vfi_vfi_WORD word2 2287 }; 2288 2289 struct lpfc_mbx_resume_rpi { 2290 uint32_t word1; 2291 #define lpfc_resume_rpi_index_SHIFT 0 2292 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2293 #define lpfc_resume_rpi_index_WORD word1 2294 #define lpfc_resume_rpi_ii_SHIFT 30 2295 #define lpfc_resume_rpi_ii_MASK 0x00000003 2296 #define lpfc_resume_rpi_ii_WORD word1 2297 #define RESUME_INDEX_RPI 0 2298 #define RESUME_INDEX_VPI 1 2299 #define RESUME_INDEX_VFI 2 2300 #define RESUME_INDEX_FCFI 3 2301 uint32_t event_tag; 2302 }; 2303 2304 #define REG_FCF_INVALID_QID 0xFFFF 2305 struct lpfc_mbx_reg_fcfi { 2306 uint32_t word1; 2307 #define lpfc_reg_fcfi_info_index_SHIFT 0 2308 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2309 #define lpfc_reg_fcfi_info_index_WORD word1 2310 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2311 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2312 #define lpfc_reg_fcfi_fcfi_WORD word1 2313 uint32_t word2; 2314 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2315 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2316 #define lpfc_reg_fcfi_rq_id1_WORD word2 2317 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2318 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2319 #define lpfc_reg_fcfi_rq_id0_WORD word2 2320 uint32_t word3; 2321 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2322 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2323 #define lpfc_reg_fcfi_rq_id3_WORD word3 2324 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2325 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2326 #define lpfc_reg_fcfi_rq_id2_WORD word3 2327 uint32_t word4; 2328 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2329 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2330 #define lpfc_reg_fcfi_type_match0_WORD word4 2331 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2332 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2333 #define lpfc_reg_fcfi_type_mask0_WORD word4 2334 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2335 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2336 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2337 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2338 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2339 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2340 uint32_t word5; 2341 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2342 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2343 #define lpfc_reg_fcfi_type_match1_WORD word5 2344 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2345 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2346 #define lpfc_reg_fcfi_type_mask1_WORD word5 2347 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2348 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2349 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2350 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2351 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2352 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2353 uint32_t word6; 2354 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2355 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2356 #define lpfc_reg_fcfi_type_match2_WORD word6 2357 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2358 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2359 #define lpfc_reg_fcfi_type_mask2_WORD word6 2360 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2361 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2362 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2363 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2364 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2365 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2366 uint32_t word7; 2367 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2368 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2369 #define lpfc_reg_fcfi_type_match3_WORD word7 2370 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2371 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2372 #define lpfc_reg_fcfi_type_mask3_WORD word7 2373 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2374 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2375 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2376 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2377 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2378 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2379 uint32_t word8; 2380 #define lpfc_reg_fcfi_mam_SHIFT 13 2381 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2382 #define lpfc_reg_fcfi_mam_WORD word8 2383 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2384 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2385 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2386 #define lpfc_reg_fcfi_vv_SHIFT 12 2387 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2388 #define lpfc_reg_fcfi_vv_WORD word8 2389 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2390 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2391 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2392 }; 2393 2394 struct lpfc_mbx_reg_fcfi_mrq { 2395 uint32_t word1; 2396 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2397 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2398 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2399 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2400 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2401 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2402 uint32_t word2; 2403 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2404 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2405 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2406 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2407 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2408 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2409 uint32_t word3; 2410 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2411 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2412 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2413 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2414 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2415 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2416 uint32_t word4; 2417 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2418 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2419 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2420 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2421 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2422 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2423 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2424 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2425 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2426 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2427 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2428 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2429 uint32_t word5; 2430 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2431 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2432 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2433 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2434 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2435 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2436 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2437 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2438 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2439 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2440 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2441 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2442 uint32_t word6; 2443 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2444 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2445 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2446 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2447 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2448 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2449 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2450 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2451 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2452 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2453 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2454 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2455 uint32_t word7; 2456 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2457 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2458 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2459 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2460 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2461 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2462 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2463 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2464 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2465 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2466 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2467 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2468 uint32_t word8; 2469 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2470 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2471 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2472 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2473 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2474 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2475 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2476 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2477 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2478 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2479 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2480 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2481 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2482 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2483 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2484 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2485 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2486 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2487 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2488 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2489 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2490 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2491 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2492 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2493 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2494 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2495 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2496 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2497 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2498 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2499 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2500 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2501 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2502 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2503 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2504 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2505 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2506 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2507 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2508 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2509 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2510 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2511 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2512 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2513 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2514 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2515 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2516 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2517 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2518 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2519 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2520 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2521 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2522 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2523 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2524 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2525 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2526 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2527 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2528 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2529 uint32_t word9; 2530 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2531 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2532 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2533 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2534 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2535 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2536 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2537 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2538 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2539 uint32_t word10; 2540 uint32_t word11; 2541 uint32_t word12; 2542 uint32_t word13; 2543 uint32_t word14; 2544 uint32_t word15; 2545 uint32_t word16; 2546 }; 2547 2548 struct lpfc_mbx_unreg_fcfi { 2549 uint32_t word1_rsv; 2550 uint32_t word2; 2551 #define lpfc_unreg_fcfi_SHIFT 0 2552 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2553 #define lpfc_unreg_fcfi_WORD word2 2554 }; 2555 2556 struct lpfc_mbx_read_rev { 2557 uint32_t word1; 2558 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2559 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2560 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2561 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2562 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2563 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2564 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2565 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2566 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2567 #define LPFC_PREDCBX_CEE_MODE 0 2568 #define LPFC_DCBX_CEE_MODE 1 2569 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2570 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2571 #define lpfc_mbx_rd_rev_vpd_WORD word1 2572 uint32_t first_hw_rev; 2573 uint32_t second_hw_rev; 2574 uint32_t word4_rsvd; 2575 uint32_t third_hw_rev; 2576 uint32_t word6; 2577 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2578 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2579 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2580 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2581 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2582 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2583 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2584 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2585 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2586 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2587 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2588 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2589 uint32_t word7_rsvd; 2590 uint32_t fw_id_rev; 2591 uint8_t fw_name[16]; 2592 uint32_t ulp_fw_id_rev; 2593 uint8_t ulp_fw_name[16]; 2594 uint32_t word18_47_rsvd[30]; 2595 uint32_t word48; 2596 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2597 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2598 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2599 uint32_t vpd_paddr_low; 2600 uint32_t vpd_paddr_high; 2601 uint32_t avail_vpd_len; 2602 uint32_t rsvd_52_63[12]; 2603 }; 2604 2605 struct lpfc_mbx_read_config { 2606 uint32_t word1; 2607 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2608 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2609 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2610 uint32_t word2; 2611 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2612 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2613 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2614 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2615 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2616 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2617 #define LPFC_LNK_TYPE_GE 0 2618 #define LPFC_LNK_TYPE_FC 1 2619 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2620 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2621 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2622 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2623 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2624 #define lpfc_mbx_rd_conf_topology_WORD word2 2625 uint32_t rsvd_3; 2626 uint32_t word4; 2627 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2628 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2629 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2630 uint32_t rsvd_5; 2631 uint32_t word6; 2632 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2633 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2634 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2635 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2636 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2637 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2638 uint32_t rsvd_7; 2639 uint32_t rsvd_8; 2640 uint32_t word9; 2641 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2642 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2643 #define lpfc_mbx_rd_conf_lmt_WORD word9 2644 uint32_t rsvd_10; 2645 uint32_t rsvd_11; 2646 uint32_t word12; 2647 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2648 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2649 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2650 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2651 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2652 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2653 uint32_t word13; 2654 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2655 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2656 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2657 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2658 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2659 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2660 uint32_t word14; 2661 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2662 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2663 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2664 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2665 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2666 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2667 uint32_t word15; 2668 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2669 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2670 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2671 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2672 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2673 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2674 uint32_t word16; 2675 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2676 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2677 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2678 uint32_t word17; 2679 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2680 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2681 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2682 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2683 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2684 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2685 uint32_t word18; 2686 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2687 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2688 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2689 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2690 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2691 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2692 }; 2693 2694 struct lpfc_mbx_request_features { 2695 uint32_t word1; 2696 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2697 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2698 #define lpfc_mbx_rq_ftr_qry_WORD word1 2699 uint32_t word2; 2700 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2701 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2702 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2703 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2704 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2705 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2706 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2707 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2708 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2709 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2710 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2711 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2712 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2713 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2714 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2715 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2716 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2717 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2718 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2719 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2720 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2721 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2722 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2723 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2724 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2725 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2726 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2727 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2728 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2729 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2730 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2731 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2732 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2733 uint32_t word3; 2734 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2735 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2736 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2737 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2738 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2739 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2740 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2741 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2742 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2743 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2744 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2745 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2746 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2747 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2748 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2749 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2750 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2751 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2752 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2753 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2754 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2755 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2756 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2757 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2758 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2759 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2760 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2761 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2762 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2763 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2764 }; 2765 2766 struct lpfc_mbx_supp_pages { 2767 uint32_t word1; 2768 #define qs_SHIFT 0 2769 #define qs_MASK 0x00000001 2770 #define qs_WORD word1 2771 #define wr_SHIFT 1 2772 #define wr_MASK 0x00000001 2773 #define wr_WORD word1 2774 #define pf_SHIFT 8 2775 #define pf_MASK 0x000000ff 2776 #define pf_WORD word1 2777 #define cpn_SHIFT 16 2778 #define cpn_MASK 0x000000ff 2779 #define cpn_WORD word1 2780 uint32_t word2; 2781 #define list_offset_SHIFT 0 2782 #define list_offset_MASK 0x000000ff 2783 #define list_offset_WORD word2 2784 #define next_offset_SHIFT 8 2785 #define next_offset_MASK 0x000000ff 2786 #define next_offset_WORD word2 2787 #define elem_cnt_SHIFT 16 2788 #define elem_cnt_MASK 0x000000ff 2789 #define elem_cnt_WORD word2 2790 uint32_t word3; 2791 #define pn_0_SHIFT 24 2792 #define pn_0_MASK 0x000000ff 2793 #define pn_0_WORD word3 2794 #define pn_1_SHIFT 16 2795 #define pn_1_MASK 0x000000ff 2796 #define pn_1_WORD word3 2797 #define pn_2_SHIFT 8 2798 #define pn_2_MASK 0x000000ff 2799 #define pn_2_WORD word3 2800 #define pn_3_SHIFT 0 2801 #define pn_3_MASK 0x000000ff 2802 #define pn_3_WORD word3 2803 uint32_t word4; 2804 #define pn_4_SHIFT 24 2805 #define pn_4_MASK 0x000000ff 2806 #define pn_4_WORD word4 2807 #define pn_5_SHIFT 16 2808 #define pn_5_MASK 0x000000ff 2809 #define pn_5_WORD word4 2810 #define pn_6_SHIFT 8 2811 #define pn_6_MASK 0x000000ff 2812 #define pn_6_WORD word4 2813 #define pn_7_SHIFT 0 2814 #define pn_7_MASK 0x000000ff 2815 #define pn_7_WORD word4 2816 uint32_t rsvd[27]; 2817 #define LPFC_SUPP_PAGES 0 2818 #define LPFC_BLOCK_GUARD_PROFILES 1 2819 #define LPFC_SLI4_PARAMETERS 2 2820 }; 2821 2822 struct lpfc_mbx_memory_dump_type3 { 2823 uint32_t word1; 2824 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2825 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2826 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2827 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2828 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2829 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2830 uint32_t word2; 2831 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2832 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 2833 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 2834 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 2835 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 2836 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 2837 uint32_t word3; 2838 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 2839 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 2840 #define lpfc_mbx_memory_dump_type3_length_WORD word3 2841 uint32_t addr_lo; 2842 uint32_t addr_hi; 2843 uint32_t return_len; 2844 }; 2845 2846 #define DMP_PAGE_A0 0xa0 2847 #define DMP_PAGE_A2 0xa2 2848 #define DMP_SFF_PAGE_A0_SIZE 256 2849 #define DMP_SFF_PAGE_A2_SIZE 256 2850 2851 #define SFP_WAVELENGTH_LC1310 1310 2852 #define SFP_WAVELENGTH_LL1550 1550 2853 2854 2855 /* 2856 * * SFF-8472 TABLE 3.4 2857 * */ 2858 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 2859 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 2860 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 2861 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 2862 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 2863 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 2864 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 2865 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 2866 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 2867 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 2868 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 2869 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 2870 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 2871 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 2872 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 2873 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 2874 2875 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 2876 2877 #define SSF_IDENTIFIER 0 2878 #define SSF_EXT_IDENTIFIER 1 2879 #define SSF_CONNECTOR 2 2880 #define SSF_TRANSCEIVER_CODE_B0 3 2881 #define SSF_TRANSCEIVER_CODE_B1 4 2882 #define SSF_TRANSCEIVER_CODE_B2 5 2883 #define SSF_TRANSCEIVER_CODE_B3 6 2884 #define SSF_TRANSCEIVER_CODE_B4 7 2885 #define SSF_TRANSCEIVER_CODE_B5 8 2886 #define SSF_TRANSCEIVER_CODE_B6 9 2887 #define SSF_TRANSCEIVER_CODE_B7 10 2888 #define SSF_ENCODING 11 2889 #define SSF_BR_NOMINAL 12 2890 #define SSF_RATE_IDENTIFIER 13 2891 #define SSF_LENGTH_9UM_KM 14 2892 #define SSF_LENGTH_9UM 15 2893 #define SSF_LENGTH_50UM_OM2 16 2894 #define SSF_LENGTH_62UM_OM1 17 2895 #define SFF_LENGTH_COPPER 18 2896 #define SSF_LENGTH_50UM_OM3 19 2897 #define SSF_VENDOR_NAME 20 2898 #define SSF_VENDOR_OUI 36 2899 #define SSF_VENDOR_PN 40 2900 #define SSF_VENDOR_REV 56 2901 #define SSF_WAVELENGTH_B1 60 2902 #define SSF_WAVELENGTH_B0 61 2903 #define SSF_CC_BASE 63 2904 #define SSF_OPTIONS_B1 64 2905 #define SSF_OPTIONS_B0 65 2906 #define SSF_BR_MAX 66 2907 #define SSF_BR_MIN 67 2908 #define SSF_VENDOR_SN 68 2909 #define SSF_DATE_CODE 84 2910 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 2911 #define SSF_ENHANCED_OPTIONS 93 2912 #define SFF_8472_COMPLIANCE 94 2913 #define SSF_CC_EXT 95 2914 #define SSF_A0_VENDOR_SPECIFIC 96 2915 2916 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 2917 2918 #define SSF_TEMP_HIGH_ALARM 0 2919 #define SSF_TEMP_LOW_ALARM 2 2920 #define SSF_TEMP_HIGH_WARNING 4 2921 #define SSF_TEMP_LOW_WARNING 6 2922 #define SSF_VOLTAGE_HIGH_ALARM 8 2923 #define SSF_VOLTAGE_LOW_ALARM 10 2924 #define SSF_VOLTAGE_HIGH_WARNING 12 2925 #define SSF_VOLTAGE_LOW_WARNING 14 2926 #define SSF_BIAS_HIGH_ALARM 16 2927 #define SSF_BIAS_LOW_ALARM 18 2928 #define SSF_BIAS_HIGH_WARNING 20 2929 #define SSF_BIAS_LOW_WARNING 22 2930 #define SSF_TXPOWER_HIGH_ALARM 24 2931 #define SSF_TXPOWER_LOW_ALARM 26 2932 #define SSF_TXPOWER_HIGH_WARNING 28 2933 #define SSF_TXPOWER_LOW_WARNING 30 2934 #define SSF_RXPOWER_HIGH_ALARM 32 2935 #define SSF_RXPOWER_LOW_ALARM 34 2936 #define SSF_RXPOWER_HIGH_WARNING 36 2937 #define SSF_RXPOWER_LOW_WARNING 38 2938 #define SSF_EXT_CAL_CONSTANTS 56 2939 #define SSF_CC_DMI 95 2940 #define SFF_TEMPERATURE_B1 96 2941 #define SFF_TEMPERATURE_B0 97 2942 #define SFF_VCC_B1 98 2943 #define SFF_VCC_B0 99 2944 #define SFF_TX_BIAS_CURRENT_B1 100 2945 #define SFF_TX_BIAS_CURRENT_B0 101 2946 #define SFF_TXPOWER_B1 102 2947 #define SFF_TXPOWER_B0 103 2948 #define SFF_RXPOWER_B1 104 2949 #define SFF_RXPOWER_B0 105 2950 #define SSF_STATUS_CONTROL 110 2951 #define SSF_ALARM_FLAGS 112 2952 #define SSF_WARNING_FLAGS 116 2953 #define SSF_EXT_TATUS_CONTROL_B1 118 2954 #define SSF_EXT_TATUS_CONTROL_B0 119 2955 #define SSF_A2_VENDOR_SPECIFIC 120 2956 #define SSF_USER_EEPROM 128 2957 #define SSF_VENDOR_CONTROL 148 2958 2959 2960 /* 2961 * Tranceiver codes Fibre Channel SFF-8472 2962 * Table 3.5. 2963 */ 2964 2965 struct sff_trasnceiver_codes_byte0 { 2966 uint8_t inifiband:4; 2967 uint8_t teng_ethernet:4; 2968 }; 2969 2970 struct sff_trasnceiver_codes_byte1 { 2971 uint8_t sonet:6; 2972 uint8_t escon:2; 2973 }; 2974 2975 struct sff_trasnceiver_codes_byte2 { 2976 uint8_t soNet:8; 2977 }; 2978 2979 struct sff_trasnceiver_codes_byte3 { 2980 uint8_t ethernet:8; 2981 }; 2982 2983 struct sff_trasnceiver_codes_byte4 { 2984 uint8_t fc_el_lo:1; 2985 uint8_t fc_lw_laser:1; 2986 uint8_t fc_sw_laser:1; 2987 uint8_t fc_md_distance:1; 2988 uint8_t fc_lg_distance:1; 2989 uint8_t fc_int_distance:1; 2990 uint8_t fc_short_distance:1; 2991 uint8_t fc_vld_distance:1; 2992 }; 2993 2994 struct sff_trasnceiver_codes_byte5 { 2995 uint8_t reserved1:1; 2996 uint8_t reserved2:1; 2997 uint8_t fc_sfp_active:1; /* Active cable */ 2998 uint8_t fc_sfp_passive:1; /* Passive cable */ 2999 uint8_t fc_lw_laser:1; /* Longwave laser */ 3000 uint8_t fc_sw_laser_sl:1; 3001 uint8_t fc_sw_laser_sn:1; 3002 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3003 }; 3004 3005 struct sff_trasnceiver_codes_byte6 { 3006 uint8_t fc_tm_sm:1; /* Single Mode */ 3007 uint8_t reserved:1; 3008 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3009 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3010 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3011 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3012 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3013 }; 3014 3015 struct sff_trasnceiver_codes_byte7 { 3016 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3017 uint8_t reserve:1; 3018 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3019 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3020 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3021 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3022 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3023 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3024 }; 3025 3026 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3027 struct user_eeprom { 3028 uint8_t vendor_name[16]; 3029 uint8_t vendor_oui[3]; 3030 uint8_t vendor_pn[816]; 3031 uint8_t vendor_rev[4]; 3032 uint8_t vendor_sn[16]; 3033 uint8_t datecode[6]; 3034 uint8_t lot_code[2]; 3035 uint8_t reserved191[57]; 3036 }; 3037 3038 struct lpfc_mbx_pc_sli4_params { 3039 uint32_t word1; 3040 #define qs_SHIFT 0 3041 #define qs_MASK 0x00000001 3042 #define qs_WORD word1 3043 #define wr_SHIFT 1 3044 #define wr_MASK 0x00000001 3045 #define wr_WORD word1 3046 #define pf_SHIFT 8 3047 #define pf_MASK 0x000000ff 3048 #define pf_WORD word1 3049 #define cpn_SHIFT 16 3050 #define cpn_MASK 0x000000ff 3051 #define cpn_WORD word1 3052 uint32_t word2; 3053 #define if_type_SHIFT 0 3054 #define if_type_MASK 0x00000007 3055 #define if_type_WORD word2 3056 #define sli_rev_SHIFT 4 3057 #define sli_rev_MASK 0x0000000f 3058 #define sli_rev_WORD word2 3059 #define sli_family_SHIFT 8 3060 #define sli_family_MASK 0x000000ff 3061 #define sli_family_WORD word2 3062 #define featurelevel_1_SHIFT 16 3063 #define featurelevel_1_MASK 0x000000ff 3064 #define featurelevel_1_WORD word2 3065 #define featurelevel_2_SHIFT 24 3066 #define featurelevel_2_MASK 0x0000001f 3067 #define featurelevel_2_WORD word2 3068 uint32_t word3; 3069 #define fcoe_SHIFT 0 3070 #define fcoe_MASK 0x00000001 3071 #define fcoe_WORD word3 3072 #define fc_SHIFT 1 3073 #define fc_MASK 0x00000001 3074 #define fc_WORD word3 3075 #define nic_SHIFT 2 3076 #define nic_MASK 0x00000001 3077 #define nic_WORD word3 3078 #define iscsi_SHIFT 3 3079 #define iscsi_MASK 0x00000001 3080 #define iscsi_WORD word3 3081 #define rdma_SHIFT 4 3082 #define rdma_MASK 0x00000001 3083 #define rdma_WORD word3 3084 uint32_t sge_supp_len; 3085 #define SLI4_PAGE_SIZE 4096 3086 uint32_t word5; 3087 #define if_page_sz_SHIFT 0 3088 #define if_page_sz_MASK 0x0000ffff 3089 #define if_page_sz_WORD word5 3090 #define loopbk_scope_SHIFT 24 3091 #define loopbk_scope_MASK 0x0000000f 3092 #define loopbk_scope_WORD word5 3093 #define rq_db_window_SHIFT 28 3094 #define rq_db_window_MASK 0x0000000f 3095 #define rq_db_window_WORD word5 3096 uint32_t word6; 3097 #define eq_pages_SHIFT 0 3098 #define eq_pages_MASK 0x0000000f 3099 #define eq_pages_WORD word6 3100 #define eqe_size_SHIFT 8 3101 #define eqe_size_MASK 0x000000ff 3102 #define eqe_size_WORD word6 3103 uint32_t word7; 3104 #define cq_pages_SHIFT 0 3105 #define cq_pages_MASK 0x0000000f 3106 #define cq_pages_WORD word7 3107 #define cqe_size_SHIFT 8 3108 #define cqe_size_MASK 0x000000ff 3109 #define cqe_size_WORD word7 3110 uint32_t word8; 3111 #define mq_pages_SHIFT 0 3112 #define mq_pages_MASK 0x0000000f 3113 #define mq_pages_WORD word8 3114 #define mqe_size_SHIFT 8 3115 #define mqe_size_MASK 0x000000ff 3116 #define mqe_size_WORD word8 3117 #define mq_elem_cnt_SHIFT 16 3118 #define mq_elem_cnt_MASK 0x000000ff 3119 #define mq_elem_cnt_WORD word8 3120 uint32_t word9; 3121 #define wq_pages_SHIFT 0 3122 #define wq_pages_MASK 0x0000ffff 3123 #define wq_pages_WORD word9 3124 #define wqe_size_SHIFT 8 3125 #define wqe_size_MASK 0x000000ff 3126 #define wqe_size_WORD word9 3127 uint32_t word10; 3128 #define rq_pages_SHIFT 0 3129 #define rq_pages_MASK 0x0000ffff 3130 #define rq_pages_WORD word10 3131 #define rqe_size_SHIFT 8 3132 #define rqe_size_MASK 0x000000ff 3133 #define rqe_size_WORD word10 3134 uint32_t word11; 3135 #define hdr_pages_SHIFT 0 3136 #define hdr_pages_MASK 0x0000000f 3137 #define hdr_pages_WORD word11 3138 #define hdr_size_SHIFT 8 3139 #define hdr_size_MASK 0x0000000f 3140 #define hdr_size_WORD word11 3141 #define hdr_pp_align_SHIFT 16 3142 #define hdr_pp_align_MASK 0x0000ffff 3143 #define hdr_pp_align_WORD word11 3144 uint32_t word12; 3145 #define sgl_pages_SHIFT 0 3146 #define sgl_pages_MASK 0x0000000f 3147 #define sgl_pages_WORD word12 3148 #define sgl_pp_align_SHIFT 16 3149 #define sgl_pp_align_MASK 0x0000ffff 3150 #define sgl_pp_align_WORD word12 3151 uint32_t rsvd_13_63[51]; 3152 }; 3153 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3154 &(~((SLI4_PAGE_SIZE)-1))) 3155 3156 struct lpfc_sli4_parameters { 3157 uint32_t word0; 3158 #define cfg_prot_type_SHIFT 0 3159 #define cfg_prot_type_MASK 0x000000FF 3160 #define cfg_prot_type_WORD word0 3161 uint32_t word1; 3162 #define cfg_ft_SHIFT 0 3163 #define cfg_ft_MASK 0x00000001 3164 #define cfg_ft_WORD word1 3165 #define cfg_sli_rev_SHIFT 4 3166 #define cfg_sli_rev_MASK 0x0000000f 3167 #define cfg_sli_rev_WORD word1 3168 #define cfg_sli_family_SHIFT 8 3169 #define cfg_sli_family_MASK 0x0000000f 3170 #define cfg_sli_family_WORD word1 3171 #define cfg_if_type_SHIFT 12 3172 #define cfg_if_type_MASK 0x0000000f 3173 #define cfg_if_type_WORD word1 3174 #define cfg_sli_hint_1_SHIFT 16 3175 #define cfg_sli_hint_1_MASK 0x000000ff 3176 #define cfg_sli_hint_1_WORD word1 3177 #define cfg_sli_hint_2_SHIFT 24 3178 #define cfg_sli_hint_2_MASK 0x0000001f 3179 #define cfg_sli_hint_2_WORD word1 3180 uint32_t word2; 3181 uint32_t word3; 3182 uint32_t word4; 3183 #define cfg_cqv_SHIFT 14 3184 #define cfg_cqv_MASK 0x00000003 3185 #define cfg_cqv_WORD word4 3186 uint32_t word5; 3187 uint32_t word6; 3188 #define cfg_mqv_SHIFT 14 3189 #define cfg_mqv_MASK 0x00000003 3190 #define cfg_mqv_WORD word6 3191 uint32_t word7; 3192 uint32_t word8; 3193 #define cfg_wqpcnt_SHIFT 0 3194 #define cfg_wqpcnt_MASK 0x0000000f 3195 #define cfg_wqpcnt_WORD word8 3196 #define cfg_wqsize_SHIFT 8 3197 #define cfg_wqsize_MASK 0x0000000f 3198 #define cfg_wqsize_WORD word8 3199 #define cfg_wqv_SHIFT 14 3200 #define cfg_wqv_MASK 0x00000003 3201 #define cfg_wqv_WORD word8 3202 #define cfg_wqpsize_SHIFT 16 3203 #define cfg_wqpsize_MASK 0x000000ff 3204 #define cfg_wqpsize_WORD word8 3205 uint32_t word9; 3206 uint32_t word10; 3207 #define cfg_rqv_SHIFT 14 3208 #define cfg_rqv_MASK 0x00000003 3209 #define cfg_rqv_WORD word10 3210 uint32_t word11; 3211 #define cfg_rq_db_window_SHIFT 28 3212 #define cfg_rq_db_window_MASK 0x0000000f 3213 #define cfg_rq_db_window_WORD word11 3214 uint32_t word12; 3215 #define cfg_fcoe_SHIFT 0 3216 #define cfg_fcoe_MASK 0x00000001 3217 #define cfg_fcoe_WORD word12 3218 #define cfg_ext_SHIFT 1 3219 #define cfg_ext_MASK 0x00000001 3220 #define cfg_ext_WORD word12 3221 #define cfg_hdrr_SHIFT 2 3222 #define cfg_hdrr_MASK 0x00000001 3223 #define cfg_hdrr_WORD word12 3224 #define cfg_phwq_SHIFT 15 3225 #define cfg_phwq_MASK 0x00000001 3226 #define cfg_phwq_WORD word12 3227 #define cfg_oas_SHIFT 25 3228 #define cfg_oas_MASK 0x00000001 3229 #define cfg_oas_WORD word12 3230 #define cfg_loopbk_scope_SHIFT 28 3231 #define cfg_loopbk_scope_MASK 0x0000000f 3232 #define cfg_loopbk_scope_WORD word12 3233 uint32_t sge_supp_len; 3234 uint32_t word14; 3235 #define cfg_sgl_page_cnt_SHIFT 0 3236 #define cfg_sgl_page_cnt_MASK 0x0000000f 3237 #define cfg_sgl_page_cnt_WORD word14 3238 #define cfg_sgl_page_size_SHIFT 8 3239 #define cfg_sgl_page_size_MASK 0x000000ff 3240 #define cfg_sgl_page_size_WORD word14 3241 #define cfg_sgl_pp_align_SHIFT 16 3242 #define cfg_sgl_pp_align_MASK 0x000000ff 3243 #define cfg_sgl_pp_align_WORD word14 3244 uint32_t word15; 3245 uint32_t word16; 3246 uint32_t word17; 3247 uint32_t word18; 3248 uint32_t word19; 3249 #define cfg_ext_embed_cb_SHIFT 0 3250 #define cfg_ext_embed_cb_MASK 0x00000001 3251 #define cfg_ext_embed_cb_WORD word19 3252 #define cfg_mds_diags_SHIFT 1 3253 #define cfg_mds_diags_MASK 0x00000001 3254 #define cfg_mds_diags_WORD word19 3255 #define cfg_nvme_SHIFT 3 3256 #define cfg_nvme_MASK 0x00000001 3257 #define cfg_nvme_WORD word19 3258 #define cfg_xib_SHIFT 4 3259 #define cfg_xib_MASK 0x00000001 3260 #define cfg_xib_WORD word19 3261 }; 3262 3263 #define LPFC_SET_UE_RECOVERY 0x10 3264 #define LPFC_SET_MDS_DIAGS 0x11 3265 struct lpfc_mbx_set_feature { 3266 struct mbox_header header; 3267 uint32_t feature; 3268 uint32_t param_len; 3269 uint32_t word6; 3270 #define lpfc_mbx_set_feature_UER_SHIFT 0 3271 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3272 #define lpfc_mbx_set_feature_UER_WORD word6 3273 #define lpfc_mbx_set_feature_mds_SHIFT 0 3274 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3275 #define lpfc_mbx_set_feature_mds_WORD word6 3276 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3277 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3278 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3279 uint32_t word7; 3280 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3281 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3282 #define lpfc_mbx_set_feature_UERP_WORD word7 3283 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3284 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3285 #define lpfc_mbx_set_feature_UESR_WORD word7 3286 }; 3287 3288 3289 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3290 struct lpfc_mbx_set_host_data { 3291 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3292 struct mbox_header header; 3293 uint32_t param_id; 3294 uint32_t param_len; 3295 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3296 }; 3297 3298 3299 struct lpfc_mbx_get_sli4_parameters { 3300 struct mbox_header header; 3301 struct lpfc_sli4_parameters sli4_parameters; 3302 }; 3303 3304 struct lpfc_rscr_desc_generic { 3305 #define LPFC_RSRC_DESC_WSIZE 22 3306 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3307 }; 3308 3309 struct lpfc_rsrc_desc_pcie { 3310 uint32_t word0; 3311 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3312 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3313 #define lpfc_rsrc_desc_pcie_type_WORD word0 3314 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3315 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3316 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3317 #define lpfc_rsrc_desc_pcie_length_WORD word0 3318 uint32_t word1; 3319 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3320 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3321 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3322 uint32_t reserved; 3323 uint32_t word3; 3324 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3325 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3326 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3327 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3328 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3329 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3330 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3331 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3332 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3333 uint32_t word4; 3334 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3335 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3336 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3337 }; 3338 3339 struct lpfc_rsrc_desc_fcfcoe { 3340 uint32_t word0; 3341 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3342 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3343 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3344 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3345 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3346 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3347 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3348 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3349 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3350 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3351 uint32_t word1; 3352 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3353 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3354 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3355 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3356 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3357 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3358 uint32_t word2; 3359 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3360 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3361 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3362 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3363 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3364 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3365 uint32_t word3; 3366 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3367 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3368 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3369 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3370 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3371 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3372 uint32_t word4; 3373 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3374 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3375 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3376 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3377 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3378 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3379 uint32_t word5; 3380 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3381 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3382 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3383 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3384 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3385 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3386 uint32_t word6; 3387 uint32_t word7; 3388 uint32_t word8; 3389 uint32_t word9; 3390 uint32_t word10; 3391 uint32_t word11; 3392 uint32_t word12; 3393 uint32_t word13; 3394 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3395 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3396 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3397 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3398 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3399 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3400 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3401 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3402 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3403 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3404 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3405 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3406 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3407 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3408 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3409 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3410 uint32_t bw_min; 3411 uint32_t bw_max; 3412 uint32_t iops_min; 3413 uint32_t iops_max; 3414 uint32_t reserved[4]; 3415 }; 3416 3417 struct lpfc_func_cfg { 3418 #define LPFC_RSRC_DESC_MAX_NUM 2 3419 uint32_t rsrc_desc_count; 3420 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3421 }; 3422 3423 struct lpfc_mbx_get_func_cfg { 3424 struct mbox_header header; 3425 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3426 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3427 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3428 struct lpfc_func_cfg func_cfg; 3429 }; 3430 3431 struct lpfc_prof_cfg { 3432 #define LPFC_RSRC_DESC_MAX_NUM 2 3433 uint32_t rsrc_desc_count; 3434 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3435 }; 3436 3437 struct lpfc_mbx_get_prof_cfg { 3438 struct mbox_header header; 3439 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3440 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3441 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3442 union { 3443 struct { 3444 uint32_t word10; 3445 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3446 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3447 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3448 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3449 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3450 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3451 } request; 3452 struct { 3453 struct lpfc_prof_cfg prof_cfg; 3454 } response; 3455 } u; 3456 }; 3457 3458 struct lpfc_controller_attribute { 3459 uint32_t version_string[8]; 3460 uint32_t manufacturer_name[8]; 3461 uint32_t supported_modes; 3462 uint32_t word17; 3463 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3464 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3465 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3466 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3467 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3468 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3469 uint32_t mbx_da_struct_ver; 3470 uint32_t ep_fw_da_struct_ver; 3471 uint32_t ncsi_ver_str[3]; 3472 uint32_t dflt_ext_timeout; 3473 uint32_t model_number[8]; 3474 uint32_t description[16]; 3475 uint32_t serial_number[8]; 3476 uint32_t ip_ver_str[8]; 3477 uint32_t fw_ver_str[8]; 3478 uint32_t bios_ver_str[8]; 3479 uint32_t redboot_ver_str[8]; 3480 uint32_t driver_ver_str[8]; 3481 uint32_t flash_fw_ver_str[8]; 3482 uint32_t functionality; 3483 uint32_t word105; 3484 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3485 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3486 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3487 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3488 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3489 #define lpfc_cntl_attr_asic_rev_WORD word105 3490 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3491 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3492 #define lpfc_cntl_attr_gen_guid0_WORD word105 3493 uint32_t gen_guid1_12[3]; 3494 uint32_t word109; 3495 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3496 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3497 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3498 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3499 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3500 #define lpfc_cntl_attr_gen_guid15_WORD word109 3501 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3502 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3503 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3504 uint32_t word110; 3505 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3506 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3507 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3508 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3509 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3510 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3511 uint32_t word111; 3512 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3513 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3514 #define lpfc_cntl_attr_cache_valid_WORD word111 3515 #define lpfc_cntl_attr_hba_status_SHIFT 8 3516 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3517 #define lpfc_cntl_attr_hba_status_WORD word111 3518 #define lpfc_cntl_attr_max_domain_SHIFT 16 3519 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3520 #define lpfc_cntl_attr_max_domain_WORD word111 3521 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3522 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3523 #define lpfc_cntl_attr_lnk_numb_WORD word111 3524 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3525 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3526 #define lpfc_cntl_attr_lnk_type_WORD word111 3527 uint32_t fw_post_status; 3528 uint32_t hba_mtu[8]; 3529 uint32_t word121; 3530 uint32_t reserved1[3]; 3531 uint32_t word125; 3532 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3533 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3534 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3535 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3536 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3537 #define lpfc_cntl_attr_pci_device_id_WORD word125 3538 uint32_t word126; 3539 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3540 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3541 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3542 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3543 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3544 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3545 uint32_t word127; 3546 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3547 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3548 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3549 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3550 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3551 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3552 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3553 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3554 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3555 #define lpfc_cntl_attr_inf_type_SHIFT 24 3556 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3557 #define lpfc_cntl_attr_inf_type_WORD word127 3558 uint32_t unique_id[2]; 3559 uint32_t word130; 3560 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3561 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3562 #define lpfc_cntl_attr_num_netfil_WORD word130 3563 uint32_t reserved2[4]; 3564 }; 3565 3566 struct lpfc_mbx_get_cntl_attributes { 3567 union lpfc_sli4_cfg_shdr cfg_shdr; 3568 struct lpfc_controller_attribute cntl_attr; 3569 }; 3570 3571 struct lpfc_mbx_get_port_name { 3572 struct mbox_header header; 3573 union { 3574 struct { 3575 uint32_t word4; 3576 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3577 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3578 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3579 } request; 3580 struct { 3581 uint32_t word4; 3582 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3583 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3584 #define lpfc_mbx_get_port_name_name0_WORD word4 3585 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3586 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3587 #define lpfc_mbx_get_port_name_name1_WORD word4 3588 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3589 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3590 #define lpfc_mbx_get_port_name_name2_WORD word4 3591 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3592 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3593 #define lpfc_mbx_get_port_name_name3_WORD word4 3594 #define LPFC_LINK_NUMBER_0 0 3595 #define LPFC_LINK_NUMBER_1 1 3596 #define LPFC_LINK_NUMBER_2 2 3597 #define LPFC_LINK_NUMBER_3 3 3598 } response; 3599 } u; 3600 }; 3601 3602 /* Mailbox Completion Queue Error Messages */ 3603 #define MB_CQE_STATUS_SUCCESS 0x0 3604 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3605 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3606 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3607 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3608 #define MB_CQE_STATUS_DMA_FAILED 0x5 3609 3610 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 3611 struct lpfc_mbx_wr_object { 3612 struct mbox_header header; 3613 union { 3614 struct { 3615 uint32_t word4; 3616 #define lpfc_wr_object_eof_SHIFT 31 3617 #define lpfc_wr_object_eof_MASK 0x00000001 3618 #define lpfc_wr_object_eof_WORD word4 3619 #define lpfc_wr_object_write_length_SHIFT 0 3620 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3621 #define lpfc_wr_object_write_length_WORD word4 3622 uint32_t write_offset; 3623 uint32_t object_name[26]; 3624 uint32_t bde_count; 3625 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3626 } request; 3627 struct { 3628 uint32_t actual_write_length; 3629 } response; 3630 } u; 3631 }; 3632 3633 /* mailbox queue entry structure */ 3634 struct lpfc_mqe { 3635 uint32_t word0; 3636 #define lpfc_mqe_status_SHIFT 16 3637 #define lpfc_mqe_status_MASK 0x0000FFFF 3638 #define lpfc_mqe_status_WORD word0 3639 #define lpfc_mqe_command_SHIFT 8 3640 #define lpfc_mqe_command_MASK 0x000000FF 3641 #define lpfc_mqe_command_WORD word0 3642 union { 3643 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3644 /* sli4 mailbox commands */ 3645 struct lpfc_mbx_sli4_config sli4_config; 3646 struct lpfc_mbx_init_vfi init_vfi; 3647 struct lpfc_mbx_reg_vfi reg_vfi; 3648 struct lpfc_mbx_reg_vfi unreg_vfi; 3649 struct lpfc_mbx_init_vpi init_vpi; 3650 struct lpfc_mbx_resume_rpi resume_rpi; 3651 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3652 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3653 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3654 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3655 struct lpfc_mbx_reg_fcfi reg_fcfi; 3656 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3657 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3658 struct lpfc_mbx_mq_create mq_create; 3659 struct lpfc_mbx_mq_create_ext mq_create_ext; 3660 struct lpfc_mbx_eq_create eq_create; 3661 struct lpfc_mbx_modify_eq_delay eq_delay; 3662 struct lpfc_mbx_cq_create cq_create; 3663 struct lpfc_mbx_cq_create_set cq_create_set; 3664 struct lpfc_mbx_wq_create wq_create; 3665 struct lpfc_mbx_rq_create rq_create; 3666 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3667 struct lpfc_mbx_mq_destroy mq_destroy; 3668 struct lpfc_mbx_eq_destroy eq_destroy; 3669 struct lpfc_mbx_cq_destroy cq_destroy; 3670 struct lpfc_mbx_wq_destroy wq_destroy; 3671 struct lpfc_mbx_rq_destroy rq_destroy; 3672 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3673 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3674 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3675 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3676 struct lpfc_mbx_nembed_cmd nembed_cmd; 3677 struct lpfc_mbx_read_rev read_rev; 3678 struct lpfc_mbx_read_vpi read_vpi; 3679 struct lpfc_mbx_read_config rd_config; 3680 struct lpfc_mbx_request_features req_ftrs; 3681 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3682 struct lpfc_mbx_query_fw_config query_fw_cfg; 3683 struct lpfc_mbx_set_beacon_config beacon_config; 3684 struct lpfc_mbx_supp_pages supp_pages; 3685 struct lpfc_mbx_pc_sli4_params sli4_params; 3686 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3687 struct lpfc_mbx_set_link_diag_state link_diag_state; 3688 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3689 struct lpfc_mbx_run_link_diag_test link_diag_test; 3690 struct lpfc_mbx_get_func_cfg get_func_cfg; 3691 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3692 struct lpfc_mbx_wr_object wr_object; 3693 struct lpfc_mbx_get_port_name get_port_name; 3694 struct lpfc_mbx_set_feature set_feature; 3695 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3696 struct lpfc_mbx_set_host_data set_host_data; 3697 struct lpfc_mbx_nop nop; 3698 } un; 3699 }; 3700 3701 struct lpfc_mcqe { 3702 uint32_t word0; 3703 #define lpfc_mcqe_status_SHIFT 0 3704 #define lpfc_mcqe_status_MASK 0x0000FFFF 3705 #define lpfc_mcqe_status_WORD word0 3706 #define lpfc_mcqe_ext_status_SHIFT 16 3707 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3708 #define lpfc_mcqe_ext_status_WORD word0 3709 uint32_t mcqe_tag0; 3710 uint32_t mcqe_tag1; 3711 uint32_t trailer; 3712 #define lpfc_trailer_valid_SHIFT 31 3713 #define lpfc_trailer_valid_MASK 0x00000001 3714 #define lpfc_trailer_valid_WORD trailer 3715 #define lpfc_trailer_async_SHIFT 30 3716 #define lpfc_trailer_async_MASK 0x00000001 3717 #define lpfc_trailer_async_WORD trailer 3718 #define lpfc_trailer_hpi_SHIFT 29 3719 #define lpfc_trailer_hpi_MASK 0x00000001 3720 #define lpfc_trailer_hpi_WORD trailer 3721 #define lpfc_trailer_completed_SHIFT 28 3722 #define lpfc_trailer_completed_MASK 0x00000001 3723 #define lpfc_trailer_completed_WORD trailer 3724 #define lpfc_trailer_consumed_SHIFT 27 3725 #define lpfc_trailer_consumed_MASK 0x00000001 3726 #define lpfc_trailer_consumed_WORD trailer 3727 #define lpfc_trailer_type_SHIFT 16 3728 #define lpfc_trailer_type_MASK 0x000000FF 3729 #define lpfc_trailer_type_WORD trailer 3730 #define lpfc_trailer_code_SHIFT 8 3731 #define lpfc_trailer_code_MASK 0x000000FF 3732 #define lpfc_trailer_code_WORD trailer 3733 #define LPFC_TRAILER_CODE_LINK 0x1 3734 #define LPFC_TRAILER_CODE_FCOE 0x2 3735 #define LPFC_TRAILER_CODE_DCBX 0x3 3736 #define LPFC_TRAILER_CODE_GRP5 0x5 3737 #define LPFC_TRAILER_CODE_FC 0x10 3738 #define LPFC_TRAILER_CODE_SLI 0x11 3739 }; 3740 3741 struct lpfc_acqe_link { 3742 uint32_t word0; 3743 #define lpfc_acqe_link_speed_SHIFT 24 3744 #define lpfc_acqe_link_speed_MASK 0x000000FF 3745 #define lpfc_acqe_link_speed_WORD word0 3746 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3747 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3748 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3749 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3750 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3751 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3752 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3753 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3754 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3755 #define lpfc_acqe_link_duplex_SHIFT 16 3756 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3757 #define lpfc_acqe_link_duplex_WORD word0 3758 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3759 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3760 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3761 #define lpfc_acqe_link_status_SHIFT 8 3762 #define lpfc_acqe_link_status_MASK 0x000000FF 3763 #define lpfc_acqe_link_status_WORD word0 3764 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3765 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3766 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3767 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3768 #define lpfc_acqe_link_type_SHIFT 6 3769 #define lpfc_acqe_link_type_MASK 0x00000003 3770 #define lpfc_acqe_link_type_WORD word0 3771 #define lpfc_acqe_link_number_SHIFT 0 3772 #define lpfc_acqe_link_number_MASK 0x0000003F 3773 #define lpfc_acqe_link_number_WORD word0 3774 uint32_t word1; 3775 #define lpfc_acqe_link_fault_SHIFT 0 3776 #define lpfc_acqe_link_fault_MASK 0x000000FF 3777 #define lpfc_acqe_link_fault_WORD word1 3778 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3779 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3780 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3781 #define lpfc_acqe_logical_link_speed_SHIFT 16 3782 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3783 #define lpfc_acqe_logical_link_speed_WORD word1 3784 uint32_t event_tag; 3785 uint32_t trailer; 3786 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3787 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3788 }; 3789 3790 struct lpfc_acqe_fip { 3791 uint32_t index; 3792 uint32_t word1; 3793 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3794 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3795 #define lpfc_acqe_fip_fcf_count_WORD word1 3796 #define lpfc_acqe_fip_event_type_SHIFT 16 3797 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3798 #define lpfc_acqe_fip_event_type_WORD word1 3799 uint32_t event_tag; 3800 uint32_t trailer; 3801 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3802 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3803 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3804 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3805 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3806 }; 3807 3808 struct lpfc_acqe_dcbx { 3809 uint32_t tlv_ttl; 3810 uint32_t reserved; 3811 uint32_t event_tag; 3812 uint32_t trailer; 3813 }; 3814 3815 struct lpfc_acqe_grp5 { 3816 uint32_t word0; 3817 #define lpfc_acqe_grp5_type_SHIFT 6 3818 #define lpfc_acqe_grp5_type_MASK 0x00000003 3819 #define lpfc_acqe_grp5_type_WORD word0 3820 #define lpfc_acqe_grp5_number_SHIFT 0 3821 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3822 #define lpfc_acqe_grp5_number_WORD word0 3823 uint32_t word1; 3824 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3825 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3826 #define lpfc_acqe_grp5_llink_spd_WORD word1 3827 uint32_t event_tag; 3828 uint32_t trailer; 3829 }; 3830 3831 struct lpfc_acqe_fc_la { 3832 uint32_t word0; 3833 #define lpfc_acqe_fc_la_speed_SHIFT 24 3834 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3835 #define lpfc_acqe_fc_la_speed_WORD word0 3836 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 3837 #define LPFC_FC_LA_SPEED_1G 0x1 3838 #define LPFC_FC_LA_SPEED_2G 0x2 3839 #define LPFC_FC_LA_SPEED_4G 0x4 3840 #define LPFC_FC_LA_SPEED_8G 0x8 3841 #define LPFC_FC_LA_SPEED_10G 0xA 3842 #define LPFC_FC_LA_SPEED_16G 0x10 3843 #define LPFC_FC_LA_SPEED_32G 0x20 3844 #define lpfc_acqe_fc_la_topology_SHIFT 16 3845 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3846 #define lpfc_acqe_fc_la_topology_WORD word0 3847 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3848 #define LPFC_FC_LA_TOP_P2P 0x1 3849 #define LPFC_FC_LA_TOP_FCAL 0x2 3850 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3851 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3852 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3853 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3854 #define lpfc_acqe_fc_la_att_type_WORD word0 3855 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3856 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3857 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3858 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 3859 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 3860 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 3861 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3862 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3863 #define lpfc_acqe_fc_la_port_type_WORD word0 3864 #define LPFC_LINK_TYPE_ETHERNET 0x0 3865 #define LPFC_LINK_TYPE_FC 0x1 3866 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3867 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3868 #define lpfc_acqe_fc_la_port_number_WORD word0 3869 uint32_t word1; 3870 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3871 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3872 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3873 #define lpfc_acqe_fc_la_fault_SHIFT 0 3874 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3875 #define lpfc_acqe_fc_la_fault_WORD word1 3876 #define LPFC_FC_LA_FAULT_NONE 0x0 3877 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3878 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3879 uint32_t event_tag; 3880 uint32_t trailer; 3881 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3882 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3883 }; 3884 3885 struct lpfc_acqe_misconfigured_event { 3886 struct { 3887 uint32_t word0; 3888 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 3889 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 3890 #define lpfc_sli_misconfigured_port0_state_WORD word0 3891 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 3892 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 3893 #define lpfc_sli_misconfigured_port1_state_WORD word0 3894 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 3895 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 3896 #define lpfc_sli_misconfigured_port2_state_WORD word0 3897 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 3898 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 3899 #define lpfc_sli_misconfigured_port3_state_WORD word0 3900 uint32_t word1; 3901 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 3902 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 3903 #define lpfc_sli_misconfigured_port0_op_WORD word1 3904 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 3905 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 3906 #define lpfc_sli_misconfigured_port0_severity_WORD word1 3907 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 3908 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 3909 #define lpfc_sli_misconfigured_port1_op_WORD word1 3910 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 3911 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 3912 #define lpfc_sli_misconfigured_port1_severity_WORD word1 3913 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 3914 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 3915 #define lpfc_sli_misconfigured_port2_op_WORD word1 3916 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 3917 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 3918 #define lpfc_sli_misconfigured_port2_severity_WORD word1 3919 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 3920 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 3921 #define lpfc_sli_misconfigured_port3_op_WORD word1 3922 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 3923 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 3924 #define lpfc_sli_misconfigured_port3_severity_WORD word1 3925 } theEvent; 3926 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3927 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3928 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3929 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3930 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 3931 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 3932 }; 3933 3934 struct lpfc_acqe_sli { 3935 uint32_t event_data1; 3936 uint32_t event_data2; 3937 uint32_t reserved; 3938 uint32_t trailer; 3939 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3940 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3941 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3942 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3943 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3944 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3945 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 3946 }; 3947 3948 /* 3949 * Define the bootstrap mailbox (bmbx) region used to communicate 3950 * mailbox command between the host and port. The mailbox consists 3951 * of a payload area of 256 bytes and a completion queue of length 3952 * 16 bytes. 3953 */ 3954 struct lpfc_bmbx_create { 3955 struct lpfc_mqe mqe; 3956 struct lpfc_mcqe mcqe; 3957 }; 3958 3959 #define SGL_ALIGN_SZ 64 3960 #define SGL_PAGE_SIZE 4096 3961 /* align SGL addr on a size boundary - adjust address up */ 3962 #define NO_XRI 0xffff 3963 3964 struct wqe_common { 3965 uint32_t word6; 3966 #define wqe_xri_tag_SHIFT 0 3967 #define wqe_xri_tag_MASK 0x0000FFFF 3968 #define wqe_xri_tag_WORD word6 3969 #define wqe_ctxt_tag_SHIFT 16 3970 #define wqe_ctxt_tag_MASK 0x0000FFFF 3971 #define wqe_ctxt_tag_WORD word6 3972 uint32_t word7; 3973 #define wqe_dif_SHIFT 0 3974 #define wqe_dif_MASK 0x00000003 3975 #define wqe_dif_WORD word7 3976 #define LPFC_WQE_DIF_PASSTHRU 1 3977 #define LPFC_WQE_DIF_STRIP 2 3978 #define LPFC_WQE_DIF_INSERT 3 3979 #define wqe_ct_SHIFT 2 3980 #define wqe_ct_MASK 0x00000003 3981 #define wqe_ct_WORD word7 3982 #define wqe_status_SHIFT 4 3983 #define wqe_status_MASK 0x0000000f 3984 #define wqe_status_WORD word7 3985 #define wqe_cmnd_SHIFT 8 3986 #define wqe_cmnd_MASK 0x000000ff 3987 #define wqe_cmnd_WORD word7 3988 #define wqe_class_SHIFT 16 3989 #define wqe_class_MASK 0x00000007 3990 #define wqe_class_WORD word7 3991 #define wqe_ar_SHIFT 19 3992 #define wqe_ar_MASK 0x00000001 3993 #define wqe_ar_WORD word7 3994 #define wqe_ag_SHIFT wqe_ar_SHIFT 3995 #define wqe_ag_MASK wqe_ar_MASK 3996 #define wqe_ag_WORD wqe_ar_WORD 3997 #define wqe_pu_SHIFT 20 3998 #define wqe_pu_MASK 0x00000003 3999 #define wqe_pu_WORD word7 4000 #define wqe_erp_SHIFT 22 4001 #define wqe_erp_MASK 0x00000001 4002 #define wqe_erp_WORD word7 4003 #define wqe_conf_SHIFT wqe_erp_SHIFT 4004 #define wqe_conf_MASK wqe_erp_MASK 4005 #define wqe_conf_WORD wqe_erp_WORD 4006 #define wqe_lnk_SHIFT 23 4007 #define wqe_lnk_MASK 0x00000001 4008 #define wqe_lnk_WORD word7 4009 #define wqe_tmo_SHIFT 24 4010 #define wqe_tmo_MASK 0x000000ff 4011 #define wqe_tmo_WORD word7 4012 uint32_t abort_tag; /* word 8 in WQE */ 4013 uint32_t word9; 4014 #define wqe_reqtag_SHIFT 0 4015 #define wqe_reqtag_MASK 0x0000FFFF 4016 #define wqe_reqtag_WORD word9 4017 #define wqe_temp_rpi_SHIFT 16 4018 #define wqe_temp_rpi_MASK 0x0000FFFF 4019 #define wqe_temp_rpi_WORD word9 4020 #define wqe_rcvoxid_SHIFT 16 4021 #define wqe_rcvoxid_MASK 0x0000FFFF 4022 #define wqe_rcvoxid_WORD word9 4023 uint32_t word10; 4024 #define wqe_ebde_cnt_SHIFT 0 4025 #define wqe_ebde_cnt_MASK 0x0000000f 4026 #define wqe_ebde_cnt_WORD word10 4027 #define wqe_nvme_SHIFT 4 4028 #define wqe_nvme_MASK 0x00000001 4029 #define wqe_nvme_WORD word10 4030 #define wqe_oas_SHIFT 6 4031 #define wqe_oas_MASK 0x00000001 4032 #define wqe_oas_WORD word10 4033 #define wqe_lenloc_SHIFT 7 4034 #define wqe_lenloc_MASK 0x00000003 4035 #define wqe_lenloc_WORD word10 4036 #define LPFC_WQE_LENLOC_NONE 0 4037 #define LPFC_WQE_LENLOC_WORD3 1 4038 #define LPFC_WQE_LENLOC_WORD12 2 4039 #define LPFC_WQE_LENLOC_WORD4 3 4040 #define wqe_qosd_SHIFT 9 4041 #define wqe_qosd_MASK 0x00000001 4042 #define wqe_qosd_WORD word10 4043 #define wqe_xbl_SHIFT 11 4044 #define wqe_xbl_MASK 0x00000001 4045 #define wqe_xbl_WORD word10 4046 #define wqe_iod_SHIFT 13 4047 #define wqe_iod_MASK 0x00000001 4048 #define wqe_iod_WORD word10 4049 #define LPFC_WQE_IOD_WRITE 0 4050 #define LPFC_WQE_IOD_READ 1 4051 #define wqe_dbde_SHIFT 14 4052 #define wqe_dbde_MASK 0x00000001 4053 #define wqe_dbde_WORD word10 4054 #define wqe_wqes_SHIFT 15 4055 #define wqe_wqes_MASK 0x00000001 4056 #define wqe_wqes_WORD word10 4057 /* Note that this field overlaps above fields */ 4058 #define wqe_wqid_SHIFT 1 4059 #define wqe_wqid_MASK 0x00007fff 4060 #define wqe_wqid_WORD word10 4061 #define wqe_pri_SHIFT 16 4062 #define wqe_pri_MASK 0x00000007 4063 #define wqe_pri_WORD word10 4064 #define wqe_pv_SHIFT 19 4065 #define wqe_pv_MASK 0x00000001 4066 #define wqe_pv_WORD word10 4067 #define wqe_xc_SHIFT 21 4068 #define wqe_xc_MASK 0x00000001 4069 #define wqe_xc_WORD word10 4070 #define wqe_sr_SHIFT 22 4071 #define wqe_sr_MASK 0x00000001 4072 #define wqe_sr_WORD word10 4073 #define wqe_ccpe_SHIFT 23 4074 #define wqe_ccpe_MASK 0x00000001 4075 #define wqe_ccpe_WORD word10 4076 #define wqe_ccp_SHIFT 24 4077 #define wqe_ccp_MASK 0x000000ff 4078 #define wqe_ccp_WORD word10 4079 uint32_t word11; 4080 #define wqe_cmd_type_SHIFT 0 4081 #define wqe_cmd_type_MASK 0x0000000f 4082 #define wqe_cmd_type_WORD word11 4083 #define wqe_els_id_SHIFT 4 4084 #define wqe_els_id_MASK 0x00000003 4085 #define wqe_els_id_WORD word11 4086 #define LPFC_ELS_ID_FLOGI 3 4087 #define LPFC_ELS_ID_FDISC 2 4088 #define LPFC_ELS_ID_LOGO 1 4089 #define LPFC_ELS_ID_DEFAULT 0 4090 #define wqe_irsp_SHIFT 4 4091 #define wqe_irsp_MASK 0x00000001 4092 #define wqe_irsp_WORD word11 4093 #define wqe_sup_SHIFT 6 4094 #define wqe_sup_MASK 0x00000001 4095 #define wqe_sup_WORD word11 4096 #define wqe_wqec_SHIFT 7 4097 #define wqe_wqec_MASK 0x00000001 4098 #define wqe_wqec_WORD word11 4099 #define wqe_irsplen_SHIFT 8 4100 #define wqe_irsplen_MASK 0x0000000f 4101 #define wqe_irsplen_WORD word11 4102 #define wqe_cqid_SHIFT 16 4103 #define wqe_cqid_MASK 0x0000ffff 4104 #define wqe_cqid_WORD word11 4105 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4106 }; 4107 4108 struct wqe_did { 4109 uint32_t word5; 4110 #define wqe_els_did_SHIFT 0 4111 #define wqe_els_did_MASK 0x00FFFFFF 4112 #define wqe_els_did_WORD word5 4113 #define wqe_xmit_bls_pt_SHIFT 28 4114 #define wqe_xmit_bls_pt_MASK 0x00000003 4115 #define wqe_xmit_bls_pt_WORD word5 4116 #define wqe_xmit_bls_ar_SHIFT 30 4117 #define wqe_xmit_bls_ar_MASK 0x00000001 4118 #define wqe_xmit_bls_ar_WORD word5 4119 #define wqe_xmit_bls_xo_SHIFT 31 4120 #define wqe_xmit_bls_xo_MASK 0x00000001 4121 #define wqe_xmit_bls_xo_WORD word5 4122 }; 4123 4124 struct lpfc_wqe_generic{ 4125 struct ulp_bde64 bde; 4126 uint32_t word3; 4127 uint32_t word4; 4128 uint32_t word5; 4129 struct wqe_common wqe_com; 4130 uint32_t payload[4]; 4131 }; 4132 4133 struct els_request64_wqe { 4134 struct ulp_bde64 bde; 4135 uint32_t payload_len; 4136 uint32_t word4; 4137 #define els_req64_sid_SHIFT 0 4138 #define els_req64_sid_MASK 0x00FFFFFF 4139 #define els_req64_sid_WORD word4 4140 #define els_req64_sp_SHIFT 24 4141 #define els_req64_sp_MASK 0x00000001 4142 #define els_req64_sp_WORD word4 4143 #define els_req64_vf_SHIFT 25 4144 #define els_req64_vf_MASK 0x00000001 4145 #define els_req64_vf_WORD word4 4146 struct wqe_did wqe_dest; 4147 struct wqe_common wqe_com; /* words 6-11 */ 4148 uint32_t word12; 4149 #define els_req64_vfid_SHIFT 1 4150 #define els_req64_vfid_MASK 0x00000FFF 4151 #define els_req64_vfid_WORD word12 4152 #define els_req64_pri_SHIFT 13 4153 #define els_req64_pri_MASK 0x00000007 4154 #define els_req64_pri_WORD word12 4155 uint32_t word13; 4156 #define els_req64_hopcnt_SHIFT 24 4157 #define els_req64_hopcnt_MASK 0x000000ff 4158 #define els_req64_hopcnt_WORD word13 4159 uint32_t word14; 4160 uint32_t max_response_payload_len; 4161 }; 4162 4163 struct xmit_els_rsp64_wqe { 4164 struct ulp_bde64 bde; 4165 uint32_t response_payload_len; 4166 uint32_t word4; 4167 #define els_rsp64_sid_SHIFT 0 4168 #define els_rsp64_sid_MASK 0x00FFFFFF 4169 #define els_rsp64_sid_WORD word4 4170 #define els_rsp64_sp_SHIFT 24 4171 #define els_rsp64_sp_MASK 0x00000001 4172 #define els_rsp64_sp_WORD word4 4173 struct wqe_did wqe_dest; 4174 struct wqe_common wqe_com; /* words 6-11 */ 4175 uint32_t word12; 4176 #define wqe_rsp_temp_rpi_SHIFT 0 4177 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4178 #define wqe_rsp_temp_rpi_WORD word12 4179 uint32_t rsvd_13_15[3]; 4180 }; 4181 4182 struct xmit_bls_rsp64_wqe { 4183 uint32_t payload0; 4184 /* Payload0 for BA_ACC */ 4185 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4186 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4187 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4188 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4189 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4190 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4191 /* Payload0 for BA_RJT */ 4192 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4193 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4194 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4195 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4196 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4197 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4198 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4199 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4200 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4201 uint32_t word1; 4202 #define xmit_bls_rsp64_rxid_SHIFT 0 4203 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4204 #define xmit_bls_rsp64_rxid_WORD word1 4205 #define xmit_bls_rsp64_oxid_SHIFT 16 4206 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4207 #define xmit_bls_rsp64_oxid_WORD word1 4208 uint32_t word2; 4209 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4210 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4211 #define xmit_bls_rsp64_seqcnthi_WORD word2 4212 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4213 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4214 #define xmit_bls_rsp64_seqcntlo_WORD word2 4215 uint32_t rsrvd3; 4216 uint32_t rsrvd4; 4217 struct wqe_did wqe_dest; 4218 struct wqe_common wqe_com; /* words 6-11 */ 4219 uint32_t word12; 4220 #define xmit_bls_rsp64_temprpi_SHIFT 0 4221 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4222 #define xmit_bls_rsp64_temprpi_WORD word12 4223 uint32_t rsvd_13_15[3]; 4224 }; 4225 4226 struct wqe_rctl_dfctl { 4227 uint32_t word5; 4228 #define wqe_si_SHIFT 2 4229 #define wqe_si_MASK 0x000000001 4230 #define wqe_si_WORD word5 4231 #define wqe_la_SHIFT 3 4232 #define wqe_la_MASK 0x000000001 4233 #define wqe_la_WORD word5 4234 #define wqe_xo_SHIFT 6 4235 #define wqe_xo_MASK 0x000000001 4236 #define wqe_xo_WORD word5 4237 #define wqe_ls_SHIFT 7 4238 #define wqe_ls_MASK 0x000000001 4239 #define wqe_ls_WORD word5 4240 #define wqe_dfctl_SHIFT 8 4241 #define wqe_dfctl_MASK 0x0000000ff 4242 #define wqe_dfctl_WORD word5 4243 #define wqe_type_SHIFT 16 4244 #define wqe_type_MASK 0x0000000ff 4245 #define wqe_type_WORD word5 4246 #define wqe_rctl_SHIFT 24 4247 #define wqe_rctl_MASK 0x0000000ff 4248 #define wqe_rctl_WORD word5 4249 }; 4250 4251 struct xmit_seq64_wqe { 4252 struct ulp_bde64 bde; 4253 uint32_t rsvd3; 4254 uint32_t relative_offset; 4255 struct wqe_rctl_dfctl wge_ctl; 4256 struct wqe_common wqe_com; /* words 6-11 */ 4257 uint32_t xmit_len; 4258 uint32_t rsvd_12_15[3]; 4259 }; 4260 struct xmit_bcast64_wqe { 4261 struct ulp_bde64 bde; 4262 uint32_t seq_payload_len; 4263 uint32_t rsvd4; 4264 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4265 struct wqe_common wqe_com; /* words 6-11 */ 4266 uint32_t rsvd_12_15[4]; 4267 }; 4268 4269 struct gen_req64_wqe { 4270 struct ulp_bde64 bde; 4271 uint32_t request_payload_len; 4272 uint32_t relative_offset; 4273 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4274 struct wqe_common wqe_com; /* words 6-11 */ 4275 uint32_t rsvd_12_14[3]; 4276 uint32_t max_response_payload_len; 4277 }; 4278 4279 /* Define NVME PRLI request to fabric. NVME is a 4280 * fabric-only protocol. 4281 * Updated to red-lined v1.08 on Sept 16, 2016 4282 */ 4283 struct lpfc_nvme_prli { 4284 uint32_t word1; 4285 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4286 #define prli_acc_rsp_code_SHIFT 8 4287 #define prli_acc_rsp_code_MASK 0x0000000f 4288 #define prli_acc_rsp_code_WORD word1 4289 #define prli_estabImagePair_SHIFT 13 4290 #define prli_estabImagePair_MASK 0x00000001 4291 #define prli_estabImagePair_WORD word1 4292 #define prli_type_code_ext_SHIFT 16 4293 #define prli_type_code_ext_MASK 0x000000ff 4294 #define prli_type_code_ext_WORD word1 4295 #define prli_type_code_SHIFT 24 4296 #define prli_type_code_MASK 0x000000ff 4297 #define prli_type_code_WORD word1 4298 uint32_t word_rsvd2; 4299 uint32_t word_rsvd3; 4300 uint32_t word4; 4301 #define prli_fba_SHIFT 0 4302 #define prli_fba_MASK 0x00000001 4303 #define prli_fba_WORD word4 4304 #define prli_disc_SHIFT 3 4305 #define prli_disc_MASK 0x00000001 4306 #define prli_disc_WORD word4 4307 #define prli_tgt_SHIFT 4 4308 #define prli_tgt_MASK 0x00000001 4309 #define prli_tgt_WORD word4 4310 #define prli_init_SHIFT 5 4311 #define prli_init_MASK 0x00000001 4312 #define prli_init_WORD word4 4313 #define prli_recov_SHIFT 8 4314 #define prli_recov_MASK 0x00000001 4315 #define prli_recov_WORD word4 4316 uint32_t word5; 4317 #define prli_fb_sz_SHIFT 0 4318 #define prli_fb_sz_MASK 0x0000ffff 4319 #define prli_fb_sz_WORD word5 4320 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4321 }; 4322 4323 struct create_xri_wqe { 4324 uint32_t rsrvd[5]; /* words 0-4 */ 4325 struct wqe_did wqe_dest; /* word 5 */ 4326 struct wqe_common wqe_com; /* words 6-11 */ 4327 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4328 }; 4329 4330 #define T_REQUEST_TAG 3 4331 #define T_XRI_TAG 1 4332 4333 struct abort_cmd_wqe { 4334 uint32_t rsrvd[3]; 4335 uint32_t word3; 4336 #define abort_cmd_ia_SHIFT 0 4337 #define abort_cmd_ia_MASK 0x000000001 4338 #define abort_cmd_ia_WORD word3 4339 #define abort_cmd_criteria_SHIFT 8 4340 #define abort_cmd_criteria_MASK 0x0000000ff 4341 #define abort_cmd_criteria_WORD word3 4342 uint32_t rsrvd4; 4343 uint32_t rsrvd5; 4344 struct wqe_common wqe_com; /* words 6-11 */ 4345 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4346 }; 4347 4348 struct fcp_iwrite64_wqe { 4349 struct ulp_bde64 bde; 4350 uint32_t word3; 4351 #define cmd_buff_len_SHIFT 16 4352 #define cmd_buff_len_MASK 0x00000ffff 4353 #define cmd_buff_len_WORD word3 4354 #define payload_offset_len_SHIFT 0 4355 #define payload_offset_len_MASK 0x0000ffff 4356 #define payload_offset_len_WORD word3 4357 uint32_t total_xfer_len; 4358 uint32_t initial_xfer_len; 4359 struct wqe_common wqe_com; /* words 6-11 */ 4360 uint32_t rsrvd12; 4361 struct ulp_bde64 ph_bde; /* words 13-15 */ 4362 }; 4363 4364 struct fcp_iread64_wqe { 4365 struct ulp_bde64 bde; 4366 uint32_t word3; 4367 #define cmd_buff_len_SHIFT 16 4368 #define cmd_buff_len_MASK 0x00000ffff 4369 #define cmd_buff_len_WORD word3 4370 #define payload_offset_len_SHIFT 0 4371 #define payload_offset_len_MASK 0x0000ffff 4372 #define payload_offset_len_WORD word3 4373 uint32_t total_xfer_len; /* word 4 */ 4374 uint32_t rsrvd5; /* word 5 */ 4375 struct wqe_common wqe_com; /* words 6-11 */ 4376 uint32_t rsrvd12; 4377 struct ulp_bde64 ph_bde; /* words 13-15 */ 4378 }; 4379 4380 struct fcp_icmnd64_wqe { 4381 struct ulp_bde64 bde; /* words 0-2 */ 4382 uint32_t word3; 4383 #define cmd_buff_len_SHIFT 16 4384 #define cmd_buff_len_MASK 0x00000ffff 4385 #define cmd_buff_len_WORD word3 4386 #define payload_offset_len_SHIFT 0 4387 #define payload_offset_len_MASK 0x0000ffff 4388 #define payload_offset_len_WORD word3 4389 uint32_t rsrvd4; /* word 4 */ 4390 uint32_t rsrvd5; /* word 5 */ 4391 struct wqe_common wqe_com; /* words 6-11 */ 4392 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4393 }; 4394 4395 struct fcp_trsp64_wqe { 4396 struct ulp_bde64 bde; 4397 uint32_t response_len; 4398 uint32_t rsvd_4_5[2]; 4399 struct wqe_common wqe_com; /* words 6-11 */ 4400 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4401 }; 4402 4403 struct fcp_tsend64_wqe { 4404 struct ulp_bde64 bde; 4405 uint32_t payload_offset_len; 4406 uint32_t relative_offset; 4407 uint32_t reserved; 4408 struct wqe_common wqe_com; /* words 6-11 */ 4409 uint32_t fcp_data_len; /* word 12 */ 4410 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4411 }; 4412 4413 struct fcp_treceive64_wqe { 4414 struct ulp_bde64 bde; 4415 uint32_t payload_offset_len; 4416 uint32_t relative_offset; 4417 uint32_t reserved; 4418 struct wqe_common wqe_com; /* words 6-11 */ 4419 uint32_t fcp_data_len; /* word 12 */ 4420 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4421 }; 4422 #define TXRDY_PAYLOAD_LEN 12 4423 4424 #define CMD_SEND_FRAME 0xE1 4425 4426 struct send_frame_wqe { 4427 struct ulp_bde64 bde; /* words 0-2 */ 4428 uint32_t frame_len; /* word 3 */ 4429 uint32_t fc_hdr_wd0; /* word 4 */ 4430 uint32_t fc_hdr_wd1; /* word 5 */ 4431 struct wqe_common wqe_com; /* words 6-11 */ 4432 uint32_t fc_hdr_wd2; /* word 12 */ 4433 uint32_t fc_hdr_wd3; /* word 13 */ 4434 uint32_t fc_hdr_wd4; /* word 14 */ 4435 uint32_t fc_hdr_wd5; /* word 15 */ 4436 }; 4437 4438 union lpfc_wqe { 4439 uint32_t words[16]; 4440 struct lpfc_wqe_generic generic; 4441 struct fcp_icmnd64_wqe fcp_icmd; 4442 struct fcp_iread64_wqe fcp_iread; 4443 struct fcp_iwrite64_wqe fcp_iwrite; 4444 struct abort_cmd_wqe abort_cmd; 4445 struct create_xri_wqe create_xri; 4446 struct xmit_bcast64_wqe xmit_bcast64; 4447 struct xmit_seq64_wqe xmit_sequence; 4448 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4449 struct xmit_els_rsp64_wqe xmit_els_rsp; 4450 struct els_request64_wqe els_req; 4451 struct gen_req64_wqe gen_req; 4452 struct fcp_trsp64_wqe fcp_trsp; 4453 struct fcp_tsend64_wqe fcp_tsend; 4454 struct fcp_treceive64_wqe fcp_treceive; 4455 struct send_frame_wqe send_frame; 4456 }; 4457 4458 union lpfc_wqe128 { 4459 uint32_t words[32]; 4460 struct lpfc_wqe_generic generic; 4461 struct fcp_icmnd64_wqe fcp_icmd; 4462 struct fcp_iread64_wqe fcp_iread; 4463 struct fcp_iwrite64_wqe fcp_iwrite; 4464 struct fcp_trsp64_wqe fcp_trsp; 4465 struct fcp_tsend64_wqe fcp_tsend; 4466 struct fcp_treceive64_wqe fcp_treceive; 4467 struct xmit_seq64_wqe xmit_sequence; 4468 struct gen_req64_wqe gen_req; 4469 }; 4470 4471 #define LPFC_GROUP_OJECT_MAGIC_G5 0xfeaa0001 4472 #define LPFC_GROUP_OJECT_MAGIC_G6 0xfeaa0003 4473 #define LPFC_FILE_TYPE_GROUP 0xf7 4474 #define LPFC_FILE_ID_GROUP 0xa2 4475 struct lpfc_grp_hdr { 4476 uint32_t size; 4477 uint32_t magic_number; 4478 uint32_t word2; 4479 #define lpfc_grp_hdr_file_type_SHIFT 24 4480 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4481 #define lpfc_grp_hdr_file_type_WORD word2 4482 #define lpfc_grp_hdr_id_SHIFT 16 4483 #define lpfc_grp_hdr_id_MASK 0x000000FF 4484 #define lpfc_grp_hdr_id_WORD word2 4485 uint8_t rev_name[128]; 4486 uint8_t date[12]; 4487 uint8_t revision[32]; 4488 }; 4489 4490 /* Defines for WQE command type */ 4491 #define FCP_COMMAND 0x0 4492 #define NVME_READ_CMD 0x0 4493 #define FCP_COMMAND_DATA_OUT 0x1 4494 #define NVME_WRITE_CMD 0x1 4495 #define FCP_COMMAND_TRECEIVE 0x2 4496 #define FCP_COMMAND_TRSP 0x3 4497 #define FCP_COMMAND_TSEND 0x7 4498 #define OTHER_COMMAND 0x8 4499 #define ELS_COMMAND_NON_FIP 0xC 4500 #define ELS_COMMAND_FIP 0xD 4501 4502 #define LPFC_NVME_EMBED_CMD 0x0 4503 #define LPFC_NVME_EMBED_WRITE 0x1 4504 #define LPFC_NVME_EMBED_READ 0x2 4505 4506 /* WQE Commands */ 4507 #define CMD_ABORT_XRI_WQE 0x0F 4508 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4509 #define CMD_XMIT_BCAST64_WQE 0x84 4510 #define CMD_ELS_REQUEST64_WQE 0x8A 4511 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4512 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4513 #define CMD_FCP_IWRITE64_WQE 0x98 4514 #define CMD_FCP_IREAD64_WQE 0x9A 4515 #define CMD_FCP_ICMND64_WQE 0x9C 4516 #define CMD_FCP_TSEND64_WQE 0x9F 4517 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4518 #define CMD_FCP_TRSP64_WQE 0xA3 4519 #define CMD_GEN_REQUEST64_WQE 0xC2 4520 4521 #define CMD_WQE_MASK 0xff 4522 4523 4524 #define LPFC_FW_DUMP 1 4525 #define LPFC_FW_RESET 2 4526 #define LPFC_DV_RESET 3 4527